SelectionDAG.cpp revision af29a5235d3a1a09e9fc2989a5d504f00fa9aaf3
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-~0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one ~0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 case ISD::VECTOR_SHUFFLE: { 460 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 461 for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements(); 462 i != e; ++i) 463 ID.AddInteger(SVN->getMaskElt(i)); 464 break; 465 } 466 } // end switch (N->getOpcode()) 467} 468 469/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 470/// data. 471static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 472 AddNodeIDOpcode(ID, N->getOpcode()); 473 // Add the return value info. 474 AddNodeIDValueTypes(ID, N->getVTList()); 475 // Add the operand info. 476 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 477 478 // Handle SDNode leafs with special info. 479 AddNodeIDCustom(ID, N); 480} 481 482/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 483/// the CSE map that carries alignment, volatility, indexing mode, and 484/// extension/truncation information. 485/// 486static inline unsigned 487encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 488 bool isVolatile, unsigned Alignment) { 489 assert((ConvType & 3) == ConvType && 490 "ConvType may not require more than 2 bits!"); 491 assert((AM & 7) == AM && 492 "AM may not require more than 3 bits!"); 493 return ConvType | 494 (AM << 2) | 495 (isVolatile << 5) | 496 ((Log2_32(Alignment) + 1) << 6); 497} 498 499//===----------------------------------------------------------------------===// 500// SelectionDAG Class 501//===----------------------------------------------------------------------===// 502 503/// doNotCSE - Return true if CSE should not be performed for this node. 504static bool doNotCSE(SDNode *N) { 505 if (N->getValueType(0) == MVT::Flag) 506 return true; // Never CSE anything that produces a flag. 507 508 switch (N->getOpcode()) { 509 default: break; 510 case ISD::HANDLENODE: 511 case ISD::DBG_LABEL: 512 case ISD::DBG_STOPPOINT: 513 case ISD::EH_LABEL: 514 case ISD::DECLARE: 515 return true; // Never CSE these nodes. 516 } 517 518 // Check that remaining values produced are not flags. 519 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 520 if (N->getValueType(i) == MVT::Flag) 521 return true; // Never CSE anything that produces a flag. 522 523 return false; 524} 525 526/// RemoveDeadNodes - This method deletes all unreachable nodes in the 527/// SelectionDAG. 528void SelectionDAG::RemoveDeadNodes() { 529 // Create a dummy node (which is not added to allnodes), that adds a reference 530 // to the root node, preventing it from being deleted. 531 HandleSDNode Dummy(getRoot()); 532 533 SmallVector<SDNode*, 128> DeadNodes; 534 535 // Add all obviously-dead nodes to the DeadNodes worklist. 536 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 537 if (I->use_empty()) 538 DeadNodes.push_back(I); 539 540 RemoveDeadNodes(DeadNodes); 541 542 // If the root changed (e.g. it was a dead load, update the root). 543 setRoot(Dummy.getValue()); 544} 545 546/// RemoveDeadNodes - This method deletes the unreachable nodes in the 547/// given list, and any nodes that become unreachable as a result. 548void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 549 DAGUpdateListener *UpdateListener) { 550 551 // Process the worklist, deleting the nodes and adding their uses to the 552 // worklist. 553 while (!DeadNodes.empty()) { 554 SDNode *N = DeadNodes.pop_back_val(); 555 556 if (UpdateListener) 557 UpdateListener->NodeDeleted(N, 0); 558 559 // Take the node out of the appropriate CSE map. 560 RemoveNodeFromCSEMaps(N); 561 562 // Next, brutally remove the operand list. This is safe to do, as there are 563 // no cycles in the graph. 564 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 565 SDUse &Use = *I++; 566 SDNode *Operand = Use.getNode(); 567 Use.set(SDValue()); 568 569 // Now that we removed this operand, see if there are no uses of it left. 570 if (Operand->use_empty()) 571 DeadNodes.push_back(Operand); 572 } 573 574 DeallocateNode(N); 575 } 576} 577 578void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 579 SmallVector<SDNode*, 16> DeadNodes(1, N); 580 RemoveDeadNodes(DeadNodes, UpdateListener); 581} 582 583void SelectionDAG::DeleteNode(SDNode *N) { 584 // First take this out of the appropriate CSE map. 585 RemoveNodeFromCSEMaps(N); 586 587 // Finally, remove uses due to operands of this node, remove from the 588 // AllNodes list, and delete the node. 589 DeleteNodeNotInCSEMaps(N); 590} 591 592void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 593 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 594 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 595 596 // Drop all of the operands and decrement used node's use counts. 597 N->DropOperands(); 598 599 DeallocateNode(N); 600} 601 602void SelectionDAG::DeallocateNode(SDNode *N) { 603 if (N->OperandsNeedDelete) 604 delete[] N->OperandList; 605 606 // Set the opcode to DELETED_NODE to help catch bugs when node 607 // memory is reallocated. 608 N->NodeType = ISD::DELETED_NODE; 609 610 NodeAllocator.Deallocate(AllNodes.remove(N)); 611} 612 613/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 614/// correspond to it. This is useful when we're about to delete or repurpose 615/// the node. We don't want future request for structurally identical nodes 616/// to return N anymore. 617bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 618 bool Erased = false; 619 switch (N->getOpcode()) { 620 case ISD::EntryToken: 621 assert(0 && "EntryToken should not be in CSEMaps!"); 622 return false; 623 case ISD::HANDLENODE: return false; // noop. 624 case ISD::CONDCODE: 625 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 626 "Cond code doesn't exist!"); 627 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 628 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 629 break; 630 case ISD::ExternalSymbol: 631 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 632 break; 633 case ISD::TargetExternalSymbol: 634 Erased = 635 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 636 break; 637 case ISD::VALUETYPE: { 638 MVT VT = cast<VTSDNode>(N)->getVT(); 639 if (VT.isExtended()) { 640 Erased = ExtendedValueTypeNodes.erase(VT); 641 } else { 642 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 643 ValueTypeNodes[VT.getSimpleVT()] = 0; 644 } 645 break; 646 } 647 default: 648 // Remove it from the CSE Map. 649 Erased = CSEMap.RemoveNode(N); 650 break; 651 } 652#ifndef NDEBUG 653 // Verify that the node was actually in one of the CSE maps, unless it has a 654 // flag result (which cannot be CSE'd) or is one of the special cases that are 655 // not subject to CSE. 656 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 657 !N->isMachineOpcode() && !doNotCSE(N)) { 658 N->dump(this); 659 cerr << "\n"; 660 assert(0 && "Node is not in map!"); 661 } 662#endif 663 return Erased; 664} 665 666/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 667/// maps and modified in place. Add it back to the CSE maps, unless an identical 668/// node already exists, in which case transfer all its users to the existing 669/// node. This transfer can potentially trigger recursive merging. 670/// 671void 672SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 673 DAGUpdateListener *UpdateListener) { 674 // For node types that aren't CSE'd, just act as if no identical node 675 // already exists. 676 if (!doNotCSE(N)) { 677 SDNode *Existing = CSEMap.GetOrInsertNode(N); 678 if (Existing != N) { 679 // If there was already an existing matching node, use ReplaceAllUsesWith 680 // to replace the dead one with the existing one. This can cause 681 // recursive merging of other unrelated nodes down the line. 682 ReplaceAllUsesWith(N, Existing, UpdateListener); 683 684 // N is now dead. Inform the listener if it exists and delete it. 685 if (UpdateListener) 686 UpdateListener->NodeDeleted(N, Existing); 687 DeleteNodeNotInCSEMaps(N); 688 return; 689 } 690 } 691 692 // If the node doesn't already exist, we updated it. Inform a listener if 693 // it exists. 694 if (UpdateListener) 695 UpdateListener->NodeUpdated(N); 696} 697 698/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 699/// were replaced with those specified. If this node is never memoized, 700/// return null, otherwise return a pointer to the slot it would take. If a 701/// node already exists with these operands, the slot will be non-null. 702SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 703 void *&InsertPos) { 704 if (doNotCSE(N)) 705 return 0; 706 707 SDValue Ops[] = { Op }; 708 FoldingSetNodeID ID; 709 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 710 AddNodeIDCustom(ID, N); 711 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 712} 713 714/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 715/// were replaced with those specified. If this node is never memoized, 716/// return null, otherwise return a pointer to the slot it would take. If a 717/// node already exists with these operands, the slot will be non-null. 718SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 719 SDValue Op1, SDValue Op2, 720 void *&InsertPos) { 721 if (doNotCSE(N)) 722 return 0; 723 724 SDValue Ops[] = { Op1, Op2 }; 725 FoldingSetNodeID ID; 726 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 727 AddNodeIDCustom(ID, N); 728 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 729} 730 731 732/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 733/// were replaced with those specified. If this node is never memoized, 734/// return null, otherwise return a pointer to the slot it would take. If a 735/// node already exists with these operands, the slot will be non-null. 736SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 737 const SDValue *Ops,unsigned NumOps, 738 void *&InsertPos) { 739 if (doNotCSE(N)) 740 return 0; 741 742 FoldingSetNodeID ID; 743 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 744 AddNodeIDCustom(ID, N); 745 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 746} 747 748/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 749void SelectionDAG::VerifyNode(SDNode *N) { 750 switch (N->getOpcode()) { 751 default: 752 break; 753 case ISD::BUILD_PAIR: { 754 MVT VT = N->getValueType(0); 755 assert(N->getNumValues() == 1 && "Too many results!"); 756 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 757 "Wrong return type!"); 758 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 759 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 760 "Mismatched operand types!"); 761 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 762 "Wrong operand type!"); 763 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 764 "Wrong return type size"); 765 break; 766 } 767 case ISD::BUILD_VECTOR: { 768 assert(N->getNumValues() == 1 && "Too many results!"); 769 assert(N->getValueType(0).isVector() && "Wrong return type!"); 770 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 771 "Wrong number of operands!"); 772 MVT EltVT = N->getValueType(0).getVectorElementType(); 773 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 774 assert((I->getValueType() == EltVT || 775 (EltVT.isInteger() && I->getValueType().isInteger() && 776 EltVT.bitsLE(I->getValueType()))) && 777 "Wrong operand type!"); 778 break; 779 } 780 } 781} 782 783/// getMVTAlignment - Compute the default alignment value for the 784/// given type. 785/// 786unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 787 const Type *Ty = VT == MVT::iPTR ? 788 PointerType::get(Type::Int8Ty, 0) : 789 VT.getTypeForMVT(); 790 791 return TLI.getTargetData()->getABITypeAlignment(Ty); 792} 793 794// EntryNode could meaningfully have debug info if we can find it... 795SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 796 : TLI(tli), FLI(fli), DW(0), 797 EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), 798 getVTList(MVT::Other)), Root(getEntryNode()) { 799 AllNodes.push_back(&EntryNode); 800} 801 802void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 803 DwarfWriter *dw) { 804 MF = &mf; 805 MMI = mmi; 806 DW = dw; 807} 808 809SelectionDAG::~SelectionDAG() { 810 allnodes_clear(); 811} 812 813void SelectionDAG::allnodes_clear() { 814 assert(&*AllNodes.begin() == &EntryNode); 815 AllNodes.remove(AllNodes.begin()); 816 while (!AllNodes.empty()) 817 DeallocateNode(AllNodes.begin()); 818} 819 820void SelectionDAG::clear() { 821 allnodes_clear(); 822 OperandAllocator.Reset(); 823 CSEMap.clear(); 824 825 ExtendedValueTypeNodes.clear(); 826 ExternalSymbols.clear(); 827 TargetExternalSymbols.clear(); 828 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 829 static_cast<CondCodeSDNode*>(0)); 830 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 831 static_cast<SDNode*>(0)); 832 833 EntryNode.UseList = 0; 834 AllNodes.push_back(&EntryNode); 835 Root = getEntryNode(); 836} 837 838SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 839 if (Op.getValueType() == VT) return Op; 840 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 841 VT.getSizeInBits()); 842 return getNode(ISD::AND, DL, Op.getValueType(), Op, 843 getConstant(Imm, Op.getValueType())); 844} 845 846/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 847/// 848SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 849 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 850 SDValue NegOne = 851 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 852 return getNode(ISD::XOR, DL, VT, Val, NegOne); 853} 854 855SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 856 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 857 assert((EltVT.getSizeInBits() >= 64 || 858 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 859 "getConstant with a uint64_t value that doesn't fit in the type!"); 860 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 861} 862 863SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 864 return getConstant(*ConstantInt::get(Val), VT, isT); 865} 866 867SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 868 assert(VT.isInteger() && "Cannot create FP integer constant!"); 869 870 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 871 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 872 "APInt size does not match type size!"); 873 874 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 875 FoldingSetNodeID ID; 876 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 877 ID.AddPointer(&Val); 878 void *IP = 0; 879 SDNode *N = NULL; 880 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 881 if (!VT.isVector()) 882 return SDValue(N, 0); 883 if (!N) { 884 N = NodeAllocator.Allocate<ConstantSDNode>(); 885 new (N) ConstantSDNode(isT, &Val, EltVT); 886 CSEMap.InsertNode(N, IP); 887 AllNodes.push_back(N); 888 } 889 890 SDValue Result(N, 0); 891 if (VT.isVector()) { 892 SmallVector<SDValue, 8> Ops; 893 Ops.assign(VT.getVectorNumElements(), Result); 894 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 895 VT, &Ops[0], Ops.size()); 896 } 897 return Result; 898} 899 900SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 901 return getConstant(Val, TLI.getPointerTy(), isTarget); 902} 903 904 905SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 906 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 907} 908 909SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 910 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 911 912 MVT EltVT = 913 VT.isVector() ? VT.getVectorElementType() : VT; 914 915 // Do the map lookup using the actual bit pattern for the floating point 916 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 917 // we don't have issues with SNANs. 918 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 919 FoldingSetNodeID ID; 920 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 921 ID.AddPointer(&V); 922 void *IP = 0; 923 SDNode *N = NULL; 924 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 925 if (!VT.isVector()) 926 return SDValue(N, 0); 927 if (!N) { 928 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 929 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 930 CSEMap.InsertNode(N, IP); 931 AllNodes.push_back(N); 932 } 933 934 SDValue Result(N, 0); 935 if (VT.isVector()) { 936 SmallVector<SDValue, 8> Ops; 937 Ops.assign(VT.getVectorNumElements(), Result); 938 // FIXME DebugLoc info might be appropriate here 939 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 940 VT, &Ops[0], Ops.size()); 941 } 942 return Result; 943} 944 945SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 946 MVT EltVT = 947 VT.isVector() ? VT.getVectorElementType() : VT; 948 if (EltVT==MVT::f32) 949 return getConstantFP(APFloat((float)Val), VT, isTarget); 950 else 951 return getConstantFP(APFloat(Val), VT, isTarget); 952} 953 954SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 955 MVT VT, int64_t Offset, 956 bool isTargetGA) { 957 unsigned Opc; 958 959 // Truncate (with sign-extension) the offset value to the pointer size. 960 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 961 if (BitWidth < 64) 962 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 963 964 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 965 if (!GVar) { 966 // If GV is an alias then use the aliasee for determining thread-localness. 967 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 968 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 969 } 970 971 if (GVar && GVar->isThreadLocal()) 972 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 973 else 974 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 975 976 FoldingSetNodeID ID; 977 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 978 ID.AddPointer(GV); 979 ID.AddInteger(Offset); 980 void *IP = 0; 981 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 982 return SDValue(E, 0); 983 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 984 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 985 CSEMap.InsertNode(N, IP); 986 AllNodes.push_back(N); 987 return SDValue(N, 0); 988} 989 990SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 991 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 992 FoldingSetNodeID ID; 993 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 994 ID.AddInteger(FI); 995 void *IP = 0; 996 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 997 return SDValue(E, 0); 998 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 999 new (N) FrameIndexSDNode(FI, VT, isTarget); 1000 CSEMap.InsertNode(N, IP); 1001 AllNodes.push_back(N); 1002 return SDValue(N, 0); 1003} 1004 1005SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1006 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1007 FoldingSetNodeID ID; 1008 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1009 ID.AddInteger(JTI); 1010 void *IP = 0; 1011 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1012 return SDValue(E, 0); 1013 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1014 new (N) JumpTableSDNode(JTI, VT, isTarget); 1015 CSEMap.InsertNode(N, IP); 1016 AllNodes.push_back(N); 1017 return SDValue(N, 0); 1018} 1019 1020SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1021 unsigned Alignment, int Offset, 1022 bool isTarget) { 1023 if (Alignment == 0) 1024 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1025 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1026 FoldingSetNodeID ID; 1027 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1028 ID.AddInteger(Alignment); 1029 ID.AddInteger(Offset); 1030 ID.AddPointer(C); 1031 void *IP = 0; 1032 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1033 return SDValue(E, 0); 1034 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1035 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1036 CSEMap.InsertNode(N, IP); 1037 AllNodes.push_back(N); 1038 return SDValue(N, 0); 1039} 1040 1041 1042SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1043 unsigned Alignment, int Offset, 1044 bool isTarget) { 1045 if (Alignment == 0) 1046 Alignment = TLI.getTargetData()->getPrefTypeAlignment(C->getType()); 1047 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1048 FoldingSetNodeID ID; 1049 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1050 ID.AddInteger(Alignment); 1051 ID.AddInteger(Offset); 1052 C->AddSelectionDAGCSEId(ID); 1053 void *IP = 0; 1054 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1055 return SDValue(E, 0); 1056 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1057 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1058 CSEMap.InsertNode(N, IP); 1059 AllNodes.push_back(N); 1060 return SDValue(N, 0); 1061} 1062 1063SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1064 FoldingSetNodeID ID; 1065 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1066 ID.AddPointer(MBB); 1067 void *IP = 0; 1068 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1069 return SDValue(E, 0); 1070 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1071 new (N) BasicBlockSDNode(MBB); 1072 CSEMap.InsertNode(N, IP); 1073 AllNodes.push_back(N); 1074 return SDValue(N, 0); 1075} 1076 1077SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1078 FoldingSetNodeID ID; 1079 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1080 ID.AddInteger(Flags.getRawBits()); 1081 void *IP = 0; 1082 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1083 return SDValue(E, 0); 1084 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1085 new (N) ARG_FLAGSSDNode(Flags); 1086 CSEMap.InsertNode(N, IP); 1087 AllNodes.push_back(N); 1088 return SDValue(N, 0); 1089} 1090 1091SDValue SelectionDAG::getValueType(MVT VT) { 1092 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1093 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1094 1095 SDNode *&N = VT.isExtended() ? 1096 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1097 1098 if (N) return SDValue(N, 0); 1099 N = NodeAllocator.Allocate<VTSDNode>(); 1100 new (N) VTSDNode(VT); 1101 AllNodes.push_back(N); 1102 return SDValue(N, 0); 1103} 1104 1105SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1106 SDNode *&N = ExternalSymbols[Sym]; 1107 if (N) return SDValue(N, 0); 1108 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1109 new (N) ExternalSymbolSDNode(false, Sym, VT); 1110 AllNodes.push_back(N); 1111 return SDValue(N, 0); 1112} 1113 1114SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1115 SDNode *&N = TargetExternalSymbols[Sym]; 1116 if (N) return SDValue(N, 0); 1117 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1118 new (N) ExternalSymbolSDNode(true, Sym, VT); 1119 AllNodes.push_back(N); 1120 return SDValue(N, 0); 1121} 1122 1123SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1124 if ((unsigned)Cond >= CondCodeNodes.size()) 1125 CondCodeNodes.resize(Cond+1); 1126 1127 if (CondCodeNodes[Cond] == 0) { 1128 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1129 new (N) CondCodeSDNode(Cond); 1130 CondCodeNodes[Cond] = N; 1131 AllNodes.push_back(N); 1132 } 1133 return SDValue(CondCodeNodes[Cond], 0); 1134} 1135 1136// commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1137// the shuffle mask M that point at N1 to point at N2, and indices that point 1138// N2 to point at N1. 1139static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { 1140 std::swap(N1, N2); 1141 int NElts = M.size(); 1142 for (int i = 0; i != NElts; ++i) { 1143 if (M[i] >= NElts) 1144 M[i] -= NElts; 1145 else if (M[i] >= 0) 1146 M[i] += NElts; 1147 } 1148} 1149 1150SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, 1151 SDValue N2, const int *Mask) { 1152 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1153 assert(VT.isVector() && N1.getValueType().isVector() && 1154 "Vector Shuffle VTs must be a vectors"); 1155 assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType() 1156 && "Vector Shuffle VTs must have same element type"); 1157 1158 // Canonicalize shuffle undef, undef -> undef 1159 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1160 return N1; 1161 1162 // Validate that all indices in Mask are within the range of the elements 1163 // input to the shuffle. 1164 unsigned NElts = VT.getVectorNumElements(); 1165 SmallVector<int, 8> MaskVec; 1166 for (unsigned i = 0; i != NElts; ++i) { 1167 assert(Mask[i] < (int)(NElts * 2) && "Index out of range"); 1168 MaskVec.push_back(Mask[i]); 1169 } 1170 1171 // Canonicalize shuffle v, v -> v, undef 1172 if (N1 == N2) { 1173 N2 = getUNDEF(VT); 1174 for (unsigned i = 0; i != NElts; ++i) 1175 if (MaskVec[i] >= (int)NElts) MaskVec[i] -= NElts; 1176 } 1177 1178 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 1179 if (N1.getOpcode() == ISD::UNDEF) 1180 commuteShuffle(N1, N2, MaskVec); 1181 1182 // Canonicalize all index into lhs, -> shuffle lhs, undef 1183 // Canonicalize all index into rhs, -> shuffle rhs, undef 1184 bool AllLHS = true, AllRHS = true; 1185 bool N2Undef = N2.getOpcode() == ISD::UNDEF; 1186 for (unsigned i = 0; i != NElts; ++i) { 1187 if (MaskVec[i] >= (int)NElts) { 1188 if (N2Undef) 1189 MaskVec[i] = -1; 1190 else 1191 AllLHS = false; 1192 } else if (MaskVec[i] >= 0) { 1193 AllRHS = false; 1194 } 1195 } 1196 if (AllLHS && AllRHS) 1197 return getUNDEF(VT); 1198 if (AllLHS && !N2Undef) 1199 N2 = getUNDEF(VT); 1200 if (AllRHS) { 1201 N1 = getUNDEF(VT); 1202 commuteShuffle(N1, N2, MaskVec); 1203 } 1204 1205 // If Identity shuffle, or all shuffle in to undef, return that node. 1206 bool AllUndef = true; 1207 bool Identity = true; 1208 for (unsigned i = 0; i != NElts; ++i) { 1209 if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false; 1210 if (MaskVec[i] >= 0) AllUndef = false; 1211 } 1212 if (Identity) 1213 return N1; 1214 if (AllUndef) 1215 return getUNDEF(VT); 1216 1217 FoldingSetNodeID ID; 1218 SDValue Ops[2] = { N1, N2 }; 1219 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2); 1220 for (unsigned i = 0; i != NElts; ++i) 1221 ID.AddInteger(MaskVec[i]); 1222 1223 void* IP = 0; 1224 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1225 return SDValue(E, 0); 1226 1227 // Allocate the mask array for the node out of the BumpPtrAllocator, since 1228 // SDNode doesn't have access to it. This memory will be "leaked" when 1229 // the node is deallocated, but recovered when the NodeAllocator is released. 1230 int *MaskAlloc = OperandAllocator.Allocate<int>(NElts); 1231 memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int)); 1232 1233 ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>(); 1234 new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc); 1235 CSEMap.InsertNode(N, IP); 1236 AllNodes.push_back(N); 1237 return SDValue(N, 0); 1238} 1239 1240SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1241 SDValue Val, SDValue DTy, 1242 SDValue STy, SDValue Rnd, SDValue Sat, 1243 ISD::CvtCode Code) { 1244 // If the src and dest types are the same and the conversion is between 1245 // integer types of the same sign or two floats, no conversion is necessary. 1246 if (DTy == STy && 1247 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1248 return Val; 1249 1250 FoldingSetNodeID ID; 1251 void* IP = 0; 1252 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1253 return SDValue(E, 0); 1254 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1255 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1256 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1257 CSEMap.InsertNode(N, IP); 1258 AllNodes.push_back(N); 1259 return SDValue(N, 0); 1260} 1261 1262SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1263 FoldingSetNodeID ID; 1264 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1265 ID.AddInteger(RegNo); 1266 void *IP = 0; 1267 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1268 return SDValue(E, 0); 1269 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1270 new (N) RegisterSDNode(RegNo, VT); 1271 CSEMap.InsertNode(N, IP); 1272 AllNodes.push_back(N); 1273 return SDValue(N, 0); 1274} 1275 1276SDValue SelectionDAG::getDbgStopPoint(DebugLoc DL, SDValue Root, 1277 unsigned Line, unsigned Col, 1278 Value *CU) { 1279 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1280 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1281 N->setDebugLoc(DL); 1282 AllNodes.push_back(N); 1283 return SDValue(N, 0); 1284} 1285 1286SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1287 SDValue Root, 1288 unsigned LabelID) { 1289 FoldingSetNodeID ID; 1290 SDValue Ops[] = { Root }; 1291 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1292 ID.AddInteger(LabelID); 1293 void *IP = 0; 1294 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1295 return SDValue(E, 0); 1296 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1297 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1298 CSEMap.InsertNode(N, IP); 1299 AllNodes.push_back(N); 1300 return SDValue(N, 0); 1301} 1302 1303SDValue SelectionDAG::getSrcValue(const Value *V) { 1304 assert((!V || isa<PointerType>(V->getType())) && 1305 "SrcValue is not a pointer?"); 1306 1307 FoldingSetNodeID ID; 1308 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1309 ID.AddPointer(V); 1310 1311 void *IP = 0; 1312 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1313 return SDValue(E, 0); 1314 1315 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1316 new (N) SrcValueSDNode(V); 1317 CSEMap.InsertNode(N, IP); 1318 AllNodes.push_back(N); 1319 return SDValue(N, 0); 1320} 1321 1322SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1323#ifndef NDEBUG 1324 const Value *v = MO.getValue(); 1325 assert((!v || isa<PointerType>(v->getType())) && 1326 "SrcValue is not a pointer?"); 1327#endif 1328 1329 FoldingSetNodeID ID; 1330 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1331 MO.Profile(ID); 1332 1333 void *IP = 0; 1334 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1335 return SDValue(E, 0); 1336 1337 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1338 new (N) MemOperandSDNode(MO); 1339 CSEMap.InsertNode(N, IP); 1340 AllNodes.push_back(N); 1341 return SDValue(N, 0); 1342} 1343 1344/// getShiftAmountOperand - Return the specified value casted to 1345/// the target's desired shift amount type. 1346SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1347 MVT OpTy = Op.getValueType(); 1348 MVT ShTy = TLI.getShiftAmountTy(); 1349 if (OpTy == ShTy || OpTy.isVector()) return Op; 1350 1351 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1352 return getNode(Opcode, Op.getDebugLoc(), ShTy, Op); 1353} 1354 1355/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1356/// specified value type. 1357SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1358 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1359 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1360 const Type *Ty = VT.getTypeForMVT(); 1361 unsigned StackAlign = 1362 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1363 1364 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1365 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1366} 1367 1368/// CreateStackTemporary - Create a stack temporary suitable for holding 1369/// either of the specified value types. 1370SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1371 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1372 VT2.getStoreSizeInBits())/8; 1373 const Type *Ty1 = VT1.getTypeForMVT(); 1374 const Type *Ty2 = VT2.getTypeForMVT(); 1375 const TargetData *TD = TLI.getTargetData(); 1376 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1377 TD->getPrefTypeAlignment(Ty2)); 1378 1379 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1380 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1381 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1382} 1383 1384SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1385 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1386 // These setcc operations always fold. 1387 switch (Cond) { 1388 default: break; 1389 case ISD::SETFALSE: 1390 case ISD::SETFALSE2: return getConstant(0, VT); 1391 case ISD::SETTRUE: 1392 case ISD::SETTRUE2: return getConstant(1, VT); 1393 1394 case ISD::SETOEQ: 1395 case ISD::SETOGT: 1396 case ISD::SETOGE: 1397 case ISD::SETOLT: 1398 case ISD::SETOLE: 1399 case ISD::SETONE: 1400 case ISD::SETO: 1401 case ISD::SETUO: 1402 case ISD::SETUEQ: 1403 case ISD::SETUNE: 1404 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1405 break; 1406 } 1407 1408 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1409 const APInt &C2 = N2C->getAPIntValue(); 1410 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1411 const APInt &C1 = N1C->getAPIntValue(); 1412 1413 switch (Cond) { 1414 default: assert(0 && "Unknown integer setcc!"); 1415 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1416 case ISD::SETNE: return getConstant(C1 != C2, VT); 1417 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1418 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1419 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1420 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1421 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1422 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1423 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1424 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1425 } 1426 } 1427 } 1428 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1429 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1430 // No compile time operations on this type yet. 1431 if (N1C->getValueType(0) == MVT::ppcf128) 1432 return SDValue(); 1433 1434 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1435 switch (Cond) { 1436 default: break; 1437 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1438 return getUNDEF(VT); 1439 // fall through 1440 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1441 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1442 return getUNDEF(VT); 1443 // fall through 1444 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1445 R==APFloat::cmpLessThan, VT); 1446 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1447 return getUNDEF(VT); 1448 // fall through 1449 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1450 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1451 return getUNDEF(VT); 1452 // fall through 1453 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1454 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1455 return getUNDEF(VT); 1456 // fall through 1457 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1458 R==APFloat::cmpEqual, VT); 1459 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1460 return getUNDEF(VT); 1461 // fall through 1462 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1463 R==APFloat::cmpEqual, VT); 1464 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1465 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1466 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1467 R==APFloat::cmpEqual, VT); 1468 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1469 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1470 R==APFloat::cmpLessThan, VT); 1471 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1472 R==APFloat::cmpUnordered, VT); 1473 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1474 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1475 } 1476 } else { 1477 // Ensure that the constant occurs on the RHS. 1478 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1479 } 1480 } 1481 1482 // Could not fold it. 1483 return SDValue(); 1484} 1485 1486/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1487/// use this predicate to simplify operations downstream. 1488bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1489 unsigned BitWidth = Op.getValueSizeInBits(); 1490 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1491} 1492 1493/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1494/// this predicate to simplify operations downstream. Mask is known to be zero 1495/// for bits that V cannot have. 1496bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1497 unsigned Depth) const { 1498 APInt KnownZero, KnownOne; 1499 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1501 return (KnownZero & Mask) == Mask; 1502} 1503 1504/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1505/// known to be either zero or one and return them in the KnownZero/KnownOne 1506/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1507/// processing. 1508void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1509 APInt &KnownZero, APInt &KnownOne, 1510 unsigned Depth) const { 1511 unsigned BitWidth = Mask.getBitWidth(); 1512 assert(BitWidth == Op.getValueType().getSizeInBits() && 1513 "Mask size mismatches value type size!"); 1514 1515 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1516 if (Depth == 6 || Mask == 0) 1517 return; // Limit search depth. 1518 1519 APInt KnownZero2, KnownOne2; 1520 1521 switch (Op.getOpcode()) { 1522 case ISD::Constant: 1523 // We know all of the bits for a constant! 1524 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1525 KnownZero = ~KnownOne & Mask; 1526 return; 1527 case ISD::AND: 1528 // If either the LHS or the RHS are Zero, the result is zero. 1529 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1530 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1531 KnownZero2, KnownOne2, Depth+1); 1532 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1533 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1534 1535 // Output known-1 bits are only known if set in both the LHS & RHS. 1536 KnownOne &= KnownOne2; 1537 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1538 KnownZero |= KnownZero2; 1539 return; 1540 case ISD::OR: 1541 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1542 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1543 KnownZero2, KnownOne2, Depth+1); 1544 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1545 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1546 1547 // Output known-0 bits are only known if clear in both the LHS & RHS. 1548 KnownZero &= KnownZero2; 1549 // Output known-1 are known to be set if set in either the LHS | RHS. 1550 KnownOne |= KnownOne2; 1551 return; 1552 case ISD::XOR: { 1553 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1554 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1555 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1556 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1557 1558 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1559 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1560 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1561 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1562 KnownZero = KnownZeroOut; 1563 return; 1564 } 1565 case ISD::MUL: { 1566 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1567 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1568 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1569 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1570 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1571 1572 // If low bits are zero in either operand, output low known-0 bits. 1573 // Also compute a conserative estimate for high known-0 bits. 1574 // More trickiness is possible, but this is sufficient for the 1575 // interesting case of alignment computation. 1576 KnownOne.clear(); 1577 unsigned TrailZ = KnownZero.countTrailingOnes() + 1578 KnownZero2.countTrailingOnes(); 1579 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1580 KnownZero2.countLeadingOnes(), 1581 BitWidth) - BitWidth; 1582 1583 TrailZ = std::min(TrailZ, BitWidth); 1584 LeadZ = std::min(LeadZ, BitWidth); 1585 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1586 APInt::getHighBitsSet(BitWidth, LeadZ); 1587 KnownZero &= Mask; 1588 return; 1589 } 1590 case ISD::UDIV: { 1591 // For the purposes of computing leading zeros we can conservatively 1592 // treat a udiv as a logical right shift by the power of 2 known to 1593 // be less than the denominator. 1594 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1595 ComputeMaskedBits(Op.getOperand(0), 1596 AllOnes, KnownZero2, KnownOne2, Depth+1); 1597 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1598 1599 KnownOne2.clear(); 1600 KnownZero2.clear(); 1601 ComputeMaskedBits(Op.getOperand(1), 1602 AllOnes, KnownZero2, KnownOne2, Depth+1); 1603 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1604 if (RHSUnknownLeadingOnes != BitWidth) 1605 LeadZ = std::min(BitWidth, 1606 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1607 1608 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1609 return; 1610 } 1611 case ISD::SELECT: 1612 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1613 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1614 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1615 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1616 1617 // Only known if known in both the LHS and RHS. 1618 KnownOne &= KnownOne2; 1619 KnownZero &= KnownZero2; 1620 return; 1621 case ISD::SELECT_CC: 1622 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1623 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1624 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1625 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1626 1627 // Only known if known in both the LHS and RHS. 1628 KnownOne &= KnownOne2; 1629 KnownZero &= KnownZero2; 1630 return; 1631 case ISD::SADDO: 1632 case ISD::UADDO: 1633 case ISD::SSUBO: 1634 case ISD::USUBO: 1635 case ISD::SMULO: 1636 case ISD::UMULO: 1637 if (Op.getResNo() != 1) 1638 return; 1639 // The boolean result conforms to getBooleanContents. Fall through. 1640 case ISD::SETCC: 1641 // If we know the result of a setcc has the top bits zero, use this info. 1642 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1643 BitWidth > 1) 1644 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1645 return; 1646 case ISD::SHL: 1647 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1648 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1649 unsigned ShAmt = SA->getZExtValue(); 1650 1651 // If the shift count is an invalid immediate, don't do anything. 1652 if (ShAmt >= BitWidth) 1653 return; 1654 1655 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1656 KnownZero, KnownOne, Depth+1); 1657 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1658 KnownZero <<= ShAmt; 1659 KnownOne <<= ShAmt; 1660 // low bits known zero. 1661 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1662 } 1663 return; 1664 case ISD::SRL: 1665 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1666 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1667 unsigned ShAmt = SA->getZExtValue(); 1668 1669 // If the shift count is an invalid immediate, don't do anything. 1670 if (ShAmt >= BitWidth) 1671 return; 1672 1673 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1674 KnownZero, KnownOne, Depth+1); 1675 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1676 KnownZero = KnownZero.lshr(ShAmt); 1677 KnownOne = KnownOne.lshr(ShAmt); 1678 1679 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1680 KnownZero |= HighBits; // High bits known zero. 1681 } 1682 return; 1683 case ISD::SRA: 1684 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1685 unsigned ShAmt = SA->getZExtValue(); 1686 1687 // If the shift count is an invalid immediate, don't do anything. 1688 if (ShAmt >= BitWidth) 1689 return; 1690 1691 APInt InDemandedMask = (Mask << ShAmt); 1692 // If any of the demanded bits are produced by the sign extension, we also 1693 // demand the input sign bit. 1694 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1695 if (HighBits.getBoolValue()) 1696 InDemandedMask |= APInt::getSignBit(BitWidth); 1697 1698 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1699 Depth+1); 1700 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1701 KnownZero = KnownZero.lshr(ShAmt); 1702 KnownOne = KnownOne.lshr(ShAmt); 1703 1704 // Handle the sign bits. 1705 APInt SignBit = APInt::getSignBit(BitWidth); 1706 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1707 1708 if (KnownZero.intersects(SignBit)) { 1709 KnownZero |= HighBits; // New bits are known zero. 1710 } else if (KnownOne.intersects(SignBit)) { 1711 KnownOne |= HighBits; // New bits are known one. 1712 } 1713 } 1714 return; 1715 case ISD::SIGN_EXTEND_INREG: { 1716 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1717 unsigned EBits = EVT.getSizeInBits(); 1718 1719 // Sign extension. Compute the demanded bits in the result that are not 1720 // present in the input. 1721 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1722 1723 APInt InSignBit = APInt::getSignBit(EBits); 1724 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1725 1726 // If the sign extended bits are demanded, we know that the sign 1727 // bit is demanded. 1728 InSignBit.zext(BitWidth); 1729 if (NewBits.getBoolValue()) 1730 InputDemandedBits |= InSignBit; 1731 1732 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1733 KnownZero, KnownOne, Depth+1); 1734 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1735 1736 // If the sign bit of the input is known set or clear, then we know the 1737 // top bits of the result. 1738 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1739 KnownZero |= NewBits; 1740 KnownOne &= ~NewBits; 1741 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1742 KnownOne |= NewBits; 1743 KnownZero &= ~NewBits; 1744 } else { // Input sign bit unknown 1745 KnownZero &= ~NewBits; 1746 KnownOne &= ~NewBits; 1747 } 1748 return; 1749 } 1750 case ISD::CTTZ: 1751 case ISD::CTLZ: 1752 case ISD::CTPOP: { 1753 unsigned LowBits = Log2_32(BitWidth)+1; 1754 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1755 KnownOne.clear(); 1756 return; 1757 } 1758 case ISD::LOAD: { 1759 if (ISD::isZEXTLoad(Op.getNode())) { 1760 LoadSDNode *LD = cast<LoadSDNode>(Op); 1761 MVT VT = LD->getMemoryVT(); 1762 unsigned MemBits = VT.getSizeInBits(); 1763 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1764 } 1765 return; 1766 } 1767 case ISD::ZERO_EXTEND: { 1768 MVT InVT = Op.getOperand(0).getValueType(); 1769 unsigned InBits = InVT.getSizeInBits(); 1770 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1771 APInt InMask = Mask; 1772 InMask.trunc(InBits); 1773 KnownZero.trunc(InBits); 1774 KnownOne.trunc(InBits); 1775 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1776 KnownZero.zext(BitWidth); 1777 KnownOne.zext(BitWidth); 1778 KnownZero |= NewBits; 1779 return; 1780 } 1781 case ISD::SIGN_EXTEND: { 1782 MVT InVT = Op.getOperand(0).getValueType(); 1783 unsigned InBits = InVT.getSizeInBits(); 1784 APInt InSignBit = APInt::getSignBit(InBits); 1785 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1786 APInt InMask = Mask; 1787 InMask.trunc(InBits); 1788 1789 // If any of the sign extended bits are demanded, we know that the sign 1790 // bit is demanded. Temporarily set this bit in the mask for our callee. 1791 if (NewBits.getBoolValue()) 1792 InMask |= InSignBit; 1793 1794 KnownZero.trunc(InBits); 1795 KnownOne.trunc(InBits); 1796 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1797 1798 // Note if the sign bit is known to be zero or one. 1799 bool SignBitKnownZero = KnownZero.isNegative(); 1800 bool SignBitKnownOne = KnownOne.isNegative(); 1801 assert(!(SignBitKnownZero && SignBitKnownOne) && 1802 "Sign bit can't be known to be both zero and one!"); 1803 1804 // If the sign bit wasn't actually demanded by our caller, we don't 1805 // want it set in the KnownZero and KnownOne result values. Reset the 1806 // mask and reapply it to the result values. 1807 InMask = Mask; 1808 InMask.trunc(InBits); 1809 KnownZero &= InMask; 1810 KnownOne &= InMask; 1811 1812 KnownZero.zext(BitWidth); 1813 KnownOne.zext(BitWidth); 1814 1815 // If the sign bit is known zero or one, the top bits match. 1816 if (SignBitKnownZero) 1817 KnownZero |= NewBits; 1818 else if (SignBitKnownOne) 1819 KnownOne |= NewBits; 1820 return; 1821 } 1822 case ISD::ANY_EXTEND: { 1823 MVT InVT = Op.getOperand(0).getValueType(); 1824 unsigned InBits = InVT.getSizeInBits(); 1825 APInt InMask = Mask; 1826 InMask.trunc(InBits); 1827 KnownZero.trunc(InBits); 1828 KnownOne.trunc(InBits); 1829 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1830 KnownZero.zext(BitWidth); 1831 KnownOne.zext(BitWidth); 1832 return; 1833 } 1834 case ISD::TRUNCATE: { 1835 MVT InVT = Op.getOperand(0).getValueType(); 1836 unsigned InBits = InVT.getSizeInBits(); 1837 APInt InMask = Mask; 1838 InMask.zext(InBits); 1839 KnownZero.zext(InBits); 1840 KnownOne.zext(InBits); 1841 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1842 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1843 KnownZero.trunc(BitWidth); 1844 KnownOne.trunc(BitWidth); 1845 break; 1846 } 1847 case ISD::AssertZext: { 1848 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1849 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1850 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1851 KnownOne, Depth+1); 1852 KnownZero |= (~InMask) & Mask; 1853 return; 1854 } 1855 case ISD::FGETSIGN: 1856 // All bits are zero except the low bit. 1857 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1858 return; 1859 1860 case ISD::SUB: { 1861 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1862 // We know that the top bits of C-X are clear if X contains less bits 1863 // than C (i.e. no wrap-around can happen). For example, 20-X is 1864 // positive if we can prove that X is >= 0 and < 16. 1865 if (CLHS->getAPIntValue().isNonNegative()) { 1866 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1867 // NLZ can't be BitWidth with no sign bit 1868 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1869 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1870 Depth+1); 1871 1872 // If all of the MaskV bits are known to be zero, then we know the 1873 // output top bits are zero, because we now know that the output is 1874 // from [0-C]. 1875 if ((KnownZero2 & MaskV) == MaskV) { 1876 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1877 // Top bits known zero. 1878 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1879 } 1880 } 1881 } 1882 } 1883 // fall through 1884 case ISD::ADD: { 1885 // Output known-0 bits are known if clear or set in both the low clear bits 1886 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1887 // low 3 bits clear. 1888 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1889 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1890 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1891 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1892 1893 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1894 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1895 KnownZeroOut = std::min(KnownZeroOut, 1896 KnownZero2.countTrailingOnes()); 1897 1898 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1899 return; 1900 } 1901 case ISD::SREM: 1902 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1903 const APInt &RA = Rem->getAPIntValue(); 1904 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1905 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1906 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1907 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1908 1909 // If the sign bit of the first operand is zero, the sign bit of 1910 // the result is zero. If the first operand has no one bits below 1911 // the second operand's single 1 bit, its sign will be zero. 1912 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1913 KnownZero2 |= ~LowBits; 1914 1915 KnownZero |= KnownZero2 & Mask; 1916 1917 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1918 } 1919 } 1920 return; 1921 case ISD::UREM: { 1922 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1923 const APInt &RA = Rem->getAPIntValue(); 1924 if (RA.isPowerOf2()) { 1925 APInt LowBits = (RA - 1); 1926 APInt Mask2 = LowBits & Mask; 1927 KnownZero |= ~LowBits & Mask; 1928 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1929 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1930 break; 1931 } 1932 } 1933 1934 // Since the result is less than or equal to either operand, any leading 1935 // zero bits in either operand must also exist in the result. 1936 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1937 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1938 Depth+1); 1939 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1940 Depth+1); 1941 1942 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1943 KnownZero2.countLeadingOnes()); 1944 KnownOne.clear(); 1945 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1946 return; 1947 } 1948 default: 1949 // Allow the target to implement this method for its nodes. 1950 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1951 case ISD::INTRINSIC_WO_CHAIN: 1952 case ISD::INTRINSIC_W_CHAIN: 1953 case ISD::INTRINSIC_VOID: 1954 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1955 } 1956 return; 1957 } 1958} 1959 1960/// ComputeNumSignBits - Return the number of times the sign bit of the 1961/// register is replicated into the other bits. We know that at least 1 bit 1962/// is always equal to the sign bit (itself), but other cases can give us 1963/// information. For example, immediately after an "SRA X, 2", we know that 1964/// the top 3 bits are all equal to each other, so we return 3. 1965unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1966 MVT VT = Op.getValueType(); 1967 assert(VT.isInteger() && "Invalid VT!"); 1968 unsigned VTBits = VT.getSizeInBits(); 1969 unsigned Tmp, Tmp2; 1970 unsigned FirstAnswer = 1; 1971 1972 if (Depth == 6) 1973 return 1; // Limit search depth. 1974 1975 switch (Op.getOpcode()) { 1976 default: break; 1977 case ISD::AssertSext: 1978 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1979 return VTBits-Tmp+1; 1980 case ISD::AssertZext: 1981 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1982 return VTBits-Tmp; 1983 1984 case ISD::Constant: { 1985 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1986 // If negative, return # leading ones. 1987 if (Val.isNegative()) 1988 return Val.countLeadingOnes(); 1989 1990 // Return # leading zeros. 1991 return Val.countLeadingZeros(); 1992 } 1993 1994 case ISD::SIGN_EXTEND: 1995 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1996 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1997 1998 case ISD::SIGN_EXTEND_INREG: 1999 // Max of the input and what this extends. 2000 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 2001 Tmp = VTBits-Tmp+1; 2002 2003 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2004 return std::max(Tmp, Tmp2); 2005 2006 case ISD::SRA: 2007 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2008 // SRA X, C -> adds C sign bits. 2009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2010 Tmp += C->getZExtValue(); 2011 if (Tmp > VTBits) Tmp = VTBits; 2012 } 2013 return Tmp; 2014 case ISD::SHL: 2015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2016 // shl destroys sign bits. 2017 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2018 if (C->getZExtValue() >= VTBits || // Bad shift. 2019 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 2020 return Tmp - C->getZExtValue(); 2021 } 2022 break; 2023 case ISD::AND: 2024 case ISD::OR: 2025 case ISD::XOR: // NOT is handled here. 2026 // Logical binary ops preserve the number of sign bits at the worst. 2027 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2028 if (Tmp != 1) { 2029 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2030 FirstAnswer = std::min(Tmp, Tmp2); 2031 // We computed what we know about the sign bits as our first 2032 // answer. Now proceed to the generic code that uses 2033 // ComputeMaskedBits, and pick whichever answer is better. 2034 } 2035 break; 2036 2037 case ISD::SELECT: 2038 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2039 if (Tmp == 1) return 1; // Early out. 2040 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2041 return std::min(Tmp, Tmp2); 2042 2043 case ISD::SADDO: 2044 case ISD::UADDO: 2045 case ISD::SSUBO: 2046 case ISD::USUBO: 2047 case ISD::SMULO: 2048 case ISD::UMULO: 2049 if (Op.getResNo() != 1) 2050 break; 2051 // The boolean result conforms to getBooleanContents. Fall through. 2052 case ISD::SETCC: 2053 // If setcc returns 0/-1, all bits are sign bits. 2054 if (TLI.getBooleanContents() == 2055 TargetLowering::ZeroOrNegativeOneBooleanContent) 2056 return VTBits; 2057 break; 2058 case ISD::ROTL: 2059 case ISD::ROTR: 2060 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 2061 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 2062 2063 // Handle rotate right by N like a rotate left by 32-N. 2064 if (Op.getOpcode() == ISD::ROTR) 2065 RotAmt = (VTBits-RotAmt) & (VTBits-1); 2066 2067 // If we aren't rotating out all of the known-in sign bits, return the 2068 // number that are left. This handles rotl(sext(x), 1) for example. 2069 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2070 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2071 } 2072 break; 2073 case ISD::ADD: 2074 // Add can have at most one carry bit. Thus we know that the output 2075 // is, at worst, one more bit than the inputs. 2076 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2077 if (Tmp == 1) return 1; // Early out. 2078 2079 // Special case decrementing a value (ADD X, -1): 2080 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 2081 if (CRHS->isAllOnesValue()) { 2082 APInt KnownZero, KnownOne; 2083 APInt Mask = APInt::getAllOnesValue(VTBits); 2084 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2085 2086 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2087 // sign bits set. 2088 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2089 return VTBits; 2090 2091 // If we are subtracting one from a positive number, there is no carry 2092 // out of the result. 2093 if (KnownZero.isNegative()) 2094 return Tmp; 2095 } 2096 2097 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2098 if (Tmp2 == 1) return 1; 2099 return std::min(Tmp, Tmp2)-1; 2100 break; 2101 2102 case ISD::SUB: 2103 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2104 if (Tmp2 == 1) return 1; 2105 2106 // Handle NEG. 2107 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2108 if (CLHS->isNullValue()) { 2109 APInt KnownZero, KnownOne; 2110 APInt Mask = APInt::getAllOnesValue(VTBits); 2111 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2112 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2113 // sign bits set. 2114 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2115 return VTBits; 2116 2117 // If the input is known to be positive (the sign bit is known clear), 2118 // the output of the NEG has the same number of sign bits as the input. 2119 if (KnownZero.isNegative()) 2120 return Tmp2; 2121 2122 // Otherwise, we treat this like a SUB. 2123 } 2124 2125 // Sub can have at most one carry bit. Thus we know that the output 2126 // is, at worst, one more bit than the inputs. 2127 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2128 if (Tmp == 1) return 1; // Early out. 2129 return std::min(Tmp, Tmp2)-1; 2130 break; 2131 case ISD::TRUNCATE: 2132 // FIXME: it's tricky to do anything useful for this, but it is an important 2133 // case for targets like X86. 2134 break; 2135 } 2136 2137 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2138 if (Op.getOpcode() == ISD::LOAD) { 2139 LoadSDNode *LD = cast<LoadSDNode>(Op); 2140 unsigned ExtType = LD->getExtensionType(); 2141 switch (ExtType) { 2142 default: break; 2143 case ISD::SEXTLOAD: // '17' bits known 2144 Tmp = LD->getMemoryVT().getSizeInBits(); 2145 return VTBits-Tmp+1; 2146 case ISD::ZEXTLOAD: // '16' bits known 2147 Tmp = LD->getMemoryVT().getSizeInBits(); 2148 return VTBits-Tmp; 2149 } 2150 } 2151 2152 // Allow the target to implement this method for its nodes. 2153 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2154 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2155 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2156 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2157 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2158 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2159 } 2160 2161 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2162 // use this information. 2163 APInt KnownZero, KnownOne; 2164 APInt Mask = APInt::getAllOnesValue(VTBits); 2165 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2166 2167 if (KnownZero.isNegative()) { // sign bit is 0 2168 Mask = KnownZero; 2169 } else if (KnownOne.isNegative()) { // sign bit is 1; 2170 Mask = KnownOne; 2171 } else { 2172 // Nothing known. 2173 return FirstAnswer; 2174 } 2175 2176 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2177 // the number of identical bits in the top of the input value. 2178 Mask = ~Mask; 2179 Mask <<= Mask.getBitWidth()-VTBits; 2180 // Return # leading zeros. We use 'min' here in case Val was zero before 2181 // shifting. We don't want to return '64' as for an i32 "0". 2182 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2183} 2184 2185 2186bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2187 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2188 if (!GA) return false; 2189 if (GA->getOffset() != 0) return false; 2190 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2191 if (!GV) return false; 2192 MachineModuleInfo *MMI = getMachineModuleInfo(); 2193 return MMI && MMI->hasDebugInfo(); 2194} 2195 2196 2197/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2198/// element of the result of the vector shuffle. 2199SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, 2200 unsigned i) { 2201 MVT VT = N->getValueType(0); 2202 DebugLoc dl = N->getDebugLoc(); 2203 if (N->getMaskElt(i) < 0) 2204 return getUNDEF(VT.getVectorElementType()); 2205 unsigned Index = N->getMaskElt(i); 2206 unsigned NumElems = VT.getVectorNumElements(); 2207 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2208 Index %= NumElems; 2209 2210 if (V.getOpcode() == ISD::BIT_CONVERT) { 2211 V = V.getOperand(0); 2212 MVT VVT = V.getValueType(); 2213 if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) 2214 return SDValue(); 2215 } 2216 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2217 return (Index == 0) ? V.getOperand(0) 2218 : getUNDEF(VT.getVectorElementType()); 2219 if (V.getOpcode() == ISD::BUILD_VECTOR) 2220 return V.getOperand(Index); 2221 if (const ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(V)) 2222 return getShuffleScalarElt(SVN, Index); 2223 return SDValue(); 2224} 2225 2226 2227/// getNode - Gets or creates the specified node. 2228/// 2229SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2230 FoldingSetNodeID ID; 2231 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2232 void *IP = 0; 2233 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2234 return SDValue(E, 0); 2235 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2236 new (N) SDNode(Opcode, DL, getVTList(VT)); 2237 CSEMap.InsertNode(N, IP); 2238 2239 AllNodes.push_back(N); 2240#ifndef NDEBUG 2241 VerifyNode(N); 2242#endif 2243 return SDValue(N, 0); 2244} 2245 2246SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2247 MVT VT, SDValue Operand) { 2248 // Constant fold unary operations with an integer constant operand. 2249 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2250 const APInt &Val = C->getAPIntValue(); 2251 unsigned BitWidth = VT.getSizeInBits(); 2252 switch (Opcode) { 2253 default: break; 2254 case ISD::SIGN_EXTEND: 2255 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2256 case ISD::ANY_EXTEND: 2257 case ISD::ZERO_EXTEND: 2258 case ISD::TRUNCATE: 2259 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2260 case ISD::UINT_TO_FP: 2261 case ISD::SINT_TO_FP: { 2262 const uint64_t zero[] = {0, 0}; 2263 // No compile time operations on this type. 2264 if (VT==MVT::ppcf128) 2265 break; 2266 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2267 (void)apf.convertFromAPInt(Val, 2268 Opcode==ISD::SINT_TO_FP, 2269 APFloat::rmNearestTiesToEven); 2270 return getConstantFP(apf, VT); 2271 } 2272 case ISD::BIT_CONVERT: 2273 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2274 return getConstantFP(Val.bitsToFloat(), VT); 2275 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2276 return getConstantFP(Val.bitsToDouble(), VT); 2277 break; 2278 case ISD::BSWAP: 2279 return getConstant(Val.byteSwap(), VT); 2280 case ISD::CTPOP: 2281 return getConstant(Val.countPopulation(), VT); 2282 case ISD::CTLZ: 2283 return getConstant(Val.countLeadingZeros(), VT); 2284 case ISD::CTTZ: 2285 return getConstant(Val.countTrailingZeros(), VT); 2286 } 2287 } 2288 2289 // Constant fold unary operations with a floating point constant operand. 2290 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2291 APFloat V = C->getValueAPF(); // make copy 2292 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2293 switch (Opcode) { 2294 case ISD::FNEG: 2295 V.changeSign(); 2296 return getConstantFP(V, VT); 2297 case ISD::FABS: 2298 V.clearSign(); 2299 return getConstantFP(V, VT); 2300 case ISD::FP_ROUND: 2301 case ISD::FP_EXTEND: { 2302 bool ignored; 2303 // This can return overflow, underflow, or inexact; we don't care. 2304 // FIXME need to be more flexible about rounding mode. 2305 (void)V.convert(*MVTToAPFloatSemantics(VT), 2306 APFloat::rmNearestTiesToEven, &ignored); 2307 return getConstantFP(V, VT); 2308 } 2309 case ISD::FP_TO_SINT: 2310 case ISD::FP_TO_UINT: { 2311 integerPart x[2]; 2312 bool ignored; 2313 assert(integerPartWidth >= 64); 2314 // FIXME need to be more flexible about rounding mode. 2315 APFloat::opStatus s = V.convertToInteger(x, VT.getSizeInBits(), 2316 Opcode==ISD::FP_TO_SINT, 2317 APFloat::rmTowardZero, &ignored); 2318 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2319 break; 2320 APInt api(VT.getSizeInBits(), 2, x); 2321 return getConstant(api, VT); 2322 } 2323 case ISD::BIT_CONVERT: 2324 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2325 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2326 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2327 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2328 break; 2329 } 2330 } 2331 } 2332 2333 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2334 switch (Opcode) { 2335 case ISD::TokenFactor: 2336 case ISD::MERGE_VALUES: 2337 case ISD::CONCAT_VECTORS: 2338 return Operand; // Factor, merge or concat of one node? No need. 2339 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2340 case ISD::FP_EXTEND: 2341 assert(VT.isFloatingPoint() && 2342 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2343 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2344 if (Operand.getOpcode() == ISD::UNDEF) 2345 return getUNDEF(VT); 2346 break; 2347 case ISD::SIGN_EXTEND: 2348 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2349 "Invalid SIGN_EXTEND!"); 2350 if (Operand.getValueType() == VT) return Operand; // noop extension 2351 assert(Operand.getValueType().bitsLT(VT) 2352 && "Invalid sext node, dst < src!"); 2353 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2354 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2355 break; 2356 case ISD::ZERO_EXTEND: 2357 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2358 "Invalid ZERO_EXTEND!"); 2359 if (Operand.getValueType() == VT) return Operand; // noop extension 2360 assert(Operand.getValueType().bitsLT(VT) 2361 && "Invalid zext node, dst < src!"); 2362 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2363 return getNode(ISD::ZERO_EXTEND, DL, VT, 2364 Operand.getNode()->getOperand(0)); 2365 break; 2366 case ISD::ANY_EXTEND: 2367 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2368 "Invalid ANY_EXTEND!"); 2369 if (Operand.getValueType() == VT) return Operand; // noop extension 2370 assert(Operand.getValueType().bitsLT(VT) 2371 && "Invalid anyext node, dst < src!"); 2372 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2373 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2374 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2375 break; 2376 case ISD::TRUNCATE: 2377 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2378 "Invalid TRUNCATE!"); 2379 if (Operand.getValueType() == VT) return Operand; // noop truncate 2380 assert(Operand.getValueType().bitsGT(VT) 2381 && "Invalid truncate node, src < dst!"); 2382 if (OpOpcode == ISD::TRUNCATE) 2383 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2384 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2385 OpOpcode == ISD::ANY_EXTEND) { 2386 // If the source is smaller than the dest, we still need an extend. 2387 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2388 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2389 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2390 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2391 else 2392 return Operand.getNode()->getOperand(0); 2393 } 2394 break; 2395 case ISD::BIT_CONVERT: 2396 // Basic sanity checking. 2397 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2398 && "Cannot BIT_CONVERT between types of different sizes!"); 2399 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2400 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2401 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2402 if (OpOpcode == ISD::UNDEF) 2403 return getUNDEF(VT); 2404 break; 2405 case ISD::SCALAR_TO_VECTOR: 2406 assert(VT.isVector() && !Operand.getValueType().isVector() && 2407 (VT.getVectorElementType() == Operand.getValueType() || 2408 (VT.getVectorElementType().isInteger() && 2409 Operand.getValueType().isInteger() && 2410 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && 2411 "Illegal SCALAR_TO_VECTOR node!"); 2412 if (OpOpcode == ISD::UNDEF) 2413 return getUNDEF(VT); 2414 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2415 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2416 isa<ConstantSDNode>(Operand.getOperand(1)) && 2417 Operand.getConstantOperandVal(1) == 0 && 2418 Operand.getOperand(0).getValueType() == VT) 2419 return Operand.getOperand(0); 2420 break; 2421 case ISD::FNEG: 2422 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2423 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2424 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2425 Operand.getNode()->getOperand(0)); 2426 if (OpOpcode == ISD::FNEG) // --X -> X 2427 return Operand.getNode()->getOperand(0); 2428 break; 2429 case ISD::FABS: 2430 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2431 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2432 break; 2433 } 2434 2435 SDNode *N; 2436 SDVTList VTs = getVTList(VT); 2437 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2438 FoldingSetNodeID ID; 2439 SDValue Ops[1] = { Operand }; 2440 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2441 void *IP = 0; 2442 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2443 return SDValue(E, 0); 2444 N = NodeAllocator.Allocate<UnarySDNode>(); 2445 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2446 CSEMap.InsertNode(N, IP); 2447 } else { 2448 N = NodeAllocator.Allocate<UnarySDNode>(); 2449 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2450 } 2451 2452 AllNodes.push_back(N); 2453#ifndef NDEBUG 2454 VerifyNode(N); 2455#endif 2456 return SDValue(N, 0); 2457} 2458 2459SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2460 MVT VT, 2461 ConstantSDNode *Cst1, 2462 ConstantSDNode *Cst2) { 2463 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2464 2465 switch (Opcode) { 2466 case ISD::ADD: return getConstant(C1 + C2, VT); 2467 case ISD::SUB: return getConstant(C1 - C2, VT); 2468 case ISD::MUL: return getConstant(C1 * C2, VT); 2469 case ISD::UDIV: 2470 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2471 break; 2472 case ISD::UREM: 2473 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2474 break; 2475 case ISD::SDIV: 2476 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2477 break; 2478 case ISD::SREM: 2479 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2480 break; 2481 case ISD::AND: return getConstant(C1 & C2, VT); 2482 case ISD::OR: return getConstant(C1 | C2, VT); 2483 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2484 case ISD::SHL: return getConstant(C1 << C2, VT); 2485 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2486 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2487 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2488 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2489 default: break; 2490 } 2491 2492 return SDValue(); 2493} 2494 2495SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2496 SDValue N1, SDValue N2) { 2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2498 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2499 switch (Opcode) { 2500 default: break; 2501 case ISD::TokenFactor: 2502 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2503 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2504 // Fold trivial token factors. 2505 if (N1.getOpcode() == ISD::EntryToken) return N2; 2506 if (N2.getOpcode() == ISD::EntryToken) return N1; 2507 if (N1 == N2) return N1; 2508 break; 2509 case ISD::CONCAT_VECTORS: 2510 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2511 // one big BUILD_VECTOR. 2512 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2513 N2.getOpcode() == ISD::BUILD_VECTOR) { 2514 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2515 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2516 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2517 } 2518 break; 2519 case ISD::AND: 2520 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2521 N1.getValueType() == VT && "Binary operator types must match!"); 2522 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2523 // worth handling here. 2524 if (N2C && N2C->isNullValue()) 2525 return N2; 2526 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2527 return N1; 2528 break; 2529 case ISD::OR: 2530 case ISD::XOR: 2531 case ISD::ADD: 2532 case ISD::SUB: 2533 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2534 N1.getValueType() == VT && "Binary operator types must match!"); 2535 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2536 // it's worth handling here. 2537 if (N2C && N2C->isNullValue()) 2538 return N1; 2539 break; 2540 case ISD::UDIV: 2541 case ISD::UREM: 2542 case ISD::MULHU: 2543 case ISD::MULHS: 2544 case ISD::MUL: 2545 case ISD::SDIV: 2546 case ISD::SREM: 2547 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2548 // fall through 2549 case ISD::FADD: 2550 case ISD::FSUB: 2551 case ISD::FMUL: 2552 case ISD::FDIV: 2553 case ISD::FREM: 2554 if (UnsafeFPMath) { 2555 if (Opcode == ISD::FADD) { 2556 // 0+x --> x 2557 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2558 if (CFP->getValueAPF().isZero()) 2559 return N2; 2560 // x+0 --> x 2561 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2562 if (CFP->getValueAPF().isZero()) 2563 return N1; 2564 } else if (Opcode == ISD::FSUB) { 2565 // x-0 --> x 2566 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2567 if (CFP->getValueAPF().isZero()) 2568 return N1; 2569 } 2570 } 2571 assert(N1.getValueType() == N2.getValueType() && 2572 N1.getValueType() == VT && "Binary operator types must match!"); 2573 break; 2574 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2575 assert(N1.getValueType() == VT && 2576 N1.getValueType().isFloatingPoint() && 2577 N2.getValueType().isFloatingPoint() && 2578 "Invalid FCOPYSIGN!"); 2579 break; 2580 case ISD::SHL: 2581 case ISD::SRA: 2582 case ISD::SRL: 2583 case ISD::ROTL: 2584 case ISD::ROTR: 2585 assert(VT == N1.getValueType() && 2586 "Shift operators return type must be the same as their first arg"); 2587 assert(VT.isInteger() && N2.getValueType().isInteger() && 2588 "Shifts only work on integers"); 2589 2590 // Always fold shifts of i1 values so the code generator doesn't need to 2591 // handle them. Since we know the size of the shift has to be less than the 2592 // size of the value, the shift/rotate count is guaranteed to be zero. 2593 if (VT == MVT::i1) 2594 return N1; 2595 break; 2596 case ISD::FP_ROUND_INREG: { 2597 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2598 assert(VT == N1.getValueType() && "Not an inreg round!"); 2599 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2600 "Cannot FP_ROUND_INREG integer types"); 2601 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2602 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2603 break; 2604 } 2605 case ISD::FP_ROUND: 2606 assert(VT.isFloatingPoint() && 2607 N1.getValueType().isFloatingPoint() && 2608 VT.bitsLE(N1.getValueType()) && 2609 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2610 if (N1.getValueType() == VT) return N1; // noop conversion. 2611 break; 2612 case ISD::AssertSext: 2613 case ISD::AssertZext: { 2614 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2615 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2616 assert(VT.isInteger() && EVT.isInteger() && 2617 "Cannot *_EXTEND_INREG FP types"); 2618 assert(EVT.bitsLE(VT) && "Not extending!"); 2619 if (VT == EVT) return N1; // noop assertion. 2620 break; 2621 } 2622 case ISD::SIGN_EXTEND_INREG: { 2623 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2624 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2625 assert(VT.isInteger() && EVT.isInteger() && 2626 "Cannot *_EXTEND_INREG FP types"); 2627 assert(EVT.bitsLE(VT) && "Not extending!"); 2628 if (EVT == VT) return N1; // Not actually extending 2629 2630 if (N1C) { 2631 APInt Val = N1C->getAPIntValue(); 2632 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2633 Val <<= Val.getBitWidth()-FromBits; 2634 Val = Val.ashr(Val.getBitWidth()-FromBits); 2635 return getConstant(Val, VT); 2636 } 2637 break; 2638 } 2639 case ISD::EXTRACT_VECTOR_ELT: 2640 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2641 if (N1.getOpcode() == ISD::UNDEF) 2642 return getUNDEF(VT); 2643 2644 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2645 // expanding copies of large vectors from registers. 2646 if (N2C && 2647 N1.getOpcode() == ISD::CONCAT_VECTORS && 2648 N1.getNumOperands() > 0) { 2649 unsigned Factor = 2650 N1.getOperand(0).getValueType().getVectorNumElements(); 2651 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2652 N1.getOperand(N2C->getZExtValue() / Factor), 2653 getConstant(N2C->getZExtValue() % Factor, 2654 N2.getValueType())); 2655 } 2656 2657 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2658 // expanding large vector constants. 2659 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { 2660 SDValue Elt = N1.getOperand(N2C->getZExtValue()); 2661 if (Elt.getValueType() != VT) { 2662 // If the vector element type is not legal, the BUILD_VECTOR operands 2663 // are promoted and implicitly truncated. Make that explicit here. 2664 assert(VT.isInteger() && Elt.getValueType().isInteger() && 2665 VT.bitsLE(Elt.getValueType()) && 2666 "Bad type for BUILD_VECTOR operand"); 2667 Elt = getNode(ISD::TRUNCATE, DL, VT, Elt); 2668 } 2669 return Elt; 2670 } 2671 2672 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2673 // operations are lowered to scalars. 2674 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2675 // If the indices are the same, return the inserted element. 2676 if (N1.getOperand(2) == N2) 2677 return N1.getOperand(1); 2678 // If the indices are known different, extract the element from 2679 // the original vector. 2680 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2681 isa<ConstantSDNode>(N2)) 2682 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2683 } 2684 break; 2685 case ISD::EXTRACT_ELEMENT: 2686 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2687 assert(!N1.getValueType().isVector() && !VT.isVector() && 2688 (N1.getValueType().isInteger() == VT.isInteger()) && 2689 "Wrong types for EXTRACT_ELEMENT!"); 2690 2691 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2692 // 64-bit integers into 32-bit parts. Instead of building the extract of 2693 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2694 if (N1.getOpcode() == ISD::BUILD_PAIR) 2695 return N1.getOperand(N2C->getZExtValue()); 2696 2697 // EXTRACT_ELEMENT of a constant int is also very common. 2698 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2699 unsigned ElementSize = VT.getSizeInBits(); 2700 unsigned Shift = ElementSize * N2C->getZExtValue(); 2701 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2702 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2703 } 2704 break; 2705 case ISD::EXTRACT_SUBVECTOR: 2706 if (N1.getValueType() == VT) // Trivial extraction. 2707 return N1; 2708 break; 2709 } 2710 2711 if (N1C) { 2712 if (N2C) { 2713 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2714 if (SV.getNode()) return SV; 2715 } else { // Cannonicalize constant to RHS if commutative 2716 if (isCommutativeBinOp(Opcode)) { 2717 std::swap(N1C, N2C); 2718 std::swap(N1, N2); 2719 } 2720 } 2721 } 2722 2723 // Constant fold FP operations. 2724 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2725 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2726 if (N1CFP) { 2727 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2728 // Cannonicalize constant to RHS if commutative 2729 std::swap(N1CFP, N2CFP); 2730 std::swap(N1, N2); 2731 } else if (N2CFP && VT != MVT::ppcf128) { 2732 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2733 APFloat::opStatus s; 2734 switch (Opcode) { 2735 case ISD::FADD: 2736 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2737 if (s != APFloat::opInvalidOp) 2738 return getConstantFP(V1, VT); 2739 break; 2740 case ISD::FSUB: 2741 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2742 if (s!=APFloat::opInvalidOp) 2743 return getConstantFP(V1, VT); 2744 break; 2745 case ISD::FMUL: 2746 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2747 if (s!=APFloat::opInvalidOp) 2748 return getConstantFP(V1, VT); 2749 break; 2750 case ISD::FDIV: 2751 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2752 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2753 return getConstantFP(V1, VT); 2754 break; 2755 case ISD::FREM : 2756 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2757 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2758 return getConstantFP(V1, VT); 2759 break; 2760 case ISD::FCOPYSIGN: 2761 V1.copySign(V2); 2762 return getConstantFP(V1, VT); 2763 default: break; 2764 } 2765 } 2766 } 2767 2768 // Canonicalize an UNDEF to the RHS, even over a constant. 2769 if (N1.getOpcode() == ISD::UNDEF) { 2770 if (isCommutativeBinOp(Opcode)) { 2771 std::swap(N1, N2); 2772 } else { 2773 switch (Opcode) { 2774 case ISD::FP_ROUND_INREG: 2775 case ISD::SIGN_EXTEND_INREG: 2776 case ISD::SUB: 2777 case ISD::FSUB: 2778 case ISD::FDIV: 2779 case ISD::FREM: 2780 case ISD::SRA: 2781 return N1; // fold op(undef, arg2) -> undef 2782 case ISD::UDIV: 2783 case ISD::SDIV: 2784 case ISD::UREM: 2785 case ISD::SREM: 2786 case ISD::SRL: 2787 case ISD::SHL: 2788 if (!VT.isVector()) 2789 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2790 // For vectors, we can't easily build an all zero vector, just return 2791 // the LHS. 2792 return N2; 2793 } 2794 } 2795 } 2796 2797 // Fold a bunch of operators when the RHS is undef. 2798 if (N2.getOpcode() == ISD::UNDEF) { 2799 switch (Opcode) { 2800 case ISD::XOR: 2801 if (N1.getOpcode() == ISD::UNDEF) 2802 // Handle undef ^ undef -> 0 special case. This is a common 2803 // idiom (misuse). 2804 return getConstant(0, VT); 2805 // fallthrough 2806 case ISD::ADD: 2807 case ISD::ADDC: 2808 case ISD::ADDE: 2809 case ISD::SUB: 2810 case ISD::FADD: 2811 case ISD::FSUB: 2812 case ISD::FMUL: 2813 case ISD::FDIV: 2814 case ISD::FREM: 2815 case ISD::UDIV: 2816 case ISD::SDIV: 2817 case ISD::UREM: 2818 case ISD::SREM: 2819 return N2; // fold op(arg1, undef) -> undef 2820 case ISD::MUL: 2821 case ISD::AND: 2822 case ISD::SRL: 2823 case ISD::SHL: 2824 if (!VT.isVector()) 2825 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2826 // For vectors, we can't easily build an all zero vector, just return 2827 // the LHS. 2828 return N1; 2829 case ISD::OR: 2830 if (!VT.isVector()) 2831 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2832 // For vectors, we can't easily build an all one vector, just return 2833 // the LHS. 2834 return N1; 2835 case ISD::SRA: 2836 return N1; 2837 } 2838 } 2839 2840 // Memoize this node if possible. 2841 SDNode *N; 2842 SDVTList VTs = getVTList(VT); 2843 if (VT != MVT::Flag) { 2844 SDValue Ops[] = { N1, N2 }; 2845 FoldingSetNodeID ID; 2846 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2847 void *IP = 0; 2848 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2849 return SDValue(E, 0); 2850 N = NodeAllocator.Allocate<BinarySDNode>(); 2851 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2852 CSEMap.InsertNode(N, IP); 2853 } else { 2854 N = NodeAllocator.Allocate<BinarySDNode>(); 2855 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2856 } 2857 2858 AllNodes.push_back(N); 2859#ifndef NDEBUG 2860 VerifyNode(N); 2861#endif 2862 return SDValue(N, 0); 2863} 2864 2865SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2866 SDValue N1, SDValue N2, SDValue N3) { 2867 // Perform various simplifications. 2868 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2869 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2870 switch (Opcode) { 2871 case ISD::CONCAT_VECTORS: 2872 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2873 // one big BUILD_VECTOR. 2874 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2875 N2.getOpcode() == ISD::BUILD_VECTOR && 2876 N3.getOpcode() == ISD::BUILD_VECTOR) { 2877 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2878 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2879 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2880 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2881 } 2882 break; 2883 case ISD::SETCC: { 2884 // Use FoldSetCC to simplify SETCC's. 2885 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2886 if (Simp.getNode()) return Simp; 2887 break; 2888 } 2889 case ISD::SELECT: 2890 if (N1C) { 2891 if (N1C->getZExtValue()) 2892 return N2; // select true, X, Y -> X 2893 else 2894 return N3; // select false, X, Y -> Y 2895 } 2896 2897 if (N2 == N3) return N2; // select C, X, X -> X 2898 break; 2899 case ISD::BRCOND: 2900 if (N2C) { 2901 if (N2C->getZExtValue()) // Unconditional branch 2902 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2903 else 2904 return N1; // Never-taken branch 2905 } 2906 break; 2907 case ISD::VECTOR_SHUFFLE: 2908 assert(0 && "should use getVectorShuffle constructor!"); 2909 break; 2910 case ISD::BIT_CONVERT: 2911 // Fold bit_convert nodes from a type to themselves. 2912 if (N1.getValueType() == VT) 2913 return N1; 2914 break; 2915 } 2916 2917 // Memoize node if it doesn't produce a flag. 2918 SDNode *N; 2919 SDVTList VTs = getVTList(VT); 2920 if (VT != MVT::Flag) { 2921 SDValue Ops[] = { N1, N2, N3 }; 2922 FoldingSetNodeID ID; 2923 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2924 void *IP = 0; 2925 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2926 return SDValue(E, 0); 2927 N = NodeAllocator.Allocate<TernarySDNode>(); 2928 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2929 CSEMap.InsertNode(N, IP); 2930 } else { 2931 N = NodeAllocator.Allocate<TernarySDNode>(); 2932 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2933 } 2934 AllNodes.push_back(N); 2935#ifndef NDEBUG 2936 VerifyNode(N); 2937#endif 2938 return SDValue(N, 0); 2939} 2940 2941SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2942 SDValue N1, SDValue N2, SDValue N3, 2943 SDValue N4) { 2944 SDValue Ops[] = { N1, N2, N3, N4 }; 2945 return getNode(Opcode, DL, VT, Ops, 4); 2946} 2947 2948SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2949 SDValue N1, SDValue N2, SDValue N3, 2950 SDValue N4, SDValue N5) { 2951 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2952 return getNode(Opcode, DL, VT, Ops, 5); 2953} 2954 2955/// getMemsetValue - Vectorized representation of the memset value 2956/// operand. 2957static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2958 DebugLoc dl) { 2959 unsigned NumBits = VT.isVector() ? 2960 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2961 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2962 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2963 unsigned Shift = 8; 2964 for (unsigned i = NumBits; i > 8; i >>= 1) { 2965 Val = (Val << Shift) | Val; 2966 Shift <<= 1; 2967 } 2968 if (VT.isInteger()) 2969 return DAG.getConstant(Val, VT); 2970 return DAG.getConstantFP(APFloat(Val), VT); 2971 } 2972 2973 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2974 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2975 unsigned Shift = 8; 2976 for (unsigned i = NumBits; i > 8; i >>= 1) { 2977 Value = DAG.getNode(ISD::OR, dl, VT, 2978 DAG.getNode(ISD::SHL, dl, VT, Value, 2979 DAG.getConstant(Shift, 2980 TLI.getShiftAmountTy())), 2981 Value); 2982 Shift <<= 1; 2983 } 2984 2985 return Value; 2986} 2987 2988/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2989/// used when a memcpy is turned into a memset when the source is a constant 2990/// string ptr. 2991static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2992 const TargetLowering &TLI, 2993 std::string &Str, unsigned Offset) { 2994 // Handle vector with all elements zero. 2995 if (Str.empty()) { 2996 if (VT.isInteger()) 2997 return DAG.getConstant(0, VT); 2998 unsigned NumElts = VT.getVectorNumElements(); 2999 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 3000 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3001 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 3002 } 3003 3004 assert(!VT.isVector() && "Can't handle vector type here!"); 3005 unsigned NumBits = VT.getSizeInBits(); 3006 unsigned MSB = NumBits / 8; 3007 uint64_t Val = 0; 3008 if (TLI.isLittleEndian()) 3009 Offset = Offset + MSB - 1; 3010 for (unsigned i = 0; i != MSB; ++i) { 3011 Val = (Val << 8) | (unsigned char)Str[Offset]; 3012 Offset += TLI.isLittleEndian() ? -1 : 1; 3013 } 3014 return DAG.getConstant(Val, VT); 3015} 3016 3017/// getMemBasePlusOffset - Returns base and offset node for the 3018/// 3019static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 3020 SelectionDAG &DAG) { 3021 MVT VT = Base.getValueType(); 3022 return DAG.getNode(ISD::ADD, Base.getDebugLoc(), 3023 VT, Base, DAG.getConstant(Offset, VT)); 3024} 3025 3026/// isMemSrcFromString - Returns true if memcpy source is a string constant. 3027/// 3028static bool isMemSrcFromString(SDValue Src, std::string &Str) { 3029 unsigned SrcDelta = 0; 3030 GlobalAddressSDNode *G = NULL; 3031 if (Src.getOpcode() == ISD::GlobalAddress) 3032 G = cast<GlobalAddressSDNode>(Src); 3033 else if (Src.getOpcode() == ISD::ADD && 3034 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 3035 Src.getOperand(1).getOpcode() == ISD::Constant) { 3036 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 3037 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 3038 } 3039 if (!G) 3040 return false; 3041 3042 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 3043 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 3044 return true; 3045 3046 return false; 3047} 3048 3049/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3050/// to replace the memset / memcpy is below the threshold. It also returns the 3051/// types of the sequence of memory ops to perform memset / memcpy. 3052static 3053bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 3054 SDValue Dst, SDValue Src, 3055 unsigned Limit, uint64_t Size, unsigned &Align, 3056 std::string &Str, bool &isSrcStr, 3057 SelectionDAG &DAG, 3058 const TargetLowering &TLI) { 3059 isSrcStr = isMemSrcFromString(Src, Str); 3060 bool isSrcConst = isa<ConstantSDNode>(Src); 3061 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 3062 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 3063 if (VT != MVT::iAny) { 3064 unsigned NewAlign = (unsigned) 3065 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 3066 // If source is a string constant, this will require an unaligned load. 3067 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3068 if (Dst.getOpcode() != ISD::FrameIndex) { 3069 // Can't change destination alignment. It requires a unaligned store. 3070 if (AllowUnalign) 3071 VT = MVT::iAny; 3072 } else { 3073 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3074 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3075 if (MFI->isFixedObjectIndex(FI)) { 3076 // Can't change destination alignment. It requires a unaligned store. 3077 if (AllowUnalign) 3078 VT = MVT::iAny; 3079 } else { 3080 // Give the stack frame object a larger alignment if needed. 3081 if (MFI->getObjectAlignment(FI) < NewAlign) 3082 MFI->setObjectAlignment(FI, NewAlign); 3083 Align = NewAlign; 3084 } 3085 } 3086 } 3087 } 3088 3089 if (VT == MVT::iAny) { 3090 if (AllowUnalign) { 3091 VT = MVT::i64; 3092 } else { 3093 switch (Align & 7) { 3094 case 0: VT = MVT::i64; break; 3095 case 4: VT = MVT::i32; break; 3096 case 2: VT = MVT::i16; break; 3097 default: VT = MVT::i8; break; 3098 } 3099 } 3100 3101 MVT LVT = MVT::i64; 3102 while (!TLI.isTypeLegal(LVT)) 3103 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3104 assert(LVT.isInteger()); 3105 3106 if (VT.bitsGT(LVT)) 3107 VT = LVT; 3108 } 3109 3110 unsigned NumMemOps = 0; 3111 while (Size != 0) { 3112 unsigned VTSize = VT.getSizeInBits() / 8; 3113 while (VTSize > Size) { 3114 // For now, only use non-vector load / store's for the left-over pieces. 3115 if (VT.isVector()) { 3116 VT = MVT::i64; 3117 while (!TLI.isTypeLegal(VT)) 3118 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3119 VTSize = VT.getSizeInBits() / 8; 3120 } else { 3121 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3122 VTSize >>= 1; 3123 } 3124 } 3125 3126 if (++NumMemOps > Limit) 3127 return false; 3128 MemOps.push_back(VT); 3129 Size -= VTSize; 3130 } 3131 3132 return true; 3133} 3134 3135static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3136 SDValue Chain, SDValue Dst, 3137 SDValue Src, uint64_t Size, 3138 unsigned Align, bool AlwaysInline, 3139 const Value *DstSV, uint64_t DstSVOff, 3140 const Value *SrcSV, uint64_t SrcSVOff){ 3141 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3142 3143 // Expand memcpy to a series of load and store ops if the size operand falls 3144 // below a certain threshold. 3145 std::vector<MVT> MemOps; 3146 uint64_t Limit = -1ULL; 3147 if (!AlwaysInline) 3148 Limit = TLI.getMaxStoresPerMemcpy(); 3149 unsigned DstAlign = Align; // Destination alignment can change. 3150 std::string Str; 3151 bool CopyFromStr; 3152 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3153 Str, CopyFromStr, DAG, TLI)) 3154 return SDValue(); 3155 3156 3157 bool isZeroStr = CopyFromStr && Str.empty(); 3158 SmallVector<SDValue, 8> OutChains; 3159 unsigned NumMemOps = MemOps.size(); 3160 uint64_t SrcOff = 0, DstOff = 0; 3161 for (unsigned i = 0; i < NumMemOps; i++) { 3162 MVT VT = MemOps[i]; 3163 unsigned VTSize = VT.getSizeInBits() / 8; 3164 SDValue Value, Store; 3165 3166 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3167 // It's unlikely a store of a vector immediate can be done in a single 3168 // instruction. It would require a load from a constantpool first. 3169 // We also handle store a vector with all zero's. 3170 // FIXME: Handle other cases where store of vector immediate is done in 3171 // a single instruction. 3172 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3173 Store = DAG.getStore(Chain, dl, Value, 3174 getMemBasePlusOffset(Dst, DstOff, DAG), 3175 DstSV, DstSVOff + DstOff, false, DstAlign); 3176 } else { 3177 Value = DAG.getLoad(VT, dl, Chain, 3178 getMemBasePlusOffset(Src, SrcOff, DAG), 3179 SrcSV, SrcSVOff + SrcOff, false, Align); 3180 Store = DAG.getStore(Chain, dl, Value, 3181 getMemBasePlusOffset(Dst, DstOff, DAG), 3182 DstSV, DstSVOff + DstOff, false, DstAlign); 3183 } 3184 OutChains.push_back(Store); 3185 SrcOff += VTSize; 3186 DstOff += VTSize; 3187 } 3188 3189 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3190 &OutChains[0], OutChains.size()); 3191} 3192 3193static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3194 SDValue Chain, SDValue Dst, 3195 SDValue Src, uint64_t Size, 3196 unsigned Align, bool AlwaysInline, 3197 const Value *DstSV, uint64_t DstSVOff, 3198 const Value *SrcSV, uint64_t SrcSVOff){ 3199 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3200 3201 // Expand memmove to a series of load and store ops if the size operand falls 3202 // below a certain threshold. 3203 std::vector<MVT> MemOps; 3204 uint64_t Limit = -1ULL; 3205 if (!AlwaysInline) 3206 Limit = TLI.getMaxStoresPerMemmove(); 3207 unsigned DstAlign = Align; // Destination alignment can change. 3208 std::string Str; 3209 bool CopyFromStr; 3210 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3211 Str, CopyFromStr, DAG, TLI)) 3212 return SDValue(); 3213 3214 uint64_t SrcOff = 0, DstOff = 0; 3215 3216 SmallVector<SDValue, 8> LoadValues; 3217 SmallVector<SDValue, 8> LoadChains; 3218 SmallVector<SDValue, 8> OutChains; 3219 unsigned NumMemOps = MemOps.size(); 3220 for (unsigned i = 0; i < NumMemOps; i++) { 3221 MVT VT = MemOps[i]; 3222 unsigned VTSize = VT.getSizeInBits() / 8; 3223 SDValue Value, Store; 3224 3225 Value = DAG.getLoad(VT, dl, Chain, 3226 getMemBasePlusOffset(Src, SrcOff, DAG), 3227 SrcSV, SrcSVOff + SrcOff, false, Align); 3228 LoadValues.push_back(Value); 3229 LoadChains.push_back(Value.getValue(1)); 3230 SrcOff += VTSize; 3231 } 3232 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3233 &LoadChains[0], LoadChains.size()); 3234 OutChains.clear(); 3235 for (unsigned i = 0; i < NumMemOps; i++) { 3236 MVT VT = MemOps[i]; 3237 unsigned VTSize = VT.getSizeInBits() / 8; 3238 SDValue Value, Store; 3239 3240 Store = DAG.getStore(Chain, dl, LoadValues[i], 3241 getMemBasePlusOffset(Dst, DstOff, DAG), 3242 DstSV, DstSVOff + DstOff, false, DstAlign); 3243 OutChains.push_back(Store); 3244 DstOff += VTSize; 3245 } 3246 3247 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3248 &OutChains[0], OutChains.size()); 3249} 3250 3251static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3252 SDValue Chain, SDValue Dst, 3253 SDValue Src, uint64_t Size, 3254 unsigned Align, 3255 const Value *DstSV, uint64_t DstSVOff) { 3256 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3257 3258 // Expand memset to a series of load/store ops if the size operand 3259 // falls below a certain threshold. 3260 std::vector<MVT> MemOps; 3261 std::string Str; 3262 bool CopyFromStr; 3263 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3264 Size, Align, Str, CopyFromStr, DAG, TLI)) 3265 return SDValue(); 3266 3267 SmallVector<SDValue, 8> OutChains; 3268 uint64_t DstOff = 0; 3269 3270 unsigned NumMemOps = MemOps.size(); 3271 for (unsigned i = 0; i < NumMemOps; i++) { 3272 MVT VT = MemOps[i]; 3273 unsigned VTSize = VT.getSizeInBits() / 8; 3274 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3275 SDValue Store = DAG.getStore(Chain, dl, Value, 3276 getMemBasePlusOffset(Dst, DstOff, DAG), 3277 DstSV, DstSVOff + DstOff); 3278 OutChains.push_back(Store); 3279 DstOff += VTSize; 3280 } 3281 3282 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3283 &OutChains[0], OutChains.size()); 3284} 3285 3286SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3287 SDValue Src, SDValue Size, 3288 unsigned Align, bool AlwaysInline, 3289 const Value *DstSV, uint64_t DstSVOff, 3290 const Value *SrcSV, uint64_t SrcSVOff) { 3291 3292 // Check to see if we should lower the memcpy to loads and stores first. 3293 // For cases within the target-specified limits, this is the best choice. 3294 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3295 if (ConstantSize) { 3296 // Memcpy with size zero? Just return the original chain. 3297 if (ConstantSize->isNullValue()) 3298 return Chain; 3299 3300 SDValue Result = 3301 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3302 ConstantSize->getZExtValue(), 3303 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3304 if (Result.getNode()) 3305 return Result; 3306 } 3307 3308 // Then check to see if we should lower the memcpy with target-specific 3309 // code. If the target chooses to do this, this is the next best. 3310 SDValue Result = 3311 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3312 AlwaysInline, 3313 DstSV, DstSVOff, SrcSV, SrcSVOff); 3314 if (Result.getNode()) 3315 return Result; 3316 3317 // If we really need inline code and the target declined to provide it, 3318 // use a (potentially long) sequence of loads and stores. 3319 if (AlwaysInline) { 3320 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3321 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3322 ConstantSize->getZExtValue(), Align, true, 3323 DstSV, DstSVOff, SrcSV, SrcSVOff); 3324 } 3325 3326 // Emit a library call. 3327 TargetLowering::ArgListTy Args; 3328 TargetLowering::ArgListEntry Entry; 3329 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3330 Entry.Node = Dst; Args.push_back(Entry); 3331 Entry.Node = Src; Args.push_back(Entry); 3332 Entry.Node = Size; Args.push_back(Entry); 3333 // FIXME: pass in DebugLoc 3334 std::pair<SDValue,SDValue> CallResult = 3335 TLI.LowerCallTo(Chain, Type::VoidTy, 3336 false, false, false, false, CallingConv::C, false, 3337 getExternalSymbol("memcpy", TLI.getPointerTy()), 3338 Args, *this, dl); 3339 return CallResult.second; 3340} 3341 3342SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3343 SDValue Src, SDValue Size, 3344 unsigned Align, 3345 const Value *DstSV, uint64_t DstSVOff, 3346 const Value *SrcSV, uint64_t SrcSVOff) { 3347 3348 // Check to see if we should lower the memmove to loads and stores first. 3349 // For cases within the target-specified limits, this is the best choice. 3350 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3351 if (ConstantSize) { 3352 // Memmove with size zero? Just return the original chain. 3353 if (ConstantSize->isNullValue()) 3354 return Chain; 3355 3356 SDValue Result = 3357 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3358 ConstantSize->getZExtValue(), 3359 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3360 if (Result.getNode()) 3361 return Result; 3362 } 3363 3364 // Then check to see if we should lower the memmove with target-specific 3365 // code. If the target chooses to do this, this is the next best. 3366 SDValue Result = 3367 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3368 DstSV, DstSVOff, SrcSV, SrcSVOff); 3369 if (Result.getNode()) 3370 return Result; 3371 3372 // Emit a library call. 3373 TargetLowering::ArgListTy Args; 3374 TargetLowering::ArgListEntry Entry; 3375 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3376 Entry.Node = Dst; Args.push_back(Entry); 3377 Entry.Node = Src; Args.push_back(Entry); 3378 Entry.Node = Size; Args.push_back(Entry); 3379 // FIXME: pass in DebugLoc 3380 std::pair<SDValue,SDValue> CallResult = 3381 TLI.LowerCallTo(Chain, Type::VoidTy, 3382 false, false, false, false, CallingConv::C, false, 3383 getExternalSymbol("memmove", TLI.getPointerTy()), 3384 Args, *this, dl); 3385 return CallResult.second; 3386} 3387 3388SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3389 SDValue Src, SDValue Size, 3390 unsigned Align, 3391 const Value *DstSV, uint64_t DstSVOff) { 3392 3393 // Check to see if we should lower the memset to stores first. 3394 // For cases within the target-specified limits, this is the best choice. 3395 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3396 if (ConstantSize) { 3397 // Memset with size zero? Just return the original chain. 3398 if (ConstantSize->isNullValue()) 3399 return Chain; 3400 3401 SDValue Result = 3402 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3403 Align, DstSV, DstSVOff); 3404 if (Result.getNode()) 3405 return Result; 3406 } 3407 3408 // Then check to see if we should lower the memset with target-specific 3409 // code. If the target chooses to do this, this is the next best. 3410 SDValue Result = 3411 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3412 DstSV, DstSVOff); 3413 if (Result.getNode()) 3414 return Result; 3415 3416 // Emit a library call. 3417 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3418 TargetLowering::ArgListTy Args; 3419 TargetLowering::ArgListEntry Entry; 3420 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3421 Args.push_back(Entry); 3422 // Extend or truncate the argument to be an i32 value for the call. 3423 if (Src.getValueType().bitsGT(MVT::i32)) 3424 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3425 else 3426 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3427 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3428 Args.push_back(Entry); 3429 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3430 Args.push_back(Entry); 3431 // FIXME: pass in DebugLoc 3432 std::pair<SDValue,SDValue> CallResult = 3433 TLI.LowerCallTo(Chain, Type::VoidTy, 3434 false, false, false, false, CallingConv::C, false, 3435 getExternalSymbol("memset", TLI.getPointerTy()), 3436 Args, *this, dl); 3437 return CallResult.second; 3438} 3439 3440SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3441 SDValue Chain, 3442 SDValue Ptr, SDValue Cmp, 3443 SDValue Swp, const Value* PtrVal, 3444 unsigned Alignment) { 3445 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3446 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3447 3448 MVT VT = Cmp.getValueType(); 3449 3450 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3451 Alignment = getMVTAlignment(MemVT); 3452 3453 SDVTList VTs = getVTList(VT, MVT::Other); 3454 FoldingSetNodeID ID; 3455 ID.AddInteger(MemVT.getRawBits()); 3456 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3457 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3458 void* IP = 0; 3459 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3460 return SDValue(E, 0); 3461 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3462 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3463 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3464 CSEMap.InsertNode(N, IP); 3465 AllNodes.push_back(N); 3466 return SDValue(N, 0); 3467} 3468 3469SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3470 SDValue Chain, 3471 SDValue Ptr, SDValue Val, 3472 const Value* PtrVal, 3473 unsigned Alignment) { 3474 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3475 Opcode == ISD::ATOMIC_LOAD_SUB || 3476 Opcode == ISD::ATOMIC_LOAD_AND || 3477 Opcode == ISD::ATOMIC_LOAD_OR || 3478 Opcode == ISD::ATOMIC_LOAD_XOR || 3479 Opcode == ISD::ATOMIC_LOAD_NAND || 3480 Opcode == ISD::ATOMIC_LOAD_MIN || 3481 Opcode == ISD::ATOMIC_LOAD_MAX || 3482 Opcode == ISD::ATOMIC_LOAD_UMIN || 3483 Opcode == ISD::ATOMIC_LOAD_UMAX || 3484 Opcode == ISD::ATOMIC_SWAP) && 3485 "Invalid Atomic Op"); 3486 3487 MVT VT = Val.getValueType(); 3488 3489 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3490 Alignment = getMVTAlignment(MemVT); 3491 3492 SDVTList VTs = getVTList(VT, MVT::Other); 3493 FoldingSetNodeID ID; 3494 ID.AddInteger(MemVT.getRawBits()); 3495 SDValue Ops[] = {Chain, Ptr, Val}; 3496 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3497 void* IP = 0; 3498 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3499 return SDValue(E, 0); 3500 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3501 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3502 Chain, Ptr, Val, PtrVal, Alignment); 3503 CSEMap.InsertNode(N, IP); 3504 AllNodes.push_back(N); 3505 return SDValue(N, 0); 3506} 3507 3508/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3509/// Allowed to return something different (and simpler) if Simplify is true. 3510SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3511 DebugLoc dl) { 3512 if (NumOps == 1) 3513 return Ops[0]; 3514 3515 SmallVector<MVT, 4> VTs; 3516 VTs.reserve(NumOps); 3517 for (unsigned i = 0; i < NumOps; ++i) 3518 VTs.push_back(Ops[i].getValueType()); 3519 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3520 Ops, NumOps); 3521} 3522 3523SDValue 3524SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3525 const MVT *VTs, unsigned NumVTs, 3526 const SDValue *Ops, unsigned NumOps, 3527 MVT MemVT, const Value *srcValue, int SVOff, 3528 unsigned Align, bool Vol, 3529 bool ReadMem, bool WriteMem) { 3530 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3531 MemVT, srcValue, SVOff, Align, Vol, 3532 ReadMem, WriteMem); 3533} 3534 3535SDValue 3536SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3537 const SDValue *Ops, unsigned NumOps, 3538 MVT MemVT, const Value *srcValue, int SVOff, 3539 unsigned Align, bool Vol, 3540 bool ReadMem, bool WriteMem) { 3541 // Memoize the node unless it returns a flag. 3542 MemIntrinsicSDNode *N; 3543 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3544 FoldingSetNodeID ID; 3545 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3546 void *IP = 0; 3547 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3548 return SDValue(E, 0); 3549 3550 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3551 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3552 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3553 CSEMap.InsertNode(N, IP); 3554 } else { 3555 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3556 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3557 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3558 } 3559 AllNodes.push_back(N); 3560 return SDValue(N, 0); 3561} 3562 3563SDValue 3564SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3565 bool IsTailCall, bool IsInreg, SDVTList VTs, 3566 const SDValue *Operands, unsigned NumOperands) { 3567 // Do not include isTailCall in the folding set profile. 3568 FoldingSetNodeID ID; 3569 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3570 ID.AddInteger(CallingConv); 3571 ID.AddInteger(IsVarArgs); 3572 void *IP = 0; 3573 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3574 // Instead of including isTailCall in the folding set, we just 3575 // set the flag of the existing node. 3576 if (!IsTailCall) 3577 cast<CallSDNode>(E)->setNotTailCall(); 3578 return SDValue(E, 0); 3579 } 3580 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3581 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3582 VTs, Operands, NumOperands); 3583 CSEMap.InsertNode(N, IP); 3584 AllNodes.push_back(N); 3585 return SDValue(N, 0); 3586} 3587 3588SDValue 3589SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3590 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3591 SDValue Ptr, SDValue Offset, 3592 const Value *SV, int SVOffset, MVT EVT, 3593 bool isVolatile, unsigned Alignment) { 3594 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3595 Alignment = getMVTAlignment(VT); 3596 3597 if (VT == EVT) { 3598 ExtType = ISD::NON_EXTLOAD; 3599 } else if (ExtType == ISD::NON_EXTLOAD) { 3600 assert(VT == EVT && "Non-extending load from different memory type!"); 3601 } else { 3602 // Extending load. 3603 if (VT.isVector()) 3604 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3605 "Invalid vector extload!"); 3606 else 3607 assert(EVT.bitsLT(VT) && 3608 "Should only be an extending load, not truncating!"); 3609 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3610 "Cannot sign/zero extend a FP/Vector load!"); 3611 assert(VT.isInteger() == EVT.isInteger() && 3612 "Cannot convert from FP to Int or Int -> FP!"); 3613 } 3614 3615 bool Indexed = AM != ISD::UNINDEXED; 3616 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3617 "Unindexed load with an offset!"); 3618 3619 SDVTList VTs = Indexed ? 3620 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3621 SDValue Ops[] = { Chain, Ptr, Offset }; 3622 FoldingSetNodeID ID; 3623 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3624 ID.AddInteger(EVT.getRawBits()); 3625 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3626 void *IP = 0; 3627 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3628 return SDValue(E, 0); 3629 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3630 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3631 Alignment, isVolatile); 3632 CSEMap.InsertNode(N, IP); 3633 AllNodes.push_back(N); 3634 return SDValue(N, 0); 3635} 3636 3637SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3638 SDValue Chain, SDValue Ptr, 3639 const Value *SV, int SVOffset, 3640 bool isVolatile, unsigned Alignment) { 3641 SDValue Undef = getUNDEF(Ptr.getValueType()); 3642 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3643 SV, SVOffset, VT, isVolatile, Alignment); 3644} 3645 3646SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3647 SDValue Chain, SDValue Ptr, 3648 const Value *SV, 3649 int SVOffset, MVT EVT, 3650 bool isVolatile, unsigned Alignment) { 3651 SDValue Undef = getUNDEF(Ptr.getValueType()); 3652 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3653 SV, SVOffset, EVT, isVolatile, Alignment); 3654} 3655 3656SDValue 3657SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3658 SDValue Offset, ISD::MemIndexedMode AM) { 3659 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3660 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3661 "Load is already a indexed load!"); 3662 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3663 LD->getChain(), Base, Offset, LD->getSrcValue(), 3664 LD->getSrcValueOffset(), LD->getMemoryVT(), 3665 LD->isVolatile(), LD->getAlignment()); 3666} 3667 3668SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3669 SDValue Ptr, const Value *SV, int SVOffset, 3670 bool isVolatile, unsigned Alignment) { 3671 MVT VT = Val.getValueType(); 3672 3673 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3674 Alignment = getMVTAlignment(VT); 3675 3676 SDVTList VTs = getVTList(MVT::Other); 3677 SDValue Undef = getUNDEF(Ptr.getValueType()); 3678 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3679 FoldingSetNodeID ID; 3680 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3681 ID.AddInteger(VT.getRawBits()); 3682 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3683 isVolatile, Alignment)); 3684 void *IP = 0; 3685 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3686 return SDValue(E, 0); 3687 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3688 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3689 VT, SV, SVOffset, Alignment, isVolatile); 3690 CSEMap.InsertNode(N, IP); 3691 AllNodes.push_back(N); 3692 return SDValue(N, 0); 3693} 3694 3695SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3696 SDValue Ptr, const Value *SV, 3697 int SVOffset, MVT SVT, 3698 bool isVolatile, unsigned Alignment) { 3699 MVT VT = Val.getValueType(); 3700 3701 if (VT == SVT) 3702 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3703 3704 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3705 assert(VT.isInteger() == SVT.isInteger() && 3706 "Can't do FP-INT conversion!"); 3707 3708 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3709 Alignment = getMVTAlignment(VT); 3710 3711 SDVTList VTs = getVTList(MVT::Other); 3712 SDValue Undef = getUNDEF(Ptr.getValueType()); 3713 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3714 FoldingSetNodeID ID; 3715 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3716 ID.AddInteger(SVT.getRawBits()); 3717 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3718 isVolatile, Alignment)); 3719 void *IP = 0; 3720 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3721 return SDValue(E, 0); 3722 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3723 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3724 SVT, SV, SVOffset, Alignment, isVolatile); 3725 CSEMap.InsertNode(N, IP); 3726 AllNodes.push_back(N); 3727 return SDValue(N, 0); 3728} 3729 3730SDValue 3731SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3732 SDValue Offset, ISD::MemIndexedMode AM) { 3733 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3734 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3735 "Store is already a indexed store!"); 3736 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3737 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3738 FoldingSetNodeID ID; 3739 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3740 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3741 ID.AddInteger(ST->getRawSubclassData()); 3742 void *IP = 0; 3743 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3744 return SDValue(E, 0); 3745 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3746 new (N) StoreSDNode(Ops, dl, VTs, AM, 3747 ST->isTruncatingStore(), ST->getMemoryVT(), 3748 ST->getSrcValue(), ST->getSrcValueOffset(), 3749 ST->getAlignment(), ST->isVolatile()); 3750 CSEMap.InsertNode(N, IP); 3751 AllNodes.push_back(N); 3752 return SDValue(N, 0); 3753} 3754 3755SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3756 SDValue Chain, SDValue Ptr, 3757 SDValue SV) { 3758 SDValue Ops[] = { Chain, Ptr, SV }; 3759 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3760} 3761 3762SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3763 const SDUse *Ops, unsigned NumOps) { 3764 switch (NumOps) { 3765 case 0: return getNode(Opcode, DL, VT); 3766 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3767 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3768 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3769 default: break; 3770 } 3771 3772 // Copy from an SDUse array into an SDValue array for use with 3773 // the regular getNode logic. 3774 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3775 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3776} 3777 3778SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3779 const SDValue *Ops, unsigned NumOps) { 3780 switch (NumOps) { 3781 case 0: return getNode(Opcode, DL, VT); 3782 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3783 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3784 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3785 default: break; 3786 } 3787 3788 switch (Opcode) { 3789 default: break; 3790 case ISD::SELECT_CC: { 3791 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3792 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3793 "LHS and RHS of condition must have same type!"); 3794 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3795 "True and False arms of SelectCC must have same type!"); 3796 assert(Ops[2].getValueType() == VT && 3797 "select_cc node must be of same type as true and false value!"); 3798 break; 3799 } 3800 case ISD::BR_CC: { 3801 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3802 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3803 "LHS/RHS of comparison should match types!"); 3804 break; 3805 } 3806 } 3807 3808 // Memoize nodes. 3809 SDNode *N; 3810 SDVTList VTs = getVTList(VT); 3811 3812 if (VT != MVT::Flag) { 3813 FoldingSetNodeID ID; 3814 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3815 void *IP = 0; 3816 3817 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3818 return SDValue(E, 0); 3819 3820 N = NodeAllocator.Allocate<SDNode>(); 3821 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3822 CSEMap.InsertNode(N, IP); 3823 } else { 3824 N = NodeAllocator.Allocate<SDNode>(); 3825 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3826 } 3827 3828 AllNodes.push_back(N); 3829#ifndef NDEBUG 3830 VerifyNode(N); 3831#endif 3832 return SDValue(N, 0); 3833} 3834 3835SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3836 const std::vector<MVT> &ResultTys, 3837 const SDValue *Ops, unsigned NumOps) { 3838 return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), 3839 Ops, NumOps); 3840} 3841 3842SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3843 const MVT *VTs, unsigned NumVTs, 3844 const SDValue *Ops, unsigned NumOps) { 3845 if (NumVTs == 1) 3846 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3847 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3848} 3849 3850SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3851 const SDValue *Ops, unsigned NumOps) { 3852 if (VTList.NumVTs == 1) 3853 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3854 3855 switch (Opcode) { 3856 // FIXME: figure out how to safely handle things like 3857 // int foo(int x) { return 1 << (x & 255); } 3858 // int bar() { return foo(256); } 3859#if 0 3860 case ISD::SRA_PARTS: 3861 case ISD::SRL_PARTS: 3862 case ISD::SHL_PARTS: 3863 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3864 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3865 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3866 else if (N3.getOpcode() == ISD::AND) 3867 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3868 // If the and is only masking out bits that cannot effect the shift, 3869 // eliminate the and. 3870 unsigned NumBits = VT.getSizeInBits()*2; 3871 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3872 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3873 } 3874 break; 3875#endif 3876 } 3877 3878 // Memoize the node unless it returns a flag. 3879 SDNode *N; 3880 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3881 FoldingSetNodeID ID; 3882 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3883 void *IP = 0; 3884 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3885 return SDValue(E, 0); 3886 if (NumOps == 1) { 3887 N = NodeAllocator.Allocate<UnarySDNode>(); 3888 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3889 } else if (NumOps == 2) { 3890 N = NodeAllocator.Allocate<BinarySDNode>(); 3891 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3892 } else if (NumOps == 3) { 3893 N = NodeAllocator.Allocate<TernarySDNode>(); 3894 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3895 } else { 3896 N = NodeAllocator.Allocate<SDNode>(); 3897 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3898 } 3899 CSEMap.InsertNode(N, IP); 3900 } else { 3901 if (NumOps == 1) { 3902 N = NodeAllocator.Allocate<UnarySDNode>(); 3903 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3904 } else if (NumOps == 2) { 3905 N = NodeAllocator.Allocate<BinarySDNode>(); 3906 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3907 } else if (NumOps == 3) { 3908 N = NodeAllocator.Allocate<TernarySDNode>(); 3909 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3910 } else { 3911 N = NodeAllocator.Allocate<SDNode>(); 3912 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3913 } 3914 } 3915 AllNodes.push_back(N); 3916#ifndef NDEBUG 3917 VerifyNode(N); 3918#endif 3919 return SDValue(N, 0); 3920} 3921 3922SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3923 return getNode(Opcode, DL, VTList, 0, 0); 3924} 3925 3926SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3927 SDValue N1) { 3928 SDValue Ops[] = { N1 }; 3929 return getNode(Opcode, DL, VTList, Ops, 1); 3930} 3931 3932SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3933 SDValue N1, SDValue N2) { 3934 SDValue Ops[] = { N1, N2 }; 3935 return getNode(Opcode, DL, VTList, Ops, 2); 3936} 3937 3938SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3939 SDValue N1, SDValue N2, SDValue N3) { 3940 SDValue Ops[] = { N1, N2, N3 }; 3941 return getNode(Opcode, DL, VTList, Ops, 3); 3942} 3943 3944SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3945 SDValue N1, SDValue N2, SDValue N3, 3946 SDValue N4) { 3947 SDValue Ops[] = { N1, N2, N3, N4 }; 3948 return getNode(Opcode, DL, VTList, Ops, 4); 3949} 3950 3951SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3952 SDValue N1, SDValue N2, SDValue N3, 3953 SDValue N4, SDValue N5) { 3954 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3955 return getNode(Opcode, DL, VTList, Ops, 5); 3956} 3957 3958SDVTList SelectionDAG::getVTList(MVT VT) { 3959 return makeVTList(SDNode::getValueTypeList(VT), 1); 3960} 3961 3962SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3963 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3964 E = VTList.rend(); I != E; ++I) 3965 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3966 return *I; 3967 3968 MVT *Array = Allocator.Allocate<MVT>(2); 3969 Array[0] = VT1; 3970 Array[1] = VT2; 3971 SDVTList Result = makeVTList(Array, 2); 3972 VTList.push_back(Result); 3973 return Result; 3974} 3975 3976SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3977 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3978 E = VTList.rend(); I != E; ++I) 3979 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3980 I->VTs[2] == VT3) 3981 return *I; 3982 3983 MVT *Array = Allocator.Allocate<MVT>(3); 3984 Array[0] = VT1; 3985 Array[1] = VT2; 3986 Array[2] = VT3; 3987 SDVTList Result = makeVTList(Array, 3); 3988 VTList.push_back(Result); 3989 return Result; 3990} 3991 3992SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3993 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3994 E = VTList.rend(); I != E; ++I) 3995 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3996 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3997 return *I; 3998 3999 MVT *Array = Allocator.Allocate<MVT>(3); 4000 Array[0] = VT1; 4001 Array[1] = VT2; 4002 Array[2] = VT3; 4003 Array[3] = VT4; 4004 SDVTList Result = makeVTList(Array, 4); 4005 VTList.push_back(Result); 4006 return Result; 4007} 4008 4009SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 4010 switch (NumVTs) { 4011 case 0: assert(0 && "Cannot have nodes without results!"); 4012 case 1: return getVTList(VTs[0]); 4013 case 2: return getVTList(VTs[0], VTs[1]); 4014 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 4015 default: break; 4016 } 4017 4018 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 4019 E = VTList.rend(); I != E; ++I) { 4020 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 4021 continue; 4022 4023 bool NoMatch = false; 4024 for (unsigned i = 2; i != NumVTs; ++i) 4025 if (VTs[i] != I->VTs[i]) { 4026 NoMatch = true; 4027 break; 4028 } 4029 if (!NoMatch) 4030 return *I; 4031 } 4032 4033 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 4034 std::copy(VTs, VTs+NumVTs, Array); 4035 SDVTList Result = makeVTList(Array, NumVTs); 4036 VTList.push_back(Result); 4037 return Result; 4038} 4039 4040 4041/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4042/// specified operands. If the resultant node already exists in the DAG, 4043/// this does not modify the specified node, instead it returns the node that 4044/// already exists. If the resultant node does not exist in the DAG, the 4045/// input node is returned. As a degenerate case, if you specify the same 4046/// input operands as the node already has, the input node is returned. 4047SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4048 SDNode *N = InN.getNode(); 4049 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4050 4051 // Check to see if there is no change. 4052 if (Op == N->getOperand(0)) return InN; 4053 4054 // See if the modified node already exists. 4055 void *InsertPos = 0; 4056 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4057 return SDValue(Existing, InN.getResNo()); 4058 4059 // Nope it doesn't. Remove the node from its current place in the maps. 4060 if (InsertPos) 4061 if (!RemoveNodeFromCSEMaps(N)) 4062 InsertPos = 0; 4063 4064 // Now we update the operands. 4065 N->OperandList[0].set(Op); 4066 4067 // If this gets put into a CSE map, add it. 4068 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4069 return InN; 4070} 4071 4072SDValue SelectionDAG:: 4073UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4074 SDNode *N = InN.getNode(); 4075 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4076 4077 // Check to see if there is no change. 4078 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4079 return InN; // No operands changed, just return the input node. 4080 4081 // See if the modified node already exists. 4082 void *InsertPos = 0; 4083 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4084 return SDValue(Existing, InN.getResNo()); 4085 4086 // Nope it doesn't. Remove the node from its current place in the maps. 4087 if (InsertPos) 4088 if (!RemoveNodeFromCSEMaps(N)) 4089 InsertPos = 0; 4090 4091 // Now we update the operands. 4092 if (N->OperandList[0] != Op1) 4093 N->OperandList[0].set(Op1); 4094 if (N->OperandList[1] != Op2) 4095 N->OperandList[1].set(Op2); 4096 4097 // If this gets put into a CSE map, add it. 4098 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4099 return InN; 4100} 4101 4102SDValue SelectionDAG:: 4103UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4104 SDValue Ops[] = { Op1, Op2, Op3 }; 4105 return UpdateNodeOperands(N, Ops, 3); 4106} 4107 4108SDValue SelectionDAG:: 4109UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4110 SDValue Op3, SDValue Op4) { 4111 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4112 return UpdateNodeOperands(N, Ops, 4); 4113} 4114 4115SDValue SelectionDAG:: 4116UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4117 SDValue Op3, SDValue Op4, SDValue Op5) { 4118 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4119 return UpdateNodeOperands(N, Ops, 5); 4120} 4121 4122SDValue SelectionDAG:: 4123UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4124 SDNode *N = InN.getNode(); 4125 assert(N->getNumOperands() == NumOps && 4126 "Update with wrong number of operands"); 4127 4128 // Check to see if there is no change. 4129 bool AnyChange = false; 4130 for (unsigned i = 0; i != NumOps; ++i) { 4131 if (Ops[i] != N->getOperand(i)) { 4132 AnyChange = true; 4133 break; 4134 } 4135 } 4136 4137 // No operands changed, just return the input node. 4138 if (!AnyChange) return InN; 4139 4140 // See if the modified node already exists. 4141 void *InsertPos = 0; 4142 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4143 return SDValue(Existing, InN.getResNo()); 4144 4145 // Nope it doesn't. Remove the node from its current place in the maps. 4146 if (InsertPos) 4147 if (!RemoveNodeFromCSEMaps(N)) 4148 InsertPos = 0; 4149 4150 // Now we update the operands. 4151 for (unsigned i = 0; i != NumOps; ++i) 4152 if (N->OperandList[i] != Ops[i]) 4153 N->OperandList[i].set(Ops[i]); 4154 4155 // If this gets put into a CSE map, add it. 4156 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4157 return InN; 4158} 4159 4160/// DropOperands - Release the operands and set this node to have 4161/// zero operands. 4162void SDNode::DropOperands() { 4163 // Unlike the code in MorphNodeTo that does this, we don't need to 4164 // watch for dead nodes here. 4165 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4166 SDUse &Use = *I++; 4167 Use.set(SDValue()); 4168 } 4169} 4170 4171/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4172/// machine opcode. 4173/// 4174SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4175 MVT VT) { 4176 SDVTList VTs = getVTList(VT); 4177 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4178} 4179 4180SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4181 MVT VT, SDValue Op1) { 4182 SDVTList VTs = getVTList(VT); 4183 SDValue Ops[] = { Op1 }; 4184 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4185} 4186 4187SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4188 MVT VT, SDValue Op1, 4189 SDValue Op2) { 4190 SDVTList VTs = getVTList(VT); 4191 SDValue Ops[] = { Op1, Op2 }; 4192 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4193} 4194 4195SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4196 MVT VT, SDValue Op1, 4197 SDValue Op2, SDValue Op3) { 4198 SDVTList VTs = getVTList(VT); 4199 SDValue Ops[] = { Op1, Op2, Op3 }; 4200 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4201} 4202 4203SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4204 MVT VT, const SDValue *Ops, 4205 unsigned NumOps) { 4206 SDVTList VTs = getVTList(VT); 4207 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4208} 4209 4210SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4211 MVT VT1, MVT VT2, const SDValue *Ops, 4212 unsigned NumOps) { 4213 SDVTList VTs = getVTList(VT1, VT2); 4214 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4215} 4216 4217SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4218 MVT VT1, MVT VT2) { 4219 SDVTList VTs = getVTList(VT1, VT2); 4220 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4221} 4222 4223SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4224 MVT VT1, MVT VT2, MVT VT3, 4225 const SDValue *Ops, unsigned NumOps) { 4226 SDVTList VTs = getVTList(VT1, VT2, VT3); 4227 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4228} 4229 4230SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4231 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4232 const SDValue *Ops, unsigned NumOps) { 4233 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4234 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4235} 4236 4237SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4238 MVT VT1, MVT VT2, 4239 SDValue Op1) { 4240 SDVTList VTs = getVTList(VT1, VT2); 4241 SDValue Ops[] = { Op1 }; 4242 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4243} 4244 4245SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4246 MVT VT1, MVT VT2, 4247 SDValue Op1, SDValue Op2) { 4248 SDVTList VTs = getVTList(VT1, VT2); 4249 SDValue Ops[] = { Op1, Op2 }; 4250 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4251} 4252 4253SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4254 MVT VT1, MVT VT2, 4255 SDValue Op1, SDValue Op2, 4256 SDValue Op3) { 4257 SDVTList VTs = getVTList(VT1, VT2); 4258 SDValue Ops[] = { Op1, Op2, Op3 }; 4259 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4260} 4261 4262SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4263 MVT VT1, MVT VT2, MVT VT3, 4264 SDValue Op1, SDValue Op2, 4265 SDValue Op3) { 4266 SDVTList VTs = getVTList(VT1, VT2, VT3); 4267 SDValue Ops[] = { Op1, Op2, Op3 }; 4268 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4269} 4270 4271SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4272 SDVTList VTs, const SDValue *Ops, 4273 unsigned NumOps) { 4274 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4275} 4276 4277SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4278 MVT VT) { 4279 SDVTList VTs = getVTList(VT); 4280 return MorphNodeTo(N, Opc, VTs, 0, 0); 4281} 4282 4283SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4284 MVT VT, SDValue Op1) { 4285 SDVTList VTs = getVTList(VT); 4286 SDValue Ops[] = { Op1 }; 4287 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4288} 4289 4290SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4291 MVT VT, SDValue Op1, 4292 SDValue Op2) { 4293 SDVTList VTs = getVTList(VT); 4294 SDValue Ops[] = { Op1, Op2 }; 4295 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4296} 4297 4298SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4299 MVT VT, SDValue Op1, 4300 SDValue Op2, SDValue Op3) { 4301 SDVTList VTs = getVTList(VT); 4302 SDValue Ops[] = { Op1, Op2, Op3 }; 4303 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4304} 4305 4306SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4307 MVT VT, const SDValue *Ops, 4308 unsigned NumOps) { 4309 SDVTList VTs = getVTList(VT); 4310 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4311} 4312 4313SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4314 MVT VT1, MVT VT2, const SDValue *Ops, 4315 unsigned NumOps) { 4316 SDVTList VTs = getVTList(VT1, VT2); 4317 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4318} 4319 4320SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4321 MVT VT1, MVT VT2) { 4322 SDVTList VTs = getVTList(VT1, VT2); 4323 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4324} 4325 4326SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4327 MVT VT1, MVT VT2, MVT VT3, 4328 const SDValue *Ops, unsigned NumOps) { 4329 SDVTList VTs = getVTList(VT1, VT2, VT3); 4330 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4331} 4332 4333SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4334 MVT VT1, MVT VT2, 4335 SDValue Op1) { 4336 SDVTList VTs = getVTList(VT1, VT2); 4337 SDValue Ops[] = { Op1 }; 4338 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4339} 4340 4341SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4342 MVT VT1, MVT VT2, 4343 SDValue Op1, SDValue Op2) { 4344 SDVTList VTs = getVTList(VT1, VT2); 4345 SDValue Ops[] = { Op1, Op2 }; 4346 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4347} 4348 4349SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4350 MVT VT1, MVT VT2, 4351 SDValue Op1, SDValue Op2, 4352 SDValue Op3) { 4353 SDVTList VTs = getVTList(VT1, VT2); 4354 SDValue Ops[] = { Op1, Op2, Op3 }; 4355 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4356} 4357 4358/// MorphNodeTo - These *mutate* the specified node to have the specified 4359/// return type, opcode, and operands. 4360/// 4361/// Note that MorphNodeTo returns the resultant node. If there is already a 4362/// node of the specified opcode and operands, it returns that node instead of 4363/// the current one. Note that the DebugLoc need not be the same. 4364/// 4365/// Using MorphNodeTo is faster than creating a new node and swapping it in 4366/// with ReplaceAllUsesWith both because it often avoids allocating a new 4367/// node, and because it doesn't require CSE recalculation for any of 4368/// the node's users. 4369/// 4370SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4371 SDVTList VTs, const SDValue *Ops, 4372 unsigned NumOps) { 4373 // If an identical node already exists, use it. 4374 void *IP = 0; 4375 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4376 FoldingSetNodeID ID; 4377 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4378 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4379 return ON; 4380 } 4381 4382 if (!RemoveNodeFromCSEMaps(N)) 4383 IP = 0; 4384 4385 // Start the morphing. 4386 N->NodeType = Opc; 4387 N->ValueList = VTs.VTs; 4388 N->NumValues = VTs.NumVTs; 4389 4390 // Clear the operands list, updating used nodes to remove this from their 4391 // use list. Keep track of any operands that become dead as a result. 4392 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4393 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4394 SDUse &Use = *I++; 4395 SDNode *Used = Use.getNode(); 4396 Use.set(SDValue()); 4397 if (Used->use_empty()) 4398 DeadNodeSet.insert(Used); 4399 } 4400 4401 // If NumOps is larger than the # of operands we currently have, reallocate 4402 // the operand list. 4403 if (NumOps > N->NumOperands) { 4404 if (N->OperandsNeedDelete) 4405 delete[] N->OperandList; 4406 4407 if (N->isMachineOpcode()) { 4408 // We're creating a final node that will live unmorphed for the 4409 // remainder of the current SelectionDAG iteration, so we can allocate 4410 // the operands directly out of a pool with no recycling metadata. 4411 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4412 N->OperandsNeedDelete = false; 4413 } else { 4414 N->OperandList = new SDUse[NumOps]; 4415 N->OperandsNeedDelete = true; 4416 } 4417 } 4418 4419 // Assign the new operands. 4420 N->NumOperands = NumOps; 4421 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4422 N->OperandList[i].setUser(N); 4423 N->OperandList[i].setInitial(Ops[i]); 4424 } 4425 4426 // Delete any nodes that are still dead after adding the uses for the 4427 // new operands. 4428 SmallVector<SDNode *, 16> DeadNodes; 4429 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4430 E = DeadNodeSet.end(); I != E; ++I) 4431 if ((*I)->use_empty()) 4432 DeadNodes.push_back(*I); 4433 RemoveDeadNodes(DeadNodes); 4434 4435 if (IP) 4436 CSEMap.InsertNode(N, IP); // Memoize the new node. 4437 return N; 4438} 4439 4440 4441/// getTargetNode - These are used for target selectors to create a new node 4442/// with specified return type(s), target opcode, and operands. 4443/// 4444/// Note that getTargetNode returns the resultant node. If there is already a 4445/// node of the specified opcode and operands, it returns that node instead of 4446/// the current one. 4447SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4448 return getNode(~Opcode, dl, VT).getNode(); 4449} 4450 4451SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4452 SDValue Op1) { 4453 return getNode(~Opcode, dl, VT, Op1).getNode(); 4454} 4455 4456SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4457 SDValue Op1, SDValue Op2) { 4458 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4459} 4460 4461SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4462 SDValue Op1, SDValue Op2, 4463 SDValue Op3) { 4464 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4465} 4466 4467SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4468 const SDValue *Ops, unsigned NumOps) { 4469 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4470} 4471 4472SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4473 MVT VT1, MVT VT2) { 4474 SDVTList VTs = getVTList(VT1, VT2); 4475 SDValue Op; 4476 return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); 4477} 4478 4479SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4480 MVT VT2, SDValue Op1) { 4481 SDVTList VTs = getVTList(VT1, VT2); 4482 return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); 4483} 4484 4485SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4486 MVT VT2, SDValue Op1, 4487 SDValue Op2) { 4488 SDVTList VTs = getVTList(VT1, VT2); 4489 SDValue Ops[] = { Op1, Op2 }; 4490 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4491} 4492 4493SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4494 MVT VT2, SDValue Op1, 4495 SDValue Op2, SDValue Op3) { 4496 SDVTList VTs = getVTList(VT1, VT2); 4497 SDValue Ops[] = { Op1, Op2, Op3 }; 4498 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4499} 4500 4501SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4502 MVT VT1, MVT VT2, 4503 const SDValue *Ops, unsigned NumOps) { 4504 SDVTList VTs = getVTList(VT1, VT2); 4505 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4506} 4507 4508SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4509 MVT VT1, MVT VT2, MVT VT3, 4510 SDValue Op1, SDValue Op2) { 4511 SDVTList VTs = getVTList(VT1, VT2, VT3); 4512 SDValue Ops[] = { Op1, Op2 }; 4513 return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); 4514} 4515 4516SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4517 MVT VT1, MVT VT2, MVT VT3, 4518 SDValue Op1, SDValue Op2, 4519 SDValue Op3) { 4520 SDVTList VTs = getVTList(VT1, VT2, VT3); 4521 SDValue Ops[] = { Op1, Op2, Op3 }; 4522 return getNode(~Opcode, dl, VTs, Ops, 3).getNode(); 4523} 4524 4525SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4526 MVT VT1, MVT VT2, MVT VT3, 4527 const SDValue *Ops, unsigned NumOps) { 4528 SDVTList VTs = getVTList(VT1, VT2, VT3); 4529 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4530} 4531 4532SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4533 MVT VT2, MVT VT3, MVT VT4, 4534 const SDValue *Ops, unsigned NumOps) { 4535 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4536 return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); 4537} 4538 4539SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4540 const std::vector<MVT> &ResultTys, 4541 const SDValue *Ops, unsigned NumOps) { 4542 return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); 4543} 4544 4545/// getNodeIfExists - Get the specified node if it's already available, or 4546/// else return NULL. 4547SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4548 const SDValue *Ops, unsigned NumOps) { 4549 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4550 FoldingSetNodeID ID; 4551 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4552 void *IP = 0; 4553 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4554 return E; 4555 } 4556 return NULL; 4557} 4558 4559/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4560/// This can cause recursive merging of nodes in the DAG. 4561/// 4562/// This version assumes From has a single result value. 4563/// 4564void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4565 DAGUpdateListener *UpdateListener) { 4566 SDNode *From = FromN.getNode(); 4567 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4568 "Cannot replace with this method!"); 4569 assert(From != To.getNode() && "Cannot replace uses of with self"); 4570 4571 // Iterate over all the existing uses of From. New uses will be added 4572 // to the beginning of the use list, which we avoid visiting. 4573 // This specifically avoids visiting uses of From that arise while the 4574 // replacement is happening, because any such uses would be the result 4575 // of CSE: If an existing node looks like From after one of its operands 4576 // is replaced by To, we don't want to replace of all its users with To 4577 // too. See PR3018 for more info. 4578 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4579 while (UI != UE) { 4580 SDNode *User = *UI; 4581 4582 // This node is about to morph, remove its old self from the CSE maps. 4583 RemoveNodeFromCSEMaps(User); 4584 4585 // A user can appear in a use list multiple times, and when this 4586 // happens the uses are usually next to each other in the list. 4587 // To help reduce the number of CSE recomputations, process all 4588 // the uses of this user that we can find this way. 4589 do { 4590 SDUse &Use = UI.getUse(); 4591 ++UI; 4592 Use.set(To); 4593 } while (UI != UE && *UI == User); 4594 4595 // Now that we have modified User, add it back to the CSE maps. If it 4596 // already exists there, recursively merge the results together. 4597 AddModifiedNodeToCSEMaps(User, UpdateListener); 4598 } 4599} 4600 4601/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4602/// This can cause recursive merging of nodes in the DAG. 4603/// 4604/// This version assumes that for each value of From, there is a 4605/// corresponding value in To in the same position with the same type. 4606/// 4607void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4608 DAGUpdateListener *UpdateListener) { 4609#ifndef NDEBUG 4610 for (unsigned i = 0, e = From->getNumValues(); i != e; ++i) 4611 assert((!From->hasAnyUseOfValue(i) || 4612 From->getValueType(i) == To->getValueType(i)) && 4613 "Cannot use this version of ReplaceAllUsesWith!"); 4614#endif 4615 4616 // Handle the trivial case. 4617 if (From == To) 4618 return; 4619 4620 // Iterate over just the existing users of From. See the comments in 4621 // the ReplaceAllUsesWith above. 4622 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4623 while (UI != UE) { 4624 SDNode *User = *UI; 4625 4626 // This node is about to morph, remove its old self from the CSE maps. 4627 RemoveNodeFromCSEMaps(User); 4628 4629 // A user can appear in a use list multiple times, and when this 4630 // happens the uses are usually next to each other in the list. 4631 // To help reduce the number of CSE recomputations, process all 4632 // the uses of this user that we can find this way. 4633 do { 4634 SDUse &Use = UI.getUse(); 4635 ++UI; 4636 Use.setNode(To); 4637 } while (UI != UE && *UI == User); 4638 4639 // Now that we have modified User, add it back to the CSE maps. If it 4640 // already exists there, recursively merge the results together. 4641 AddModifiedNodeToCSEMaps(User, UpdateListener); 4642 } 4643} 4644 4645/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4646/// This can cause recursive merging of nodes in the DAG. 4647/// 4648/// This version can replace From with any result values. To must match the 4649/// number and types of values returned by From. 4650void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4651 const SDValue *To, 4652 DAGUpdateListener *UpdateListener) { 4653 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4654 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4655 4656 // Iterate over just the existing users of From. See the comments in 4657 // the ReplaceAllUsesWith above. 4658 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4659 while (UI != UE) { 4660 SDNode *User = *UI; 4661 4662 // This node is about to morph, remove its old self from the CSE maps. 4663 RemoveNodeFromCSEMaps(User); 4664 4665 // A user can appear in a use list multiple times, and when this 4666 // happens the uses are usually next to each other in the list. 4667 // To help reduce the number of CSE recomputations, process all 4668 // the uses of this user that we can find this way. 4669 do { 4670 SDUse &Use = UI.getUse(); 4671 const SDValue &ToOp = To[Use.getResNo()]; 4672 ++UI; 4673 Use.set(ToOp); 4674 } while (UI != UE && *UI == User); 4675 4676 // Now that we have modified User, add it back to the CSE maps. If it 4677 // already exists there, recursively merge the results together. 4678 AddModifiedNodeToCSEMaps(User, UpdateListener); 4679 } 4680} 4681 4682/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4683/// uses of other values produced by From.getNode() alone. The Deleted 4684/// vector is handled the same way as for ReplaceAllUsesWith. 4685void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4686 DAGUpdateListener *UpdateListener){ 4687 // Handle the really simple, really trivial case efficiently. 4688 if (From == To) return; 4689 4690 // Handle the simple, trivial, case efficiently. 4691 if (From.getNode()->getNumValues() == 1) { 4692 ReplaceAllUsesWith(From, To, UpdateListener); 4693 return; 4694 } 4695 4696 // Iterate over just the existing users of From. See the comments in 4697 // the ReplaceAllUsesWith above. 4698 SDNode::use_iterator UI = From.getNode()->use_begin(), 4699 UE = From.getNode()->use_end(); 4700 while (UI != UE) { 4701 SDNode *User = *UI; 4702 bool UserRemovedFromCSEMaps = false; 4703 4704 // A user can appear in a use list multiple times, and when this 4705 // happens the uses are usually next to each other in the list. 4706 // To help reduce the number of CSE recomputations, process all 4707 // the uses of this user that we can find this way. 4708 do { 4709 SDUse &Use = UI.getUse(); 4710 4711 // Skip uses of different values from the same node. 4712 if (Use.getResNo() != From.getResNo()) { 4713 ++UI; 4714 continue; 4715 } 4716 4717 // If this node hasn't been modified yet, it's still in the CSE maps, 4718 // so remove its old self from the CSE maps. 4719 if (!UserRemovedFromCSEMaps) { 4720 RemoveNodeFromCSEMaps(User); 4721 UserRemovedFromCSEMaps = true; 4722 } 4723 4724 ++UI; 4725 Use.set(To); 4726 } while (UI != UE && *UI == User); 4727 4728 // We are iterating over all uses of the From node, so if a use 4729 // doesn't use the specific value, no changes are made. 4730 if (!UserRemovedFromCSEMaps) 4731 continue; 4732 4733 // Now that we have modified User, add it back to the CSE maps. If it 4734 // already exists there, recursively merge the results together. 4735 AddModifiedNodeToCSEMaps(User, UpdateListener); 4736 } 4737} 4738 4739namespace { 4740 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4741 /// to record information about a use. 4742 struct UseMemo { 4743 SDNode *User; 4744 unsigned Index; 4745 SDUse *Use; 4746 }; 4747 4748 /// operator< - Sort Memos by User. 4749 bool operator<(const UseMemo &L, const UseMemo &R) { 4750 return (intptr_t)L.User < (intptr_t)R.User; 4751 } 4752} 4753 4754/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4755/// uses of other values produced by From.getNode() alone. The same value 4756/// may appear in both the From and To list. The Deleted vector is 4757/// handled the same way as for ReplaceAllUsesWith. 4758void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4759 const SDValue *To, 4760 unsigned Num, 4761 DAGUpdateListener *UpdateListener){ 4762 // Handle the simple, trivial case efficiently. 4763 if (Num == 1) 4764 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4765 4766 // Read up all the uses and make records of them. This helps 4767 // processing new uses that are introduced during the 4768 // replacement process. 4769 SmallVector<UseMemo, 4> Uses; 4770 for (unsigned i = 0; i != Num; ++i) { 4771 unsigned FromResNo = From[i].getResNo(); 4772 SDNode *FromNode = From[i].getNode(); 4773 for (SDNode::use_iterator UI = FromNode->use_begin(), 4774 E = FromNode->use_end(); UI != E; ++UI) { 4775 SDUse &Use = UI.getUse(); 4776 if (Use.getResNo() == FromResNo) { 4777 UseMemo Memo = { *UI, i, &Use }; 4778 Uses.push_back(Memo); 4779 } 4780 } 4781 } 4782 4783 // Sort the uses, so that all the uses from a given User are together. 4784 std::sort(Uses.begin(), Uses.end()); 4785 4786 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4787 UseIndex != UseIndexEnd; ) { 4788 // We know that this user uses some value of From. If it is the right 4789 // value, update it. 4790 SDNode *User = Uses[UseIndex].User; 4791 4792 // This node is about to morph, remove its old self from the CSE maps. 4793 RemoveNodeFromCSEMaps(User); 4794 4795 // The Uses array is sorted, so all the uses for a given User 4796 // are next to each other in the list. 4797 // To help reduce the number of CSE recomputations, process all 4798 // the uses of this user that we can find this way. 4799 do { 4800 unsigned i = Uses[UseIndex].Index; 4801 SDUse &Use = *Uses[UseIndex].Use; 4802 ++UseIndex; 4803 4804 Use.set(To[i]); 4805 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4806 4807 // Now that we have modified User, add it back to the CSE maps. If it 4808 // already exists there, recursively merge the results together. 4809 AddModifiedNodeToCSEMaps(User, UpdateListener); 4810 } 4811} 4812 4813/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4814/// based on their topological order. It returns the maximum id and a vector 4815/// of the SDNodes* in assigned order by reference. 4816unsigned SelectionDAG::AssignTopologicalOrder() { 4817 4818 unsigned DAGSize = 0; 4819 4820 // SortedPos tracks the progress of the algorithm. Nodes before it are 4821 // sorted, nodes after it are unsorted. When the algorithm completes 4822 // it is at the end of the list. 4823 allnodes_iterator SortedPos = allnodes_begin(); 4824 4825 // Visit all the nodes. Move nodes with no operands to the front of 4826 // the list immediately. Annotate nodes that do have operands with their 4827 // operand count. Before we do this, the Node Id fields of the nodes 4828 // may contain arbitrary values. After, the Node Id fields for nodes 4829 // before SortedPos will contain the topological sort index, and the 4830 // Node Id fields for nodes At SortedPos and after will contain the 4831 // count of outstanding operands. 4832 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4833 SDNode *N = I++; 4834 unsigned Degree = N->getNumOperands(); 4835 if (Degree == 0) { 4836 // A node with no uses, add it to the result array immediately. 4837 N->setNodeId(DAGSize++); 4838 allnodes_iterator Q = N; 4839 if (Q != SortedPos) 4840 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4841 ++SortedPos; 4842 } else { 4843 // Temporarily use the Node Id as scratch space for the degree count. 4844 N->setNodeId(Degree); 4845 } 4846 } 4847 4848 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4849 // such that by the time the end is reached all nodes will be sorted. 4850 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4851 SDNode *N = I; 4852 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4853 UI != UE; ++UI) { 4854 SDNode *P = *UI; 4855 unsigned Degree = P->getNodeId(); 4856 --Degree; 4857 if (Degree == 0) { 4858 // All of P's operands are sorted, so P may sorted now. 4859 P->setNodeId(DAGSize++); 4860 if (P != SortedPos) 4861 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4862 ++SortedPos; 4863 } else { 4864 // Update P's outstanding operand count. 4865 P->setNodeId(Degree); 4866 } 4867 } 4868 } 4869 4870 assert(SortedPos == AllNodes.end() && 4871 "Topological sort incomplete!"); 4872 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4873 "First node in topological sort is not the entry token!"); 4874 assert(AllNodes.front().getNodeId() == 0 && 4875 "First node in topological sort has non-zero id!"); 4876 assert(AllNodes.front().getNumOperands() == 0 && 4877 "First node in topological sort has operands!"); 4878 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4879 "Last node in topologic sort has unexpected id!"); 4880 assert(AllNodes.back().use_empty() && 4881 "Last node in topologic sort has users!"); 4882 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4883 return DAGSize; 4884} 4885 4886 4887 4888//===----------------------------------------------------------------------===// 4889// SDNode Class 4890//===----------------------------------------------------------------------===// 4891 4892HandleSDNode::~HandleSDNode() { 4893 DropOperands(); 4894} 4895 4896GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4897 MVT VT, int64_t o) 4898 : SDNode(isa<GlobalVariable>(GA) && 4899 cast<GlobalVariable>(GA)->isThreadLocal() ? 4900 // Thread Local 4901 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4902 // Non Thread Local 4903 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4904 DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) { 4905 TheGlobal = const_cast<GlobalValue*>(GA); 4906} 4907 4908MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4909 const Value *srcValue, int SVO, 4910 unsigned alignment, bool vol) 4911 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4912 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4913 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4914 assert(getAlignment() == alignment && "Alignment representation error!"); 4915 assert(isVolatile() == vol && "Volatile representation error!"); 4916} 4917 4918MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4919 const SDValue *Ops, 4920 unsigned NumOps, MVT memvt, const Value *srcValue, 4921 int SVO, unsigned alignment, bool vol) 4922 : SDNode(Opc, dl, VTs, Ops, NumOps), 4923 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4924 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4925 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4926 assert(getAlignment() == alignment && "Alignment representation error!"); 4927 assert(isVolatile() == vol && "Volatile representation error!"); 4928} 4929 4930/// getMemOperand - Return a MachineMemOperand object describing the memory 4931/// reference performed by this memory reference. 4932MachineMemOperand MemSDNode::getMemOperand() const { 4933 int Flags = 0; 4934 if (isa<LoadSDNode>(this)) 4935 Flags = MachineMemOperand::MOLoad; 4936 else if (isa<StoreSDNode>(this)) 4937 Flags = MachineMemOperand::MOStore; 4938 else if (isa<AtomicSDNode>(this)) { 4939 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4940 } 4941 else { 4942 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4943 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4944 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4945 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4946 } 4947 4948 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4949 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4950 4951 // Check if the memory reference references a frame index 4952 const FrameIndexSDNode *FI = 4953 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4954 if (!getSrcValue() && FI) 4955 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4956 Flags, 0, Size, getAlignment()); 4957 else 4958 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4959 Size, getAlignment()); 4960} 4961 4962/// Profile - Gather unique data for the node. 4963/// 4964void SDNode::Profile(FoldingSetNodeID &ID) const { 4965 AddNodeIDNode(ID, this); 4966} 4967 4968/// getValueTypeList - Return a pointer to the specified value type. 4969/// 4970const MVT *SDNode::getValueTypeList(MVT VT) { 4971 if (VT.isExtended()) { 4972 static std::set<MVT, MVT::compareRawBits> EVTs; 4973 return &(*EVTs.insert(VT).first); 4974 } else { 4975 static MVT VTs[MVT::LAST_VALUETYPE]; 4976 VTs[VT.getSimpleVT()] = VT; 4977 return &VTs[VT.getSimpleVT()]; 4978 } 4979} 4980 4981/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 4982/// indicated value. This method ignores uses of other values defined by this 4983/// operation. 4984bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 4985 assert(Value < getNumValues() && "Bad value!"); 4986 4987 // TODO: Only iterate over uses of a given value of the node 4988 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 4989 if (UI.getUse().getResNo() == Value) { 4990 if (NUses == 0) 4991 return false; 4992 --NUses; 4993 } 4994 } 4995 4996 // Found exactly the right number of uses? 4997 return NUses == 0; 4998} 4999 5000 5001/// hasAnyUseOfValue - Return true if there are any use of the indicated 5002/// value. This method ignores uses of other values defined by this operation. 5003bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5004 assert(Value < getNumValues() && "Bad value!"); 5005 5006 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5007 if (UI.getUse().getResNo() == Value) 5008 return true; 5009 5010 return false; 5011} 5012 5013 5014/// isOnlyUserOf - Return true if this node is the only use of N. 5015/// 5016bool SDNode::isOnlyUserOf(SDNode *N) const { 5017 bool Seen = false; 5018 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5019 SDNode *User = *I; 5020 if (User == this) 5021 Seen = true; 5022 else 5023 return false; 5024 } 5025 5026 return Seen; 5027} 5028 5029/// isOperand - Return true if this node is an operand of N. 5030/// 5031bool SDValue::isOperandOf(SDNode *N) const { 5032 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5033 if (*this == N->getOperand(i)) 5034 return true; 5035 return false; 5036} 5037 5038bool SDNode::isOperandOf(SDNode *N) const { 5039 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5040 if (this == N->OperandList[i].getNode()) 5041 return true; 5042 return false; 5043} 5044 5045/// reachesChainWithoutSideEffects - Return true if this operand (which must 5046/// be a chain) reaches the specified operand without crossing any 5047/// side-effecting instructions. In practice, this looks through token 5048/// factors and non-volatile loads. In order to remain efficient, this only 5049/// looks a couple of nodes in, it does not do an exhaustive search. 5050bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5051 unsigned Depth) const { 5052 if (*this == Dest) return true; 5053 5054 // Don't search too deeply, we just want to be able to see through 5055 // TokenFactor's etc. 5056 if (Depth == 0) return false; 5057 5058 // If this is a token factor, all inputs to the TF happen in parallel. If any 5059 // of the operands of the TF reach dest, then we can do the xform. 5060 if (getOpcode() == ISD::TokenFactor) { 5061 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5062 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5063 return true; 5064 return false; 5065 } 5066 5067 // Loads don't have side effects, look through them. 5068 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5069 if (!Ld->isVolatile()) 5070 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5071 } 5072 return false; 5073} 5074 5075 5076static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5077 SmallPtrSet<SDNode *, 32> &Visited) { 5078 if (found || !Visited.insert(N)) 5079 return; 5080 5081 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5082 SDNode *Op = N->getOperand(i).getNode(); 5083 if (Op == P) { 5084 found = true; 5085 return; 5086 } 5087 findPredecessor(Op, P, found, Visited); 5088 } 5089} 5090 5091/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5092/// is either an operand of N or it can be reached by recursively traversing 5093/// up the operands. 5094/// NOTE: this is an expensive method. Use it carefully. 5095bool SDNode::isPredecessorOf(SDNode *N) const { 5096 SmallPtrSet<SDNode *, 32> Visited; 5097 bool found = false; 5098 findPredecessor(N, this, found, Visited); 5099 return found; 5100} 5101 5102uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5103 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5104 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5105} 5106 5107std::string SDNode::getOperationName(const SelectionDAG *G) const { 5108 switch (getOpcode()) { 5109 default: 5110 if (getOpcode() < ISD::BUILTIN_OP_END) 5111 return "<<Unknown DAG Node>>"; 5112 if (isMachineOpcode()) { 5113 if (G) 5114 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5115 if (getMachineOpcode() < TII->getNumOpcodes()) 5116 return TII->get(getMachineOpcode()).getName(); 5117 return "<<Unknown Machine Node>>"; 5118 } 5119 if (G) { 5120 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5121 const char *Name = TLI.getTargetNodeName(getOpcode()); 5122 if (Name) return Name; 5123 return "<<Unknown Target Node>>"; 5124 } 5125 return "<<Unknown Node>>"; 5126 5127#ifndef NDEBUG 5128 case ISD::DELETED_NODE: 5129 return "<<Deleted Node!>>"; 5130#endif 5131 case ISD::PREFETCH: return "Prefetch"; 5132 case ISD::MEMBARRIER: return "MemBarrier"; 5133 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5134 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5135 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5136 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5137 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5138 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5139 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5140 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5141 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5142 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5143 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5144 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5145 case ISD::PCMARKER: return "PCMarker"; 5146 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5147 case ISD::SRCVALUE: return "SrcValue"; 5148 case ISD::MEMOPERAND: return "MemOperand"; 5149 case ISD::EntryToken: return "EntryToken"; 5150 case ISD::TokenFactor: return "TokenFactor"; 5151 case ISD::AssertSext: return "AssertSext"; 5152 case ISD::AssertZext: return "AssertZext"; 5153 5154 case ISD::BasicBlock: return "BasicBlock"; 5155 case ISD::ARG_FLAGS: return "ArgFlags"; 5156 case ISD::VALUETYPE: return "ValueType"; 5157 case ISD::Register: return "Register"; 5158 5159 case ISD::Constant: return "Constant"; 5160 case ISD::ConstantFP: return "ConstantFP"; 5161 case ISD::GlobalAddress: return "GlobalAddress"; 5162 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5163 case ISD::FrameIndex: return "FrameIndex"; 5164 case ISD::JumpTable: return "JumpTable"; 5165 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5166 case ISD::RETURNADDR: return "RETURNADDR"; 5167 case ISD::FRAMEADDR: return "FRAMEADDR"; 5168 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5169 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5170 case ISD::EHSELECTION: return "EHSELECTION"; 5171 case ISD::EH_RETURN: return "EH_RETURN"; 5172 case ISD::ConstantPool: return "ConstantPool"; 5173 case ISD::ExternalSymbol: return "ExternalSymbol"; 5174 case ISD::INTRINSIC_WO_CHAIN: { 5175 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5176 return Intrinsic::getName((Intrinsic::ID)IID); 5177 } 5178 case ISD::INTRINSIC_VOID: 5179 case ISD::INTRINSIC_W_CHAIN: { 5180 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5181 return Intrinsic::getName((Intrinsic::ID)IID); 5182 } 5183 5184 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5185 case ISD::TargetConstant: return "TargetConstant"; 5186 case ISD::TargetConstantFP:return "TargetConstantFP"; 5187 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5188 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5189 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5190 case ISD::TargetJumpTable: return "TargetJumpTable"; 5191 case ISD::TargetConstantPool: return "TargetConstantPool"; 5192 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5193 5194 case ISD::CopyToReg: return "CopyToReg"; 5195 case ISD::CopyFromReg: return "CopyFromReg"; 5196 case ISD::UNDEF: return "undef"; 5197 case ISD::MERGE_VALUES: return "merge_values"; 5198 case ISD::INLINEASM: return "inlineasm"; 5199 case ISD::DBG_LABEL: return "dbg_label"; 5200 case ISD::EH_LABEL: return "eh_label"; 5201 case ISD::DECLARE: return "declare"; 5202 case ISD::HANDLENODE: return "handlenode"; 5203 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5204 case ISD::CALL: return "call"; 5205 5206 // Unary operators 5207 case ISD::FABS: return "fabs"; 5208 case ISD::FNEG: return "fneg"; 5209 case ISD::FSQRT: return "fsqrt"; 5210 case ISD::FSIN: return "fsin"; 5211 case ISD::FCOS: return "fcos"; 5212 case ISD::FPOWI: return "fpowi"; 5213 case ISD::FPOW: return "fpow"; 5214 case ISD::FTRUNC: return "ftrunc"; 5215 case ISD::FFLOOR: return "ffloor"; 5216 case ISD::FCEIL: return "fceil"; 5217 case ISD::FRINT: return "frint"; 5218 case ISD::FNEARBYINT: return "fnearbyint"; 5219 5220 // Binary operators 5221 case ISD::ADD: return "add"; 5222 case ISD::SUB: return "sub"; 5223 case ISD::MUL: return "mul"; 5224 case ISD::MULHU: return "mulhu"; 5225 case ISD::MULHS: return "mulhs"; 5226 case ISD::SDIV: return "sdiv"; 5227 case ISD::UDIV: return "udiv"; 5228 case ISD::SREM: return "srem"; 5229 case ISD::UREM: return "urem"; 5230 case ISD::SMUL_LOHI: return "smul_lohi"; 5231 case ISD::UMUL_LOHI: return "umul_lohi"; 5232 case ISD::SDIVREM: return "sdivrem"; 5233 case ISD::UDIVREM: return "udivrem"; 5234 case ISD::AND: return "and"; 5235 case ISD::OR: return "or"; 5236 case ISD::XOR: return "xor"; 5237 case ISD::SHL: return "shl"; 5238 case ISD::SRA: return "sra"; 5239 case ISD::SRL: return "srl"; 5240 case ISD::ROTL: return "rotl"; 5241 case ISD::ROTR: return "rotr"; 5242 case ISD::FADD: return "fadd"; 5243 case ISD::FSUB: return "fsub"; 5244 case ISD::FMUL: return "fmul"; 5245 case ISD::FDIV: return "fdiv"; 5246 case ISD::FREM: return "frem"; 5247 case ISD::FCOPYSIGN: return "fcopysign"; 5248 case ISD::FGETSIGN: return "fgetsign"; 5249 5250 case ISD::SETCC: return "setcc"; 5251 case ISD::VSETCC: return "vsetcc"; 5252 case ISD::SELECT: return "select"; 5253 case ISD::SELECT_CC: return "select_cc"; 5254 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5255 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5256 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5257 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5258 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5259 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5260 case ISD::CARRY_FALSE: return "carry_false"; 5261 case ISD::ADDC: return "addc"; 5262 case ISD::ADDE: return "adde"; 5263 case ISD::SADDO: return "saddo"; 5264 case ISD::UADDO: return "uaddo"; 5265 case ISD::SSUBO: return "ssubo"; 5266 case ISD::USUBO: return "usubo"; 5267 case ISD::SMULO: return "smulo"; 5268 case ISD::UMULO: return "umulo"; 5269 case ISD::SUBC: return "subc"; 5270 case ISD::SUBE: return "sube"; 5271 case ISD::SHL_PARTS: return "shl_parts"; 5272 case ISD::SRA_PARTS: return "sra_parts"; 5273 case ISD::SRL_PARTS: return "srl_parts"; 5274 5275 // Conversion operators. 5276 case ISD::SIGN_EXTEND: return "sign_extend"; 5277 case ISD::ZERO_EXTEND: return "zero_extend"; 5278 case ISD::ANY_EXTEND: return "any_extend"; 5279 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5280 case ISD::TRUNCATE: return "truncate"; 5281 case ISD::FP_ROUND: return "fp_round"; 5282 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5283 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5284 case ISD::FP_EXTEND: return "fp_extend"; 5285 5286 case ISD::SINT_TO_FP: return "sint_to_fp"; 5287 case ISD::UINT_TO_FP: return "uint_to_fp"; 5288 case ISD::FP_TO_SINT: return "fp_to_sint"; 5289 case ISD::FP_TO_UINT: return "fp_to_uint"; 5290 case ISD::BIT_CONVERT: return "bit_convert"; 5291 5292 case ISD::CONVERT_RNDSAT: { 5293 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5294 default: assert(0 && "Unknown cvt code!"); 5295 case ISD::CVT_FF: return "cvt_ff"; 5296 case ISD::CVT_FS: return "cvt_fs"; 5297 case ISD::CVT_FU: return "cvt_fu"; 5298 case ISD::CVT_SF: return "cvt_sf"; 5299 case ISD::CVT_UF: return "cvt_uf"; 5300 case ISD::CVT_SS: return "cvt_ss"; 5301 case ISD::CVT_SU: return "cvt_su"; 5302 case ISD::CVT_US: return "cvt_us"; 5303 case ISD::CVT_UU: return "cvt_uu"; 5304 } 5305 } 5306 5307 // Control flow instructions 5308 case ISD::BR: return "br"; 5309 case ISD::BRIND: return "brind"; 5310 case ISD::BR_JT: return "br_jt"; 5311 case ISD::BRCOND: return "brcond"; 5312 case ISD::BR_CC: return "br_cc"; 5313 case ISD::RET: return "ret"; 5314 case ISD::CALLSEQ_START: return "callseq_start"; 5315 case ISD::CALLSEQ_END: return "callseq_end"; 5316 5317 // Other operators 5318 case ISD::LOAD: return "load"; 5319 case ISD::STORE: return "store"; 5320 case ISD::VAARG: return "vaarg"; 5321 case ISD::VACOPY: return "vacopy"; 5322 case ISD::VAEND: return "vaend"; 5323 case ISD::VASTART: return "vastart"; 5324 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5325 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5326 case ISD::BUILD_PAIR: return "build_pair"; 5327 case ISD::STACKSAVE: return "stacksave"; 5328 case ISD::STACKRESTORE: return "stackrestore"; 5329 case ISD::TRAP: return "trap"; 5330 5331 // Bit manipulation 5332 case ISD::BSWAP: return "bswap"; 5333 case ISD::CTPOP: return "ctpop"; 5334 case ISD::CTTZ: return "cttz"; 5335 case ISD::CTLZ: return "ctlz"; 5336 5337 // Debug info 5338 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5339 case ISD::DEBUG_LOC: return "debug_loc"; 5340 5341 // Trampolines 5342 case ISD::TRAMPOLINE: return "trampoline"; 5343 5344 case ISD::CONDCODE: 5345 switch (cast<CondCodeSDNode>(this)->get()) { 5346 default: assert(0 && "Unknown setcc condition!"); 5347 case ISD::SETOEQ: return "setoeq"; 5348 case ISD::SETOGT: return "setogt"; 5349 case ISD::SETOGE: return "setoge"; 5350 case ISD::SETOLT: return "setolt"; 5351 case ISD::SETOLE: return "setole"; 5352 case ISD::SETONE: return "setone"; 5353 5354 case ISD::SETO: return "seto"; 5355 case ISD::SETUO: return "setuo"; 5356 case ISD::SETUEQ: return "setue"; 5357 case ISD::SETUGT: return "setugt"; 5358 case ISD::SETUGE: return "setuge"; 5359 case ISD::SETULT: return "setult"; 5360 case ISD::SETULE: return "setule"; 5361 case ISD::SETUNE: return "setune"; 5362 5363 case ISD::SETEQ: return "seteq"; 5364 case ISD::SETGT: return "setgt"; 5365 case ISD::SETGE: return "setge"; 5366 case ISD::SETLT: return "setlt"; 5367 case ISD::SETLE: return "setle"; 5368 case ISD::SETNE: return "setne"; 5369 } 5370 } 5371} 5372 5373const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5374 switch (AM) { 5375 default: 5376 return ""; 5377 case ISD::PRE_INC: 5378 return "<pre-inc>"; 5379 case ISD::PRE_DEC: 5380 return "<pre-dec>"; 5381 case ISD::POST_INC: 5382 return "<post-inc>"; 5383 case ISD::POST_DEC: 5384 return "<post-dec>"; 5385 } 5386} 5387 5388std::string ISD::ArgFlagsTy::getArgFlagsString() { 5389 std::string S = "< "; 5390 5391 if (isZExt()) 5392 S += "zext "; 5393 if (isSExt()) 5394 S += "sext "; 5395 if (isInReg()) 5396 S += "inreg "; 5397 if (isSRet()) 5398 S += "sret "; 5399 if (isByVal()) 5400 S += "byval "; 5401 if (isNest()) 5402 S += "nest "; 5403 if (getByValAlign()) 5404 S += "byval-align:" + utostr(getByValAlign()) + " "; 5405 if (getOrigAlign()) 5406 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5407 if (getByValSize()) 5408 S += "byval-size:" + utostr(getByValSize()) + " "; 5409 return S + ">"; 5410} 5411 5412void SDNode::dump() const { dump(0); } 5413void SDNode::dump(const SelectionDAG *G) const { 5414 print(errs(), G); 5415} 5416 5417void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5418 OS << (void*)this << ": "; 5419 5420 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5421 if (i) OS << ","; 5422 if (getValueType(i) == MVT::Other) 5423 OS << "ch"; 5424 else 5425 OS << getValueType(i).getMVTString(); 5426 } 5427 OS << " = " << getOperationName(G); 5428} 5429 5430void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5431 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5432 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(this); 5433 OS << "<"; 5434 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) { 5435 int Idx = SVN->getMaskElt(i); 5436 if (i) OS << ","; 5437 if (Idx < 0) 5438 OS << "u"; 5439 else 5440 OS << Idx; 5441 } 5442 OS << ">"; 5443 } 5444 5445 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5446 OS << '<' << CSDN->getAPIntValue() << '>'; 5447 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5448 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5449 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5450 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5451 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5452 else { 5453 OS << "<APFloat("; 5454 CSDN->getValueAPF().bitcastToAPInt().dump(); 5455 OS << ")>"; 5456 } 5457 } else if (const GlobalAddressSDNode *GADN = 5458 dyn_cast<GlobalAddressSDNode>(this)) { 5459 int64_t offset = GADN->getOffset(); 5460 OS << '<'; 5461 WriteAsOperand(OS, GADN->getGlobal()); 5462 OS << '>'; 5463 if (offset > 0) 5464 OS << " + " << offset; 5465 else 5466 OS << " " << offset; 5467 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5468 OS << "<" << FIDN->getIndex() << ">"; 5469 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5470 OS << "<" << JTDN->getIndex() << ">"; 5471 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5472 int offset = CP->getOffset(); 5473 if (CP->isMachineConstantPoolEntry()) 5474 OS << "<" << *CP->getMachineCPVal() << ">"; 5475 else 5476 OS << "<" << *CP->getConstVal() << ">"; 5477 if (offset > 0) 5478 OS << " + " << offset; 5479 else 5480 OS << " " << offset; 5481 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5482 OS << "<"; 5483 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5484 if (LBB) 5485 OS << LBB->getName() << " "; 5486 OS << (const void*)BBDN->getBasicBlock() << ">"; 5487 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5488 if (G && R->getReg() && 5489 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5490 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5491 } else { 5492 OS << " #" << R->getReg(); 5493 } 5494 } else if (const ExternalSymbolSDNode *ES = 5495 dyn_cast<ExternalSymbolSDNode>(this)) { 5496 OS << "'" << ES->getSymbol() << "'"; 5497 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5498 if (M->getValue()) 5499 OS << "<" << M->getValue() << ">"; 5500 else 5501 OS << "<null>"; 5502 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5503 if (M->MO.getValue()) 5504 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5505 else 5506 OS << "<null:" << M->MO.getOffset() << ">"; 5507 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5508 OS << N->getArgFlags().getArgFlagsString(); 5509 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5510 OS << ":" << N->getVT().getMVTString(); 5511 } 5512 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5513 const Value *SrcValue = LD->getSrcValue(); 5514 int SrcOffset = LD->getSrcValueOffset(); 5515 OS << " <"; 5516 if (SrcValue) 5517 OS << SrcValue; 5518 else 5519 OS << "null"; 5520 OS << ":" << SrcOffset << ">"; 5521 5522 bool doExt = true; 5523 switch (LD->getExtensionType()) { 5524 default: doExt = false; break; 5525 case ISD::EXTLOAD: OS << " <anyext "; break; 5526 case ISD::SEXTLOAD: OS << " <sext "; break; 5527 case ISD::ZEXTLOAD: OS << " <zext "; break; 5528 } 5529 if (doExt) 5530 OS << LD->getMemoryVT().getMVTString() << ">"; 5531 5532 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5533 if (*AM) 5534 OS << " " << AM; 5535 if (LD->isVolatile()) 5536 OS << " <volatile>"; 5537 OS << " alignment=" << LD->getAlignment(); 5538 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5539 const Value *SrcValue = ST->getSrcValue(); 5540 int SrcOffset = ST->getSrcValueOffset(); 5541 OS << " <"; 5542 if (SrcValue) 5543 OS << SrcValue; 5544 else 5545 OS << "null"; 5546 OS << ":" << SrcOffset << ">"; 5547 5548 if (ST->isTruncatingStore()) 5549 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5550 5551 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5552 if (*AM) 5553 OS << " " << AM; 5554 if (ST->isVolatile()) 5555 OS << " <volatile>"; 5556 OS << " alignment=" << ST->getAlignment(); 5557 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5558 const Value *SrcValue = AT->getSrcValue(); 5559 int SrcOffset = AT->getSrcValueOffset(); 5560 OS << " <"; 5561 if (SrcValue) 5562 OS << SrcValue; 5563 else 5564 OS << "null"; 5565 OS << ":" << SrcOffset << ">"; 5566 if (AT->isVolatile()) 5567 OS << " <volatile>"; 5568 OS << " alignment=" << AT->getAlignment(); 5569 } 5570} 5571 5572void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5573 print_types(OS, G); 5574 OS << " "; 5575 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5576 if (i) OS << ", "; 5577 OS << (void*)getOperand(i).getNode(); 5578 if (unsigned RN = getOperand(i).getResNo()) 5579 OS << ":" << RN; 5580 } 5581 print_details(OS, G); 5582} 5583 5584static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5585 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5586 if (N->getOperand(i).getNode()->hasOneUse()) 5587 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5588 else 5589 cerr << "\n" << std::string(indent+2, ' ') 5590 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5591 5592 5593 cerr << "\n" << std::string(indent, ' '); 5594 N->dump(G); 5595} 5596 5597void SelectionDAG::dump() const { 5598 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5599 5600 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5601 I != E; ++I) { 5602 const SDNode *N = I; 5603 if (!N->hasOneUse() && N != getRoot().getNode()) 5604 DumpNodes(N, 2, this); 5605 } 5606 5607 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5608 5609 cerr << "\n\n"; 5610} 5611 5612void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5613 print_types(OS, G); 5614 print_details(OS, G); 5615} 5616 5617typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5618static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5619 const SelectionDAG *G, VisitedSDNodeSet &once) { 5620 if (!once.insert(N)) // If we've been here before, return now. 5621 return; 5622 // Dump the current SDNode, but don't end the line yet. 5623 OS << std::string(indent, ' '); 5624 N->printr(OS, G); 5625 // Having printed this SDNode, walk the children: 5626 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5627 const SDNode *child = N->getOperand(i).getNode(); 5628 if (i) OS << ","; 5629 OS << " "; 5630 if (child->getNumOperands() == 0) { 5631 // This child has no grandchildren; print it inline right here. 5632 child->printr(OS, G); 5633 once.insert(child); 5634 } else { // Just the address. FIXME: also print the child's opcode 5635 OS << (void*)child; 5636 if (unsigned RN = N->getOperand(i).getResNo()) 5637 OS << ":" << RN; 5638 } 5639 } 5640 OS << "\n"; 5641 // Dump children that have grandchildren on their own line(s). 5642 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5643 const SDNode *child = N->getOperand(i).getNode(); 5644 DumpNodesr(OS, child, indent+2, G, once); 5645 } 5646} 5647 5648void SDNode::dumpr() const { 5649 VisitedSDNodeSet once; 5650 DumpNodesr(errs(), this, 0, 0, once); 5651} 5652 5653 5654// getAddressSpace - Return the address space this GlobalAddress belongs to. 5655unsigned GlobalAddressSDNode::getAddressSpace() const { 5656 return getGlobal()->getType()->getAddressSpace(); 5657} 5658 5659 5660const Type *ConstantPoolSDNode::getType() const { 5661 if (isMachineConstantPoolEntry()) 5662 return Val.MachineCPVal->getType(); 5663 return Val.ConstVal->getType(); 5664} 5665 5666bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, 5667 APInt &SplatUndef, 5668 unsigned &SplatBitSize, 5669 bool &HasAnyUndefs, 5670 unsigned MinSplatBits) { 5671 MVT VT = getValueType(0); 5672 assert(VT.isVector() && "Expected a vector type"); 5673 unsigned sz = VT.getSizeInBits(); 5674 if (MinSplatBits > sz) 5675 return false; 5676 5677 SplatValue = APInt(sz, 0); 5678 SplatUndef = APInt(sz, 0); 5679 5680 // Get the bits. Bits with undefined values (when the corresponding element 5681 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared 5682 // in SplatValue. If any of the values are not constant, give up and return 5683 // false. 5684 unsigned int nOps = getNumOperands(); 5685 assert(nOps > 0 && "isConstantSplat has 0-size build vector"); 5686 unsigned EltBitSize = VT.getVectorElementType().getSizeInBits(); 5687 for (unsigned i = 0; i < nOps; ++i) { 5688 SDValue OpVal = getOperand(i); 5689 unsigned BitPos = i * EltBitSize; 5690 5691 if (OpVal.getOpcode() == ISD::UNDEF) 5692 SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos +EltBitSize); 5693 else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) 5694 SplatValue |= (APInt(CN->getAPIntValue()).zextOrTrunc(EltBitSize). 5695 zextOrTrunc(sz) << BitPos); 5696 else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) 5697 SplatValue |= CN->getValueAPF().bitcastToAPInt().zextOrTrunc(sz) <<BitPos; 5698 else 5699 return false; 5700 } 5701 5702 // The build_vector is all constants or undefs. Find the smallest element 5703 // size that splats the vector. 5704 5705 HasAnyUndefs = (SplatUndef != 0); 5706 while (sz > 8) { 5707 5708 unsigned HalfSize = sz / 2; 5709 APInt HighValue = APInt(SplatValue).lshr(HalfSize).trunc(HalfSize); 5710 APInt LowValue = APInt(SplatValue).trunc(HalfSize); 5711 APInt HighUndef = APInt(SplatUndef).lshr(HalfSize).trunc(HalfSize); 5712 APInt LowUndef = APInt(SplatUndef).trunc(HalfSize); 5713 5714 // If the two halves do not match (ignoring undef bits), stop here. 5715 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) || 5716 MinSplatBits > HalfSize) 5717 break; 5718 5719 SplatValue = HighValue | LowValue; 5720 SplatUndef = HighUndef & LowUndef; 5721 5722 sz = HalfSize; 5723 } 5724 5725 SplatBitSize = sz; 5726 return true; 5727} 5728 5729bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) { 5730 // Find the first non-undef value in the shuffle mask. 5731 unsigned i, e; 5732 for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) 5733 /* search */; 5734 5735 assert(i != e && "VECTOR_SHUFFLE node with all undef indices!"); 5736 5737 // Make sure all remaining elements are either undef or the same as the first 5738 // non-undef value. 5739 for (int Idx = Mask[i]; i != e; ++i) 5740 if (Mask[i] >= 0 && Mask[i] != Idx) 5741 return false; 5742 return true; 5743} 5744