SelectionDAG.cpp revision c975e1dedcffd55894a14b41ccdb7255aaf19034
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/MRegisterInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Target/TargetMachine.h" 24#include <iostream> 25#include <set> 26#include <cmath> 27#include <algorithm> 28using namespace llvm; 29 30static bool isCommutativeBinOp(unsigned Opcode) { 31 switch (Opcode) { 32 case ISD::ADD: 33 case ISD::MUL: 34 case ISD::AND: 35 case ISD::OR: 36 case ISD::XOR: return true; 37 default: return false; // FIXME: Need commutative info for user ops! 38 } 39} 40 41static bool isAssociativeBinOp(unsigned Opcode) { 42 switch (Opcode) { 43 case ISD::ADD: 44 case ISD::MUL: 45 case ISD::AND: 46 case ISD::OR: 47 case ISD::XOR: return true; 48 default: return false; // FIXME: Need associative info for user ops! 49 } 50} 51 52// isInvertibleForFree - Return true if there is no cost to emitting the logical 53// inverse of this node. 54static bool isInvertibleForFree(SDOperand N) { 55 if (isa<ConstantSDNode>(N.Val)) return true; 56 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 57 return true; 58 return false; 59} 60 61//===----------------------------------------------------------------------===// 62// ConstantFPSDNode Class 63//===----------------------------------------------------------------------===// 64 65/// isExactlyValue - We don't rely on operator== working on double values, as 66/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 67/// As such, this method can be used to do an exact bit-for-bit comparison of 68/// two floating point values. 69bool ConstantFPSDNode::isExactlyValue(double V) const { 70 return DoubleToBits(V) == DoubleToBits(Value); 71} 72 73//===----------------------------------------------------------------------===// 74// ISD Class 75//===----------------------------------------------------------------------===// 76 77/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 78/// when given the operation for (X op Y). 79ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 80 // To perform this operation, we just need to swap the L and G bits of the 81 // operation. 82 unsigned OldL = (Operation >> 2) & 1; 83 unsigned OldG = (Operation >> 1) & 1; 84 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 85 (OldL << 1) | // New G bit 86 (OldG << 2)); // New L bit. 87} 88 89/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 90/// 'op' is a valid SetCC operation. 91ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 92 unsigned Operation = Op; 93 if (isInteger) 94 Operation ^= 7; // Flip L, G, E bits, but not U. 95 else 96 Operation ^= 15; // Flip all of the condition bits. 97 if (Operation > ISD::SETTRUE2) 98 Operation &= ~8; // Don't let N and U bits get set. 99 return ISD::CondCode(Operation); 100} 101 102 103/// isSignedOp - For an integer comparison, return 1 if the comparison is a 104/// signed operation and 2 if the result is an unsigned comparison. Return zero 105/// if the operation does not depend on the sign of the input (setne and seteq). 106static int isSignedOp(ISD::CondCode Opcode) { 107 switch (Opcode) { 108 default: assert(0 && "Illegal integer setcc operation!"); 109 case ISD::SETEQ: 110 case ISD::SETNE: return 0; 111 case ISD::SETLT: 112 case ISD::SETLE: 113 case ISD::SETGT: 114 case ISD::SETGE: return 1; 115 case ISD::SETULT: 116 case ISD::SETULE: 117 case ISD::SETUGT: 118 case ISD::SETUGE: return 2; 119 } 120} 121 122/// getSetCCOrOperation - Return the result of a logical OR between different 123/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 124/// returns SETCC_INVALID if it is not possible to represent the resultant 125/// comparison. 126ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 127 bool isInteger) { 128 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 129 // Cannot fold a signed integer setcc with an unsigned integer setcc. 130 return ISD::SETCC_INVALID; 131 132 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 133 134 // If the N and U bits get set then the resultant comparison DOES suddenly 135 // care about orderedness, and is true when ordered. 136 if (Op > ISD::SETTRUE2) 137 Op &= ~16; // Clear the N bit. 138 return ISD::CondCode(Op); 139} 140 141/// getSetCCAndOperation - Return the result of a logical AND between different 142/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 143/// function returns zero if it is not possible to represent the resultant 144/// comparison. 145ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 146 bool isInteger) { 147 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 148 // Cannot fold a signed setcc with an unsigned setcc. 149 return ISD::SETCC_INVALID; 150 151 // Combine all of the condition bits. 152 return ISD::CondCode(Op1 & Op2); 153} 154 155const TargetMachine &SelectionDAG::getTarget() const { 156 return TLI.getTargetMachine(); 157} 158 159//===----------------------------------------------------------------------===// 160// SelectionDAG Class 161//===----------------------------------------------------------------------===// 162 163/// RemoveDeadNodes - This method deletes all unreachable nodes in the 164/// SelectionDAG, including nodes (like loads) that have uses of their token 165/// chain but no other uses and no side effect. If a node is passed in as an 166/// argument, it is used as the seed for node deletion. 167void SelectionDAG::RemoveDeadNodes(SDNode *N) { 168 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 169 170 // Create a dummy node (which is not added to allnodes), that adds a reference 171 // to the root node, preventing it from being deleted. 172 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 173 174 // If we have a hint to start from, use it. 175 if (N) DeleteNodeIfDead(N, &AllNodeSet); 176 177 Restart: 178 unsigned NumNodes = AllNodeSet.size(); 179 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 180 I != E; ++I) { 181 // Try to delete this node. 182 DeleteNodeIfDead(*I, &AllNodeSet); 183 184 // If we actually deleted any nodes, do not use invalid iterators in 185 // AllNodeSet. 186 if (AllNodeSet.size() != NumNodes) 187 goto Restart; 188 } 189 190 // Restore AllNodes. 191 if (AllNodes.size() != NumNodes) 192 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 193 194 // If the root changed (e.g. it was a dead load, update the root). 195 setRoot(DummyNode->getOperand(0)); 196 197 // Now that we are done with the dummy node, delete it. 198 DummyNode->getOperand(0).Val->removeUser(DummyNode); 199 delete DummyNode; 200} 201 202 203void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 204 if (!N->use_empty()) 205 return; 206 207 // Okay, we really are going to delete this node. First take this out of the 208 // appropriate CSE map. 209 RemoveNodeFromCSEMaps(N); 210 211 // Next, brutally remove the operand list. This is safe to do, as there are 212 // no cycles in the graph. 213 while (!N->Operands.empty()) { 214 SDNode *O = N->Operands.back().Val; 215 N->Operands.pop_back(); 216 O->removeUser(N); 217 218 // Now that we removed this operand, see if there are no uses of it left. 219 DeleteNodeIfDead(O, NodeSet); 220 } 221 222 // Remove the node from the nodes set and delete it. 223 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 224 AllNodeSet.erase(N); 225 226 // Now that the node is gone, check to see if any of the operands of this node 227 // are dead now. 228 delete N; 229} 230 231/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 232/// correspond to it. This is useful when we're about to delete or repurpose 233/// the node. We don't want future request for structurally identical nodes 234/// to return N anymore. 235void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 236 switch (N->getOpcode()) { 237 case ISD::Constant: 238 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 239 N->getValueType(0))); 240 break; 241 case ISD::TargetConstant: 242 TargetConstants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 243 N->getValueType(0))); 244 break; 245 case ISD::ConstantFP: { 246 uint64_t V = DoubleToBits(cast<ConstantFPSDNode>(N)->getValue()); 247 ConstantFPs.erase(std::make_pair(V, N->getValueType(0))); 248 break; 249 } 250 case ISD::CONDCODE: 251 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 252 "Cond code doesn't exist!"); 253 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 254 break; 255 case ISD::GlobalAddress: 256 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 257 break; 258 case ISD::TargetGlobalAddress: 259 TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 260 break; 261 case ISD::FrameIndex: 262 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 263 break; 264 case ISD::ConstantPool: 265 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 266 break; 267 case ISD::BasicBlock: 268 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 269 break; 270 case ISD::ExternalSymbol: 271 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 272 break; 273 case ISD::VALUETYPE: 274 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 275 break; 276 case ISD::Register: 277 RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0; 278 break; 279 case ISD::SRCVALUE: { 280 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 281 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 282 break; 283 } 284 case ISD::LOAD: 285 Loads.erase(std::make_pair(N->getOperand(1), 286 std::make_pair(N->getOperand(0), 287 N->getValueType(0)))); 288 break; 289 default: 290 if (N->getNumOperands() == 1) 291 UnaryOps.erase(std::make_pair(N->getOpcode(), 292 std::make_pair(N->getOperand(0), 293 N->getValueType(0)))); 294 else if (N->getNumOperands() == 2) 295 BinaryOps.erase(std::make_pair(N->getOpcode(), 296 std::make_pair(N->getOperand(0), 297 N->getOperand(1)))); 298 else if (N->getNumValues() == 1) { 299 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 300 OneResultNodes.erase(std::make_pair(N->getOpcode(), 301 std::make_pair(N->getValueType(0), 302 Ops))); 303 } else { 304 // Remove the node from the ArbitraryNodes map. 305 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 306 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 307 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 308 std::make_pair(RV, Ops))); 309 } 310 break; 311 } 312} 313 314/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 315/// has been taken out and modified in some way. If the specified node already 316/// exists in the CSE maps, do not modify the maps, but return the existing node 317/// instead. If it doesn't exist, add it and return null. 318/// 319SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 320 assert(N->getNumOperands() && "This is a leaf node!"); 321 if (N->getOpcode() == ISD::LOAD) { 322 SDNode *&L = Loads[std::make_pair(N->getOperand(1), 323 std::make_pair(N->getOperand(0), 324 N->getValueType(0)))]; 325 if (L) return L; 326 L = N; 327 } else if (N->getNumOperands() == 1) { 328 SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(), 329 std::make_pair(N->getOperand(0), 330 N->getValueType(0)))]; 331 if (U) return U; 332 U = N; 333 } else if (N->getNumOperands() == 2) { 334 SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(), 335 std::make_pair(N->getOperand(0), 336 N->getOperand(1)))]; 337 if (B) return B; 338 B = N; 339 } else if (N->getNumValues() == 1) { 340 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 341 SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(), 342 std::make_pair(N->getValueType(0), Ops))]; 343 if (ORN) return ORN; 344 ORN = N; 345 } else { 346 // Remove the node from the ArbitraryNodes map. 347 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 348 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 349 SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(), 350 std::make_pair(RV, Ops))]; 351 if (AN) return AN; 352 AN = N; 353 } 354 return 0; 355 356} 357 358 359 360SelectionDAG::~SelectionDAG() { 361 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 362 delete AllNodes[i]; 363} 364 365SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 366 if (Op.getValueType() == VT) return Op; 367 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 368 return getNode(ISD::AND, Op.getValueType(), Op, 369 getConstant(Imm, Op.getValueType())); 370} 371 372SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 373 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 374 // Mask out any bits that are not valid for this constant. 375 if (VT != MVT::i64) 376 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 377 378 SDNode *&N = Constants[std::make_pair(Val, VT)]; 379 if (N) return SDOperand(N, 0); 380 N = new ConstantSDNode(false, Val, VT); 381 AllNodes.push_back(N); 382 return SDOperand(N, 0); 383} 384 385SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) { 386 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 387 // Mask out any bits that are not valid for this constant. 388 if (VT != MVT::i64) 389 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 390 391 SDNode *&N = TargetConstants[std::make_pair(Val, VT)]; 392 if (N) return SDOperand(N, 0); 393 N = new ConstantSDNode(true, Val, VT); 394 AllNodes.push_back(N); 395 return SDOperand(N, 0); 396} 397 398SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 399 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 400 if (VT == MVT::f32) 401 Val = (float)Val; // Mask out extra precision. 402 403 // Do the map lookup using the actual bit pattern for the floating point 404 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 405 // we don't have issues with SNANs. 406 SDNode *&N = ConstantFPs[std::make_pair(DoubleToBits(Val), VT)]; 407 if (N) return SDOperand(N, 0); 408 N = new ConstantFPSDNode(Val, VT); 409 AllNodes.push_back(N); 410 return SDOperand(N, 0); 411} 412 413 414 415SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 416 MVT::ValueType VT) { 417 SDNode *&N = GlobalValues[GV]; 418 if (N) return SDOperand(N, 0); 419 N = new GlobalAddressSDNode(false, GV, VT); 420 AllNodes.push_back(N); 421 return SDOperand(N, 0); 422} 423 424SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV, 425 MVT::ValueType VT) { 426 SDNode *&N = TargetGlobalValues[GV]; 427 if (N) return SDOperand(N, 0); 428 N = new GlobalAddressSDNode(true, GV, VT); 429 AllNodes.push_back(N); 430 return SDOperand(N, 0); 431} 432 433SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 434 SDNode *&N = FrameIndices[FI]; 435 if (N) return SDOperand(N, 0); 436 N = new FrameIndexSDNode(FI, VT); 437 AllNodes.push_back(N); 438 return SDOperand(N, 0); 439} 440 441SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 442 SDNode *N = ConstantPoolIndices[CPIdx]; 443 if (N) return SDOperand(N, 0); 444 N = new ConstantPoolSDNode(CPIdx, VT); 445 AllNodes.push_back(N); 446 return SDOperand(N, 0); 447} 448 449SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 450 SDNode *&N = BBNodes[MBB]; 451 if (N) return SDOperand(N, 0); 452 N = new BasicBlockSDNode(MBB); 453 AllNodes.push_back(N); 454 return SDOperand(N, 0); 455} 456 457SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 458 if ((unsigned)VT >= ValueTypeNodes.size()) 459 ValueTypeNodes.resize(VT+1); 460 if (ValueTypeNodes[VT] == 0) { 461 ValueTypeNodes[VT] = new VTSDNode(VT); 462 AllNodes.push_back(ValueTypeNodes[VT]); 463 } 464 465 return SDOperand(ValueTypeNodes[VT], 0); 466} 467 468SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 469 SDNode *&N = ExternalSymbols[Sym]; 470 if (N) return SDOperand(N, 0); 471 N = new ExternalSymbolSDNode(Sym, VT); 472 AllNodes.push_back(N); 473 return SDOperand(N, 0); 474} 475 476SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 477 if ((unsigned)Cond >= CondCodeNodes.size()) 478 CondCodeNodes.resize(Cond+1); 479 480 if (CondCodeNodes[Cond] == 0) { 481 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 482 AllNodes.push_back(CondCodeNodes[Cond]); 483 } 484 return SDOperand(CondCodeNodes[Cond], 0); 485} 486 487SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) { 488 if (Reg >= RegNodes.size()) 489 RegNodes.resize(Reg+1); 490 RegisterSDNode *&Result = RegNodes[Reg]; 491 if (Result) { 492 assert(Result->getValueType(0) == VT && 493 "Inconsistent value types for machine registers"); 494 } else { 495 Result = new RegisterSDNode(Reg, VT); 496 AllNodes.push_back(Result); 497 } 498 return SDOperand(Result, 0); 499} 500 501SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 502 SDOperand N2, ISD::CondCode Cond) { 503 // These setcc operations always fold. 504 switch (Cond) { 505 default: break; 506 case ISD::SETFALSE: 507 case ISD::SETFALSE2: return getConstant(0, VT); 508 case ISD::SETTRUE: 509 case ISD::SETTRUE2: return getConstant(1, VT); 510 } 511 512 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 513 uint64_t C2 = N2C->getValue(); 514 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 515 uint64_t C1 = N1C->getValue(); 516 517 // Sign extend the operands if required 518 if (ISD::isSignedIntSetCC(Cond)) { 519 C1 = N1C->getSignExtended(); 520 C2 = N2C->getSignExtended(); 521 } 522 523 switch (Cond) { 524 default: assert(0 && "Unknown integer setcc!"); 525 case ISD::SETEQ: return getConstant(C1 == C2, VT); 526 case ISD::SETNE: return getConstant(C1 != C2, VT); 527 case ISD::SETULT: return getConstant(C1 < C2, VT); 528 case ISD::SETUGT: return getConstant(C1 > C2, VT); 529 case ISD::SETULE: return getConstant(C1 <= C2, VT); 530 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 531 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 532 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 533 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 534 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 535 } 536 } else { 537 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 538 // the comparison on the input. 539 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 540 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 541 542 // If the comparison constant has bits in the upper part, the 543 // zero-extended value could never match. 544 if (C2 & (~0ULL << InSize)) { 545 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 546 switch (Cond) { 547 case ISD::SETUGT: 548 case ISD::SETUGE: 549 case ISD::SETEQ: return getConstant(0, VT); 550 case ISD::SETULT: 551 case ISD::SETULE: 552 case ISD::SETNE: return getConstant(1, VT); 553 case ISD::SETGT: 554 case ISD::SETGE: 555 // True if the sign bit of C2 is set. 556 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 557 case ISD::SETLT: 558 case ISD::SETLE: 559 // True if the sign bit of C2 isn't set. 560 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 561 default: 562 break; 563 } 564 } 565 566 // Otherwise, we can perform the comparison with the low bits. 567 switch (Cond) { 568 case ISD::SETEQ: 569 case ISD::SETNE: 570 case ISD::SETUGT: 571 case ISD::SETUGE: 572 case ISD::SETULT: 573 case ISD::SETULE: 574 return getSetCC(VT, N1.getOperand(0), 575 getConstant(C2, N1.getOperand(0).getValueType()), 576 Cond); 577 default: 578 break; // todo, be more careful with signed comparisons 579 } 580 } 581 582 uint64_t MinVal, MaxVal; 583 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 584 if (ISD::isSignedIntSetCC(Cond)) { 585 MinVal = 1ULL << (OperandBitSize-1); 586 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 587 MaxVal = ~0ULL >> (65-OperandBitSize); 588 else 589 MaxVal = 0; 590 } else { 591 MinVal = 0; 592 MaxVal = ~0ULL >> (64-OperandBitSize); 593 } 594 595 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 596 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 597 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 598 --C2; // X >= C1 --> X > (C1-1) 599 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 600 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 601 } 602 603 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 604 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 605 ++C2; // X <= C1 --> X < (C1+1) 606 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 607 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 608 } 609 610 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 611 return getConstant(0, VT); // X < MIN --> false 612 613 // Canonicalize setgt X, Min --> setne X, Min 614 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 615 return getSetCC(VT, N1, N2, ISD::SETNE); 616 617 // If we have setult X, 1, turn it into seteq X, 0 618 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 619 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 620 ISD::SETEQ); 621 // If we have setugt X, Max-1, turn it into seteq X, Max 622 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 623 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 624 ISD::SETEQ); 625 626 // If we have "setcc X, C1", check to see if we can shrink the immediate 627 // by changing cc. 628 629 // SETUGT X, SINTMAX -> SETLT X, 0 630 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 631 C2 == (~0ULL >> (65-OperandBitSize))) 632 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 633 634 // FIXME: Implement the rest of these. 635 636 637 // Fold bit comparisons when we can. 638 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 639 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 640 if (ConstantSDNode *AndRHS = 641 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 642 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 643 // Perform the xform if the AND RHS is a single bit. 644 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 645 return getNode(ISD::SRL, VT, N1, 646 getConstant(Log2_64(AndRHS->getValue()), 647 TLI.getShiftAmountTy())); 648 } 649 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 650 // (X & 8) == 8 --> (X & 8) >> 3 651 // Perform the xform if C2 is a single bit. 652 if ((C2 & (C2-1)) == 0) { 653 return getNode(ISD::SRL, VT, N1, 654 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 655 } 656 } 657 } 658 } 659 } else if (isa<ConstantSDNode>(N1.Val)) { 660 // Ensure that the constant occurs on the RHS. 661 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 662 } 663 664 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 665 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 666 double C1 = N1C->getValue(), C2 = N2C->getValue(); 667 668 switch (Cond) { 669 default: break; // FIXME: Implement the rest of these! 670 case ISD::SETEQ: return getConstant(C1 == C2, VT); 671 case ISD::SETNE: return getConstant(C1 != C2, VT); 672 case ISD::SETLT: return getConstant(C1 < C2, VT); 673 case ISD::SETGT: return getConstant(C1 > C2, VT); 674 case ISD::SETLE: return getConstant(C1 <= C2, VT); 675 case ISD::SETGE: return getConstant(C1 >= C2, VT); 676 } 677 } else { 678 // Ensure that the constant occurs on the RHS. 679 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 680 } 681 682 if (N1 == N2) { 683 // We can always fold X == Y for integer setcc's. 684 if (MVT::isInteger(N1.getValueType())) 685 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 686 unsigned UOF = ISD::getUnorderedFlavor(Cond); 687 if (UOF == 2) // FP operators that are undefined on NaNs. 688 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 689 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 690 return getConstant(UOF, VT); 691 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 692 // if it is not already. 693 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 694 if (NewCond != Cond) 695 return getSetCC(VT, N1, N2, NewCond); 696 } 697 698 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 699 MVT::isInteger(N1.getValueType())) { 700 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 701 N1.getOpcode() == ISD::XOR) { 702 // Simplify (X+Y) == (X+Z) --> Y == Z 703 if (N1.getOpcode() == N2.getOpcode()) { 704 if (N1.getOperand(0) == N2.getOperand(0)) 705 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 706 if (N1.getOperand(1) == N2.getOperand(1)) 707 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 708 if (isCommutativeBinOp(N1.getOpcode())) { 709 // If X op Y == Y op X, try other combinations. 710 if (N1.getOperand(0) == N2.getOperand(1)) 711 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 712 if (N1.getOperand(1) == N2.getOperand(0)) 713 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 714 } 715 } 716 717 // FIXME: move this stuff to the DAG Combiner when it exists! 718 719 // Simplify (X+Z) == X --> Z == 0 720 if (N1.getOperand(0) == N2) 721 return getSetCC(VT, N1.getOperand(1), 722 getConstant(0, N1.getValueType()), Cond); 723 if (N1.getOperand(1) == N2) { 724 if (isCommutativeBinOp(N1.getOpcode())) 725 return getSetCC(VT, N1.getOperand(0), 726 getConstant(0, N1.getValueType()), Cond); 727 else { 728 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 729 // (Z-X) == X --> Z == X<<1 730 return getSetCC(VT, N1.getOperand(0), 731 getNode(ISD::SHL, N2.getValueType(), 732 N2, getConstant(1, TLI.getShiftAmountTy())), 733 Cond); 734 } 735 } 736 } 737 738 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 739 N2.getOpcode() == ISD::XOR) { 740 // Simplify X == (X+Z) --> Z == 0 741 if (N2.getOperand(0) == N1) { 742 return getSetCC(VT, N2.getOperand(1), 743 getConstant(0, N2.getValueType()), Cond); 744 } else if (N2.getOperand(1) == N1) { 745 if (isCommutativeBinOp(N2.getOpcode())) { 746 return getSetCC(VT, N2.getOperand(0), 747 getConstant(0, N2.getValueType()), Cond); 748 } else { 749 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 750 // X == (Z-X) --> X<<1 == Z 751 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 752 getConstant(1, TLI.getShiftAmountTy())), 753 N2.getOperand(0), Cond); 754 } 755 } 756 } 757 } 758 759 // Fold away ALL boolean setcc's. 760 if (N1.getValueType() == MVT::i1) { 761 switch (Cond) { 762 default: assert(0 && "Unknown integer setcc!"); 763 case ISD::SETEQ: // X == Y -> (X^Y)^1 764 N1 = getNode(ISD::XOR, MVT::i1, 765 getNode(ISD::XOR, MVT::i1, N1, N2), 766 getConstant(1, MVT::i1)); 767 break; 768 case ISD::SETNE: // X != Y --> (X^Y) 769 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 770 break; 771 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 772 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 773 N1 = getNode(ISD::AND, MVT::i1, N2, 774 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 775 break; 776 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 777 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 778 N1 = getNode(ISD::AND, MVT::i1, N1, 779 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 780 break; 781 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 782 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 783 N1 = getNode(ISD::OR, MVT::i1, N2, 784 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 785 break; 786 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 787 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 788 N1 = getNode(ISD::OR, MVT::i1, N1, 789 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 790 break; 791 } 792 if (VT != MVT::i1) 793 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 794 return N1; 795 } 796 797 // Could not fold it. 798 return SDOperand(); 799} 800 801SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2, 802 SDOperand N3, SDOperand N4, 803 ISD::CondCode CC) { 804 MVT::ValueType VT = N3.getValueType(); 805 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 806 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 807 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 808 809 // Check to see if we can simplify the select into an fabs node 810 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 811 // Allow either -0.0 or 0.0 812 if (CFP->getValue() == 0.0) { 813 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 814 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 815 N1 == N3 && N4.getOpcode() == ISD::FNEG && 816 N1 == N4.getOperand(0)) 817 return getNode(ISD::FABS, VT, N1); 818 819 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 820 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 821 N1 == N4 && N3.getOpcode() == ISD::FNEG && 822 N3.getOperand(0) == N4) 823 return getNode(ISD::FABS, VT, N4); 824 } 825 } 826 827 // Check to see if we can perform the "gzip trick", transforming 828 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 829 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 830 MVT::isInteger(N1.getValueType()) && 831 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 832 MVT::ValueType XType = N1.getValueType(); 833 MVT::ValueType AType = N3.getValueType(); 834 if (XType >= AType) { 835 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 836 // single-bit constant. FIXME: remove once the dag combiner 837 // exists. 838 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 839 unsigned ShCtV = Log2_64(N3C->getValue()); 840 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 841 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 842 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 843 if (XType > AType) 844 Shift = getNode(ISD::TRUNCATE, AType, Shift); 845 return getNode(ISD::AND, AType, Shift, N3); 846 } 847 SDOperand Shift = getNode(ISD::SRA, XType, N1, 848 getConstant(MVT::getSizeInBits(XType)-1, 849 TLI.getShiftAmountTy())); 850 if (XType > AType) 851 Shift = getNode(ISD::TRUNCATE, AType, Shift); 852 return getNode(ISD::AND, AType, Shift, N3); 853 } 854 } 855 856 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 857 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 858 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 859 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 860 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 861 MVT::ValueType XType = N1.getValueType(); 862 if (SubC->isNullValue() && MVT::isInteger(XType)) { 863 SDOperand Shift = getNode(ISD::SRA, XType, N1, 864 getConstant(MVT::getSizeInBits(XType)-1, 865 TLI.getShiftAmountTy())); 866 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 867 Shift); 868 } 869 } 870 } 871 872 // Could not fold it. 873 return SDOperand(); 874} 875 876/// getNode - Gets or creates the specified node. 877/// 878SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 879 SDNode *N = new SDNode(Opcode, VT); 880 AllNodes.push_back(N); 881 return SDOperand(N, 0); 882} 883 884SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 885 SDOperand Operand) { 886 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 887 uint64_t Val = C->getValue(); 888 switch (Opcode) { 889 default: break; 890 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 891 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 892 case ISD::TRUNCATE: return getConstant(Val, VT); 893 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 894 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 895 } 896 } 897 898 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 899 switch (Opcode) { 900 case ISD::FNEG: 901 return getConstantFP(-C->getValue(), VT); 902 case ISD::FP_ROUND: 903 case ISD::FP_EXTEND: 904 return getConstantFP(C->getValue(), VT); 905 case ISD::FP_TO_SINT: 906 return getConstant((int64_t)C->getValue(), VT); 907 case ISD::FP_TO_UINT: 908 return getConstant((uint64_t)C->getValue(), VT); 909 } 910 911 unsigned OpOpcode = Operand.Val->getOpcode(); 912 switch (Opcode) { 913 case ISD::TokenFactor: 914 return Operand; // Factor of one node? No factor. 915 case ISD::SIGN_EXTEND: 916 if (Operand.getValueType() == VT) return Operand; // noop extension 917 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 918 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 919 break; 920 case ISD::ZERO_EXTEND: 921 if (Operand.getValueType() == VT) return Operand; // noop extension 922 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 923 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 924 break; 925 case ISD::TRUNCATE: 926 if (Operand.getValueType() == VT) return Operand; // noop truncate 927 if (OpOpcode == ISD::TRUNCATE) 928 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 929 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 930 // If the source is smaller than the dest, we still need an extend. 931 if (Operand.Val->getOperand(0).getValueType() < VT) 932 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 933 else if (Operand.Val->getOperand(0).getValueType() > VT) 934 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 935 else 936 return Operand.Val->getOperand(0); 937 } 938 break; 939 case ISD::FNEG: 940 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 941 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 942 Operand.Val->getOperand(0)); 943 if (OpOpcode == ISD::FNEG) // --X -> X 944 return Operand.Val->getOperand(0); 945 break; 946 case ISD::FABS: 947 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 948 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 949 break; 950 } 951 952 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 953 if (N) return SDOperand(N, 0); 954 N = new SDNode(Opcode, Operand); 955 N->setValueTypes(VT); 956 AllNodes.push_back(N); 957 return SDOperand(N, 0); 958} 959 960/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 961/// this predicate to simplify operations downstream. V and Mask are known to 962/// be the same type. 963static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 964 const TargetLowering &TLI) { 965 unsigned SrcBits; 966 if (Mask == 0) return true; 967 968 // If we know the result of a setcc has the top bits zero, use this info. 969 switch (Op.getOpcode()) { 970 case ISD::Constant: 971 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 972 973 case ISD::SETCC: 974 return ((Mask & 1) == 0) && 975 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 976 977 case ISD::ZEXTLOAD: 978 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 979 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 980 case ISD::ZERO_EXTEND: 981 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 982 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 983 984 case ISD::AND: 985 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 986 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 987 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 988 989 // FALL THROUGH 990 case ISD::OR: 991 case ISD::XOR: 992 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 993 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 994 case ISD::SELECT: 995 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 996 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 997 998 case ISD::SRL: 999 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 1000 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1001 uint64_t NewVal = Mask << ShAmt->getValue(); 1002 SrcBits = MVT::getSizeInBits(Op.getValueType()); 1003 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 1004 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1005 } 1006 return false; 1007 case ISD::SHL: 1008 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 1009 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1010 uint64_t NewVal = Mask >> ShAmt->getValue(); 1011 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1012 } 1013 return false; 1014 // TODO we could handle some SRA cases here. 1015 default: break; 1016 } 1017 1018 return false; 1019} 1020 1021 1022 1023SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1024 SDOperand N1, SDOperand N2) { 1025#ifndef NDEBUG 1026 switch (Opcode) { 1027 case ISD::TokenFactor: 1028 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 1029 N2.getValueType() == MVT::Other && "Invalid token factor!"); 1030 break; 1031 case ISD::AND: 1032 case ISD::OR: 1033 case ISD::XOR: 1034 case ISD::UDIV: 1035 case ISD::UREM: 1036 case ISD::MULHU: 1037 case ISD::MULHS: 1038 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 1039 // fall through 1040 case ISD::ADD: 1041 case ISD::SUB: 1042 case ISD::MUL: 1043 case ISD::SDIV: 1044 case ISD::SREM: 1045 assert(N1.getValueType() == N2.getValueType() && 1046 N1.getValueType() == VT && "Binary operator types must match!"); 1047 break; 1048 1049 case ISD::SHL: 1050 case ISD::SRA: 1051 case ISD::SRL: 1052 assert(VT == N1.getValueType() && 1053 "Shift operators return type must be the same as their first arg"); 1054 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 1055 VT != MVT::i1 && "Shifts only work on integers"); 1056 break; 1057 case ISD::FP_ROUND_INREG: { 1058 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1059 assert(VT == N1.getValueType() && "Not an inreg round!"); 1060 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 1061 "Cannot FP_ROUND_INREG integer types"); 1062 assert(EVT <= VT && "Not rounding down!"); 1063 break; 1064 } 1065 case ISD::SIGN_EXTEND_INREG: { 1066 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1067 assert(VT == N1.getValueType() && "Not an inreg extend!"); 1068 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 1069 "Cannot *_EXTEND_INREG FP types"); 1070 assert(EVT <= VT && "Not extending!"); 1071 } 1072 1073 default: break; 1074 } 1075#endif 1076 1077 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1078 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1079 if (N1C) { 1080 if (N2C) { 1081 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 1082 switch (Opcode) { 1083 case ISD::ADD: return getConstant(C1 + C2, VT); 1084 case ISD::SUB: return getConstant(C1 - C2, VT); 1085 case ISD::MUL: return getConstant(C1 * C2, VT); 1086 case ISD::UDIV: 1087 if (C2) return getConstant(C1 / C2, VT); 1088 break; 1089 case ISD::UREM : 1090 if (C2) return getConstant(C1 % C2, VT); 1091 break; 1092 case ISD::SDIV : 1093 if (C2) return getConstant(N1C->getSignExtended() / 1094 N2C->getSignExtended(), VT); 1095 break; 1096 case ISD::SREM : 1097 if (C2) return getConstant(N1C->getSignExtended() % 1098 N2C->getSignExtended(), VT); 1099 break; 1100 case ISD::AND : return getConstant(C1 & C2, VT); 1101 case ISD::OR : return getConstant(C1 | C2, VT); 1102 case ISD::XOR : return getConstant(C1 ^ C2, VT); 1103 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 1104 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 1105 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 1106 default: break; 1107 } 1108 1109 } else { // Cannonicalize constant to RHS if commutative 1110 if (isCommutativeBinOp(Opcode)) { 1111 std::swap(N1C, N2C); 1112 std::swap(N1, N2); 1113 } 1114 } 1115 1116 switch (Opcode) { 1117 default: break; 1118 case ISD::SHL: // shl 0, X -> 0 1119 if (N1C->isNullValue()) return N1; 1120 break; 1121 case ISD::SRL: // srl 0, X -> 0 1122 if (N1C->isNullValue()) return N1; 1123 break; 1124 case ISD::SRA: // sra -1, X -> -1 1125 if (N1C->isAllOnesValue()) return N1; 1126 break; 1127 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1128 // Extending a constant? Just return the extended constant. 1129 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1130 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1131 } 1132 } 1133 1134 if (N2C) { 1135 uint64_t C2 = N2C->getValue(); 1136 1137 switch (Opcode) { 1138 case ISD::ADD: 1139 if (!C2) return N1; // add X, 0 -> X 1140 break; 1141 case ISD::SUB: 1142 if (!C2) return N1; // sub X, 0 -> X 1143 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1144 case ISD::MUL: 1145 if (!C2) return N2; // mul X, 0 -> 0 1146 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1147 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1148 1149 // FIXME: Move this to the DAG combiner when it exists. 1150 if ((C2 & C2-1) == 0) { 1151 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1152 return getNode(ISD::SHL, VT, N1, ShAmt); 1153 } 1154 break; 1155 1156 case ISD::MULHU: 1157 case ISD::MULHS: 1158 if (!C2) return N2; // mul X, 0 -> 0 1159 1160 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1161 return getConstant(0, VT); 1162 1163 // Many others could be handled here, including -1, powers of 2, etc. 1164 break; 1165 1166 case ISD::UDIV: 1167 // FIXME: Move this to the DAG combiner when it exists. 1168 if ((C2 & C2-1) == 0 && C2) { 1169 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1170 return getNode(ISD::SRL, VT, N1, ShAmt); 1171 } 1172 break; 1173 1174 case ISD::SHL: 1175 case ISD::SRL: 1176 case ISD::SRA: 1177 // If the shift amount is bigger than the size of the data, then all the 1178 // bits are shifted out. Simplify to undef. 1179 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1180 return getNode(ISD::UNDEF, N1.getValueType()); 1181 } 1182 if (C2 == 0) return N1; 1183 1184 if (Opcode == ISD::SRA) { 1185 // If the sign bit is known to be zero, switch this to a SRL. 1186 if (MaskedValueIsZero(N1, 1187 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), 1188 TLI)) 1189 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1190 } else { 1191 // If the part left over is known to be zero, the whole thing is zero. 1192 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1193 if (Opcode == ISD::SRL) { 1194 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1195 return getConstant(0, N1.getValueType()); 1196 } else if (Opcode == ISD::SHL) { 1197 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1198 return getConstant(0, N1.getValueType()); 1199 } 1200 } 1201 1202 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1203 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1204 unsigned OpSAC = OpSA->getValue(); 1205 if (N1.getOpcode() == ISD::SHL) { 1206 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1207 return getConstant(0, N1.getValueType()); 1208 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1209 getConstant(C2+OpSAC, N2.getValueType())); 1210 } else if (N1.getOpcode() == ISD::SRL) { 1211 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1212 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1213 getConstant(~0ULL << OpSAC, VT)); 1214 if (C2 > OpSAC) { 1215 return getNode(ISD::SHL, VT, Mask, 1216 getConstant(C2-OpSAC, N2.getValueType())); 1217 } else { 1218 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1219 return getNode(ISD::SRL, VT, Mask, 1220 getConstant(OpSAC-C2, N2.getValueType())); 1221 } 1222 } else if (N1.getOpcode() == ISD::SRA) { 1223 // if C1 == C2, just mask out low bits. 1224 if (C2 == OpSAC) 1225 return getNode(ISD::AND, VT, N1.getOperand(0), 1226 getConstant(~0ULL << C2, VT)); 1227 } 1228 } 1229 break; 1230 1231 case ISD::AND: 1232 if (!C2) return N2; // X and 0 -> 0 1233 if (N2C->isAllOnesValue()) 1234 return N1; // X and -1 -> X 1235 1236 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1237 return getConstant(0, VT); 1238 1239 { 1240 uint64_t NotC2 = ~C2; 1241 if (VT != MVT::i64) 1242 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1243 1244 if (MaskedValueIsZero(N1, NotC2, TLI)) 1245 return N1; // if (X & ~C2) -> 0, the and is redundant 1246 } 1247 1248 // FIXME: Should add a corresponding version of this for 1249 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1250 // we don't have yet. 1251 1252 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1253 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1254 // If we are masking out the part of our input that was extended, just 1255 // mask the input to the extension directly. 1256 unsigned ExtendBits = 1257 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1258 if ((C2 & (~0ULL << ExtendBits)) == 0) 1259 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1260 } else if (N1.getOpcode() == ISD::OR) { 1261 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1262 if ((ORI->getValue() & C2) == C2) { 1263 // If the 'or' is setting all of the bits that we are masking for, 1264 // we know the result of the AND will be the AND mask itself. 1265 return N2; 1266 } 1267 } 1268 break; 1269 case ISD::OR: 1270 if (!C2)return N1; // X or 0 -> X 1271 if (N2C->isAllOnesValue()) 1272 return N2; // X or -1 -> -1 1273 break; 1274 case ISD::XOR: 1275 if (!C2) return N1; // X xor 0 -> X 1276 if (N2C->isAllOnesValue()) { 1277 if (N1.Val->getOpcode() == ISD::SETCC){ 1278 SDNode *SetCC = N1.Val; 1279 // !(X op Y) -> (X !op Y) 1280 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1281 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1282 return getSetCC(SetCC->getValueType(0), 1283 SetCC->getOperand(0), SetCC->getOperand(1), 1284 ISD::getSetCCInverse(CC, isInteger)); 1285 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1286 SDNode *Op = N1.Val; 1287 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1288 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1289 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1290 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1291 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1292 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1293 if (Op->getOpcode() == ISD::AND) 1294 return getNode(ISD::OR, VT, LHS, RHS); 1295 return getNode(ISD::AND, VT, LHS, RHS); 1296 } 1297 } 1298 // X xor -1 -> not(x) ? 1299 } 1300 break; 1301 } 1302 1303 // Reassociate ((X op C1) op C2) if possible. 1304 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1305 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1306 return getNode(Opcode, VT, N1.Val->getOperand(0), 1307 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1308 } 1309 1310 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1311 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1312 if (N1CFP) { 1313 if (N2CFP) { 1314 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1315 switch (Opcode) { 1316 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1317 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1318 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1319 case ISD::SDIV: 1320 if (C2) return getConstantFP(C1 / C2, VT); 1321 break; 1322 case ISD::SREM : 1323 if (C2) return getConstantFP(fmod(C1, C2), VT); 1324 break; 1325 default: break; 1326 } 1327 1328 } else { // Cannonicalize constant to RHS if commutative 1329 if (isCommutativeBinOp(Opcode)) { 1330 std::swap(N1CFP, N2CFP); 1331 std::swap(N1, N2); 1332 } 1333 } 1334 1335 if (Opcode == ISD::FP_ROUND_INREG) 1336 return getNode(ISD::FP_EXTEND, VT, 1337 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1338 } 1339 1340 // Finally, fold operations that do not require constants. 1341 switch (Opcode) { 1342 case ISD::TokenFactor: 1343 if (N1.getOpcode() == ISD::EntryToken) 1344 return N2; 1345 if (N2.getOpcode() == ISD::EntryToken) 1346 return N1; 1347 break; 1348 1349 case ISD::AND: 1350 case ISD::OR: 1351 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1352 SDNode *LHS = N1.Val, *RHS = N2.Val; 1353 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1354 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1355 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1356 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1357 1358 if (LR == RR && isa<ConstantSDNode>(LR) && 1359 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1360 // (X != 0) | (Y != 0) -> (X|Y != 0) 1361 // (X == 0) & (Y == 0) -> (X|Y == 0) 1362 // (X < 0) | (Y < 0) -> (X|Y < 0) 1363 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1364 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1365 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1366 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1367 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1368 Op2); 1369 1370 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1371 // (X == -1) & (Y == -1) -> (X&Y == -1) 1372 // (X != -1) | (Y != -1) -> (X&Y != -1) 1373 // (X > -1) | (Y > -1) -> (X&Y > -1) 1374 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1375 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1376 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1377 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1378 LR, Op2); 1379 // (X > -1) & (Y > -1) -> (X|Y > -1) 1380 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1381 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1382 LR, Op2); 1383 } 1384 } 1385 1386 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1387 if (LL == RR && LR == RL) { 1388 Op2 = ISD::getSetCCSwappedOperands(Op2); 1389 goto MatchedBackwards; 1390 } 1391 1392 if (LL == RL && LR == RR) { 1393 MatchedBackwards: 1394 ISD::CondCode Result; 1395 bool isInteger = MVT::isInteger(LL.getValueType()); 1396 if (Opcode == ISD::OR) 1397 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1398 else 1399 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1400 1401 if (Result != ISD::SETCC_INVALID) 1402 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1403 } 1404 } 1405 1406 // and/or zext(a), zext(b) -> zext(and/or a, b) 1407 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1408 N2.getOpcode() == ISD::ZERO_EXTEND && 1409 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1410 return getNode(ISD::ZERO_EXTEND, VT, 1411 getNode(Opcode, N1.getOperand(0).getValueType(), 1412 N1.getOperand(0), N2.getOperand(0))); 1413 break; 1414 case ISD::XOR: 1415 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1416 break; 1417 case ISD::ADD: 1418 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1419 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1420 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1421 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1422 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1423 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1424 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1425 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1426 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1427 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1428 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1429 !MVT::isFloatingPoint(N2.getValueType())) 1430 return N2.Val->getOperand(0); // A+(B-A) -> B 1431 break; 1432 case ISD::SUB: 1433 if (N1.getOpcode() == ISD::ADD) { 1434 if (N1.Val->getOperand(0) == N2 && 1435 !MVT::isFloatingPoint(N2.getValueType())) 1436 return N1.Val->getOperand(1); // (A+B)-A == B 1437 if (N1.Val->getOperand(1) == N2 && 1438 !MVT::isFloatingPoint(N2.getValueType())) 1439 return N1.Val->getOperand(0); // (A+B)-B == A 1440 } 1441 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1442 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1443 break; 1444 case ISD::FP_ROUND_INREG: 1445 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1446 break; 1447 case ISD::SIGN_EXTEND_INREG: { 1448 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1449 if (EVT == VT) return N1; // Not actually extending 1450 1451 // If we are sign extending an extension, use the original source. 1452 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1453 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1454 return N1; 1455 1456 // If we are sign extending a sextload, return just the load. 1457 if (N1.getOpcode() == ISD::SEXTLOAD) 1458 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1459 return N1; 1460 1461 // If we are extending the result of a setcc, and we already know the 1462 // contents of the top bits, eliminate the extension. 1463 if (N1.getOpcode() == ISD::SETCC && 1464 TLI.getSetCCResultContents() == 1465 TargetLowering::ZeroOrNegativeOneSetCCResult) 1466 return N1; 1467 1468 // If we are sign extending the result of an (and X, C) operation, and we 1469 // know the extended bits are zeros already, don't do the extend. 1470 if (N1.getOpcode() == ISD::AND) 1471 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1472 uint64_t Mask = N1C->getValue(); 1473 unsigned NumBits = MVT::getSizeInBits(EVT); 1474 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1475 return N1; 1476 } 1477 break; 1478 } 1479 1480 // FIXME: figure out how to safely handle things like 1481 // int foo(int x) { return 1 << (x & 255); } 1482 // int bar() { return foo(256); } 1483#if 0 1484 case ISD::SHL: 1485 case ISD::SRL: 1486 case ISD::SRA: 1487 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1488 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1489 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1490 else if (N2.getOpcode() == ISD::AND) 1491 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1492 // If the and is only masking out bits that cannot effect the shift, 1493 // eliminate the and. 1494 unsigned NumBits = MVT::getSizeInBits(VT); 1495 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1496 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1497 } 1498 break; 1499#endif 1500 } 1501 1502 // Memoize this node if possible. 1503 SDNode *N; 1504 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1505 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1506 if (BON) return SDOperand(BON, 0); 1507 1508 BON = N = new SDNode(Opcode, N1, N2); 1509 } else { 1510 N = new SDNode(Opcode, N1, N2); 1511 } 1512 1513 N->setValueTypes(VT); 1514 AllNodes.push_back(N); 1515 return SDOperand(N, 0); 1516} 1517 1518// setAdjCallChain - This method changes the token chain of an 1519// CALLSEQ_START/END node to be the specified operand. 1520void SDNode::setAdjCallChain(SDOperand N) { 1521 assert(N.getValueType() == MVT::Other); 1522 assert((getOpcode() == ISD::CALLSEQ_START || 1523 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1524 1525 Operands[0].Val->removeUser(this); 1526 Operands[0] = N; 1527 N.Val->Uses.push_back(this); 1528} 1529 1530 1531 1532SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1533 SDOperand Chain, SDOperand Ptr, 1534 SDOperand SV) { 1535 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1536 if (N) return SDOperand(N, 0); 1537 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1538 1539 // Loads have a token chain. 1540 N->setValueTypes(VT, MVT::Other); 1541 AllNodes.push_back(N); 1542 return SDOperand(N, 0); 1543} 1544 1545 1546SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1547 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1548 MVT::ValueType EVT) { 1549 std::vector<SDOperand> Ops; 1550 Ops.reserve(4); 1551 Ops.push_back(Chain); 1552 Ops.push_back(Ptr); 1553 Ops.push_back(SV); 1554 Ops.push_back(getValueType(EVT)); 1555 std::vector<MVT::ValueType> VTs; 1556 VTs.reserve(2); 1557 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1558 return getNode(Opcode, VTs, Ops); 1559} 1560 1561SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1562 SDOperand N1, SDOperand N2, SDOperand N3) { 1563 // Perform various simplifications. 1564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1565 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1566 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1567 switch (Opcode) { 1568 case ISD::SETCC: { 1569 // Use SimplifySetCC to simplify SETCC's. 1570 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1571 if (Simp.Val) return Simp; 1572 break; 1573 } 1574 case ISD::SELECT: 1575 if (N1C) 1576 if (N1C->getValue()) 1577 return N2; // select true, X, Y -> X 1578 else 1579 return N3; // select false, X, Y -> Y 1580 1581 if (N2 == N3) return N2; // select C, X, X -> X 1582 1583 if (VT == MVT::i1) { // Boolean SELECT 1584 if (N2C) { 1585 if (N2C->getValue()) // select C, 1, X -> C | X 1586 return getNode(ISD::OR, VT, N1, N3); 1587 else // select C, 0, X -> ~C & X 1588 return getNode(ISD::AND, VT, 1589 getNode(ISD::XOR, N1.getValueType(), N1, 1590 getConstant(1, N1.getValueType())), N3); 1591 } else if (N3C) { 1592 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1593 return getNode(ISD::OR, VT, 1594 getNode(ISD::XOR, N1.getValueType(), N1, 1595 getConstant(1, N1.getValueType())), N2); 1596 else // select C, X, 0 -> C & X 1597 return getNode(ISD::AND, VT, N1, N2); 1598 } 1599 1600 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1601 return getNode(ISD::OR, VT, N1, N3); 1602 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1603 return getNode(ISD::AND, VT, N1, N2); 1604 } 1605 if (N1.getOpcode() == ISD::SETCC) { 1606 SDOperand Simp = SimplifySelectCC(N1.getOperand(0), N1.getOperand(1), N2, 1607 N3, cast<CondCodeSDNode>(N1.getOperand(2))->get()); 1608 if (Simp.Val) return Simp; 1609 } 1610 break; 1611 case ISD::BRCOND: 1612 if (N2C) 1613 if (N2C->getValue()) // Unconditional branch 1614 return getNode(ISD::BR, MVT::Other, N1, N3); 1615 else 1616 return N1; // Never-taken branch 1617 break; 1618 } 1619 1620 std::vector<SDOperand> Ops; 1621 Ops.reserve(3); 1622 Ops.push_back(N1); 1623 Ops.push_back(N2); 1624 Ops.push_back(N3); 1625 1626 // Memoize nodes. 1627 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1628 if (N) return SDOperand(N, 0); 1629 1630 N = new SDNode(Opcode, N1, N2, N3); 1631 N->setValueTypes(VT); 1632 AllNodes.push_back(N); 1633 return SDOperand(N, 0); 1634} 1635 1636SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1637 SDOperand N1, SDOperand N2, SDOperand N3, 1638 SDOperand N4) { 1639 std::vector<SDOperand> Ops; 1640 Ops.reserve(4); 1641 Ops.push_back(N1); 1642 Ops.push_back(N2); 1643 Ops.push_back(N3); 1644 Ops.push_back(N4); 1645 return getNode(Opcode, VT, Ops); 1646} 1647 1648SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1649 SDOperand N1, SDOperand N2, SDOperand N3, 1650 SDOperand N4, SDOperand N5) { 1651 if (ISD::SELECT_CC == Opcode) { 1652 assert(N1.getValueType() == N2.getValueType() && 1653 "LHS and RHS of condition must have same type!"); 1654 assert(N3.getValueType() == N4.getValueType() && 1655 "True and False arms of SelectCC must have same type!"); 1656 assert(N3.getValueType() == VT && 1657 "select_cc node must be of same type as true and false value!"); 1658 SDOperand Simp = SimplifySelectCC(N1, N2, N3, N4, 1659 cast<CondCodeSDNode>(N5)->get()); 1660 if (Simp.Val) return Simp; 1661 } 1662 1663 std::vector<SDOperand> Ops; 1664 Ops.reserve(5); 1665 Ops.push_back(N1); 1666 Ops.push_back(N2); 1667 Ops.push_back(N3); 1668 Ops.push_back(N4); 1669 Ops.push_back(N5); 1670 return getNode(Opcode, VT, Ops); 1671} 1672 1673 1674SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1675 assert((!V || isa<PointerType>(V->getType())) && 1676 "SrcValue is not a pointer?"); 1677 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1678 if (N) return SDOperand(N, 0); 1679 1680 N = new SrcValueSDNode(V, Offset); 1681 AllNodes.push_back(N); 1682 return SDOperand(N, 0); 1683} 1684 1685SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1686 std::vector<SDOperand> &Ops) { 1687 switch (Ops.size()) { 1688 case 0: return getNode(Opcode, VT); 1689 case 1: return getNode(Opcode, VT, Ops[0]); 1690 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1691 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1692 default: break; 1693 } 1694 1695 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1696 switch (Opcode) { 1697 default: break; 1698 case ISD::BRCONDTWOWAY: 1699 if (N1C) 1700 if (N1C->getValue()) // Unconditional branch to true dest. 1701 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1702 else // Unconditional branch to false dest. 1703 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1704 break; 1705 case ISD::BRTWOWAY_CC: 1706 assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); 1707 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1708 "LHS and RHS of comparison must have same type!"); 1709 break; 1710 case ISD::TRUNCSTORE: { 1711 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1712 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1713#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1714 // If this is a truncating store of a constant, convert to the desired type 1715 // and store it instead. 1716 if (isa<Constant>(Ops[0])) { 1717 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1718 if (isa<Constant>(Op)) 1719 N1 = Op; 1720 } 1721 // Also for ConstantFP? 1722#endif 1723 if (Ops[0].getValueType() == EVT) // Normal store? 1724 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1725 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1726 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1727 "Can't do FP-INT conversion!"); 1728 break; 1729 } 1730 } 1731 1732 // Memoize nodes. 1733 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1734 if (N) return SDOperand(N, 0); 1735 N = new SDNode(Opcode, Ops); 1736 N->setValueTypes(VT); 1737 AllNodes.push_back(N); 1738 return SDOperand(N, 0); 1739} 1740 1741SDOperand SelectionDAG::getNode(unsigned Opcode, 1742 std::vector<MVT::ValueType> &ResultTys, 1743 std::vector<SDOperand> &Ops) { 1744 if (ResultTys.size() == 1) 1745 return getNode(Opcode, ResultTys[0], Ops); 1746 1747 switch (Opcode) { 1748 case ISD::EXTLOAD: 1749 case ISD::SEXTLOAD: 1750 case ISD::ZEXTLOAD: { 1751 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1752 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1753 // If they are asking for an extending load from/to the same thing, return a 1754 // normal load. 1755 if (ResultTys[0] == EVT) 1756 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1757 assert(EVT < ResultTys[0] && 1758 "Should only be an extending load, not truncating!"); 1759 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1760 "Cannot sign/zero extend a FP load!"); 1761 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1762 "Cannot convert from FP to Int or Int -> FP!"); 1763 break; 1764 } 1765 1766 // FIXME: figure out how to safely handle things like 1767 // int foo(int x) { return 1 << (x & 255); } 1768 // int bar() { return foo(256); } 1769#if 0 1770 case ISD::SRA_PARTS: 1771 case ISD::SRL_PARTS: 1772 case ISD::SHL_PARTS: 1773 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1774 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1775 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1776 else if (N3.getOpcode() == ISD::AND) 1777 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1778 // If the and is only masking out bits that cannot effect the shift, 1779 // eliminate the and. 1780 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1781 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1782 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1783 } 1784 break; 1785#endif 1786 } 1787 1788 // Memoize the node. 1789 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1790 Ops))]; 1791 if (N) return SDOperand(N, 0); 1792 N = new SDNode(Opcode, Ops); 1793 N->setValueTypes(ResultTys); 1794 AllNodes.push_back(N); 1795 return SDOperand(N, 0); 1796} 1797 1798 1799/// SelectNodeTo - These are used for target selectors to *mutate* the 1800/// specified node to have the specified return type, Target opcode, and 1801/// operands. Note that target opcodes are stored as 1802/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. 1803void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1804 unsigned TargetOpc, SDOperand Op1) { 1805 RemoveNodeFromCSEMaps(N); 1806 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1807 N->setValueTypes(VT); 1808 N->setOperands(Op1); 1809} 1810void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1811 unsigned TargetOpc, SDOperand Op1, 1812 SDOperand Op2) { 1813 RemoveNodeFromCSEMaps(N); 1814 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1815 N->setValueTypes(VT); 1816 N->setOperands(Op1, Op2); 1817} 1818void SelectionDAG::SelectNodeTo(SDNode *N, 1819 MVT::ValueType VT1, MVT::ValueType VT2, 1820 unsigned TargetOpc, SDOperand Op1, 1821 SDOperand Op2) { 1822 RemoveNodeFromCSEMaps(N); 1823 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1824 N->setValueTypes(VT1, VT2); 1825 N->setOperands(Op1, Op2); 1826} 1827void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1828 unsigned TargetOpc, SDOperand Op1, 1829 SDOperand Op2, SDOperand Op3) { 1830 RemoveNodeFromCSEMaps(N); 1831 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1832 N->setValueTypes(VT); 1833 N->setOperands(Op1, Op2, Op3); 1834} 1835void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT1, 1836 MVT::ValueType VT2, 1837 unsigned TargetOpc, SDOperand Op1, 1838 SDOperand Op2, SDOperand Op3) { 1839 RemoveNodeFromCSEMaps(N); 1840 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1841 N->setValueTypes(VT1, VT2); 1842 N->setOperands(Op1, Op2, Op3); 1843} 1844 1845void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1846 unsigned TargetOpc, SDOperand Op1, 1847 SDOperand Op2, SDOperand Op3, SDOperand Op4) { 1848 RemoveNodeFromCSEMaps(N); 1849 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1850 N->setValueTypes(VT); 1851 N->setOperands(Op1, Op2, Op3, Op4); 1852} 1853void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1854 unsigned TargetOpc, SDOperand Op1, 1855 SDOperand Op2, SDOperand Op3, SDOperand Op4, 1856 SDOperand Op5) { 1857 RemoveNodeFromCSEMaps(N); 1858 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1859 N->setValueTypes(VT); 1860 N->setOperands(Op1, Op2, Op3, Op4, Op5); 1861} 1862 1863/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 1864/// This can cause recursive merging of nodes in the DAG. 1865/// 1866void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) { 1867 assert(From != To && "Cannot replace uses of with self"); 1868 while (!From->use_empty()) { 1869 // Process users until they are all gone. 1870 SDNode *U = *From->use_begin(); 1871 1872 // This node is about to morph, remove its old self from the CSE maps. 1873 RemoveNodeFromCSEMaps(U); 1874 1875 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 1876 if (U->getOperand(i).Val == From) { 1877 assert(From->getValueType(U->getOperand(i).ResNo) == 1878 To->getValueType(U->getOperand(i).ResNo)); 1879 From->removeUser(U); 1880 U->Operands[i].Val = To; 1881 To->addUser(U); 1882 } 1883 1884 // Now that we have modified U, add it back to the CSE maps. If it already 1885 // exists there, recursively merge the results together. 1886 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 1887 ReplaceAllUsesWith(U, Existing); 1888 // U is now dead. 1889 } 1890} 1891 1892//===----------------------------------------------------------------------===// 1893// SDNode Class 1894//===----------------------------------------------------------------------===// 1895 1896/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1897/// indicated value. This method ignores uses of other values defined by this 1898/// operation. 1899bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1900 assert(Value < getNumValues() && "Bad value!"); 1901 1902 // If there is only one value, this is easy. 1903 if (getNumValues() == 1) 1904 return use_size() == NUses; 1905 if (Uses.size() < NUses) return false; 1906 1907 SDOperand TheValue(this, Value); 1908 1909 std::set<SDNode*> UsersHandled; 1910 1911 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1912 UI != E; ++UI) { 1913 SDNode *User = *UI; 1914 if (User->getNumOperands() == 1 || 1915 UsersHandled.insert(User).second) // First time we've seen this? 1916 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1917 if (User->getOperand(i) == TheValue) { 1918 if (NUses == 0) 1919 return false; // too many uses 1920 --NUses; 1921 } 1922 } 1923 1924 // Found exactly the right number of uses? 1925 return NUses == 0; 1926} 1927 1928 1929const char *SDNode::getOperationName(const SelectionDAG *G) const { 1930 switch (getOpcode()) { 1931 default: 1932 if (getOpcode() < ISD::BUILTIN_OP_END) 1933 return "<<Unknown DAG Node>>"; 1934 else { 1935 if (G) 1936 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 1937 return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); 1938 return "<<Unknown Target Node>>"; 1939 } 1940 1941 case ISD::PCMARKER: return "PCMarker"; 1942 case ISD::SRCVALUE: return "SrcValue"; 1943 case ISD::VALUETYPE: return "ValueType"; 1944 case ISD::EntryToken: return "EntryToken"; 1945 case ISD::TokenFactor: return "TokenFactor"; 1946 case ISD::Constant: return "Constant"; 1947 case ISD::TargetConstant: return "TargetConstant"; 1948 case ISD::ConstantFP: return "ConstantFP"; 1949 case ISD::GlobalAddress: return "GlobalAddress"; 1950 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 1951 case ISD::FrameIndex: return "FrameIndex"; 1952 case ISD::BasicBlock: return "BasicBlock"; 1953 case ISD::Register: return "Register"; 1954 case ISD::ExternalSymbol: return "ExternalSymbol"; 1955 case ISD::ConstantPool: return "ConstantPoolIndex"; 1956 case ISD::CopyToReg: return "CopyToReg"; 1957 case ISD::CopyFromReg: return "CopyFromReg"; 1958 case ISD::ImplicitDef: return "ImplicitDef"; 1959 case ISD::UNDEF: return "undef"; 1960 1961 // Unary operators 1962 case ISD::FABS: return "fabs"; 1963 case ISD::FNEG: return "fneg"; 1964 case ISD::FSQRT: return "fsqrt"; 1965 case ISD::FSIN: return "fsin"; 1966 case ISD::FCOS: return "fcos"; 1967 1968 // Binary operators 1969 case ISD::ADD: return "add"; 1970 case ISD::SUB: return "sub"; 1971 case ISD::MUL: return "mul"; 1972 case ISD::MULHU: return "mulhu"; 1973 case ISD::MULHS: return "mulhs"; 1974 case ISD::SDIV: return "sdiv"; 1975 case ISD::UDIV: return "udiv"; 1976 case ISD::SREM: return "srem"; 1977 case ISD::UREM: return "urem"; 1978 case ISD::AND: return "and"; 1979 case ISD::OR: return "or"; 1980 case ISD::XOR: return "xor"; 1981 case ISD::SHL: return "shl"; 1982 case ISD::SRA: return "sra"; 1983 case ISD::SRL: return "srl"; 1984 1985 case ISD::SETCC: return "setcc"; 1986 case ISD::SELECT: return "select"; 1987 case ISD::SELECT_CC: return "select_cc"; 1988 case ISD::ADD_PARTS: return "add_parts"; 1989 case ISD::SUB_PARTS: return "sub_parts"; 1990 case ISD::SHL_PARTS: return "shl_parts"; 1991 case ISD::SRA_PARTS: return "sra_parts"; 1992 case ISD::SRL_PARTS: return "srl_parts"; 1993 1994 // Conversion operators. 1995 case ISD::SIGN_EXTEND: return "sign_extend"; 1996 case ISD::ZERO_EXTEND: return "zero_extend"; 1997 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 1998 case ISD::TRUNCATE: return "truncate"; 1999 case ISD::FP_ROUND: return "fp_round"; 2000 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 2001 case ISD::FP_EXTEND: return "fp_extend"; 2002 2003 case ISD::SINT_TO_FP: return "sint_to_fp"; 2004 case ISD::UINT_TO_FP: return "uint_to_fp"; 2005 case ISD::FP_TO_SINT: return "fp_to_sint"; 2006 case ISD::FP_TO_UINT: return "fp_to_uint"; 2007 2008 // Control flow instructions 2009 case ISD::BR: return "br"; 2010 case ISD::BRCOND: return "brcond"; 2011 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 2012 case ISD::BR_CC: return "br_cc"; 2013 case ISD::BRTWOWAY_CC: return "brtwoway_cc"; 2014 case ISD::RET: return "ret"; 2015 case ISD::CALL: return "call"; 2016 case ISD::TAILCALL:return "tailcall"; 2017 case ISD::CALLSEQ_START: return "callseq_start"; 2018 case ISD::CALLSEQ_END: return "callseq_end"; 2019 2020 // Other operators 2021 case ISD::LOAD: return "load"; 2022 case ISD::STORE: return "store"; 2023 case ISD::EXTLOAD: return "extload"; 2024 case ISD::SEXTLOAD: return "sextload"; 2025 case ISD::ZEXTLOAD: return "zextload"; 2026 case ISD::TRUNCSTORE: return "truncstore"; 2027 2028 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 2029 case ISD::EXTRACT_ELEMENT: return "extract_element"; 2030 case ISD::BUILD_PAIR: return "build_pair"; 2031 case ISD::MEMSET: return "memset"; 2032 case ISD::MEMCPY: return "memcpy"; 2033 case ISD::MEMMOVE: return "memmove"; 2034 2035 // Bit counting 2036 case ISD::CTPOP: return "ctpop"; 2037 case ISD::CTTZ: return "cttz"; 2038 case ISD::CTLZ: return "ctlz"; 2039 2040 // IO Intrinsics 2041 case ISD::READPORT: return "readport"; 2042 case ISD::WRITEPORT: return "writeport"; 2043 case ISD::READIO: return "readio"; 2044 case ISD::WRITEIO: return "writeio"; 2045 2046 case ISD::CONDCODE: 2047 switch (cast<CondCodeSDNode>(this)->get()) { 2048 default: assert(0 && "Unknown setcc condition!"); 2049 case ISD::SETOEQ: return "setoeq"; 2050 case ISD::SETOGT: return "setogt"; 2051 case ISD::SETOGE: return "setoge"; 2052 case ISD::SETOLT: return "setolt"; 2053 case ISD::SETOLE: return "setole"; 2054 case ISD::SETONE: return "setone"; 2055 2056 case ISD::SETO: return "seto"; 2057 case ISD::SETUO: return "setuo"; 2058 case ISD::SETUEQ: return "setue"; 2059 case ISD::SETUGT: return "setugt"; 2060 case ISD::SETUGE: return "setuge"; 2061 case ISD::SETULT: return "setult"; 2062 case ISD::SETULE: return "setule"; 2063 case ISD::SETUNE: return "setune"; 2064 2065 case ISD::SETEQ: return "seteq"; 2066 case ISD::SETGT: return "setgt"; 2067 case ISD::SETGE: return "setge"; 2068 case ISD::SETLT: return "setlt"; 2069 case ISD::SETLE: return "setle"; 2070 case ISD::SETNE: return "setne"; 2071 } 2072 } 2073} 2074 2075void SDNode::dump() const { dump(0); } 2076void SDNode::dump(const SelectionDAG *G) const { 2077 std::cerr << (void*)this << ": "; 2078 2079 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 2080 if (i) std::cerr << ","; 2081 if (getValueType(i) == MVT::Other) 2082 std::cerr << "ch"; 2083 else 2084 std::cerr << MVT::getValueTypeString(getValueType(i)); 2085 } 2086 std::cerr << " = " << getOperationName(G); 2087 2088 std::cerr << " "; 2089 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 2090 if (i) std::cerr << ", "; 2091 std::cerr << (void*)getOperand(i).Val; 2092 if (unsigned RN = getOperand(i).ResNo) 2093 std::cerr << ":" << RN; 2094 } 2095 2096 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 2097 std::cerr << "<" << CSDN->getValue() << ">"; 2098 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 2099 std::cerr << "<" << CSDN->getValue() << ">"; 2100 } else if (const GlobalAddressSDNode *GADN = 2101 dyn_cast<GlobalAddressSDNode>(this)) { 2102 std::cerr << "<"; 2103 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 2104 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 2105 std::cerr << "<" << FIDN->getIndex() << ">"; 2106 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 2107 std::cerr << "<" << CP->getIndex() << ">"; 2108 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 2109 std::cerr << "<"; 2110 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 2111 if (LBB) 2112 std::cerr << LBB->getName() << " "; 2113 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 2114 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 2115 if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) { 2116 std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg()); 2117 } else { 2118 std::cerr << " #" << R->getReg(); 2119 } 2120 } else if (const ExternalSymbolSDNode *ES = 2121 dyn_cast<ExternalSymbolSDNode>(this)) { 2122 std::cerr << "'" << ES->getSymbol() << "'"; 2123 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 2124 if (M->getValue()) 2125 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 2126 else 2127 std::cerr << "<null:" << M->getOffset() << ">"; 2128 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 2129 std::cerr << ":" << getValueTypeString(N->getVT()); 2130 } 2131} 2132 2133static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) { 2134 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 2135 if (N->getOperand(i).Val->hasOneUse()) 2136 DumpNodes(N->getOperand(i).Val, indent+2, G); 2137 else 2138 std::cerr << "\n" << std::string(indent+2, ' ') 2139 << (void*)N->getOperand(i).Val << ": <multiple use>"; 2140 2141 2142 std::cerr << "\n" << std::string(indent, ' '); 2143 N->dump(G); 2144} 2145 2146void SelectionDAG::dump() const { 2147 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 2148 std::vector<SDNode*> Nodes(AllNodes); 2149 std::sort(Nodes.begin(), Nodes.end()); 2150 2151 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 2152 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 2153 DumpNodes(Nodes[i], 2, this); 2154 } 2155 2156 DumpNodes(getRoot().Val, 2, this); 2157 2158 std::cerr << "\n\n"; 2159} 2160 2161