SelectionDAG.cpp revision f90b2a7742ddeddc448586cc050818a664419e74
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13#include "llvm/CodeGen/SelectionDAG.h" 14#include "llvm/Constants.h" 15#include "llvm/Analysis/ValueTracking.h" 16#include "llvm/GlobalAlias.h" 17#include "llvm/GlobalVariable.h" 18#include "llvm/Intrinsics.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Assembly/Writer.h" 21#include "llvm/CallingConv.h" 22#include "llvm/CodeGen/MachineBasicBlock.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineModuleInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/Target/TargetData.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SetVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/StringExtras.h" 41#include <algorithm> 42#include <cmath> 43using namespace llvm; 44 45/// makeVTList - Return an instance of the SDVTList struct initialized with the 46/// specified members. 47static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { 48 SDVTList Res = {VTs, NumVTs}; 49 return Res; 50} 51 52static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { 53 switch (VT.getSimpleVT()) { 54 default: assert(0 && "Unknown FP format"); 55 case MVT::f32: return &APFloat::IEEEsingle; 56 case MVT::f64: return &APFloat::IEEEdouble; 57 case MVT::f80: return &APFloat::x87DoubleExtended; 58 case MVT::f128: return &APFloat::IEEEquad; 59 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 60 } 61} 62 63SelectionDAG::DAGUpdateListener::~DAGUpdateListener() {} 64 65//===----------------------------------------------------------------------===// 66// ConstantFPSDNode Class 67//===----------------------------------------------------------------------===// 68 69/// isExactlyValue - We don't rely on operator== working on double values, as 70/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 71/// As such, this method can be used to do an exact bit-for-bit comparison of 72/// two floating point values. 73bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { 74 return getValueAPF().bitwiseIsEqual(V); 75} 76 77bool ConstantFPSDNode::isValueValidForType(MVT VT, 78 const APFloat& Val) { 79 assert(VT.isFloatingPoint() && "Can only convert between FP types"); 80 81 // PPC long double cannot be converted to any other type. 82 if (VT == MVT::ppcf128 || 83 &Val.getSemantics() == &APFloat::PPCDoubleDouble) 84 return false; 85 86 // convert modifies in place, so make a copy. 87 APFloat Val2 = APFloat(Val); 88 bool losesInfo; 89 (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, 90 &losesInfo); 91 return !losesInfo; 92} 93 94//===----------------------------------------------------------------------===// 95// ISD Namespace 96//===----------------------------------------------------------------------===// 97 98/// isBuildVectorAllOnes - Return true if the specified node is a 99/// BUILD_VECTOR where all of the elements are ~0 or undef. 100bool ISD::isBuildVectorAllOnes(const SDNode *N) { 101 // Look through a bit convert. 102 if (N->getOpcode() == ISD::BIT_CONVERT) 103 N = N->getOperand(0).getNode(); 104 105 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 106 107 unsigned i = 0, e = N->getNumOperands(); 108 109 // Skip over all of the undef values. 110 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 111 ++i; 112 113 // Do not accept an all-undef vector. 114 if (i == e) return false; 115 116 // Do not accept build_vectors that aren't all constants or which have non-~0 117 // elements. 118 SDValue NotZero = N->getOperand(i); 119 if (isa<ConstantSDNode>(NotZero)) { 120 if (!cast<ConstantSDNode>(NotZero)->isAllOnesValue()) 121 return false; 122 } else if (isa<ConstantFPSDNode>(NotZero)) { 123 if (!cast<ConstantFPSDNode>(NotZero)->getValueAPF(). 124 bitcastToAPInt().isAllOnesValue()) 125 return false; 126 } else 127 return false; 128 129 // Okay, we have at least one ~0 value, check to see if the rest match or are 130 // undefs. 131 for (++i; i != e; ++i) 132 if (N->getOperand(i) != NotZero && 133 N->getOperand(i).getOpcode() != ISD::UNDEF) 134 return false; 135 return true; 136} 137 138 139/// isBuildVectorAllZeros - Return true if the specified node is a 140/// BUILD_VECTOR where all of the elements are 0 or undef. 141bool ISD::isBuildVectorAllZeros(const SDNode *N) { 142 // Look through a bit convert. 143 if (N->getOpcode() == ISD::BIT_CONVERT) 144 N = N->getOperand(0).getNode(); 145 146 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; 147 148 unsigned i = 0, e = N->getNumOperands(); 149 150 // Skip over all of the undef values. 151 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 152 ++i; 153 154 // Do not accept an all-undef vector. 155 if (i == e) return false; 156 157 // Do not accept build_vectors that aren't all constants or which have non-~0 158 // elements. 159 SDValue Zero = N->getOperand(i); 160 if (isa<ConstantSDNode>(Zero)) { 161 if (!cast<ConstantSDNode>(Zero)->isNullValue()) 162 return false; 163 } else if (isa<ConstantFPSDNode>(Zero)) { 164 if (!cast<ConstantFPSDNode>(Zero)->getValueAPF().isPosZero()) 165 return false; 166 } else 167 return false; 168 169 // Okay, we have at least one ~0 value, check to see if the rest match or are 170 // undefs. 171 for (++i; i != e; ++i) 172 if (N->getOperand(i) != Zero && 173 N->getOperand(i).getOpcode() != ISD::UNDEF) 174 return false; 175 return true; 176} 177 178/// isScalarToVector - Return true if the specified node is a 179/// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low 180/// element is not an undef. 181bool ISD::isScalarToVector(const SDNode *N) { 182 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) 183 return true; 184 185 if (N->getOpcode() != ISD::BUILD_VECTOR) 186 return false; 187 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 188 return false; 189 unsigned NumElems = N->getNumOperands(); 190 for (unsigned i = 1; i < NumElems; ++i) { 191 SDValue V = N->getOperand(i); 192 if (V.getOpcode() != ISD::UNDEF) 193 return false; 194 } 195 return true; 196} 197 198 199/// isDebugLabel - Return true if the specified node represents a debug 200/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). 201bool ISD::isDebugLabel(const SDNode *N) { 202 SDValue Zero; 203 if (N->getOpcode() == ISD::DBG_LABEL) 204 return true; 205 if (N->isMachineOpcode() && 206 N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL) 207 return true; 208 return false; 209} 210 211/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 212/// when given the operation for (X op Y). 213ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 214 // To perform this operation, we just need to swap the L and G bits of the 215 // operation. 216 unsigned OldL = (Operation >> 2) & 1; 217 unsigned OldG = (Operation >> 1) & 1; 218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 219 (OldL << 1) | // New G bit 220 (OldG << 2)); // New L bit. 221} 222 223/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 224/// 'op' is a valid SetCC operation. 225ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 226 unsigned Operation = Op; 227 if (isInteger) 228 Operation ^= 7; // Flip L, G, E bits, but not U. 229 else 230 Operation ^= 15; // Flip all of the condition bits. 231 232 if (Operation > ISD::SETTRUE2) 233 Operation &= ~8; // Don't let N and U bits get set. 234 235 return ISD::CondCode(Operation); 236} 237 238 239/// isSignedOp - For an integer comparison, return 1 if the comparison is a 240/// signed operation and 2 if the result is an unsigned comparison. Return zero 241/// if the operation does not depend on the sign of the input (setne and seteq). 242static int isSignedOp(ISD::CondCode Opcode) { 243 switch (Opcode) { 244 default: assert(0 && "Illegal integer setcc operation!"); 245 case ISD::SETEQ: 246 case ISD::SETNE: return 0; 247 case ISD::SETLT: 248 case ISD::SETLE: 249 case ISD::SETGT: 250 case ISD::SETGE: return 1; 251 case ISD::SETULT: 252 case ISD::SETULE: 253 case ISD::SETUGT: 254 case ISD::SETUGE: return 2; 255 } 256} 257 258/// getSetCCOrOperation - Return the result of a logical OR between different 259/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 260/// returns SETCC_INVALID if it is not possible to represent the resultant 261/// comparison. 262ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 263 bool isInteger) { 264 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 265 // Cannot fold a signed integer setcc with an unsigned integer setcc. 266 return ISD::SETCC_INVALID; 267 268 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 269 270 // If the N and U bits get set then the resultant comparison DOES suddenly 271 // care about orderedness, and is true when ordered. 272 if (Op > ISD::SETTRUE2) 273 Op &= ~16; // Clear the U bit if the N bit is set. 274 275 // Canonicalize illegal integer setcc's. 276 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 277 Op = ISD::SETNE; 278 279 return ISD::CondCode(Op); 280} 281 282/// getSetCCAndOperation - Return the result of a logical AND between different 283/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 284/// function returns zero if it is not possible to represent the resultant 285/// comparison. 286ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 287 bool isInteger) { 288 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 289 // Cannot fold a signed setcc with an unsigned setcc. 290 return ISD::SETCC_INVALID; 291 292 // Combine all of the condition bits. 293 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); 294 295 // Canonicalize illegal integer setcc's. 296 if (isInteger) { 297 switch (Result) { 298 default: break; 299 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 300 case ISD::SETOEQ: // SETEQ & SETU[LG]E 301 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE 302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 303 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE 304 } 305 } 306 307 return Result; 308} 309 310const TargetMachine &SelectionDAG::getTarget() const { 311 return MF->getTarget(); 312} 313 314//===----------------------------------------------------------------------===// 315// SDNode Profile Support 316//===----------------------------------------------------------------------===// 317 318/// AddNodeIDOpcode - Add the node opcode to the NodeID data. 319/// 320static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) { 321 ID.AddInteger(OpC); 322} 323 324/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them 325/// solely with their pointer. 326static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) { 327 ID.AddPointer(VTList.VTs); 328} 329 330/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 331/// 332static void AddNodeIDOperands(FoldingSetNodeID &ID, 333 const SDValue *Ops, unsigned NumOps) { 334 for (; NumOps; --NumOps, ++Ops) { 335 ID.AddPointer(Ops->getNode()); 336 ID.AddInteger(Ops->getResNo()); 337 } 338} 339 340/// AddNodeIDOperands - Various routines for adding operands to the NodeID data. 341/// 342static void AddNodeIDOperands(FoldingSetNodeID &ID, 343 const SDUse *Ops, unsigned NumOps) { 344 for (; NumOps; --NumOps, ++Ops) { 345 ID.AddPointer(Ops->getNode()); 346 ID.AddInteger(Ops->getResNo()); 347 } 348} 349 350static void AddNodeIDNode(FoldingSetNodeID &ID, 351 unsigned short OpC, SDVTList VTList, 352 const SDValue *OpList, unsigned N) { 353 AddNodeIDOpcode(ID, OpC); 354 AddNodeIDValueTypes(ID, VTList); 355 AddNodeIDOperands(ID, OpList, N); 356} 357 358/// AddNodeIDCustom - If this is an SDNode with special info, add this info to 359/// the NodeID data. 360static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { 361 switch (N->getOpcode()) { 362 default: break; // Normal nodes don't need extra info. 363 case ISD::ARG_FLAGS: 364 ID.AddInteger(cast<ARG_FLAGSSDNode>(N)->getArgFlags().getRawBits()); 365 break; 366 case ISD::TargetConstant: 367 case ISD::Constant: 368 ID.AddPointer(cast<ConstantSDNode>(N)->getConstantIntValue()); 369 break; 370 case ISD::TargetConstantFP: 371 case ISD::ConstantFP: { 372 ID.AddPointer(cast<ConstantFPSDNode>(N)->getConstantFPValue()); 373 break; 374 } 375 case ISD::TargetGlobalAddress: 376 case ISD::GlobalAddress: 377 case ISD::TargetGlobalTLSAddress: 378 case ISD::GlobalTLSAddress: { 379 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 380 ID.AddPointer(GA->getGlobal()); 381 ID.AddInteger(GA->getOffset()); 382 break; 383 } 384 case ISD::BasicBlock: 385 ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock()); 386 break; 387 case ISD::Register: 388 ID.AddInteger(cast<RegisterSDNode>(N)->getReg()); 389 break; 390 case ISD::DBG_STOPPOINT: { 391 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(N); 392 ID.AddInteger(DSP->getLine()); 393 ID.AddInteger(DSP->getColumn()); 394 ID.AddPointer(DSP->getCompileUnit()); 395 break; 396 } 397 case ISD::SRCVALUE: 398 ID.AddPointer(cast<SrcValueSDNode>(N)->getValue()); 399 break; 400 case ISD::MEMOPERAND: { 401 const MachineMemOperand &MO = cast<MemOperandSDNode>(N)->MO; 402 MO.Profile(ID); 403 break; 404 } 405 case ISD::FrameIndex: 406 case ISD::TargetFrameIndex: 407 ID.AddInteger(cast<FrameIndexSDNode>(N)->getIndex()); 408 break; 409 case ISD::JumpTable: 410 case ISD::TargetJumpTable: 411 ID.AddInteger(cast<JumpTableSDNode>(N)->getIndex()); 412 break; 413 case ISD::ConstantPool: 414 case ISD::TargetConstantPool: { 415 const ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N); 416 ID.AddInteger(CP->getAlignment()); 417 ID.AddInteger(CP->getOffset()); 418 if (CP->isMachineConstantPoolEntry()) 419 CP->getMachineCPVal()->AddSelectionDAGCSEId(ID); 420 else 421 ID.AddPointer(CP->getConstVal()); 422 break; 423 } 424 case ISD::CALL: { 425 const CallSDNode *Call = cast<CallSDNode>(N); 426 ID.AddInteger(Call->getCallingConv()); 427 ID.AddInteger(Call->isVarArg()); 428 break; 429 } 430 case ISD::LOAD: { 431 const LoadSDNode *LD = cast<LoadSDNode>(N); 432 ID.AddInteger(LD->getMemoryVT().getRawBits()); 433 ID.AddInteger(LD->getRawSubclassData()); 434 break; 435 } 436 case ISD::STORE: { 437 const StoreSDNode *ST = cast<StoreSDNode>(N); 438 ID.AddInteger(ST->getMemoryVT().getRawBits()); 439 ID.AddInteger(ST->getRawSubclassData()); 440 break; 441 } 442 case ISD::ATOMIC_CMP_SWAP: 443 case ISD::ATOMIC_SWAP: 444 case ISD::ATOMIC_LOAD_ADD: 445 case ISD::ATOMIC_LOAD_SUB: 446 case ISD::ATOMIC_LOAD_AND: 447 case ISD::ATOMIC_LOAD_OR: 448 case ISD::ATOMIC_LOAD_XOR: 449 case ISD::ATOMIC_LOAD_NAND: 450 case ISD::ATOMIC_LOAD_MIN: 451 case ISD::ATOMIC_LOAD_MAX: 452 case ISD::ATOMIC_LOAD_UMIN: 453 case ISD::ATOMIC_LOAD_UMAX: { 454 const AtomicSDNode *AT = cast<AtomicSDNode>(N); 455 ID.AddInteger(AT->getMemoryVT().getRawBits()); 456 ID.AddInteger(AT->getRawSubclassData()); 457 break; 458 } 459 } // end switch (N->getOpcode()) 460} 461 462/// AddNodeIDNode - Generic routine for adding a nodes info to the NodeID 463/// data. 464static void AddNodeIDNode(FoldingSetNodeID &ID, const SDNode *N) { 465 AddNodeIDOpcode(ID, N->getOpcode()); 466 // Add the return value info. 467 AddNodeIDValueTypes(ID, N->getVTList()); 468 // Add the operand info. 469 AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands()); 470 471 // Handle SDNode leafs with special info. 472 AddNodeIDCustom(ID, N); 473} 474 475/// encodeMemSDNodeFlags - Generic routine for computing a value for use in 476/// the CSE map that carries alignment, volatility, indexing mode, and 477/// extension/truncation information. 478/// 479static inline unsigned 480encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, 481 bool isVolatile, unsigned Alignment) { 482 assert((ConvType & 3) == ConvType && 483 "ConvType may not require more than 2 bits!"); 484 assert((AM & 7) == AM && 485 "AM may not require more than 3 bits!"); 486 return ConvType | 487 (AM << 2) | 488 (isVolatile << 5) | 489 ((Log2_32(Alignment) + 1) << 6); 490} 491 492//===----------------------------------------------------------------------===// 493// SelectionDAG Class 494//===----------------------------------------------------------------------===// 495 496/// doNotCSE - Return true if CSE should not be performed for this node. 497static bool doNotCSE(SDNode *N) { 498 if (N->getValueType(0) == MVT::Flag) 499 return true; // Never CSE anything that produces a flag. 500 501 switch (N->getOpcode()) { 502 default: break; 503 case ISD::HANDLENODE: 504 case ISD::DBG_LABEL: 505 case ISD::DBG_STOPPOINT: 506 case ISD::EH_LABEL: 507 case ISD::DECLARE: 508 return true; // Never CSE these nodes. 509 } 510 511 // Check that remaining values produced are not flags. 512 for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) 513 if (N->getValueType(i) == MVT::Flag) 514 return true; // Never CSE anything that produces a flag. 515 516 return false; 517} 518 519/// RemoveDeadNodes - This method deletes all unreachable nodes in the 520/// SelectionDAG. 521void SelectionDAG::RemoveDeadNodes() { 522 // Create a dummy node (which is not added to allnodes), that adds a reference 523 // to the root node, preventing it from being deleted. 524 HandleSDNode Dummy(getRoot()); 525 526 SmallVector<SDNode*, 128> DeadNodes; 527 528 // Add all obviously-dead nodes to the DeadNodes worklist. 529 for (allnodes_iterator I = allnodes_begin(), E = allnodes_end(); I != E; ++I) 530 if (I->use_empty()) 531 DeadNodes.push_back(I); 532 533 RemoveDeadNodes(DeadNodes); 534 535 // If the root changed (e.g. it was a dead load, update the root). 536 setRoot(Dummy.getValue()); 537} 538 539/// RemoveDeadNodes - This method deletes the unreachable nodes in the 540/// given list, and any nodes that become unreachable as a result. 541void SelectionDAG::RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes, 542 DAGUpdateListener *UpdateListener) { 543 544 // Process the worklist, deleting the nodes and adding their uses to the 545 // worklist. 546 while (!DeadNodes.empty()) { 547 SDNode *N = DeadNodes.pop_back_val(); 548 549 if (UpdateListener) 550 UpdateListener->NodeDeleted(N, 0); 551 552 // Take the node out of the appropriate CSE map. 553 RemoveNodeFromCSEMaps(N); 554 555 // Next, brutally remove the operand list. This is safe to do, as there are 556 // no cycles in the graph. 557 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 558 SDUse &Use = *I++; 559 SDNode *Operand = Use.getNode(); 560 Use.set(SDValue()); 561 562 // Now that we removed this operand, see if there are no uses of it left. 563 if (Operand->use_empty()) 564 DeadNodes.push_back(Operand); 565 } 566 567 DeallocateNode(N); 568 } 569} 570 571void SelectionDAG::RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener){ 572 SmallVector<SDNode*, 16> DeadNodes(1, N); 573 RemoveDeadNodes(DeadNodes, UpdateListener); 574} 575 576void SelectionDAG::DeleteNode(SDNode *N) { 577 // First take this out of the appropriate CSE map. 578 RemoveNodeFromCSEMaps(N); 579 580 // Finally, remove uses due to operands of this node, remove from the 581 // AllNodes list, and delete the node. 582 DeleteNodeNotInCSEMaps(N); 583} 584 585void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *N) { 586 assert(N != AllNodes.begin() && "Cannot delete the entry node!"); 587 assert(N->use_empty() && "Cannot delete a node that is not dead!"); 588 589 // Drop all of the operands and decrement used node's use counts. 590 N->DropOperands(); 591 592 DeallocateNode(N); 593} 594 595void SelectionDAG::DeallocateNode(SDNode *N) { 596 if (N->OperandsNeedDelete) 597 delete[] N->OperandList; 598 599 // Set the opcode to DELETED_NODE to help catch bugs when node 600 // memory is reallocated. 601 N->NodeType = ISD::DELETED_NODE; 602 603 NodeAllocator.Deallocate(AllNodes.remove(N)); 604} 605 606/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 607/// correspond to it. This is useful when we're about to delete or repurpose 608/// the node. We don't want future request for structurally identical nodes 609/// to return N anymore. 610bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 611 bool Erased = false; 612 switch (N->getOpcode()) { 613 case ISD::EntryToken: 614 assert(0 && "EntryToken should not be in CSEMaps!"); 615 return false; 616 case ISD::HANDLENODE: return false; // noop. 617 case ISD::CONDCODE: 618 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 619 "Cond code doesn't exist!"); 620 Erased = CondCodeNodes[cast<CondCodeSDNode>(N)->get()] != 0; 621 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 622 break; 623 case ISD::ExternalSymbol: 624 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 625 break; 626 case ISD::TargetExternalSymbol: 627 Erased = 628 TargetExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 629 break; 630 case ISD::VALUETYPE: { 631 MVT VT = cast<VTSDNode>(N)->getVT(); 632 if (VT.isExtended()) { 633 Erased = ExtendedValueTypeNodes.erase(VT); 634 } else { 635 Erased = ValueTypeNodes[VT.getSimpleVT()] != 0; 636 ValueTypeNodes[VT.getSimpleVT()] = 0; 637 } 638 break; 639 } 640 default: 641 // Remove it from the CSE Map. 642 Erased = CSEMap.RemoveNode(N); 643 break; 644 } 645#ifndef NDEBUG 646 // Verify that the node was actually in one of the CSE maps, unless it has a 647 // flag result (which cannot be CSE'd) or is one of the special cases that are 648 // not subject to CSE. 649 if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && 650 !N->isMachineOpcode() && !doNotCSE(N)) { 651 N->dump(this); 652 cerr << "\n"; 653 assert(0 && "Node is not in map!"); 654 } 655#endif 656 return Erased; 657} 658 659/// AddModifiedNodeToCSEMaps - The specified node has been removed from the CSE 660/// maps and modified in place. Add it back to the CSE maps, unless an identical 661/// node already exists, in which case transfer all its users to the existing 662/// node. This transfer can potentially trigger recursive merging. 663/// 664void 665SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N, 666 DAGUpdateListener *UpdateListener) { 667 // For node types that aren't CSE'd, just act as if no identical node 668 // already exists. 669 if (!doNotCSE(N)) { 670 SDNode *Existing = CSEMap.GetOrInsertNode(N); 671 if (Existing != N) { 672 // If there was already an existing matching node, use ReplaceAllUsesWith 673 // to replace the dead one with the existing one. This can cause 674 // recursive merging of other unrelated nodes down the line. 675 ReplaceAllUsesWith(N, Existing, UpdateListener); 676 677 // N is now dead. Inform the listener if it exists and delete it. 678 if (UpdateListener) 679 UpdateListener->NodeDeleted(N, Existing); 680 DeleteNodeNotInCSEMaps(N); 681 return; 682 } 683 } 684 685 // If the node doesn't already exist, we updated it. Inform a listener if 686 // it exists. 687 if (UpdateListener) 688 UpdateListener->NodeUpdated(N); 689} 690 691/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 692/// were replaced with those specified. If this node is never memoized, 693/// return null, otherwise return a pointer to the slot it would take. If a 694/// node already exists with these operands, the slot will be non-null. 695SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, SDValue Op, 696 void *&InsertPos) { 697 if (doNotCSE(N)) 698 return 0; 699 700 SDValue Ops[] = { Op }; 701 FoldingSetNodeID ID; 702 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 1); 703 AddNodeIDCustom(ID, N); 704 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 705} 706 707/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 708/// were replaced with those specified. If this node is never memoized, 709/// return null, otherwise return a pointer to the slot it would take. If a 710/// node already exists with these operands, the slot will be non-null. 711SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 712 SDValue Op1, SDValue Op2, 713 void *&InsertPos) { 714 if (doNotCSE(N)) 715 return 0; 716 717 SDValue Ops[] = { Op1, Op2 }; 718 FoldingSetNodeID ID; 719 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, 2); 720 AddNodeIDCustom(ID, N); 721 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 722} 723 724 725/// FindModifiedNodeSlot - Find a slot for the specified node if its operands 726/// were replaced with those specified. If this node is never memoized, 727/// return null, otherwise return a pointer to the slot it would take. If a 728/// node already exists with these operands, the slot will be non-null. 729SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, 730 const SDValue *Ops,unsigned NumOps, 731 void *&InsertPos) { 732 if (doNotCSE(N)) 733 return 0; 734 735 FoldingSetNodeID ID; 736 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps); 737 AddNodeIDCustom(ID, N); 738 return CSEMap.FindNodeOrInsertPos(ID, InsertPos); 739} 740 741/// VerifyNode - Sanity check the given node. Aborts if it is invalid. 742void SelectionDAG::VerifyNode(SDNode *N) { 743 switch (N->getOpcode()) { 744 default: 745 break; 746 case ISD::BUILD_PAIR: { 747 MVT VT = N->getValueType(0); 748 assert(N->getNumValues() == 1 && "Too many results!"); 749 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && 750 "Wrong return type!"); 751 assert(N->getNumOperands() == 2 && "Wrong number of operands!"); 752 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 753 "Mismatched operand types!"); 754 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 755 "Wrong operand type!"); 756 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && 757 "Wrong return type size"); 758 break; 759 } 760 case ISD::BUILD_VECTOR: { 761 assert(N->getNumValues() == 1 && "Too many results!"); 762 assert(N->getValueType(0).isVector() && "Wrong return type!"); 763 assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && 764 "Wrong number of operands!"); 765 // FIXME: Change vector_shuffle to a variadic node with mask elements being 766 // operands of the node. Currently the mask is a BUILD_VECTOR passed as an 767 // operand, and it is not always possible to legalize it. Turning off the 768 // following checks at least makes it possible to legalize most of the time. 769// MVT EltVT = N->getValueType(0).getVectorElementType(); 770// for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) 771// assert(I->getValueType() == EltVT && 772// "Wrong operand type!"); 773 break; 774 } 775 } 776} 777 778/// getMVTAlignment - Compute the default alignment value for the 779/// given type. 780/// 781unsigned SelectionDAG::getMVTAlignment(MVT VT) const { 782 const Type *Ty = VT == MVT::iPTR ? 783 PointerType::get(Type::Int8Ty, 0) : 784 VT.getTypeForMVT(); 785 786 return TLI.getTargetData()->getABITypeAlignment(Ty); 787} 788 789SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) 790 : TLI(tli), FLI(fli), DW(0), 791 EntryNode(ISD::EntryToken, getVTList(MVT::Other)), 792 Root(getEntryNode()) { 793 AllNodes.push_back(&EntryNode); 794} 795 796void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi, 797 DwarfWriter *dw) { 798 MF = &mf; 799 MMI = mmi; 800 DW = dw; 801} 802 803SelectionDAG::~SelectionDAG() { 804 allnodes_clear(); 805} 806 807void SelectionDAG::allnodes_clear() { 808 assert(&*AllNodes.begin() == &EntryNode); 809 AllNodes.remove(AllNodes.begin()); 810 while (!AllNodes.empty()) 811 DeallocateNode(AllNodes.begin()); 812} 813 814void SelectionDAG::clear() { 815 allnodes_clear(); 816 OperandAllocator.Reset(); 817 CSEMap.clear(); 818 819 ExtendedValueTypeNodes.clear(); 820 ExternalSymbols.clear(); 821 TargetExternalSymbols.clear(); 822 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), 823 static_cast<CondCodeSDNode*>(0)); 824 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), 825 static_cast<SDNode*>(0)); 826 827 EntryNode.UseList = 0; 828 AllNodes.push_back(&EntryNode); 829 Root = getEntryNode(); 830} 831 832SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { 833 if (Op.getValueType() == VT) return Op; 834 APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), 835 VT.getSizeInBits()); 836 return getNode(ISD::AND, DL, Op.getValueType(), Op, 837 getConstant(Imm, Op.getValueType())); 838} 839 840/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). 841/// 842SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { 843 SDValue NegOne; 844 if (VT.isVector()) { 845 MVT EltVT = VT.getVectorElementType(); 846 SDValue NegOneElt = 847 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT); 848 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt); 849 NegOne = getNode(ISD::BUILD_VECTOR, DL, VT, &NegOnes[0], NegOnes.size()); 850 } else { 851 NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 852 } 853 return getNode(ISD::XOR, DL, VT, Val, NegOne); 854} 855 856SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { 857 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 858 assert((EltVT.getSizeInBits() >= 64 || 859 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && 860 "getConstant with a uint64_t value that doesn't fit in the type!"); 861 return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); 862} 863 864SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { 865 return getConstant(*ConstantInt::get(Val), VT, isT); 866} 867 868SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { 869 assert(VT.isInteger() && "Cannot create FP integer constant!"); 870 871 MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 872 assert(Val.getBitWidth() == EltVT.getSizeInBits() && 873 "APInt size does not match type size!"); 874 875 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; 876 FoldingSetNodeID ID; 877 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 878 ID.AddPointer(&Val); 879 void *IP = 0; 880 SDNode *N = NULL; 881 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 882 if (!VT.isVector()) 883 return SDValue(N, 0); 884 if (!N) { 885 N = NodeAllocator.Allocate<ConstantSDNode>(); 886 new (N) ConstantSDNode(isT, &Val, EltVT); 887 CSEMap.InsertNode(N, IP); 888 AllNodes.push_back(N); 889 } 890 891 SDValue Result(N, 0); 892 if (VT.isVector()) { 893 SmallVector<SDValue, 8> Ops; 894 Ops.assign(VT.getVectorNumElements(), Result); 895 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 896 VT, &Ops[0], Ops.size()); 897 } 898 return Result; 899} 900 901SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { 902 return getConstant(Val, TLI.getPointerTy(), isTarget); 903} 904 905 906SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { 907 return getConstantFP(*ConstantFP::get(V), VT, isTarget); 908} 909 910SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ 911 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); 912 913 MVT EltVT = 914 VT.isVector() ? VT.getVectorElementType() : VT; 915 916 // Do the map lookup using the actual bit pattern for the floating point 917 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 918 // we don't have issues with SNANs. 919 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; 920 FoldingSetNodeID ID; 921 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0); 922 ID.AddPointer(&V); 923 void *IP = 0; 924 SDNode *N = NULL; 925 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP))) 926 if (!VT.isVector()) 927 return SDValue(N, 0); 928 if (!N) { 929 N = NodeAllocator.Allocate<ConstantFPSDNode>(); 930 new (N) ConstantFPSDNode(isTarget, &V, EltVT); 931 CSEMap.InsertNode(N, IP); 932 AllNodes.push_back(N); 933 } 934 935 SDValue Result(N, 0); 936 if (VT.isVector()) { 937 SmallVector<SDValue, 8> Ops; 938 Ops.assign(VT.getVectorNumElements(), Result); 939 // FIXME DebugLoc info might be appropriate here 940 Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), 941 VT, &Ops[0], Ops.size()); 942 } 943 return Result; 944} 945 946SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { 947 MVT EltVT = 948 VT.isVector() ? VT.getVectorElementType() : VT; 949 if (EltVT==MVT::f32) 950 return getConstantFP(APFloat((float)Val), VT, isTarget); 951 else 952 return getConstantFP(APFloat(Val), VT, isTarget); 953} 954 955SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, 956 MVT VT, int64_t Offset, 957 bool isTargetGA) { 958 unsigned Opc; 959 960 // Truncate (with sign-extension) the offset value to the pointer size. 961 unsigned BitWidth = TLI.getPointerTy().getSizeInBits(); 962 if (BitWidth < 64) 963 Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); 964 965 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 966 if (!GVar) { 967 // If GV is an alias then use the aliasee for determining thread-localness. 968 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 969 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 970 } 971 972 if (GVar && GVar->isThreadLocal()) 973 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress; 974 else 975 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; 976 977 FoldingSetNodeID ID; 978 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 979 ID.AddPointer(GV); 980 ID.AddInteger(Offset); 981 void *IP = 0; 982 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 983 return SDValue(E, 0); 984 SDNode *N = NodeAllocator.Allocate<GlobalAddressSDNode>(); 985 new (N) GlobalAddressSDNode(isTargetGA, GV, VT, Offset); 986 CSEMap.InsertNode(N, IP); 987 AllNodes.push_back(N); 988 return SDValue(N, 0); 989} 990 991SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { 992 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; 993 FoldingSetNodeID ID; 994 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 995 ID.AddInteger(FI); 996 void *IP = 0; 997 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 998 return SDValue(E, 0); 999 SDNode *N = NodeAllocator.Allocate<FrameIndexSDNode>(); 1000 new (N) FrameIndexSDNode(FI, VT, isTarget); 1001 CSEMap.InsertNode(N, IP); 1002 AllNodes.push_back(N); 1003 return SDValue(N, 0); 1004} 1005 1006SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget){ 1007 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; 1008 FoldingSetNodeID ID; 1009 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1010 ID.AddInteger(JTI); 1011 void *IP = 0; 1012 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1013 return SDValue(E, 0); 1014 SDNode *N = NodeAllocator.Allocate<JumpTableSDNode>(); 1015 new (N) JumpTableSDNode(JTI, VT, isTarget); 1016 CSEMap.InsertNode(N, IP); 1017 AllNodes.push_back(N); 1018 return SDValue(N, 0); 1019} 1020 1021SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, 1022 unsigned Alignment, int Offset, 1023 bool isTarget) { 1024 if (Alignment == 0) 1025 Alignment = 1026 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1027 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1028 FoldingSetNodeID ID; 1029 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1030 ID.AddInteger(Alignment); 1031 ID.AddInteger(Offset); 1032 ID.AddPointer(C); 1033 void *IP = 0; 1034 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1035 return SDValue(E, 0); 1036 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1037 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1038 CSEMap.InsertNode(N, IP); 1039 AllNodes.push_back(N); 1040 return SDValue(N, 0); 1041} 1042 1043 1044SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, 1045 unsigned Alignment, int Offset, 1046 bool isTarget) { 1047 if (Alignment == 0) 1048 Alignment = 1049 TLI.getTargetData()->getPreferredTypeAlignmentShift(C->getType()); 1050 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; 1051 FoldingSetNodeID ID; 1052 AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); 1053 ID.AddInteger(Alignment); 1054 ID.AddInteger(Offset); 1055 C->AddSelectionDAGCSEId(ID); 1056 void *IP = 0; 1057 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1058 return SDValue(E, 0); 1059 SDNode *N = NodeAllocator.Allocate<ConstantPoolSDNode>(); 1060 new (N) ConstantPoolSDNode(isTarget, C, VT, Offset, Alignment); 1061 CSEMap.InsertNode(N, IP); 1062 AllNodes.push_back(N); 1063 return SDValue(N, 0); 1064} 1065 1066SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 1067 FoldingSetNodeID ID; 1068 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1069 ID.AddPointer(MBB); 1070 void *IP = 0; 1071 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1072 return SDValue(E, 0); 1073 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1074 new (N) BasicBlockSDNode(MBB); 1075 CSEMap.InsertNode(N, IP); 1076 AllNodes.push_back(N); 1077 return SDValue(N, 0); 1078} 1079 1080SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl) { 1081 FoldingSetNodeID ID; 1082 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); 1083 ID.AddPointer(MBB); 1084 void *IP = 0; 1085 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1086 return SDValue(E, 0); 1087 SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>(); 1088 new (N) BasicBlockSDNode(MBB, dl); 1089 CSEMap.InsertNode(N, IP); 1090 AllNodes.push_back(N); 1091 return SDValue(N, 0); 1092} 1093 1094SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) { 1095 FoldingSetNodeID ID; 1096 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0); 1097 ID.AddInteger(Flags.getRawBits()); 1098 void *IP = 0; 1099 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1100 return SDValue(E, 0); 1101 SDNode *N = NodeAllocator.Allocate<ARG_FLAGSSDNode>(); 1102 new (N) ARG_FLAGSSDNode(Flags); 1103 CSEMap.InsertNode(N, IP); 1104 AllNodes.push_back(N); 1105 return SDValue(N, 0); 1106} 1107 1108SDValue SelectionDAG::getValueType(MVT VT) { 1109 if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) 1110 ValueTypeNodes.resize(VT.getSimpleVT()+1); 1111 1112 SDNode *&N = VT.isExtended() ? 1113 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT()]; 1114 1115 if (N) return SDValue(N, 0); 1116 N = NodeAllocator.Allocate<VTSDNode>(); 1117 new (N) VTSDNode(VT); 1118 AllNodes.push_back(N); 1119 return SDValue(N, 0); 1120} 1121 1122SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { 1123 SDNode *&N = ExternalSymbols[Sym]; 1124 if (N) return SDValue(N, 0); 1125 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1126 new (N) ExternalSymbolSDNode(false, Sym, VT); 1127 AllNodes.push_back(N); 1128 return SDValue(N, 0); 1129} 1130 1131SDValue SelectionDAG::getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT) { 1132 SDNode *&N = ExternalSymbols[Sym]; 1133 if (N) return SDValue(N, 0); 1134 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1135 new (N) ExternalSymbolSDNode(false, dl, Sym, VT); 1136 AllNodes.push_back(N); 1137 return SDValue(N, 0); 1138} 1139 1140SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) { 1141 SDNode *&N = TargetExternalSymbols[Sym]; 1142 if (N) return SDValue(N, 0); 1143 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1144 new (N) ExternalSymbolSDNode(true, Sym, VT); 1145 AllNodes.push_back(N); 1146 return SDValue(N, 0); 1147} 1148 1149SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, DebugLoc dl, 1150 MVT VT) { 1151 SDNode *&N = TargetExternalSymbols[Sym]; 1152 if (N) return SDValue(N, 0); 1153 N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); 1154 new (N) ExternalSymbolSDNode(true, dl, Sym, VT); 1155 AllNodes.push_back(N); 1156 return SDValue(N, 0); 1157} 1158 1159SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { 1160 if ((unsigned)Cond >= CondCodeNodes.size()) 1161 CondCodeNodes.resize(Cond+1); 1162 1163 if (CondCodeNodes[Cond] == 0) { 1164 CondCodeSDNode *N = NodeAllocator.Allocate<CondCodeSDNode>(); 1165 new (N) CondCodeSDNode(Cond); 1166 CondCodeNodes[Cond] = N; 1167 AllNodes.push_back(N); 1168 } 1169 return SDValue(CondCodeNodes[Cond], 0); 1170} 1171 1172SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, 1173 SDValue Val, SDValue DTy, 1174 SDValue STy, SDValue Rnd, SDValue Sat, 1175 ISD::CvtCode Code) { 1176 // If the src and dest types are the same and the conversion is between 1177 // integer types of the same sign or two floats, no conversion is necessary. 1178 if (DTy == STy && 1179 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF)) 1180 return Val; 1181 1182 FoldingSetNodeID ID; 1183 void* IP = 0; 1184 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1185 return SDValue(E, 0); 1186 CvtRndSatSDNode *N = NodeAllocator.Allocate<CvtRndSatSDNode>(); 1187 SDValue Ops[] = { Val, DTy, STy, Rnd, Sat }; 1188 new (N) CvtRndSatSDNode(VT, dl, Ops, 5, Code); 1189 CSEMap.InsertNode(N, IP); 1190 AllNodes.push_back(N); 1191 return SDValue(N, 0); 1192} 1193 1194SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { 1195 FoldingSetNodeID ID; 1196 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); 1197 ID.AddInteger(RegNo); 1198 void *IP = 0; 1199 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1200 return SDValue(E, 0); 1201 SDNode *N = NodeAllocator.Allocate<RegisterSDNode>(); 1202 new (N) RegisterSDNode(RegNo, VT); 1203 CSEMap.InsertNode(N, IP); 1204 AllNodes.push_back(N); 1205 return SDValue(N, 0); 1206} 1207 1208SDValue SelectionDAG::getDbgStopPoint(SDValue Root, 1209 unsigned Line, unsigned Col, 1210 Value *CU) { 1211 SDNode *N = NodeAllocator.Allocate<DbgStopPointSDNode>(); 1212 new (N) DbgStopPointSDNode(Root, Line, Col, CU); 1213 AllNodes.push_back(N); 1214 return SDValue(N, 0); 1215} 1216 1217SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, 1218 SDValue Root, 1219 unsigned LabelID) { 1220 FoldingSetNodeID ID; 1221 SDValue Ops[] = { Root }; 1222 AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); 1223 ID.AddInteger(LabelID); 1224 void *IP = 0; 1225 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1226 return SDValue(E, 0); 1227 SDNode *N = NodeAllocator.Allocate<LabelSDNode>(); 1228 new (N) LabelSDNode(Opcode, dl, Root, LabelID); 1229 CSEMap.InsertNode(N, IP); 1230 AllNodes.push_back(N); 1231 return SDValue(N, 0); 1232} 1233 1234SDValue SelectionDAG::getSrcValue(const Value *V) { 1235 assert((!V || isa<PointerType>(V->getType())) && 1236 "SrcValue is not a pointer?"); 1237 1238 FoldingSetNodeID ID; 1239 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); 1240 ID.AddPointer(V); 1241 1242 void *IP = 0; 1243 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1244 return SDValue(E, 0); 1245 1246 SDNode *N = NodeAllocator.Allocate<SrcValueSDNode>(); 1247 new (N) SrcValueSDNode(V); 1248 CSEMap.InsertNode(N, IP); 1249 AllNodes.push_back(N); 1250 return SDValue(N, 0); 1251} 1252 1253SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { 1254#ifndef NDEBUG 1255 const Value *v = MO.getValue(); 1256 assert((!v || isa<PointerType>(v->getType())) && 1257 "SrcValue is not a pointer?"); 1258#endif 1259 1260 FoldingSetNodeID ID; 1261 AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); 1262 MO.Profile(ID); 1263 1264 void *IP = 0; 1265 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 1266 return SDValue(E, 0); 1267 1268 SDNode *N = NodeAllocator.Allocate<MemOperandSDNode>(); 1269 new (N) MemOperandSDNode(MO); 1270 CSEMap.InsertNode(N, IP); 1271 AllNodes.push_back(N); 1272 return SDValue(N, 0); 1273} 1274 1275/// getShiftAmountOperand - Return the specified value casted to 1276/// the target's desired shift amount type. 1277SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { 1278 MVT OpTy = Op.getValueType(); 1279 MVT ShTy = TLI.getShiftAmountTy(); 1280 if (OpTy == ShTy || OpTy.isVector()) return Op; 1281 1282 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1283 return getNode(Opcode, ShTy, Op); 1284} 1285 1286/// CreateStackTemporary - Create a stack temporary, suitable for holding the 1287/// specified value type. 1288SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { 1289 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1290 unsigned ByteSize = VT.getStoreSizeInBits()/8; 1291 const Type *Ty = VT.getTypeForMVT(); 1292 unsigned StackAlign = 1293 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); 1294 1295 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 1296 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1297} 1298 1299/// CreateStackTemporary - Create a stack temporary suitable for holding 1300/// either of the specified value types. 1301SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { 1302 unsigned Bytes = std::max(VT1.getStoreSizeInBits(), 1303 VT2.getStoreSizeInBits())/8; 1304 const Type *Ty1 = VT1.getTypeForMVT(); 1305 const Type *Ty2 = VT2.getTypeForMVT(); 1306 const TargetData *TD = TLI.getTargetData(); 1307 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), 1308 TD->getPrefTypeAlignment(Ty2)); 1309 1310 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); 1311 int FrameIdx = FrameInfo->CreateStackObject(Bytes, Align); 1312 return getFrameIndex(FrameIdx, TLI.getPointerTy()); 1313} 1314 1315SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, 1316 SDValue N2, ISD::CondCode Cond, DebugLoc dl) { 1317 // These setcc operations always fold. 1318 switch (Cond) { 1319 default: break; 1320 case ISD::SETFALSE: 1321 case ISD::SETFALSE2: return getConstant(0, VT); 1322 case ISD::SETTRUE: 1323 case ISD::SETTRUE2: return getConstant(1, VT); 1324 1325 case ISD::SETOEQ: 1326 case ISD::SETOGT: 1327 case ISD::SETOGE: 1328 case ISD::SETOLT: 1329 case ISD::SETOLE: 1330 case ISD::SETONE: 1331 case ISD::SETO: 1332 case ISD::SETUO: 1333 case ISD::SETUEQ: 1334 case ISD::SETUNE: 1335 assert(!N1.getValueType().isInteger() && "Illegal setcc for integer!"); 1336 break; 1337 } 1338 1339 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode())) { 1340 const APInt &C2 = N2C->getAPIntValue(); 1341 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1342 const APInt &C1 = N1C->getAPIntValue(); 1343 1344 switch (Cond) { 1345 default: assert(0 && "Unknown integer setcc!"); 1346 case ISD::SETEQ: return getConstant(C1 == C2, VT); 1347 case ISD::SETNE: return getConstant(C1 != C2, VT); 1348 case ISD::SETULT: return getConstant(C1.ult(C2), VT); 1349 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT); 1350 case ISD::SETULE: return getConstant(C1.ule(C2), VT); 1351 case ISD::SETUGE: return getConstant(C1.uge(C2), VT); 1352 case ISD::SETLT: return getConstant(C1.slt(C2), VT); 1353 case ISD::SETGT: return getConstant(C1.sgt(C2), VT); 1354 case ISD::SETLE: return getConstant(C1.sle(C2), VT); 1355 case ISD::SETGE: return getConstant(C1.sge(C2), VT); 1356 } 1357 } 1358 } 1359 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1360 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { 1361 // No compile time operations on this type yet. 1362 if (N1C->getValueType(0) == MVT::ppcf128) 1363 return SDValue(); 1364 1365 APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); 1366 switch (Cond) { 1367 default: break; 1368 case ISD::SETEQ: if (R==APFloat::cmpUnordered) 1369 return getNode(ISD::UNDEF, dl, VT); 1370 // fall through 1371 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT); 1372 case ISD::SETNE: if (R==APFloat::cmpUnordered) 1373 return getNode(ISD::UNDEF, dl, VT); 1374 // fall through 1375 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan || 1376 R==APFloat::cmpLessThan, VT); 1377 case ISD::SETLT: if (R==APFloat::cmpUnordered) 1378 return getNode(ISD::UNDEF, dl, VT); 1379 // fall through 1380 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT); 1381 case ISD::SETGT: if (R==APFloat::cmpUnordered) 1382 return getNode(ISD::UNDEF, dl, VT); 1383 // fall through 1384 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT); 1385 case ISD::SETLE: if (R==APFloat::cmpUnordered) 1386 return getNode(ISD::UNDEF, dl, VT); 1387 // fall through 1388 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || 1389 R==APFloat::cmpEqual, VT); 1390 case ISD::SETGE: if (R==APFloat::cmpUnordered) 1391 return getNode(ISD::UNDEF, dl, VT); 1392 // fall through 1393 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || 1394 R==APFloat::cmpEqual, VT); 1395 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); 1396 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT); 1397 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || 1398 R==APFloat::cmpEqual, VT); 1399 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT); 1400 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || 1401 R==APFloat::cmpLessThan, VT); 1402 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan || 1403 R==APFloat::cmpUnordered, VT); 1404 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT); 1405 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT); 1406 } 1407 } else { 1408 // Ensure that the constant occurs on the RHS. 1409 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 1410 } 1411 } 1412 1413 // Could not fold it. 1414 return SDValue(); 1415} 1416 1417/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We 1418/// use this predicate to simplify operations downstream. 1419bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const { 1420 unsigned BitWidth = Op.getValueSizeInBits(); 1421 return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth); 1422} 1423 1424/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1425/// this predicate to simplify operations downstream. Mask is known to be zero 1426/// for bits that V cannot have. 1427bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, 1428 unsigned Depth) const { 1429 APInt KnownZero, KnownOne; 1430 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1431 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1432 return (KnownZero & Mask) == Mask; 1433} 1434 1435/// ComputeMaskedBits - Determine which of the bits specified in Mask are 1436/// known to be either zero or one and return them in the KnownZero/KnownOne 1437/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 1438/// processing. 1439void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, 1440 APInt &KnownZero, APInt &KnownOne, 1441 unsigned Depth) const { 1442 unsigned BitWidth = Mask.getBitWidth(); 1443 assert(BitWidth == Op.getValueType().getSizeInBits() && 1444 "Mask size mismatches value type size!"); 1445 1446 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 1447 if (Depth == 6 || Mask == 0) 1448 return; // Limit search depth. 1449 1450 APInt KnownZero2, KnownOne2; 1451 1452 switch (Op.getOpcode()) { 1453 case ISD::Constant: 1454 // We know all of the bits for a constant! 1455 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & Mask; 1456 KnownZero = ~KnownOne & Mask; 1457 return; 1458 case ISD::AND: 1459 // If either the LHS or the RHS are Zero, the result is zero. 1460 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1461 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownZero, 1462 KnownZero2, KnownOne2, Depth+1); 1463 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1464 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1465 1466 // Output known-1 bits are only known if set in both the LHS & RHS. 1467 KnownOne &= KnownOne2; 1468 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1469 KnownZero |= KnownZero2; 1470 return; 1471 case ISD::OR: 1472 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1473 ComputeMaskedBits(Op.getOperand(0), Mask & ~KnownOne, 1474 KnownZero2, KnownOne2, Depth+1); 1475 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1476 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1477 1478 // Output known-0 bits are only known if clear in both the LHS & RHS. 1479 KnownZero &= KnownZero2; 1480 // Output known-1 are known to be set if set in either the LHS | RHS. 1481 KnownOne |= KnownOne2; 1482 return; 1483 case ISD::XOR: { 1484 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1485 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1486 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1487 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1488 1489 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1490 APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1491 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1492 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1493 KnownZero = KnownZeroOut; 1494 return; 1495 } 1496 case ISD::MUL: { 1497 APInt Mask2 = APInt::getAllOnesValue(BitWidth); 1498 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero, KnownOne, Depth+1); 1499 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1501 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1502 1503 // If low bits are zero in either operand, output low known-0 bits. 1504 // Also compute a conserative estimate for high known-0 bits. 1505 // More trickiness is possible, but this is sufficient for the 1506 // interesting case of alignment computation. 1507 KnownOne.clear(); 1508 unsigned TrailZ = KnownZero.countTrailingOnes() + 1509 KnownZero2.countTrailingOnes(); 1510 unsigned LeadZ = std::max(KnownZero.countLeadingOnes() + 1511 KnownZero2.countLeadingOnes(), 1512 BitWidth) - BitWidth; 1513 1514 TrailZ = std::min(TrailZ, BitWidth); 1515 LeadZ = std::min(LeadZ, BitWidth); 1516 KnownZero = APInt::getLowBitsSet(BitWidth, TrailZ) | 1517 APInt::getHighBitsSet(BitWidth, LeadZ); 1518 KnownZero &= Mask; 1519 return; 1520 } 1521 case ISD::UDIV: { 1522 // For the purposes of computing leading zeros we can conservatively 1523 // treat a udiv as a logical right shift by the power of 2 known to 1524 // be less than the denominator. 1525 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1526 ComputeMaskedBits(Op.getOperand(0), 1527 AllOnes, KnownZero2, KnownOne2, Depth+1); 1528 unsigned LeadZ = KnownZero2.countLeadingOnes(); 1529 1530 KnownOne2.clear(); 1531 KnownZero2.clear(); 1532 ComputeMaskedBits(Op.getOperand(1), 1533 AllOnes, KnownZero2, KnownOne2, Depth+1); 1534 unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); 1535 if (RHSUnknownLeadingOnes != BitWidth) 1536 LeadZ = std::min(BitWidth, 1537 LeadZ + BitWidth - RHSUnknownLeadingOnes - 1); 1538 1539 KnownZero = APInt::getHighBitsSet(BitWidth, LeadZ) & Mask; 1540 return; 1541 } 1542 case ISD::SELECT: 1543 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 1544 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 1545 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1546 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1547 1548 // Only known if known in both the LHS and RHS. 1549 KnownOne &= KnownOne2; 1550 KnownZero &= KnownZero2; 1551 return; 1552 case ISD::SELECT_CC: 1553 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 1554 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 1555 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1556 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1557 1558 // Only known if known in both the LHS and RHS. 1559 KnownOne &= KnownOne2; 1560 KnownZero &= KnownZero2; 1561 return; 1562 case ISD::SADDO: 1563 case ISD::UADDO: 1564 case ISD::SSUBO: 1565 case ISD::USUBO: 1566 case ISD::SMULO: 1567 case ISD::UMULO: 1568 if (Op.getResNo() != 1) 1569 return; 1570 // The boolean result conforms to getBooleanContents. Fall through. 1571 case ISD::SETCC: 1572 // If we know the result of a setcc has the top bits zero, use this info. 1573 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent && 1574 BitWidth > 1) 1575 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1576 return; 1577 case ISD::SHL: 1578 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 1579 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1580 unsigned ShAmt = SA->getZExtValue(); 1581 1582 // If the shift count is an invalid immediate, don't do anything. 1583 if (ShAmt >= BitWidth) 1584 return; 1585 1586 ComputeMaskedBits(Op.getOperand(0), Mask.lshr(ShAmt), 1587 KnownZero, KnownOne, Depth+1); 1588 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1589 KnownZero <<= ShAmt; 1590 KnownOne <<= ShAmt; 1591 // low bits known zero. 1592 KnownZero |= APInt::getLowBitsSet(BitWidth, ShAmt); 1593 } 1594 return; 1595 case ISD::SRL: 1596 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 1597 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1598 unsigned ShAmt = SA->getZExtValue(); 1599 1600 // If the shift count is an invalid immediate, don't do anything. 1601 if (ShAmt >= BitWidth) 1602 return; 1603 1604 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt), 1605 KnownZero, KnownOne, Depth+1); 1606 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1607 KnownZero = KnownZero.lshr(ShAmt); 1608 KnownOne = KnownOne.lshr(ShAmt); 1609 1610 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1611 KnownZero |= HighBits; // High bits known zero. 1612 } 1613 return; 1614 case ISD::SRA: 1615 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1616 unsigned ShAmt = SA->getZExtValue(); 1617 1618 // If the shift count is an invalid immediate, don't do anything. 1619 if (ShAmt >= BitWidth) 1620 return; 1621 1622 APInt InDemandedMask = (Mask << ShAmt); 1623 // If any of the demanded bits are produced by the sign extension, we also 1624 // demand the input sign bit. 1625 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt) & Mask; 1626 if (HighBits.getBoolValue()) 1627 InDemandedMask |= APInt::getSignBit(BitWidth); 1628 1629 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 1630 Depth+1); 1631 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1632 KnownZero = KnownZero.lshr(ShAmt); 1633 KnownOne = KnownOne.lshr(ShAmt); 1634 1635 // Handle the sign bits. 1636 APInt SignBit = APInt::getSignBit(BitWidth); 1637 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. 1638 1639 if (KnownZero.intersects(SignBit)) { 1640 KnownZero |= HighBits; // New bits are known zero. 1641 } else if (KnownOne.intersects(SignBit)) { 1642 KnownOne |= HighBits; // New bits are known one. 1643 } 1644 } 1645 return; 1646 case ISD::SIGN_EXTEND_INREG: { 1647 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1648 unsigned EBits = EVT.getSizeInBits(); 1649 1650 // Sign extension. Compute the demanded bits in the result that are not 1651 // present in the input. 1652 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - EBits) & Mask; 1653 1654 APInt InSignBit = APInt::getSignBit(EBits); 1655 APInt InputDemandedBits = Mask & APInt::getLowBitsSet(BitWidth, EBits); 1656 1657 // If the sign extended bits are demanded, we know that the sign 1658 // bit is demanded. 1659 InSignBit.zext(BitWidth); 1660 if (NewBits.getBoolValue()) 1661 InputDemandedBits |= InSignBit; 1662 1663 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1664 KnownZero, KnownOne, Depth+1); 1665 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1666 1667 // If the sign bit of the input is known set or clear, then we know the 1668 // top bits of the result. 1669 if (KnownZero.intersects(InSignBit)) { // Input sign bit known clear 1670 KnownZero |= NewBits; 1671 KnownOne &= ~NewBits; 1672 } else if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1673 KnownOne |= NewBits; 1674 KnownZero &= ~NewBits; 1675 } else { // Input sign bit unknown 1676 KnownZero &= ~NewBits; 1677 KnownOne &= ~NewBits; 1678 } 1679 return; 1680 } 1681 case ISD::CTTZ: 1682 case ISD::CTLZ: 1683 case ISD::CTPOP: { 1684 unsigned LowBits = Log2_32(BitWidth)+1; 1685 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits); 1686 KnownOne.clear(); 1687 return; 1688 } 1689 case ISD::LOAD: { 1690 if (ISD::isZEXTLoad(Op.getNode())) { 1691 LoadSDNode *LD = cast<LoadSDNode>(Op); 1692 MVT VT = LD->getMemoryVT(); 1693 unsigned MemBits = VT.getSizeInBits(); 1694 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; 1695 } 1696 return; 1697 } 1698 case ISD::ZERO_EXTEND: { 1699 MVT InVT = Op.getOperand(0).getValueType(); 1700 unsigned InBits = InVT.getSizeInBits(); 1701 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1702 APInt InMask = Mask; 1703 InMask.trunc(InBits); 1704 KnownZero.trunc(InBits); 1705 KnownOne.trunc(InBits); 1706 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1707 KnownZero.zext(BitWidth); 1708 KnownOne.zext(BitWidth); 1709 KnownZero |= NewBits; 1710 return; 1711 } 1712 case ISD::SIGN_EXTEND: { 1713 MVT InVT = Op.getOperand(0).getValueType(); 1714 unsigned InBits = InVT.getSizeInBits(); 1715 APInt InSignBit = APInt::getSignBit(InBits); 1716 APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; 1717 APInt InMask = Mask; 1718 InMask.trunc(InBits); 1719 1720 // If any of the sign extended bits are demanded, we know that the sign 1721 // bit is demanded. Temporarily set this bit in the mask for our callee. 1722 if (NewBits.getBoolValue()) 1723 InMask |= InSignBit; 1724 1725 KnownZero.trunc(InBits); 1726 KnownOne.trunc(InBits); 1727 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1728 1729 // Note if the sign bit is known to be zero or one. 1730 bool SignBitKnownZero = KnownZero.isNegative(); 1731 bool SignBitKnownOne = KnownOne.isNegative(); 1732 assert(!(SignBitKnownZero && SignBitKnownOne) && 1733 "Sign bit can't be known to be both zero and one!"); 1734 1735 // If the sign bit wasn't actually demanded by our caller, we don't 1736 // want it set in the KnownZero and KnownOne result values. Reset the 1737 // mask and reapply it to the result values. 1738 InMask = Mask; 1739 InMask.trunc(InBits); 1740 KnownZero &= InMask; 1741 KnownOne &= InMask; 1742 1743 KnownZero.zext(BitWidth); 1744 KnownOne.zext(BitWidth); 1745 1746 // If the sign bit is known zero or one, the top bits match. 1747 if (SignBitKnownZero) 1748 KnownZero |= NewBits; 1749 else if (SignBitKnownOne) 1750 KnownOne |= NewBits; 1751 return; 1752 } 1753 case ISD::ANY_EXTEND: { 1754 MVT InVT = Op.getOperand(0).getValueType(); 1755 unsigned InBits = InVT.getSizeInBits(); 1756 APInt InMask = Mask; 1757 InMask.trunc(InBits); 1758 KnownZero.trunc(InBits); 1759 KnownOne.trunc(InBits); 1760 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1761 KnownZero.zext(BitWidth); 1762 KnownOne.zext(BitWidth); 1763 return; 1764 } 1765 case ISD::TRUNCATE: { 1766 MVT InVT = Op.getOperand(0).getValueType(); 1767 unsigned InBits = InVT.getSizeInBits(); 1768 APInt InMask = Mask; 1769 InMask.zext(InBits); 1770 KnownZero.zext(InBits); 1771 KnownOne.zext(InBits); 1772 ComputeMaskedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, Depth+1); 1773 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1774 KnownZero.trunc(BitWidth); 1775 KnownOne.trunc(BitWidth); 1776 break; 1777 } 1778 case ISD::AssertZext: { 1779 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1780 APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); 1781 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1782 KnownOne, Depth+1); 1783 KnownZero |= (~InMask) & Mask; 1784 return; 1785 } 1786 case ISD::FGETSIGN: 1787 // All bits are zero except the low bit. 1788 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - 1); 1789 return; 1790 1791 case ISD::SUB: { 1792 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 1793 // We know that the top bits of C-X are clear if X contains less bits 1794 // than C (i.e. no wrap-around can happen). For example, 20-X is 1795 // positive if we can prove that X is >= 0 and < 16. 1796 if (CLHS->getAPIntValue().isNonNegative()) { 1797 unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); 1798 // NLZ can't be BitWidth with no sign bit 1799 APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); 1800 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero2, KnownOne2, 1801 Depth+1); 1802 1803 // If all of the MaskV bits are known to be zero, then we know the 1804 // output top bits are zero, because we now know that the output is 1805 // from [0-C]. 1806 if ((KnownZero2 & MaskV) == MaskV) { 1807 unsigned NLZ2 = CLHS->getAPIntValue().countLeadingZeros(); 1808 // Top bits known zero. 1809 KnownZero = APInt::getHighBitsSet(BitWidth, NLZ2) & Mask; 1810 } 1811 } 1812 } 1813 } 1814 // fall through 1815 case ISD::ADD: { 1816 // Output known-0 bits are known if clear or set in both the low clear bits 1817 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1818 // low 3 bits clear. 1819 APInt Mask2 = APInt::getLowBitsSet(BitWidth, Mask.countTrailingOnes()); 1820 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero2, KnownOne2, Depth+1); 1821 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1822 unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); 1823 1824 ComputeMaskedBits(Op.getOperand(1), Mask2, KnownZero2, KnownOne2, Depth+1); 1825 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1826 KnownZeroOut = std::min(KnownZeroOut, 1827 KnownZero2.countTrailingOnes()); 1828 1829 KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); 1830 return; 1831 } 1832 case ISD::SREM: 1833 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1834 const APInt &RA = Rem->getAPIntValue(); 1835 if (RA.isPowerOf2() || (-RA).isPowerOf2()) { 1836 APInt LowBits = RA.isStrictlyPositive() ? (RA - 1) : ~RA; 1837 APInt Mask2 = LowBits | APInt::getSignBit(BitWidth); 1838 ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1); 1839 1840 // If the sign bit of the first operand is zero, the sign bit of 1841 // the result is zero. If the first operand has no one bits below 1842 // the second operand's single 1 bit, its sign will be zero. 1843 if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits)) 1844 KnownZero2 |= ~LowBits; 1845 1846 KnownZero |= KnownZero2 & Mask; 1847 1848 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1849 } 1850 } 1851 return; 1852 case ISD::UREM: { 1853 if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1854 const APInt &RA = Rem->getAPIntValue(); 1855 if (RA.isPowerOf2()) { 1856 APInt LowBits = (RA - 1); 1857 APInt Mask2 = LowBits & Mask; 1858 KnownZero |= ~LowBits & Mask; 1859 ComputeMaskedBits(Op.getOperand(0), Mask2, KnownZero, KnownOne,Depth+1); 1860 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 1861 break; 1862 } 1863 } 1864 1865 // Since the result is less than or equal to either operand, any leading 1866 // zero bits in either operand must also exist in the result. 1867 APInt AllOnes = APInt::getAllOnesValue(BitWidth); 1868 ComputeMaskedBits(Op.getOperand(0), AllOnes, KnownZero, KnownOne, 1869 Depth+1); 1870 ComputeMaskedBits(Op.getOperand(1), AllOnes, KnownZero2, KnownOne2, 1871 Depth+1); 1872 1873 uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), 1874 KnownZero2.countLeadingOnes()); 1875 KnownOne.clear(); 1876 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & Mask; 1877 return; 1878 } 1879 default: 1880 // Allow the target to implement this method for its nodes. 1881 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1882 case ISD::INTRINSIC_WO_CHAIN: 1883 case ISD::INTRINSIC_W_CHAIN: 1884 case ISD::INTRINSIC_VOID: 1885 TLI.computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne, *this); 1886 } 1887 return; 1888 } 1889} 1890 1891/// ComputeNumSignBits - Return the number of times the sign bit of the 1892/// register is replicated into the other bits. We know that at least 1 bit 1893/// is always equal to the sign bit (itself), but other cases can give us 1894/// information. For example, immediately after an "SRA X, 2", we know that 1895/// the top 3 bits are all equal to each other, so we return 3. 1896unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ 1897 MVT VT = Op.getValueType(); 1898 assert(VT.isInteger() && "Invalid VT!"); 1899 unsigned VTBits = VT.getSizeInBits(); 1900 unsigned Tmp, Tmp2; 1901 unsigned FirstAnswer = 1; 1902 1903 if (Depth == 6) 1904 return 1; // Limit search depth. 1905 1906 switch (Op.getOpcode()) { 1907 default: break; 1908 case ISD::AssertSext: 1909 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1910 return VTBits-Tmp+1; 1911 case ISD::AssertZext: 1912 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1913 return VTBits-Tmp; 1914 1915 case ISD::Constant: { 1916 const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue(); 1917 // If negative, return # leading ones. 1918 if (Val.isNegative()) 1919 return Val.countLeadingOnes(); 1920 1921 // Return # leading zeros. 1922 return Val.countLeadingZeros(); 1923 } 1924 1925 case ISD::SIGN_EXTEND: 1926 Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits(); 1927 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1928 1929 case ISD::SIGN_EXTEND_INREG: 1930 // Max of the input and what this extends. 1931 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); 1932 Tmp = VTBits-Tmp+1; 1933 1934 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1935 return std::max(Tmp, Tmp2); 1936 1937 case ISD::SRA: 1938 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1939 // SRA X, C -> adds C sign bits. 1940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1941 Tmp += C->getZExtValue(); 1942 if (Tmp > VTBits) Tmp = VTBits; 1943 } 1944 return Tmp; 1945 case ISD::SHL: 1946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1947 // shl destroys sign bits. 1948 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1949 if (C->getZExtValue() >= VTBits || // Bad shift. 1950 C->getZExtValue() >= Tmp) break; // Shifted all sign bits out. 1951 return Tmp - C->getZExtValue(); 1952 } 1953 break; 1954 case ISD::AND: 1955 case ISD::OR: 1956 case ISD::XOR: // NOT is handled here. 1957 // Logical binary ops preserve the number of sign bits at the worst. 1958 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1959 if (Tmp != 1) { 1960 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1961 FirstAnswer = std::min(Tmp, Tmp2); 1962 // We computed what we know about the sign bits as our first 1963 // answer. Now proceed to the generic code that uses 1964 // ComputeMaskedBits, and pick whichever answer is better. 1965 } 1966 break; 1967 1968 case ISD::SELECT: 1969 Tmp = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1970 if (Tmp == 1) return 1; // Early out. 1971 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 1972 return std::min(Tmp, Tmp2); 1973 1974 case ISD::SADDO: 1975 case ISD::UADDO: 1976 case ISD::SSUBO: 1977 case ISD::USUBO: 1978 case ISD::SMULO: 1979 case ISD::UMULO: 1980 if (Op.getResNo() != 1) 1981 break; 1982 // The boolean result conforms to getBooleanContents. Fall through. 1983 case ISD::SETCC: 1984 // If setcc returns 0/-1, all bits are sign bits. 1985 if (TLI.getBooleanContents() == 1986 TargetLowering::ZeroOrNegativeOneBooleanContent) 1987 return VTBits; 1988 break; 1989 case ISD::ROTL: 1990 case ISD::ROTR: 1991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1992 unsigned RotAmt = C->getZExtValue() & (VTBits-1); 1993 1994 // Handle rotate right by N like a rotate left by 32-N. 1995 if (Op.getOpcode() == ISD::ROTR) 1996 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1997 1998 // If we aren't rotating out all of the known-in sign bits, return the 1999 // number that are left. This handles rotl(sext(x), 1) for example. 2000 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2001 if (Tmp > RotAmt+1) return Tmp-RotAmt; 2002 } 2003 break; 2004 case ISD::ADD: 2005 // Add can have at most one carry bit. Thus we know that the output 2006 // is, at worst, one more bit than the inputs. 2007 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2008 if (Tmp == 1) return 1; // Early out. 2009 2010 // Special case decrementing a value (ADD X, -1): 2011 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2012 if (CRHS->isAllOnesValue()) { 2013 APInt KnownZero, KnownOne; 2014 APInt Mask = APInt::getAllOnesValue(VTBits); 2015 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2016 2017 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2018 // sign bits set. 2019 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2020 return VTBits; 2021 2022 // If we are subtracting one from a positive number, there is no carry 2023 // out of the result. 2024 if (KnownZero.isNegative()) 2025 return Tmp; 2026 } 2027 2028 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2029 if (Tmp2 == 1) return 1; 2030 return std::min(Tmp, Tmp2)-1; 2031 break; 2032 2033 case ISD::SUB: 2034 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2035 if (Tmp2 == 1) return 1; 2036 2037 // Handle NEG. 2038 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 2039 if (CLHS->isNullValue()) { 2040 APInt KnownZero, KnownOne; 2041 APInt Mask = APInt::getAllOnesValue(VTBits); 2042 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 2043 // If the input is known to be 0 or 1, the output is 0/-1, which is all 2044 // sign bits set. 2045 if ((KnownZero | APInt(VTBits, 1)) == Mask) 2046 return VTBits; 2047 2048 // If the input is known to be positive (the sign bit is known clear), 2049 // the output of the NEG has the same number of sign bits as the input. 2050 if (KnownZero.isNegative()) 2051 return Tmp2; 2052 2053 // Otherwise, we treat this like a SUB. 2054 } 2055 2056 // Sub can have at most one carry bit. Thus we know that the output 2057 // is, at worst, one more bit than the inputs. 2058 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2059 if (Tmp == 1) return 1; // Early out. 2060 return std::min(Tmp, Tmp2)-1; 2061 break; 2062 case ISD::TRUNCATE: 2063 // FIXME: it's tricky to do anything useful for this, but it is an important 2064 // case for targets like X86. 2065 break; 2066 } 2067 2068 // Handle LOADX separately here. EXTLOAD case will fallthrough. 2069 if (Op.getOpcode() == ISD::LOAD) { 2070 LoadSDNode *LD = cast<LoadSDNode>(Op); 2071 unsigned ExtType = LD->getExtensionType(); 2072 switch (ExtType) { 2073 default: break; 2074 case ISD::SEXTLOAD: // '17' bits known 2075 Tmp = LD->getMemoryVT().getSizeInBits(); 2076 return VTBits-Tmp+1; 2077 case ISD::ZEXTLOAD: // '16' bits known 2078 Tmp = LD->getMemoryVT().getSizeInBits(); 2079 return VTBits-Tmp; 2080 } 2081 } 2082 2083 // Allow the target to implement this method for its nodes. 2084 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 2085 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 2086 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 2087 Op.getOpcode() == ISD::INTRINSIC_VOID) { 2088 unsigned NumBits = TLI.ComputeNumSignBitsForTargetNode(Op, Depth); 2089 if (NumBits > 1) FirstAnswer = std::max(FirstAnswer, NumBits); 2090 } 2091 2092 // Finally, if we can prove that the top bits of the result are 0's or 1's, 2093 // use this information. 2094 APInt KnownZero, KnownOne; 2095 APInt Mask = APInt::getAllOnesValue(VTBits); 2096 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 2097 2098 if (KnownZero.isNegative()) { // sign bit is 0 2099 Mask = KnownZero; 2100 } else if (KnownOne.isNegative()) { // sign bit is 1; 2101 Mask = KnownOne; 2102 } else { 2103 // Nothing known. 2104 return FirstAnswer; 2105 } 2106 2107 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 2108 // the number of identical bits in the top of the input value. 2109 Mask = ~Mask; 2110 Mask <<= Mask.getBitWidth()-VTBits; 2111 // Return # leading zeros. We use 'min' here in case Val was zero before 2112 // shifting. We don't want to return '64' as for an i32 "0". 2113 return std::max(FirstAnswer, std::min(VTBits, Mask.countLeadingZeros())); 2114} 2115 2116 2117bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { 2118 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2119 if (!GA) return false; 2120 if (GA->getOffset() != 0) return false; 2121 GlobalVariable *GV = dyn_cast<GlobalVariable>(GA->getGlobal()); 2122 if (!GV) return false; 2123 MachineModuleInfo *MMI = getMachineModuleInfo(); 2124 return MMI && MMI->hasDebugInfo(); 2125} 2126 2127 2128/// getShuffleScalarElt - Returns the scalar element that will make up the ith 2129/// element of the result of the vector shuffle. 2130SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) { 2131 MVT VT = N->getValueType(0); 2132 DebugLoc dl = N->getDebugLoc(); 2133 SDValue PermMask = N->getOperand(2); 2134 SDValue Idx = PermMask.getOperand(i); 2135 if (Idx.getOpcode() == ISD::UNDEF) 2136 return getNode(ISD::UNDEF, dl, VT.getVectorElementType()); 2137 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 2138 unsigned NumElems = PermMask.getNumOperands(); 2139 SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 2140 Index %= NumElems; 2141 2142 if (V.getOpcode() == ISD::BIT_CONVERT) { 2143 V = V.getOperand(0); 2144 MVT VVT = V.getValueType(); 2145 if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems) 2146 return SDValue(); 2147 } 2148 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 2149 return (Index == 0) ? V.getOperand(0) 2150 : getNode(ISD::UNDEF, dl, VT.getVectorElementType()); 2151 if (V.getOpcode() == ISD::BUILD_VECTOR) 2152 return V.getOperand(Index); 2153 if (V.getOpcode() == ISD::VECTOR_SHUFFLE) 2154 return getShuffleScalarElt(V.getNode(), Index); 2155 return SDValue(); 2156} 2157 2158 2159/// getNode - Gets or creates the specified node. 2160/// 2161SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) { 2162 return getNode(Opcode, DebugLoc::getUnknownLoc(), VT); 2163} 2164 2165SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { 2166 FoldingSetNodeID ID; 2167 AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); 2168 void *IP = 0; 2169 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2170 return SDValue(E, 0); 2171 SDNode *N = NodeAllocator.Allocate<SDNode>(); 2172 new (N) SDNode(Opcode, DL, SDNode::getSDVTList(VT)); 2173 CSEMap.InsertNode(N, IP); 2174 2175 AllNodes.push_back(N); 2176#ifndef NDEBUG 2177 VerifyNode(N); 2178#endif 2179 return SDValue(N, 0); 2180} 2181 2182SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) { 2183 return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Operand); 2184} 2185 2186SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 2187 MVT VT, SDValue Operand) { 2188 // Constant fold unary operations with an integer constant operand. 2189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { 2190 const APInt &Val = C->getAPIntValue(); 2191 unsigned BitWidth = VT.getSizeInBits(); 2192 switch (Opcode) { 2193 default: break; 2194 case ISD::SIGN_EXTEND: 2195 return getConstant(APInt(Val).sextOrTrunc(BitWidth), VT); 2196 case ISD::ANY_EXTEND: 2197 case ISD::ZERO_EXTEND: 2198 case ISD::TRUNCATE: 2199 return getConstant(APInt(Val).zextOrTrunc(BitWidth), VT); 2200 case ISD::UINT_TO_FP: 2201 case ISD::SINT_TO_FP: { 2202 const uint64_t zero[] = {0, 0}; 2203 // No compile time operations on this type. 2204 if (VT==MVT::ppcf128) 2205 break; 2206 APFloat apf = APFloat(APInt(BitWidth, 2, zero)); 2207 (void)apf.convertFromAPInt(Val, 2208 Opcode==ISD::SINT_TO_FP, 2209 APFloat::rmNearestTiesToEven); 2210 return getConstantFP(apf, VT); 2211 } 2212 case ISD::BIT_CONVERT: 2213 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 2214 return getConstantFP(Val.bitsToFloat(), VT); 2215 else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) 2216 return getConstantFP(Val.bitsToDouble(), VT); 2217 break; 2218 case ISD::BSWAP: 2219 return getConstant(Val.byteSwap(), VT); 2220 case ISD::CTPOP: 2221 return getConstant(Val.countPopulation(), VT); 2222 case ISD::CTLZ: 2223 return getConstant(Val.countLeadingZeros(), VT); 2224 case ISD::CTTZ: 2225 return getConstant(Val.countTrailingZeros(), VT); 2226 } 2227 } 2228 2229 // Constant fold unary operations with a floating point constant operand. 2230 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { 2231 APFloat V = C->getValueAPF(); // make copy 2232 if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { 2233 switch (Opcode) { 2234 case ISD::FNEG: 2235 V.changeSign(); 2236 return getConstantFP(V, VT); 2237 case ISD::FABS: 2238 V.clearSign(); 2239 return getConstantFP(V, VT); 2240 case ISD::FP_ROUND: 2241 case ISD::FP_EXTEND: { 2242 bool ignored; 2243 // This can return overflow, underflow, or inexact; we don't care. 2244 // FIXME need to be more flexible about rounding mode. 2245 (void)V.convert(*MVTToAPFloatSemantics(VT), 2246 APFloat::rmNearestTiesToEven, &ignored); 2247 return getConstantFP(V, VT); 2248 } 2249 case ISD::FP_TO_SINT: 2250 case ISD::FP_TO_UINT: { 2251 integerPart x; 2252 bool ignored; 2253 assert(integerPartWidth >= 64); 2254 // FIXME need to be more flexible about rounding mode. 2255 APFloat::opStatus s = V.convertToInteger(&x, 64U, 2256 Opcode==ISD::FP_TO_SINT, 2257 APFloat::rmTowardZero, &ignored); 2258 if (s==APFloat::opInvalidOp) // inexact is OK, in fact usual 2259 break; 2260 return getConstant(x, VT); 2261 } 2262 case ISD::BIT_CONVERT: 2263 if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 2264 return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); 2265 else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) 2266 return getConstant(V.bitcastToAPInt().getZExtValue(), VT); 2267 break; 2268 } 2269 } 2270 } 2271 2272 unsigned OpOpcode = Operand.getNode()->getOpcode(); 2273 switch (Opcode) { 2274 case ISD::TokenFactor: 2275 case ISD::MERGE_VALUES: 2276 case ISD::CONCAT_VECTORS: 2277 return Operand; // Factor, merge or concat of one node? No need. 2278 case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); 2279 case ISD::FP_EXTEND: 2280 assert(VT.isFloatingPoint() && 2281 Operand.getValueType().isFloatingPoint() && "Invalid FP cast!"); 2282 if (Operand.getValueType() == VT) return Operand; // noop conversion. 2283 if (Operand.getOpcode() == ISD::UNDEF) 2284 return getNode(ISD::UNDEF, DL, VT); 2285 break; 2286 case ISD::SIGN_EXTEND: 2287 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2288 "Invalid SIGN_EXTEND!"); 2289 if (Operand.getValueType() == VT) return Operand; // noop extension 2290 assert(Operand.getValueType().bitsLT(VT) 2291 && "Invalid sext node, dst < src!"); 2292 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 2293 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2294 break; 2295 case ISD::ZERO_EXTEND: 2296 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2297 "Invalid ZERO_EXTEND!"); 2298 if (Operand.getValueType() == VT) return Operand; // noop extension 2299 assert(Operand.getValueType().bitsLT(VT) 2300 && "Invalid zext node, dst < src!"); 2301 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 2302 return getNode(ISD::ZERO_EXTEND, DL, VT, 2303 Operand.getNode()->getOperand(0)); 2304 break; 2305 case ISD::ANY_EXTEND: 2306 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2307 "Invalid ANY_EXTEND!"); 2308 if (Operand.getValueType() == VT) return Operand; // noop extension 2309 assert(Operand.getValueType().bitsLT(VT) 2310 && "Invalid anyext node, dst < src!"); 2311 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) 2312 // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) 2313 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2314 break; 2315 case ISD::TRUNCATE: 2316 assert(VT.isInteger() && Operand.getValueType().isInteger() && 2317 "Invalid TRUNCATE!"); 2318 if (Operand.getValueType() == VT) return Operand; // noop truncate 2319 assert(Operand.getValueType().bitsGT(VT) 2320 && "Invalid truncate node, src < dst!"); 2321 if (OpOpcode == ISD::TRUNCATE) 2322 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2323 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || 2324 OpOpcode == ISD::ANY_EXTEND) { 2325 // If the source is smaller than the dest, we still need an extend. 2326 if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT)) 2327 return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); 2328 else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) 2329 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0)); 2330 else 2331 return Operand.getNode()->getOperand(0); 2332 } 2333 break; 2334 case ISD::BIT_CONVERT: 2335 // Basic sanity checking. 2336 assert(VT.getSizeInBits() == Operand.getValueType().getSizeInBits() 2337 && "Cannot BIT_CONVERT between types of different sizes!"); 2338 if (VT == Operand.getValueType()) return Operand; // noop conversion. 2339 if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x) 2340 return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0)); 2341 if (OpOpcode == ISD::UNDEF) 2342 return getNode(ISD::UNDEF, DL, VT); 2343 break; 2344 case ISD::SCALAR_TO_VECTOR: 2345 assert(VT.isVector() && !Operand.getValueType().isVector() && 2346 VT.getVectorElementType() == Operand.getValueType() && 2347 "Illegal SCALAR_TO_VECTOR node!"); 2348 if (OpOpcode == ISD::UNDEF) 2349 return getNode(ISD::UNDEF, DL, VT); 2350 // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined. 2351 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && 2352 isa<ConstantSDNode>(Operand.getOperand(1)) && 2353 Operand.getConstantOperandVal(1) == 0 && 2354 Operand.getOperand(0).getValueType() == VT) 2355 return Operand.getOperand(0); 2356 break; 2357 case ISD::FNEG: 2358 // -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0 2359 if (UnsafeFPMath && OpOpcode == ISD::FSUB) 2360 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1), 2361 Operand.getNode()->getOperand(0)); 2362 if (OpOpcode == ISD::FNEG) // --X -> X 2363 return Operand.getNode()->getOperand(0); 2364 break; 2365 case ISD::FABS: 2366 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 2367 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0)); 2368 break; 2369 } 2370 2371 SDNode *N; 2372 SDVTList VTs = getVTList(VT); 2373 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 2374 FoldingSetNodeID ID; 2375 SDValue Ops[1] = { Operand }; 2376 AddNodeIDNode(ID, Opcode, VTs, Ops, 1); 2377 void *IP = 0; 2378 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2379 return SDValue(E, 0); 2380 N = NodeAllocator.Allocate<UnarySDNode>(); 2381 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2382 CSEMap.InsertNode(N, IP); 2383 } else { 2384 N = NodeAllocator.Allocate<UnarySDNode>(); 2385 new (N) UnarySDNode(Opcode, DL, VTs, Operand); 2386 } 2387 2388 AllNodes.push_back(N); 2389#ifndef NDEBUG 2390 VerifyNode(N); 2391#endif 2392 return SDValue(N, 0); 2393} 2394 2395SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, 2396 MVT VT, 2397 ConstantSDNode *Cst1, 2398 ConstantSDNode *Cst2) { 2399 const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); 2400 2401 switch (Opcode) { 2402 case ISD::ADD: return getConstant(C1 + C2, VT); 2403 case ISD::SUB: return getConstant(C1 - C2, VT); 2404 case ISD::MUL: return getConstant(C1 * C2, VT); 2405 case ISD::UDIV: 2406 if (C2.getBoolValue()) return getConstant(C1.udiv(C2), VT); 2407 break; 2408 case ISD::UREM: 2409 if (C2.getBoolValue()) return getConstant(C1.urem(C2), VT); 2410 break; 2411 case ISD::SDIV: 2412 if (C2.getBoolValue()) return getConstant(C1.sdiv(C2), VT); 2413 break; 2414 case ISD::SREM: 2415 if (C2.getBoolValue()) return getConstant(C1.srem(C2), VT); 2416 break; 2417 case ISD::AND: return getConstant(C1 & C2, VT); 2418 case ISD::OR: return getConstant(C1 | C2, VT); 2419 case ISD::XOR: return getConstant(C1 ^ C2, VT); 2420 case ISD::SHL: return getConstant(C1 << C2, VT); 2421 case ISD::SRL: return getConstant(C1.lshr(C2), VT); 2422 case ISD::SRA: return getConstant(C1.ashr(C2), VT); 2423 case ISD::ROTL: return getConstant(C1.rotl(C2), VT); 2424 case ISD::ROTR: return getConstant(C1.rotr(C2), VT); 2425 default: break; 2426 } 2427 2428 return SDValue(); 2429} 2430 2431SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2432 SDValue N1, SDValue N2) { 2433 return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2); 2434} 2435 2436SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2437 SDValue N1, SDValue N2) { 2438 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2439 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2440 switch (Opcode) { 2441 default: break; 2442 case ISD::TokenFactor: 2443 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 2444 N2.getValueType() == MVT::Other && "Invalid token factor!"); 2445 // Fold trivial token factors. 2446 if (N1.getOpcode() == ISD::EntryToken) return N2; 2447 if (N2.getOpcode() == ISD::EntryToken) return N1; 2448 if (N1 == N2) return N1; 2449 break; 2450 case ISD::CONCAT_VECTORS: 2451 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2452 // one big BUILD_VECTOR. 2453 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2454 N2.getOpcode() == ISD::BUILD_VECTOR) { 2455 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2456 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2457 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2458 } 2459 break; 2460 case ISD::AND: 2461 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2462 N1.getValueType() == VT && "Binary operator types must match!"); 2463 // (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's 2464 // worth handling here. 2465 if (N2C && N2C->isNullValue()) 2466 return N2; 2467 if (N2C && N2C->isAllOnesValue()) // X & -1 -> X 2468 return N1; 2469 break; 2470 case ISD::OR: 2471 case ISD::XOR: 2472 case ISD::ADD: 2473 case ISD::SUB: 2474 assert(VT.isInteger() && N1.getValueType() == N2.getValueType() && 2475 N1.getValueType() == VT && "Binary operator types must match!"); 2476 // (X ^|+- 0) -> X. This commonly occurs when legalizing i64 values, so 2477 // it's worth handling here. 2478 if (N2C && N2C->isNullValue()) 2479 return N1; 2480 break; 2481 case ISD::UDIV: 2482 case ISD::UREM: 2483 case ISD::MULHU: 2484 case ISD::MULHS: 2485 case ISD::MUL: 2486 case ISD::SDIV: 2487 case ISD::SREM: 2488 assert(VT.isInteger() && "This operator does not apply to FP types!"); 2489 // fall through 2490 case ISD::FADD: 2491 case ISD::FSUB: 2492 case ISD::FMUL: 2493 case ISD::FDIV: 2494 case ISD::FREM: 2495 if (UnsafeFPMath) { 2496 if (Opcode == ISD::FADD) { 2497 // 0+x --> x 2498 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) 2499 if (CFP->getValueAPF().isZero()) 2500 return N2; 2501 // x+0 --> x 2502 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2503 if (CFP->getValueAPF().isZero()) 2504 return N1; 2505 } else if (Opcode == ISD::FSUB) { 2506 // x-0 --> x 2507 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) 2508 if (CFP->getValueAPF().isZero()) 2509 return N1; 2510 } 2511 } 2512 assert(N1.getValueType() == N2.getValueType() && 2513 N1.getValueType() == VT && "Binary operator types must match!"); 2514 break; 2515 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. 2516 assert(N1.getValueType() == VT && 2517 N1.getValueType().isFloatingPoint() && 2518 N2.getValueType().isFloatingPoint() && 2519 "Invalid FCOPYSIGN!"); 2520 break; 2521 case ISD::SHL: 2522 case ISD::SRA: 2523 case ISD::SRL: 2524 case ISD::ROTL: 2525 case ISD::ROTR: 2526 assert(VT == N1.getValueType() && 2527 "Shift operators return type must be the same as their first arg"); 2528 assert(VT.isInteger() && N2.getValueType().isInteger() && 2529 "Shifts only work on integers"); 2530 2531 // Always fold shifts of i1 values so the code generator doesn't need to 2532 // handle them. Since we know the size of the shift has to be less than the 2533 // size of the value, the shift/rotate count is guaranteed to be zero. 2534 if (VT == MVT::i1) 2535 return N1; 2536 break; 2537 case ISD::FP_ROUND_INREG: { 2538 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2539 assert(VT == N1.getValueType() && "Not an inreg round!"); 2540 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && 2541 "Cannot FP_ROUND_INREG integer types"); 2542 assert(EVT.bitsLE(VT) && "Not rounding down!"); 2543 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 2544 break; 2545 } 2546 case ISD::FP_ROUND: 2547 assert(VT.isFloatingPoint() && 2548 N1.getValueType().isFloatingPoint() && 2549 VT.bitsLE(N1.getValueType()) && 2550 isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!"); 2551 if (N1.getValueType() == VT) return N1; // noop conversion. 2552 break; 2553 case ISD::AssertSext: 2554 case ISD::AssertZext: { 2555 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2556 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2557 assert(VT.isInteger() && EVT.isInteger() && 2558 "Cannot *_EXTEND_INREG FP types"); 2559 assert(EVT.bitsLE(VT) && "Not extending!"); 2560 if (VT == EVT) return N1; // noop assertion. 2561 break; 2562 } 2563 case ISD::SIGN_EXTEND_INREG: { 2564 MVT EVT = cast<VTSDNode>(N2)->getVT(); 2565 assert(VT == N1.getValueType() && "Not an inreg extend!"); 2566 assert(VT.isInteger() && EVT.isInteger() && 2567 "Cannot *_EXTEND_INREG FP types"); 2568 assert(EVT.bitsLE(VT) && "Not extending!"); 2569 if (EVT == VT) return N1; // Not actually extending 2570 2571 if (N1C) { 2572 APInt Val = N1C->getAPIntValue(); 2573 unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits(); 2574 Val <<= Val.getBitWidth()-FromBits; 2575 Val = Val.ashr(Val.getBitWidth()-FromBits); 2576 return getConstant(Val, VT); 2577 } 2578 break; 2579 } 2580 case ISD::EXTRACT_VECTOR_ELT: 2581 // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF. 2582 if (N1.getOpcode() == ISD::UNDEF) 2583 return getNode(ISD::UNDEF, DL, VT); 2584 2585 // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is 2586 // expanding copies of large vectors from registers. 2587 if (N2C && 2588 N1.getOpcode() == ISD::CONCAT_VECTORS && 2589 N1.getNumOperands() > 0) { 2590 unsigned Factor = 2591 N1.getOperand(0).getValueType().getVectorNumElements(); 2592 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, 2593 N1.getOperand(N2C->getZExtValue() / Factor), 2594 getConstant(N2C->getZExtValue() % Factor, 2595 N2.getValueType())); 2596 } 2597 2598 // EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is 2599 // expanding large vector constants. 2600 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) 2601 return N1.getOperand(N2C->getZExtValue()); 2602 2603 // EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector 2604 // operations are lowered to scalars. 2605 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { 2606 // If the indices are the same, return the inserted element. 2607 if (N1.getOperand(2) == N2) 2608 return N1.getOperand(1); 2609 // If the indices are known different, extract the element from 2610 // the original vector. 2611 else if (isa<ConstantSDNode>(N1.getOperand(2)) && 2612 isa<ConstantSDNode>(N2)) 2613 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2); 2614 } 2615 break; 2616 case ISD::EXTRACT_ELEMENT: 2617 assert(N2C && (unsigned)N2C->getZExtValue() < 2 && "Bad EXTRACT_ELEMENT!"); 2618 assert(!N1.getValueType().isVector() && !VT.isVector() && 2619 (N1.getValueType().isInteger() == VT.isInteger()) && 2620 "Wrong types for EXTRACT_ELEMENT!"); 2621 2622 // EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding 2623 // 64-bit integers into 32-bit parts. Instead of building the extract of 2624 // the BUILD_PAIR, only to have legalize rip it apart, just do it now. 2625 if (N1.getOpcode() == ISD::BUILD_PAIR) 2626 return N1.getOperand(N2C->getZExtValue()); 2627 2628 // EXTRACT_ELEMENT of a constant int is also very common. 2629 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2630 unsigned ElementSize = VT.getSizeInBits(); 2631 unsigned Shift = ElementSize * N2C->getZExtValue(); 2632 APInt ShiftedVal = C->getAPIntValue().lshr(Shift); 2633 return getConstant(ShiftedVal.trunc(ElementSize), VT); 2634 } 2635 break; 2636 case ISD::EXTRACT_SUBVECTOR: 2637 if (N1.getValueType() == VT) // Trivial extraction. 2638 return N1; 2639 break; 2640 } 2641 2642 if (N1C) { 2643 if (N2C) { 2644 SDValue SV = FoldConstantArithmetic(Opcode, VT, N1C, N2C); 2645 if (SV.getNode()) return SV; 2646 } else { // Cannonicalize constant to RHS if commutative 2647 if (isCommutativeBinOp(Opcode)) { 2648 std::swap(N1C, N2C); 2649 std::swap(N1, N2); 2650 } 2651 } 2652 } 2653 2654 // Constant fold FP operations. 2655 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.getNode()); 2656 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.getNode()); 2657 if (N1CFP) { 2658 if (!N2CFP && isCommutativeBinOp(Opcode)) { 2659 // Cannonicalize constant to RHS if commutative 2660 std::swap(N1CFP, N2CFP); 2661 std::swap(N1, N2); 2662 } else if (N2CFP && VT != MVT::ppcf128) { 2663 APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); 2664 APFloat::opStatus s; 2665 switch (Opcode) { 2666 case ISD::FADD: 2667 s = V1.add(V2, APFloat::rmNearestTiesToEven); 2668 if (s != APFloat::opInvalidOp) 2669 return getConstantFP(V1, VT); 2670 break; 2671 case ISD::FSUB: 2672 s = V1.subtract(V2, APFloat::rmNearestTiesToEven); 2673 if (s!=APFloat::opInvalidOp) 2674 return getConstantFP(V1, VT); 2675 break; 2676 case ISD::FMUL: 2677 s = V1.multiply(V2, APFloat::rmNearestTiesToEven); 2678 if (s!=APFloat::opInvalidOp) 2679 return getConstantFP(V1, VT); 2680 break; 2681 case ISD::FDIV: 2682 s = V1.divide(V2, APFloat::rmNearestTiesToEven); 2683 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2684 return getConstantFP(V1, VT); 2685 break; 2686 case ISD::FREM : 2687 s = V1.mod(V2, APFloat::rmNearestTiesToEven); 2688 if (s!=APFloat::opInvalidOp && s!=APFloat::opDivByZero) 2689 return getConstantFP(V1, VT); 2690 break; 2691 case ISD::FCOPYSIGN: 2692 V1.copySign(V2); 2693 return getConstantFP(V1, VT); 2694 default: break; 2695 } 2696 } 2697 } 2698 2699 // Canonicalize an UNDEF to the RHS, even over a constant. 2700 if (N1.getOpcode() == ISD::UNDEF) { 2701 if (isCommutativeBinOp(Opcode)) { 2702 std::swap(N1, N2); 2703 } else { 2704 switch (Opcode) { 2705 case ISD::FP_ROUND_INREG: 2706 case ISD::SIGN_EXTEND_INREG: 2707 case ISD::SUB: 2708 case ISD::FSUB: 2709 case ISD::FDIV: 2710 case ISD::FREM: 2711 case ISD::SRA: 2712 return N1; // fold op(undef, arg2) -> undef 2713 case ISD::UDIV: 2714 case ISD::SDIV: 2715 case ISD::UREM: 2716 case ISD::SREM: 2717 case ISD::SRL: 2718 case ISD::SHL: 2719 if (!VT.isVector()) 2720 return getConstant(0, VT); // fold op(undef, arg2) -> 0 2721 // For vectors, we can't easily build an all zero vector, just return 2722 // the LHS. 2723 return N2; 2724 } 2725 } 2726 } 2727 2728 // Fold a bunch of operators when the RHS is undef. 2729 if (N2.getOpcode() == ISD::UNDEF) { 2730 switch (Opcode) { 2731 case ISD::XOR: 2732 if (N1.getOpcode() == ISD::UNDEF) 2733 // Handle undef ^ undef -> 0 special case. This is a common 2734 // idiom (misuse). 2735 return getConstant(0, VT); 2736 // fallthrough 2737 case ISD::ADD: 2738 case ISD::ADDC: 2739 case ISD::ADDE: 2740 case ISD::SUB: 2741 case ISD::FADD: 2742 case ISD::FSUB: 2743 case ISD::FMUL: 2744 case ISD::FDIV: 2745 case ISD::FREM: 2746 case ISD::UDIV: 2747 case ISD::SDIV: 2748 case ISD::UREM: 2749 case ISD::SREM: 2750 return N2; // fold op(arg1, undef) -> undef 2751 case ISD::MUL: 2752 case ISD::AND: 2753 case ISD::SRL: 2754 case ISD::SHL: 2755 if (!VT.isVector()) 2756 return getConstant(0, VT); // fold op(arg1, undef) -> 0 2757 // For vectors, we can't easily build an all zero vector, just return 2758 // the LHS. 2759 return N1; 2760 case ISD::OR: 2761 if (!VT.isVector()) 2762 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 2763 // For vectors, we can't easily build an all one vector, just return 2764 // the LHS. 2765 return N1; 2766 case ISD::SRA: 2767 return N1; 2768 } 2769 } 2770 2771 // Memoize this node if possible. 2772 SDNode *N; 2773 SDVTList VTs = getVTList(VT); 2774 if (VT != MVT::Flag) { 2775 SDValue Ops[] = { N1, N2 }; 2776 FoldingSetNodeID ID; 2777 AddNodeIDNode(ID, Opcode, VTs, Ops, 2); 2778 void *IP = 0; 2779 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2780 return SDValue(E, 0); 2781 N = NodeAllocator.Allocate<BinarySDNode>(); 2782 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2783 CSEMap.InsertNode(N, IP); 2784 } else { 2785 N = NodeAllocator.Allocate<BinarySDNode>(); 2786 new (N) BinarySDNode(Opcode, DL, VTs, N1, N2); 2787 } 2788 2789 AllNodes.push_back(N); 2790#ifndef NDEBUG 2791 VerifyNode(N); 2792#endif 2793 return SDValue(N, 0); 2794} 2795 2796SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2797 SDValue N1, SDValue N2, SDValue N3) { 2798 return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3); 2799} 2800 2801SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2802 SDValue N1, SDValue N2, SDValue N3) { 2803 // Perform various simplifications. 2804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 2805 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 2806 switch (Opcode) { 2807 case ISD::CONCAT_VECTORS: 2808 // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to 2809 // one big BUILD_VECTOR. 2810 if (N1.getOpcode() == ISD::BUILD_VECTOR && 2811 N2.getOpcode() == ISD::BUILD_VECTOR && 2812 N3.getOpcode() == ISD::BUILD_VECTOR) { 2813 SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end()); 2814 Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end()); 2815 Elts.insert(Elts.end(), N3.getNode()->op_begin(), N3.getNode()->op_end()); 2816 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); 2817 } 2818 break; 2819 case ISD::SETCC: { 2820 // Use FoldSetCC to simplify SETCC's. 2821 SDValue Simp = FoldSetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get(), DL); 2822 if (Simp.getNode()) return Simp; 2823 break; 2824 } 2825 case ISD::SELECT: 2826 if (N1C) { 2827 if (N1C->getZExtValue()) 2828 return N2; // select true, X, Y -> X 2829 else 2830 return N3; // select false, X, Y -> Y 2831 } 2832 2833 if (N2 == N3) return N2; // select C, X, X -> X 2834 break; 2835 case ISD::BRCOND: 2836 if (N2C) { 2837 if (N2C->getZExtValue()) // Unconditional branch 2838 return getNode(ISD::BR, DL, MVT::Other, N1, N3); 2839 else 2840 return N1; // Never-taken branch 2841 } 2842 break; 2843 case ISD::VECTOR_SHUFFLE: 2844 assert(N1.getValueType() == N2.getValueType() && 2845 N1.getValueType().isVector() && 2846 VT.isVector() && N3.getValueType().isVector() && 2847 N3.getOpcode() == ISD::BUILD_VECTOR && 2848 VT.getVectorNumElements() == N3.getNumOperands() && 2849 "Illegal VECTOR_SHUFFLE node!"); 2850 break; 2851 case ISD::BIT_CONVERT: 2852 // Fold bit_convert nodes from a type to themselves. 2853 if (N1.getValueType() == VT) 2854 return N1; 2855 break; 2856 } 2857 2858 // Memoize node if it doesn't produce a flag. 2859 SDNode *N; 2860 SDVTList VTs = getVTList(VT); 2861 if (VT != MVT::Flag) { 2862 SDValue Ops[] = { N1, N2, N3 }; 2863 FoldingSetNodeID ID; 2864 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 2865 void *IP = 0; 2866 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 2867 return SDValue(E, 0); 2868 N = NodeAllocator.Allocate<TernarySDNode>(); 2869 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2870 CSEMap.InsertNode(N, IP); 2871 } else { 2872 N = NodeAllocator.Allocate<TernarySDNode>(); 2873 new (N) TernarySDNode(Opcode, DL, VTs, N1, N2, N3); 2874 } 2875 AllNodes.push_back(N); 2876#ifndef NDEBUG 2877 VerifyNode(N); 2878#endif 2879 return SDValue(N, 0); 2880} 2881 2882SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2883 SDValue N1, SDValue N2, SDValue N3, 2884 SDValue N4) { 2885 return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4); 2886} 2887 2888SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2889 SDValue N1, SDValue N2, SDValue N3, 2890 SDValue N4) { 2891 SDValue Ops[] = { N1, N2, N3, N4 }; 2892 return getNode(Opcode, DL, VT, Ops, 4); 2893} 2894 2895SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 2896 SDValue N1, SDValue N2, SDValue N3, 2897 SDValue N4, SDValue N5) { 2898 return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4, N5); 2899} 2900 2901SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 2902 SDValue N1, SDValue N2, SDValue N3, 2903 SDValue N4, SDValue N5) { 2904 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 2905 return getNode(Opcode, DL, VT, Ops, 5); 2906} 2907 2908/// getMemsetValue - Vectorized representation of the memset value 2909/// operand. 2910static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, 2911 DebugLoc dl) { 2912 unsigned NumBits = VT.isVector() ? 2913 VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); 2914 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) { 2915 APInt Val = APInt(NumBits, C->getZExtValue() & 255); 2916 unsigned Shift = 8; 2917 for (unsigned i = NumBits; i > 8; i >>= 1) { 2918 Val = (Val << Shift) | Val; 2919 Shift <<= 1; 2920 } 2921 if (VT.isInteger()) 2922 return DAG.getConstant(Val, VT); 2923 return DAG.getConstantFP(APFloat(Val), VT); 2924 } 2925 2926 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2927 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value); 2928 unsigned Shift = 8; 2929 for (unsigned i = NumBits; i > 8; i >>= 1) { 2930 Value = DAG.getNode(ISD::OR, dl, VT, 2931 DAG.getNode(ISD::SHL, dl, VT, Value, 2932 DAG.getConstant(Shift, 2933 TLI.getShiftAmountTy())), 2934 Value); 2935 Shift <<= 1; 2936 } 2937 2938 return Value; 2939} 2940 2941/// getMemsetStringVal - Similar to getMemsetValue. Except this is only 2942/// used when a memcpy is turned into a memset when the source is a constant 2943/// string ptr. 2944static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, 2945 const TargetLowering &TLI, 2946 std::string &Str, unsigned Offset) { 2947 // Handle vector with all elements zero. 2948 if (Str.empty()) { 2949 if (VT.isInteger()) 2950 return DAG.getConstant(0, VT); 2951 unsigned NumElts = VT.getVectorNumElements(); 2952 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 2953 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 2954 DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); 2955 } 2956 2957 assert(!VT.isVector() && "Can't handle vector type here!"); 2958 unsigned NumBits = VT.getSizeInBits(); 2959 unsigned MSB = NumBits / 8; 2960 uint64_t Val = 0; 2961 if (TLI.isLittleEndian()) 2962 Offset = Offset + MSB - 1; 2963 for (unsigned i = 0; i != MSB; ++i) { 2964 Val = (Val << 8) | (unsigned char)Str[Offset]; 2965 Offset += TLI.isLittleEndian() ? -1 : 1; 2966 } 2967 return DAG.getConstant(Val, VT); 2968} 2969 2970/// getMemBasePlusOffset - Returns base and offset node for the 2971/// 2972static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, 2973 SelectionDAG &DAG) { 2974 MVT VT = Base.getValueType(); 2975 return DAG.getNode(ISD::ADD, Base.getNode()->getDebugLoc(), 2976 VT, Base, DAG.getConstant(Offset, VT)); 2977} 2978 2979/// isMemSrcFromString - Returns true if memcpy source is a string constant. 2980/// 2981static bool isMemSrcFromString(SDValue Src, std::string &Str) { 2982 unsigned SrcDelta = 0; 2983 GlobalAddressSDNode *G = NULL; 2984 if (Src.getOpcode() == ISD::GlobalAddress) 2985 G = cast<GlobalAddressSDNode>(Src); 2986 else if (Src.getOpcode() == ISD::ADD && 2987 Src.getOperand(0).getOpcode() == ISD::GlobalAddress && 2988 Src.getOperand(1).getOpcode() == ISD::Constant) { 2989 G = cast<GlobalAddressSDNode>(Src.getOperand(0)); 2990 SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue(); 2991 } 2992 if (!G) 2993 return false; 2994 2995 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal()); 2996 if (GV && GetConstantStringInfo(GV, Str, SrcDelta, false)) 2997 return true; 2998 2999 return false; 3000} 3001 3002/// MeetsMaxMemopRequirement - Determines if the number of memory ops required 3003/// to replace the memset / memcpy is below the threshold. It also returns the 3004/// types of the sequence of memory ops to perform memset / memcpy. 3005static 3006bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, 3007 SDValue Dst, SDValue Src, 3008 unsigned Limit, uint64_t Size, unsigned &Align, 3009 std::string &Str, bool &isSrcStr, 3010 SelectionDAG &DAG, 3011 const TargetLowering &TLI) { 3012 isSrcStr = isMemSrcFromString(Src, Str); 3013 bool isSrcConst = isa<ConstantSDNode>(Src); 3014 bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); 3015 MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr); 3016 if (VT != MVT::iAny) { 3017 unsigned NewAlign = (unsigned) 3018 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); 3019 // If source is a string constant, this will require an unaligned load. 3020 if (NewAlign > Align && (isSrcConst || AllowUnalign)) { 3021 if (Dst.getOpcode() != ISD::FrameIndex) { 3022 // Can't change destination alignment. It requires a unaligned store. 3023 if (AllowUnalign) 3024 VT = MVT::iAny; 3025 } else { 3026 int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); 3027 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3028 if (MFI->isFixedObjectIndex(FI)) { 3029 // Can't change destination alignment. It requires a unaligned store. 3030 if (AllowUnalign) 3031 VT = MVT::iAny; 3032 } else { 3033 // Give the stack frame object a larger alignment if needed. 3034 if (MFI->getObjectAlignment(FI) < NewAlign) 3035 MFI->setObjectAlignment(FI, NewAlign); 3036 Align = NewAlign; 3037 } 3038 } 3039 } 3040 } 3041 3042 if (VT == MVT::iAny) { 3043 if (AllowUnalign) { 3044 VT = MVT::i64; 3045 } else { 3046 switch (Align & 7) { 3047 case 0: VT = MVT::i64; break; 3048 case 4: VT = MVT::i32; break; 3049 case 2: VT = MVT::i16; break; 3050 default: VT = MVT::i8; break; 3051 } 3052 } 3053 3054 MVT LVT = MVT::i64; 3055 while (!TLI.isTypeLegal(LVT)) 3056 LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); 3057 assert(LVT.isInteger()); 3058 3059 if (VT.bitsGT(LVT)) 3060 VT = LVT; 3061 } 3062 3063 unsigned NumMemOps = 0; 3064 while (Size != 0) { 3065 unsigned VTSize = VT.getSizeInBits() / 8; 3066 while (VTSize > Size) { 3067 // For now, only use non-vector load / store's for the left-over pieces. 3068 if (VT.isVector()) { 3069 VT = MVT::i64; 3070 while (!TLI.isTypeLegal(VT)) 3071 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3072 VTSize = VT.getSizeInBits() / 8; 3073 } else { 3074 VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); 3075 VTSize >>= 1; 3076 } 3077 } 3078 3079 if (++NumMemOps > Limit) 3080 return false; 3081 MemOps.push_back(VT); 3082 Size -= VTSize; 3083 } 3084 3085 return true; 3086} 3087 3088static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3089 SDValue Chain, SDValue Dst, 3090 SDValue Src, uint64_t Size, 3091 unsigned Align, bool AlwaysInline, 3092 const Value *DstSV, uint64_t DstSVOff, 3093 const Value *SrcSV, uint64_t SrcSVOff){ 3094 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3095 3096 // Expand memcpy to a series of load and store ops if the size operand falls 3097 // below a certain threshold. 3098 std::vector<MVT> MemOps; 3099 uint64_t Limit = -1ULL; 3100 if (!AlwaysInline) 3101 Limit = TLI.getMaxStoresPerMemcpy(); 3102 unsigned DstAlign = Align; // Destination alignment can change. 3103 std::string Str; 3104 bool CopyFromStr; 3105 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3106 Str, CopyFromStr, DAG, TLI)) 3107 return SDValue(); 3108 3109 3110 bool isZeroStr = CopyFromStr && Str.empty(); 3111 SmallVector<SDValue, 8> OutChains; 3112 unsigned NumMemOps = MemOps.size(); 3113 uint64_t SrcOff = 0, DstOff = 0; 3114 for (unsigned i = 0; i < NumMemOps; i++) { 3115 MVT VT = MemOps[i]; 3116 unsigned VTSize = VT.getSizeInBits() / 8; 3117 SDValue Value, Store; 3118 3119 if (CopyFromStr && (isZeroStr || !VT.isVector())) { 3120 // It's unlikely a store of a vector immediate can be done in a single 3121 // instruction. It would require a load from a constantpool first. 3122 // We also handle store a vector with all zero's. 3123 // FIXME: Handle other cases where store of vector immediate is done in 3124 // a single instruction. 3125 Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff); 3126 Store = DAG.getStore(Chain, dl, Value, 3127 getMemBasePlusOffset(Dst, DstOff, DAG), 3128 DstSV, DstSVOff + DstOff, false, DstAlign); 3129 } else { 3130 Value = DAG.getLoad(VT, dl, Chain, 3131 getMemBasePlusOffset(Src, SrcOff, DAG), 3132 SrcSV, SrcSVOff + SrcOff, false, Align); 3133 Store = DAG.getStore(Chain, dl, Value, 3134 getMemBasePlusOffset(Dst, DstOff, DAG), 3135 DstSV, DstSVOff + DstOff, false, DstAlign); 3136 } 3137 OutChains.push_back(Store); 3138 SrcOff += VTSize; 3139 DstOff += VTSize; 3140 } 3141 3142 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3143 &OutChains[0], OutChains.size()); 3144} 3145 3146static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, 3147 SDValue Chain, SDValue Dst, 3148 SDValue Src, uint64_t Size, 3149 unsigned Align, bool AlwaysInline, 3150 const Value *DstSV, uint64_t DstSVOff, 3151 const Value *SrcSV, uint64_t SrcSVOff){ 3152 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3153 3154 // Expand memmove to a series of load and store ops if the size operand falls 3155 // below a certain threshold. 3156 std::vector<MVT> MemOps; 3157 uint64_t Limit = -1ULL; 3158 if (!AlwaysInline) 3159 Limit = TLI.getMaxStoresPerMemmove(); 3160 unsigned DstAlign = Align; // Destination alignment can change. 3161 std::string Str; 3162 bool CopyFromStr; 3163 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, Limit, Size, DstAlign, 3164 Str, CopyFromStr, DAG, TLI)) 3165 return SDValue(); 3166 3167 uint64_t SrcOff = 0, DstOff = 0; 3168 3169 SmallVector<SDValue, 8> LoadValues; 3170 SmallVector<SDValue, 8> LoadChains; 3171 SmallVector<SDValue, 8> OutChains; 3172 unsigned NumMemOps = MemOps.size(); 3173 for (unsigned i = 0; i < NumMemOps; i++) { 3174 MVT VT = MemOps[i]; 3175 unsigned VTSize = VT.getSizeInBits() / 8; 3176 SDValue Value, Store; 3177 3178 Value = DAG.getLoad(VT, dl, Chain, 3179 getMemBasePlusOffset(Src, SrcOff, DAG), 3180 SrcSV, SrcSVOff + SrcOff, false, Align); 3181 LoadValues.push_back(Value); 3182 LoadChains.push_back(Value.getValue(1)); 3183 SrcOff += VTSize; 3184 } 3185 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3186 &LoadChains[0], LoadChains.size()); 3187 OutChains.clear(); 3188 for (unsigned i = 0; i < NumMemOps; i++) { 3189 MVT VT = MemOps[i]; 3190 unsigned VTSize = VT.getSizeInBits() / 8; 3191 SDValue Value, Store; 3192 3193 Store = DAG.getStore(Chain, dl, LoadValues[i], 3194 getMemBasePlusOffset(Dst, DstOff, DAG), 3195 DstSV, DstSVOff + DstOff, false, DstAlign); 3196 OutChains.push_back(Store); 3197 DstOff += VTSize; 3198 } 3199 3200 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3201 &OutChains[0], OutChains.size()); 3202} 3203 3204static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, 3205 SDValue Chain, SDValue Dst, 3206 SDValue Src, uint64_t Size, 3207 unsigned Align, 3208 const Value *DstSV, uint64_t DstSVOff) { 3209 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3210 3211 // Expand memset to a series of load/store ops if the size operand 3212 // falls below a certain threshold. 3213 std::vector<MVT> MemOps; 3214 std::string Str; 3215 bool CopyFromStr; 3216 if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), 3217 Size, Align, Str, CopyFromStr, DAG, TLI)) 3218 return SDValue(); 3219 3220 SmallVector<SDValue, 8> OutChains; 3221 uint64_t DstOff = 0; 3222 3223 unsigned NumMemOps = MemOps.size(); 3224 for (unsigned i = 0; i < NumMemOps; i++) { 3225 MVT VT = MemOps[i]; 3226 unsigned VTSize = VT.getSizeInBits() / 8; 3227 SDValue Value = getMemsetValue(Src, VT, DAG, dl); 3228 SDValue Store = DAG.getStore(Chain, dl, Value, 3229 getMemBasePlusOffset(Dst, DstOff, DAG), 3230 DstSV, DstSVOff + DstOff); 3231 OutChains.push_back(Store); 3232 DstOff += VTSize; 3233 } 3234 3235 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3236 &OutChains[0], OutChains.size()); 3237} 3238 3239SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, 3240 SDValue Src, SDValue Size, 3241 unsigned Align, bool AlwaysInline, 3242 const Value *DstSV, uint64_t DstSVOff, 3243 const Value *SrcSV, uint64_t SrcSVOff) { 3244 3245 // Check to see if we should lower the memcpy to loads and stores first. 3246 // For cases within the target-specified limits, this is the best choice. 3247 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3248 if (ConstantSize) { 3249 // Memcpy with size zero? Just return the original chain. 3250 if (ConstantSize->isNullValue()) 3251 return Chain; 3252 3253 SDValue Result = 3254 getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3255 ConstantSize->getZExtValue(), 3256 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3257 if (Result.getNode()) 3258 return Result; 3259 } 3260 3261 // Then check to see if we should lower the memcpy with target-specific 3262 // code. If the target chooses to do this, this is the next best. 3263 SDValue Result = 3264 TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align, 3265 AlwaysInline, 3266 DstSV, DstSVOff, SrcSV, SrcSVOff); 3267 if (Result.getNode()) 3268 return Result; 3269 3270 // If we really need inline code and the target declined to provide it, 3271 // use a (potentially long) sequence of loads and stores. 3272 if (AlwaysInline) { 3273 assert(ConstantSize && "AlwaysInline requires a constant size!"); 3274 return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, 3275 ConstantSize->getZExtValue(), Align, true, 3276 DstSV, DstSVOff, SrcSV, SrcSVOff); 3277 } 3278 3279 // Emit a library call. 3280 TargetLowering::ArgListTy Args; 3281 TargetLowering::ArgListEntry Entry; 3282 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3283 Entry.Node = Dst; Args.push_back(Entry); 3284 Entry.Node = Src; Args.push_back(Entry); 3285 Entry.Node = Size; Args.push_back(Entry); 3286 // FIXME: pass in DebugLoc 3287 std::pair<SDValue,SDValue> CallResult = 3288 TLI.LowerCallTo(Chain, Type::VoidTy, 3289 false, false, false, false, CallingConv::C, false, 3290 getExternalSymbol("memcpy", TLI.getPointerTy()), 3291 Args, *this, dl); 3292 return CallResult.second; 3293} 3294 3295SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, 3296 SDValue Src, SDValue Size, 3297 unsigned Align, 3298 const Value *DstSV, uint64_t DstSVOff, 3299 const Value *SrcSV, uint64_t SrcSVOff) { 3300 3301 // Check to see if we should lower the memmove to loads and stores first. 3302 // For cases within the target-specified limits, this is the best choice. 3303 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3304 if (ConstantSize) { 3305 // Memmove with size zero? Just return the original chain. 3306 if (ConstantSize->isNullValue()) 3307 return Chain; 3308 3309 SDValue Result = 3310 getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src, 3311 ConstantSize->getZExtValue(), 3312 Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff); 3313 if (Result.getNode()) 3314 return Result; 3315 } 3316 3317 // Then check to see if we should lower the memmove with target-specific 3318 // code. If the target chooses to do this, this is the next best. 3319 SDValue Result = 3320 TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align, 3321 DstSV, DstSVOff, SrcSV, SrcSVOff); 3322 if (Result.getNode()) 3323 return Result; 3324 3325 // Emit a library call. 3326 TargetLowering::ArgListTy Args; 3327 TargetLowering::ArgListEntry Entry; 3328 Entry.Ty = TLI.getTargetData()->getIntPtrType(); 3329 Entry.Node = Dst; Args.push_back(Entry); 3330 Entry.Node = Src; Args.push_back(Entry); 3331 Entry.Node = Size; Args.push_back(Entry); 3332 // FIXME: pass in DebugLoc 3333 std::pair<SDValue,SDValue> CallResult = 3334 TLI.LowerCallTo(Chain, Type::VoidTy, 3335 false, false, false, false, CallingConv::C, false, 3336 getExternalSymbol("memmove", TLI.getPointerTy()), 3337 Args, *this, dl); 3338 return CallResult.second; 3339} 3340 3341SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, 3342 SDValue Src, SDValue Size, 3343 unsigned Align, 3344 const Value *DstSV, uint64_t DstSVOff) { 3345 3346 // Check to see if we should lower the memset to stores first. 3347 // For cases within the target-specified limits, this is the best choice. 3348 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 3349 if (ConstantSize) { 3350 // Memset with size zero? Just return the original chain. 3351 if (ConstantSize->isNullValue()) 3352 return Chain; 3353 3354 SDValue Result = 3355 getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), 3356 Align, DstSV, DstSVOff); 3357 if (Result.getNode()) 3358 return Result; 3359 } 3360 3361 // Then check to see if we should lower the memset with target-specific 3362 // code. If the target chooses to do this, this is the next best. 3363 SDValue Result = 3364 TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align, 3365 DstSV, DstSVOff); 3366 if (Result.getNode()) 3367 return Result; 3368 3369 // Emit a library call. 3370 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 3371 TargetLowering::ArgListTy Args; 3372 TargetLowering::ArgListEntry Entry; 3373 Entry.Node = Dst; Entry.Ty = IntPtrTy; 3374 Args.push_back(Entry); 3375 // Extend or truncate the argument to be an i32 value for the call. 3376 if (Src.getValueType().bitsGT(MVT::i32)) 3377 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); 3378 else 3379 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); 3380 Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 3381 Args.push_back(Entry); 3382 Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; 3383 Args.push_back(Entry); 3384 // FIXME: pass in DebugLoc 3385 std::pair<SDValue,SDValue> CallResult = 3386 TLI.LowerCallTo(Chain, Type::VoidTy, 3387 false, false, false, false, CallingConv::C, false, 3388 getExternalSymbol("memset", TLI.getPointerTy()), 3389 Args, *this, dl); 3390 return CallResult.second; 3391} 3392 3393SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3394 SDValue Chain, 3395 SDValue Ptr, SDValue Cmp, 3396 SDValue Swp, const Value* PtrVal, 3397 unsigned Alignment) { 3398 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); 3399 assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); 3400 3401 MVT VT = Cmp.getValueType(); 3402 3403 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3404 Alignment = getMVTAlignment(MemVT); 3405 3406 SDVTList VTs = getVTList(VT, MVT::Other); 3407 FoldingSetNodeID ID; 3408 ID.AddInteger(MemVT.getRawBits()); 3409 SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; 3410 AddNodeIDNode(ID, Opcode, VTs, Ops, 4); 3411 void* IP = 0; 3412 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3413 return SDValue(E, 0); 3414 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3415 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3416 Chain, Ptr, Cmp, Swp, PtrVal, Alignment); 3417 CSEMap.InsertNode(N, IP); 3418 AllNodes.push_back(N); 3419 return SDValue(N, 0); 3420} 3421 3422SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, 3423 SDValue Chain, 3424 SDValue Ptr, SDValue Val, 3425 const Value* PtrVal, 3426 unsigned Alignment) { 3427 assert((Opcode == ISD::ATOMIC_LOAD_ADD || 3428 Opcode == ISD::ATOMIC_LOAD_SUB || 3429 Opcode == ISD::ATOMIC_LOAD_AND || 3430 Opcode == ISD::ATOMIC_LOAD_OR || 3431 Opcode == ISD::ATOMIC_LOAD_XOR || 3432 Opcode == ISD::ATOMIC_LOAD_NAND || 3433 Opcode == ISD::ATOMIC_LOAD_MIN || 3434 Opcode == ISD::ATOMIC_LOAD_MAX || 3435 Opcode == ISD::ATOMIC_LOAD_UMIN || 3436 Opcode == ISD::ATOMIC_LOAD_UMAX || 3437 Opcode == ISD::ATOMIC_SWAP) && 3438 "Invalid Atomic Op"); 3439 3440 MVT VT = Val.getValueType(); 3441 3442 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3443 Alignment = getMVTAlignment(MemVT); 3444 3445 SDVTList VTs = getVTList(VT, MVT::Other); 3446 FoldingSetNodeID ID; 3447 ID.AddInteger(MemVT.getRawBits()); 3448 SDValue Ops[] = {Chain, Ptr, Val}; 3449 AddNodeIDNode(ID, Opcode, VTs, Ops, 3); 3450 void* IP = 0; 3451 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3452 return SDValue(E, 0); 3453 SDNode* N = NodeAllocator.Allocate<AtomicSDNode>(); 3454 new (N) AtomicSDNode(Opcode, dl, VTs, MemVT, 3455 Chain, Ptr, Val, PtrVal, Alignment); 3456 CSEMap.InsertNode(N, IP); 3457 AllNodes.push_back(N); 3458 return SDValue(N, 0); 3459} 3460 3461/// getMergeValues - Create a MERGE_VALUES node from the given operands. 3462/// Allowed to return something different (and simpler) if Simplify is true. 3463SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, 3464 DebugLoc dl) { 3465 if (NumOps == 1) 3466 return Ops[0]; 3467 3468 SmallVector<MVT, 4> VTs; 3469 VTs.reserve(NumOps); 3470 for (unsigned i = 0; i < NumOps; ++i) 3471 VTs.push_back(Ops[i].getValueType()); 3472 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps), 3473 Ops, NumOps); 3474} 3475 3476SDValue 3477SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, 3478 const MVT *VTs, unsigned NumVTs, 3479 const SDValue *Ops, unsigned NumOps, 3480 MVT MemVT, const Value *srcValue, int SVOff, 3481 unsigned Align, bool Vol, 3482 bool ReadMem, bool WriteMem) { 3483 return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, 3484 MemVT, srcValue, SVOff, Align, Vol, 3485 ReadMem, WriteMem); 3486} 3487 3488SDValue 3489SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, 3490 const SDValue *Ops, unsigned NumOps, 3491 MVT MemVT, const Value *srcValue, int SVOff, 3492 unsigned Align, bool Vol, 3493 bool ReadMem, bool WriteMem) { 3494 // Memoize the node unless it returns a flag. 3495 MemIntrinsicSDNode *N; 3496 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3497 FoldingSetNodeID ID; 3498 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3499 void *IP = 0; 3500 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3501 return SDValue(E, 0); 3502 3503 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3504 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3505 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3506 CSEMap.InsertNode(N, IP); 3507 } else { 3508 N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); 3509 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT, 3510 srcValue, SVOff, Align, Vol, ReadMem, WriteMem); 3511 } 3512 AllNodes.push_back(N); 3513 return SDValue(N, 0); 3514} 3515 3516SDValue 3517SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs, 3518 bool IsTailCall, bool IsInreg, SDVTList VTs, 3519 const SDValue *Operands, unsigned NumOperands) { 3520 // Do not include isTailCall in the folding set profile. 3521 FoldingSetNodeID ID; 3522 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands); 3523 ID.AddInteger(CallingConv); 3524 ID.AddInteger(IsVarArgs); 3525 void *IP = 0; 3526 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) { 3527 // Instead of including isTailCall in the folding set, we just 3528 // set the flag of the existing node. 3529 if (!IsTailCall) 3530 cast<CallSDNode>(E)->setNotTailCall(); 3531 return SDValue(E, 0); 3532 } 3533 SDNode *N = NodeAllocator.Allocate<CallSDNode>(); 3534 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg, 3535 VTs, Operands, NumOperands); 3536 CSEMap.InsertNode(N, IP); 3537 AllNodes.push_back(N); 3538 return SDValue(N, 0); 3539} 3540 3541SDValue 3542SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, 3543 ISD::LoadExtType ExtType, MVT VT, SDValue Chain, 3544 SDValue Ptr, SDValue Offset, 3545 const Value *SV, int SVOffset, MVT EVT, 3546 bool isVolatile, unsigned Alignment) { 3547 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3548 Alignment = getMVTAlignment(VT); 3549 3550 if (VT == EVT) { 3551 ExtType = ISD::NON_EXTLOAD; 3552 } else if (ExtType == ISD::NON_EXTLOAD) { 3553 assert(VT == EVT && "Non-extending load from different memory type!"); 3554 } else { 3555 // Extending load. 3556 if (VT.isVector()) 3557 assert(EVT.getVectorNumElements() == VT.getVectorNumElements() && 3558 "Invalid vector extload!"); 3559 else 3560 assert(EVT.bitsLT(VT) && 3561 "Should only be an extending load, not truncating!"); 3562 assert((ExtType == ISD::EXTLOAD || VT.isInteger()) && 3563 "Cannot sign/zero extend a FP/Vector load!"); 3564 assert(VT.isInteger() == EVT.isInteger() && 3565 "Cannot convert from FP to Int or Int -> FP!"); 3566 } 3567 3568 bool Indexed = AM != ISD::UNINDEXED; 3569 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) && 3570 "Unindexed load with an offset!"); 3571 3572 SDVTList VTs = Indexed ? 3573 getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); 3574 SDValue Ops[] = { Chain, Ptr, Offset }; 3575 FoldingSetNodeID ID; 3576 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); 3577 ID.AddInteger(EVT.getRawBits()); 3578 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment)); 3579 void *IP = 0; 3580 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3581 return SDValue(E, 0); 3582 SDNode *N = NodeAllocator.Allocate<LoadSDNode>(); 3583 new (N) LoadSDNode(Ops, dl, VTs, AM, ExtType, EVT, SV, SVOffset, 3584 Alignment, isVolatile); 3585 CSEMap.InsertNode(N, IP); 3586 AllNodes.push_back(N); 3587 return SDValue(N, 0); 3588} 3589 3590SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, 3591 SDValue Chain, SDValue Ptr, 3592 const Value *SV, int SVOffset, 3593 bool isVolatile, unsigned Alignment) { 3594 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3595 return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef, 3596 SV, SVOffset, VT, isVolatile, Alignment); 3597} 3598 3599SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, 3600 SDValue Chain, SDValue Ptr, 3601 const Value *SV, 3602 int SVOffset, MVT EVT, 3603 bool isVolatile, unsigned Alignment) { 3604 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3605 return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, 3606 SV, SVOffset, EVT, isVolatile, Alignment); 3607} 3608 3609SDValue 3610SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, 3611 SDValue Offset, ISD::MemIndexedMode AM) { 3612 LoadSDNode *LD = cast<LoadSDNode>(OrigLoad); 3613 assert(LD->getOffset().getOpcode() == ISD::UNDEF && 3614 "Load is already a indexed load!"); 3615 return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(), 3616 LD->getChain(), Base, Offset, LD->getSrcValue(), 3617 LD->getSrcValueOffset(), LD->getMemoryVT(), 3618 LD->isVolatile(), LD->getAlignment()); 3619} 3620 3621SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, 3622 SDValue Ptr, const Value *SV, int SVOffset, 3623 bool isVolatile, unsigned Alignment) { 3624 MVT VT = Val.getValueType(); 3625 3626 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3627 Alignment = getMVTAlignment(VT); 3628 3629 SDVTList VTs = getVTList(MVT::Other); 3630 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3631 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3632 FoldingSetNodeID ID; 3633 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3634 ID.AddInteger(VT.getRawBits()); 3635 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, 3636 isVolatile, Alignment)); 3637 void *IP = 0; 3638 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3639 return SDValue(E, 0); 3640 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3641 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, false, 3642 VT, SV, SVOffset, Alignment, isVolatile); 3643 CSEMap.InsertNode(N, IP); 3644 AllNodes.push_back(N); 3645 return SDValue(N, 0); 3646} 3647 3648SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, 3649 SDValue Ptr, const Value *SV, 3650 int SVOffset, MVT SVT, 3651 bool isVolatile, unsigned Alignment) { 3652 MVT VT = Val.getValueType(); 3653 3654 if (VT == SVT) 3655 return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); 3656 3657 assert(VT.bitsGT(SVT) && "Not a truncation?"); 3658 assert(VT.isInteger() == SVT.isInteger() && 3659 "Can't do FP-INT conversion!"); 3660 3661 if (Alignment == 0) // Ensure that codegen never sees alignment 0 3662 Alignment = getMVTAlignment(VT); 3663 3664 SDVTList VTs = getVTList(MVT::Other); 3665 SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType()); 3666 SDValue Ops[] = { Chain, Val, Ptr, Undef }; 3667 FoldingSetNodeID ID; 3668 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3669 ID.AddInteger(SVT.getRawBits()); 3670 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, 3671 isVolatile, Alignment)); 3672 void *IP = 0; 3673 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3674 return SDValue(E, 0); 3675 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3676 new (N) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, true, 3677 SVT, SV, SVOffset, Alignment, isVolatile); 3678 CSEMap.InsertNode(N, IP); 3679 AllNodes.push_back(N); 3680 return SDValue(N, 0); 3681} 3682 3683SDValue 3684SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, 3685 SDValue Offset, ISD::MemIndexedMode AM) { 3686 StoreSDNode *ST = cast<StoreSDNode>(OrigStore); 3687 assert(ST->getOffset().getOpcode() == ISD::UNDEF && 3688 "Store is already a indexed store!"); 3689 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); 3690 SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; 3691 FoldingSetNodeID ID; 3692 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); 3693 ID.AddInteger(ST->getMemoryVT().getRawBits()); 3694 ID.AddInteger(ST->getRawSubclassData()); 3695 void *IP = 0; 3696 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3697 return SDValue(E, 0); 3698 SDNode *N = NodeAllocator.Allocate<StoreSDNode>(); 3699 new (N) StoreSDNode(Ops, dl, VTs, AM, 3700 ST->isTruncatingStore(), ST->getMemoryVT(), 3701 ST->getSrcValue(), ST->getSrcValueOffset(), 3702 ST->getAlignment(), ST->isVolatile()); 3703 CSEMap.InsertNode(N, IP); 3704 AllNodes.push_back(N); 3705 return SDValue(N, 0); 3706} 3707 3708SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, 3709 SDValue Chain, SDValue Ptr, 3710 SDValue SV) { 3711 SDValue Ops[] = { Chain, Ptr, SV }; 3712 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); 3713} 3714 3715SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, 3716 const SDUse *Ops, unsigned NumOps) { 3717 return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps); 3718} 3719 3720SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3721 const SDUse *Ops, unsigned NumOps) { 3722 switch (NumOps) { 3723 case 0: return getNode(Opcode, DL, VT); 3724 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3725 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3726 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3727 default: break; 3728 } 3729 3730 // Copy from an SDUse array into an SDValue array for use with 3731 // the regular getNode logic. 3732 SmallVector<SDValue, 8> NewOps(Ops, Ops + NumOps); 3733 return getNode(Opcode, DL, VT, &NewOps[0], NumOps); 3734} 3735 3736SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, 3737 const SDValue *Ops, unsigned NumOps) { 3738 switch (NumOps) { 3739 case 0: return getNode(Opcode, DL, VT); 3740 case 1: return getNode(Opcode, DL, VT, Ops[0]); 3741 case 2: return getNode(Opcode, DL, VT, Ops[0], Ops[1]); 3742 case 3: return getNode(Opcode, DL, VT, Ops[0], Ops[1], Ops[2]); 3743 default: break; 3744 } 3745 3746 switch (Opcode) { 3747 default: break; 3748 case ISD::SELECT_CC: { 3749 assert(NumOps == 5 && "SELECT_CC takes 5 operands!"); 3750 assert(Ops[0].getValueType() == Ops[1].getValueType() && 3751 "LHS and RHS of condition must have same type!"); 3752 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3753 "True and False arms of SelectCC must have same type!"); 3754 assert(Ops[2].getValueType() == VT && 3755 "select_cc node must be of same type as true and false value!"); 3756 break; 3757 } 3758 case ISD::BR_CC: { 3759 assert(NumOps == 5 && "BR_CC takes 5 operands!"); 3760 assert(Ops[2].getValueType() == Ops[3].getValueType() && 3761 "LHS/RHS of comparison should match types!"); 3762 break; 3763 } 3764 } 3765 3766 // Memoize nodes. 3767 SDNode *N; 3768 SDVTList VTs = getVTList(VT); 3769 3770 if (VT != MVT::Flag) { 3771 FoldingSetNodeID ID; 3772 AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); 3773 void *IP = 0; 3774 3775 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3776 return SDValue(E, 0); 3777 3778 N = NodeAllocator.Allocate<SDNode>(); 3779 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3780 CSEMap.InsertNode(N, IP); 3781 } else { 3782 N = NodeAllocator.Allocate<SDNode>(); 3783 new (N) SDNode(Opcode, DL, VTs, Ops, NumOps); 3784 } 3785 3786 AllNodes.push_back(N); 3787#ifndef NDEBUG 3788 VerifyNode(N); 3789#endif 3790 return SDValue(N, 0); 3791} 3792 3793SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3794 const std::vector<MVT> &ResultTys, 3795 const SDValue *Ops, unsigned NumOps) { 3796 return getNode(Opcode, DL, getNodeValueTypes(ResultTys), ResultTys.size(), 3797 Ops, NumOps); 3798} 3799 3800SDValue SelectionDAG::getNode(unsigned Opcode, 3801 const MVT *VTs, unsigned NumVTs, 3802 const SDValue *Ops, unsigned NumOps) { 3803 return getNode(Opcode, DebugLoc::getUnknownLoc(), VTs, NumVTs, Ops, NumOps); 3804} 3805 3806SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, 3807 const MVT *VTs, unsigned NumVTs, 3808 const SDValue *Ops, unsigned NumOps) { 3809 if (NumVTs == 1) 3810 return getNode(Opcode, DL, VTs[0], Ops, NumOps); 3811 return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps); 3812} 3813 3814SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList, 3815 const SDValue *Ops, unsigned NumOps) { 3816 return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, Ops, NumOps); 3817} 3818 3819SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3820 const SDValue *Ops, unsigned NumOps) { 3821 if (VTList.NumVTs == 1) 3822 return getNode(Opcode, DL, VTList.VTs[0], Ops, NumOps); 3823 3824 switch (Opcode) { 3825 // FIXME: figure out how to safely handle things like 3826 // int foo(int x) { return 1 << (x & 255); } 3827 // int bar() { return foo(256); } 3828#if 0 3829 case ISD::SRA_PARTS: 3830 case ISD::SRL_PARTS: 3831 case ISD::SHL_PARTS: 3832 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 3833 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 3834 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3835 else if (N3.getOpcode() == ISD::AND) 3836 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 3837 // If the and is only masking out bits that cannot effect the shift, 3838 // eliminate the and. 3839 unsigned NumBits = VT.getSizeInBits()*2; 3840 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 3841 return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); 3842 } 3843 break; 3844#endif 3845 } 3846 3847 // Memoize the node unless it returns a flag. 3848 SDNode *N; 3849 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 3850 FoldingSetNodeID ID; 3851 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 3852 void *IP = 0; 3853 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 3854 return SDValue(E, 0); 3855 if (NumOps == 1) { 3856 N = NodeAllocator.Allocate<UnarySDNode>(); 3857 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3858 } else if (NumOps == 2) { 3859 N = NodeAllocator.Allocate<BinarySDNode>(); 3860 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3861 } else if (NumOps == 3) { 3862 N = NodeAllocator.Allocate<TernarySDNode>(); 3863 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3864 } else { 3865 N = NodeAllocator.Allocate<SDNode>(); 3866 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3867 } 3868 CSEMap.InsertNode(N, IP); 3869 } else { 3870 if (NumOps == 1) { 3871 N = NodeAllocator.Allocate<UnarySDNode>(); 3872 new (N) UnarySDNode(Opcode, DL, VTList, Ops[0]); 3873 } else if (NumOps == 2) { 3874 N = NodeAllocator.Allocate<BinarySDNode>(); 3875 new (N) BinarySDNode(Opcode, DL, VTList, Ops[0], Ops[1]); 3876 } else if (NumOps == 3) { 3877 N = NodeAllocator.Allocate<TernarySDNode>(); 3878 new (N) TernarySDNode(Opcode, DL, VTList, Ops[0], Ops[1], Ops[2]); 3879 } else { 3880 N = NodeAllocator.Allocate<SDNode>(); 3881 new (N) SDNode(Opcode, DL, VTList, Ops, NumOps); 3882 } 3883 } 3884 AllNodes.push_back(N); 3885#ifndef NDEBUG 3886 VerifyNode(N); 3887#endif 3888 return SDValue(N, 0); 3889} 3890 3891SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) { 3892 return getNode(Opcode, DL, VTList, 0, 0); 3893} 3894 3895SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3896 SDValue N1) { 3897 SDValue Ops[] = { N1 }; 3898 return getNode(Opcode, DL, VTList, Ops, 1); 3899} 3900 3901SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3902 SDValue N1, SDValue N2) { 3903 SDValue Ops[] = { N1, N2 }; 3904 return getNode(Opcode, DL, VTList, Ops, 2); 3905} 3906 3907SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3908 SDValue N1, SDValue N2, SDValue N3) { 3909 SDValue Ops[] = { N1, N2, N3 }; 3910 return getNode(Opcode, DL, VTList, Ops, 3); 3911} 3912 3913SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3914 SDValue N1, SDValue N2, SDValue N3, 3915 SDValue N4) { 3916 SDValue Ops[] = { N1, N2, N3, N4 }; 3917 return getNode(Opcode, DL, VTList, Ops, 4); 3918} 3919 3920SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, 3921 SDValue N1, SDValue N2, SDValue N3, 3922 SDValue N4, SDValue N5) { 3923 SDValue Ops[] = { N1, N2, N3, N4, N5 }; 3924 return getNode(Opcode, DL, VTList, Ops, 5); 3925} 3926 3927SDVTList SelectionDAG::getVTList(MVT VT) { 3928 return makeVTList(SDNode::getValueTypeList(VT), 1); 3929} 3930 3931SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { 3932 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3933 E = VTList.rend(); I != E; ++I) 3934 if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) 3935 return *I; 3936 3937 MVT *Array = Allocator.Allocate<MVT>(2); 3938 Array[0] = VT1; 3939 Array[1] = VT2; 3940 SDVTList Result = makeVTList(Array, 2); 3941 VTList.push_back(Result); 3942 return Result; 3943} 3944 3945SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { 3946 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3947 E = VTList.rend(); I != E; ++I) 3948 if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3949 I->VTs[2] == VT3) 3950 return *I; 3951 3952 MVT *Array = Allocator.Allocate<MVT>(3); 3953 Array[0] = VT1; 3954 Array[1] = VT2; 3955 Array[2] = VT3; 3956 SDVTList Result = makeVTList(Array, 3); 3957 VTList.push_back(Result); 3958 return Result; 3959} 3960 3961SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { 3962 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3963 E = VTList.rend(); I != E; ++I) 3964 if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && 3965 I->VTs[2] == VT3 && I->VTs[3] == VT4) 3966 return *I; 3967 3968 MVT *Array = Allocator.Allocate<MVT>(3); 3969 Array[0] = VT1; 3970 Array[1] = VT2; 3971 Array[2] = VT3; 3972 Array[3] = VT4; 3973 SDVTList Result = makeVTList(Array, 4); 3974 VTList.push_back(Result); 3975 return Result; 3976} 3977 3978SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { 3979 switch (NumVTs) { 3980 case 0: assert(0 && "Cannot have nodes without results!"); 3981 case 1: return getVTList(VTs[0]); 3982 case 2: return getVTList(VTs[0], VTs[1]); 3983 case 3: return getVTList(VTs[0], VTs[1], VTs[2]); 3984 default: break; 3985 } 3986 3987 for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), 3988 E = VTList.rend(); I != E; ++I) { 3989 if (I->NumVTs != NumVTs || VTs[0] != I->VTs[0] || VTs[1] != I->VTs[1]) 3990 continue; 3991 3992 bool NoMatch = false; 3993 for (unsigned i = 2; i != NumVTs; ++i) 3994 if (VTs[i] != I->VTs[i]) { 3995 NoMatch = true; 3996 break; 3997 } 3998 if (!NoMatch) 3999 return *I; 4000 } 4001 4002 MVT *Array = Allocator.Allocate<MVT>(NumVTs); 4003 std::copy(VTs, VTs+NumVTs, Array); 4004 SDVTList Result = makeVTList(Array, NumVTs); 4005 VTList.push_back(Result); 4006 return Result; 4007} 4008 4009 4010/// UpdateNodeOperands - *Mutate* the specified node in-place to have the 4011/// specified operands. If the resultant node already exists in the DAG, 4012/// this does not modify the specified node, instead it returns the node that 4013/// already exists. If the resultant node does not exist in the DAG, the 4014/// input node is returned. As a degenerate case, if you specify the same 4015/// input operands as the node already has, the input node is returned. 4016SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { 4017 SDNode *N = InN.getNode(); 4018 assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); 4019 4020 // Check to see if there is no change. 4021 if (Op == N->getOperand(0)) return InN; 4022 4023 // See if the modified node already exists. 4024 void *InsertPos = 0; 4025 if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) 4026 return SDValue(Existing, InN.getResNo()); 4027 4028 // Nope it doesn't. Remove the node from its current place in the maps. 4029 if (InsertPos) 4030 if (!RemoveNodeFromCSEMaps(N)) 4031 InsertPos = 0; 4032 4033 // Now we update the operands. 4034 N->OperandList[0].set(Op); 4035 4036 // If this gets put into a CSE map, add it. 4037 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4038 return InN; 4039} 4040 4041SDValue SelectionDAG:: 4042UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { 4043 SDNode *N = InN.getNode(); 4044 assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); 4045 4046 // Check to see if there is no change. 4047 if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) 4048 return InN; // No operands changed, just return the input node. 4049 4050 // See if the modified node already exists. 4051 void *InsertPos = 0; 4052 if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) 4053 return SDValue(Existing, InN.getResNo()); 4054 4055 // Nope it doesn't. Remove the node from its current place in the maps. 4056 if (InsertPos) 4057 if (!RemoveNodeFromCSEMaps(N)) 4058 InsertPos = 0; 4059 4060 // Now we update the operands. 4061 if (N->OperandList[0] != Op1) 4062 N->OperandList[0].set(Op1); 4063 if (N->OperandList[1] != Op2) 4064 N->OperandList[1].set(Op2); 4065 4066 // If this gets put into a CSE map, add it. 4067 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4068 return InN; 4069} 4070 4071SDValue SelectionDAG:: 4072UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { 4073 SDValue Ops[] = { Op1, Op2, Op3 }; 4074 return UpdateNodeOperands(N, Ops, 3); 4075} 4076 4077SDValue SelectionDAG:: 4078UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4079 SDValue Op3, SDValue Op4) { 4080 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 4081 return UpdateNodeOperands(N, Ops, 4); 4082} 4083 4084SDValue SelectionDAG:: 4085UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, 4086 SDValue Op3, SDValue Op4, SDValue Op5) { 4087 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 4088 return UpdateNodeOperands(N, Ops, 5); 4089} 4090 4091SDValue SelectionDAG:: 4092UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { 4093 SDNode *N = InN.getNode(); 4094 assert(N->getNumOperands() == NumOps && 4095 "Update with wrong number of operands"); 4096 4097 // Check to see if there is no change. 4098 bool AnyChange = false; 4099 for (unsigned i = 0; i != NumOps; ++i) { 4100 if (Ops[i] != N->getOperand(i)) { 4101 AnyChange = true; 4102 break; 4103 } 4104 } 4105 4106 // No operands changed, just return the input node. 4107 if (!AnyChange) return InN; 4108 4109 // See if the modified node already exists. 4110 void *InsertPos = 0; 4111 if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) 4112 return SDValue(Existing, InN.getResNo()); 4113 4114 // Nope it doesn't. Remove the node from its current place in the maps. 4115 if (InsertPos) 4116 if (!RemoveNodeFromCSEMaps(N)) 4117 InsertPos = 0; 4118 4119 // Now we update the operands. 4120 for (unsigned i = 0; i != NumOps; ++i) 4121 if (N->OperandList[i] != Ops[i]) 4122 N->OperandList[i].set(Ops[i]); 4123 4124 // If this gets put into a CSE map, add it. 4125 if (InsertPos) CSEMap.InsertNode(N, InsertPos); 4126 return InN; 4127} 4128 4129/// DropOperands - Release the operands and set this node to have 4130/// zero operands. 4131void SDNode::DropOperands() { 4132 // Unlike the code in MorphNodeTo that does this, we don't need to 4133 // watch for dead nodes here. 4134 for (op_iterator I = op_begin(), E = op_end(); I != E; ) { 4135 SDUse &Use = *I++; 4136 Use.set(SDValue()); 4137 } 4138} 4139 4140/// SelectNodeTo - These are wrappers around MorphNodeTo that accept a 4141/// machine opcode. 4142/// 4143SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4144 MVT VT) { 4145 SDVTList VTs = getVTList(VT); 4146 return SelectNodeTo(N, MachineOpc, VTs, 0, 0); 4147} 4148 4149SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4150 MVT VT, SDValue Op1) { 4151 SDVTList VTs = getVTList(VT); 4152 SDValue Ops[] = { Op1 }; 4153 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4154} 4155 4156SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4157 MVT VT, SDValue Op1, 4158 SDValue Op2) { 4159 SDVTList VTs = getVTList(VT); 4160 SDValue Ops[] = { Op1, Op2 }; 4161 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4162} 4163 4164SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4165 MVT VT, SDValue Op1, 4166 SDValue Op2, SDValue Op3) { 4167 SDVTList VTs = getVTList(VT); 4168 SDValue Ops[] = { Op1, Op2, Op3 }; 4169 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4170} 4171 4172SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4173 MVT VT, const SDValue *Ops, 4174 unsigned NumOps) { 4175 SDVTList VTs = getVTList(VT); 4176 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4177} 4178 4179SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4180 MVT VT1, MVT VT2, const SDValue *Ops, 4181 unsigned NumOps) { 4182 SDVTList VTs = getVTList(VT1, VT2); 4183 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4184} 4185 4186SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4187 MVT VT1, MVT VT2) { 4188 SDVTList VTs = getVTList(VT1, VT2); 4189 return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); 4190} 4191 4192SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4193 MVT VT1, MVT VT2, MVT VT3, 4194 const SDValue *Ops, unsigned NumOps) { 4195 SDVTList VTs = getVTList(VT1, VT2, VT3); 4196 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4197} 4198 4199SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4200 MVT VT1, MVT VT2, MVT VT3, MVT VT4, 4201 const SDValue *Ops, unsigned NumOps) { 4202 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); 4203 return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); 4204} 4205 4206SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4207 MVT VT1, MVT VT2, 4208 SDValue Op1) { 4209 SDVTList VTs = getVTList(VT1, VT2); 4210 SDValue Ops[] = { Op1 }; 4211 return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); 4212} 4213 4214SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4215 MVT VT1, MVT VT2, 4216 SDValue Op1, SDValue Op2) { 4217 SDVTList VTs = getVTList(VT1, VT2); 4218 SDValue Ops[] = { Op1, Op2 }; 4219 return SelectNodeTo(N, MachineOpc, VTs, Ops, 2); 4220} 4221 4222SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4223 MVT VT1, MVT VT2, 4224 SDValue Op1, SDValue Op2, 4225 SDValue Op3) { 4226 SDVTList VTs = getVTList(VT1, VT2); 4227 SDValue Ops[] = { Op1, Op2, Op3 }; 4228 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4229} 4230 4231SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4232 MVT VT1, MVT VT2, MVT VT3, 4233 SDValue Op1, SDValue Op2, 4234 SDValue Op3) { 4235 SDVTList VTs = getVTList(VT1, VT2, VT3); 4236 SDValue Ops[] = { Op1, Op2, Op3 }; 4237 return SelectNodeTo(N, MachineOpc, VTs, Ops, 3); 4238} 4239 4240SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, 4241 SDVTList VTs, const SDValue *Ops, 4242 unsigned NumOps) { 4243 return MorphNodeTo(N, ~MachineOpc, VTs, Ops, NumOps); 4244} 4245 4246SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4247 MVT VT) { 4248 SDVTList VTs = getVTList(VT); 4249 return MorphNodeTo(N, Opc, VTs, 0, 0); 4250} 4251 4252SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4253 MVT VT, SDValue Op1) { 4254 SDVTList VTs = getVTList(VT); 4255 SDValue Ops[] = { Op1 }; 4256 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4257} 4258 4259SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4260 MVT VT, SDValue Op1, 4261 SDValue Op2) { 4262 SDVTList VTs = getVTList(VT); 4263 SDValue Ops[] = { Op1, Op2 }; 4264 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4265} 4266 4267SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4268 MVT VT, SDValue Op1, 4269 SDValue Op2, SDValue Op3) { 4270 SDVTList VTs = getVTList(VT); 4271 SDValue Ops[] = { Op1, Op2, Op3 }; 4272 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4273} 4274 4275SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4276 MVT VT, const SDValue *Ops, 4277 unsigned NumOps) { 4278 SDVTList VTs = getVTList(VT); 4279 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4280} 4281 4282SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4283 MVT VT1, MVT VT2, const SDValue *Ops, 4284 unsigned NumOps) { 4285 SDVTList VTs = getVTList(VT1, VT2); 4286 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4287} 4288 4289SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4290 MVT VT1, MVT VT2) { 4291 SDVTList VTs = getVTList(VT1, VT2); 4292 return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); 4293} 4294 4295SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4296 MVT VT1, MVT VT2, MVT VT3, 4297 const SDValue *Ops, unsigned NumOps) { 4298 SDVTList VTs = getVTList(VT1, VT2, VT3); 4299 return MorphNodeTo(N, Opc, VTs, Ops, NumOps); 4300} 4301 4302SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4303 MVT VT1, MVT VT2, 4304 SDValue Op1) { 4305 SDVTList VTs = getVTList(VT1, VT2); 4306 SDValue Ops[] = { Op1 }; 4307 return MorphNodeTo(N, Opc, VTs, Ops, 1); 4308} 4309 4310SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4311 MVT VT1, MVT VT2, 4312 SDValue Op1, SDValue Op2) { 4313 SDVTList VTs = getVTList(VT1, VT2); 4314 SDValue Ops[] = { Op1, Op2 }; 4315 return MorphNodeTo(N, Opc, VTs, Ops, 2); 4316} 4317 4318SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4319 MVT VT1, MVT VT2, 4320 SDValue Op1, SDValue Op2, 4321 SDValue Op3) { 4322 SDVTList VTs = getVTList(VT1, VT2); 4323 SDValue Ops[] = { Op1, Op2, Op3 }; 4324 return MorphNodeTo(N, Opc, VTs, Ops, 3); 4325} 4326 4327/// MorphNodeTo - These *mutate* the specified node to have the specified 4328/// return type, opcode, and operands. 4329/// 4330/// Note that MorphNodeTo returns the resultant node. If there is already a 4331/// node of the specified opcode and operands, it returns that node instead of 4332/// the current one. Note that the DebugLoc need not be the same. 4333/// 4334/// Using MorphNodeTo is faster than creating a new node and swapping it in 4335/// with ReplaceAllUsesWith both because it often avoids allocating a new 4336/// node, and because it doesn't require CSE recalculation for any of 4337/// the node's users. 4338/// 4339SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, 4340 SDVTList VTs, const SDValue *Ops, 4341 unsigned NumOps) { 4342 // If an identical node already exists, use it. 4343 void *IP = 0; 4344 if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { 4345 FoldingSetNodeID ID; 4346 AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); 4347 if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) 4348 return ON; 4349 } 4350 4351 if (!RemoveNodeFromCSEMaps(N)) 4352 IP = 0; 4353 4354 // Start the morphing. 4355 N->NodeType = Opc; 4356 N->ValueList = VTs.VTs; 4357 N->NumValues = VTs.NumVTs; 4358 4359 // Clear the operands list, updating used nodes to remove this from their 4360 // use list. Keep track of any operands that become dead as a result. 4361 SmallPtrSet<SDNode*, 16> DeadNodeSet; 4362 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) { 4363 SDUse &Use = *I++; 4364 SDNode *Used = Use.getNode(); 4365 Use.set(SDValue()); 4366 if (Used->use_empty()) 4367 DeadNodeSet.insert(Used); 4368 } 4369 4370 // If NumOps is larger than the # of operands we currently have, reallocate 4371 // the operand list. 4372 if (NumOps > N->NumOperands) { 4373 if (N->OperandsNeedDelete) 4374 delete[] N->OperandList; 4375 4376 if (N->isMachineOpcode()) { 4377 // We're creating a final node that will live unmorphed for the 4378 // remainder of the current SelectionDAG iteration, so we can allocate 4379 // the operands directly out of a pool with no recycling metadata. 4380 N->OperandList = OperandAllocator.Allocate<SDUse>(NumOps); 4381 N->OperandsNeedDelete = false; 4382 } else { 4383 N->OperandList = new SDUse[NumOps]; 4384 N->OperandsNeedDelete = true; 4385 } 4386 } 4387 4388 // Assign the new operands. 4389 N->NumOperands = NumOps; 4390 for (unsigned i = 0, e = NumOps; i != e; ++i) { 4391 N->OperandList[i].setUser(N); 4392 N->OperandList[i].setInitial(Ops[i]); 4393 } 4394 4395 // Delete any nodes that are still dead after adding the uses for the 4396 // new operands. 4397 SmallVector<SDNode *, 16> DeadNodes; 4398 for (SmallPtrSet<SDNode *, 16>::iterator I = DeadNodeSet.begin(), 4399 E = DeadNodeSet.end(); I != E; ++I) 4400 if ((*I)->use_empty()) 4401 DeadNodes.push_back(*I); 4402 RemoveDeadNodes(DeadNodes); 4403 4404 if (IP) 4405 CSEMap.InsertNode(N, IP); // Memoize the new node. 4406 return N; 4407} 4408 4409 4410/// getTargetNode - These are used for target selectors to create a new node 4411/// with specified return type(s), target opcode, and operands. 4412/// 4413/// Note that getTargetNode returns the resultant node. If there is already a 4414/// node of the specified opcode and operands, it returns that node instead of 4415/// the current one. 4416SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) { 4417 return getNode(~Opcode, VT).getNode(); 4418} 4419SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { 4420 return getNode(~Opcode, dl, VT).getNode(); 4421} 4422 4423SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) { 4424 return getNode(~Opcode, VT, Op1).getNode(); 4425} 4426SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4427 SDValue Op1) { 4428 return getNode(~Opcode, dl, VT, Op1).getNode(); 4429} 4430 4431SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4432 SDValue Op1, SDValue Op2) { 4433 return getNode(~Opcode, VT, Op1, Op2).getNode(); 4434} 4435SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4436 SDValue Op1, SDValue Op2) { 4437 return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); 4438} 4439 4440SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, 4441 SDValue Op1, SDValue Op2, 4442 SDValue Op3) { 4443 return getNode(~Opcode, VT, Op1, Op2, Op3).getNode(); 4444} 4445SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4446 SDValue Op1, SDValue Op2, 4447 SDValue Op3) { 4448 return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); 4449} 4450 4451SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, 4452 const SDValue *Ops, unsigned NumOps) { 4453 return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); 4454} 4455 4456SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) { 4457 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4458 SDValue Op; 4459 return getNode(~Opcode, VTs, 2, &Op, 0).getNode(); 4460} 4461SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4462 MVT VT1, MVT VT2) { 4463 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4464 SDValue Op; 4465 return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode(); 4466} 4467 4468SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4469 MVT VT2, SDValue Op1) { 4470 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4471 return getNode(~Opcode, VTs, 2, &Op1, 1).getNode(); 4472} 4473SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4474 MVT VT2, SDValue Op1) { 4475 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4476 return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode(); 4477} 4478 4479SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4480 MVT VT2, SDValue Op1, 4481 SDValue Op2) { 4482 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4483 SDValue Ops[] = { Op1, Op2 }; 4484 return getNode(~Opcode, VTs, 2, Ops, 2).getNode(); 4485} 4486SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4487 MVT VT2, SDValue Op1, 4488 SDValue Op2) { 4489 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4490 SDValue Ops[] = { Op1, Op2 }; 4491 return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode(); 4492} 4493 4494SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, 4495 MVT VT2, SDValue Op1, 4496 SDValue Op2, SDValue Op3) { 4497 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4498 SDValue Ops[] = { Op1, Op2, Op3 }; 4499 return getNode(~Opcode, VTs, 2, Ops, 3).getNode(); 4500} 4501SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4502 MVT VT2, SDValue Op1, 4503 SDValue Op2, SDValue Op3) { 4504 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4505 SDValue Ops[] = { Op1, Op2, Op3 }; 4506 return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode(); 4507} 4508 4509SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4510 MVT VT1, MVT VT2, 4511 const SDValue *Ops, unsigned NumOps) { 4512 const MVT *VTs = getNodeValueTypes(VT1, VT2); 4513 return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode(); 4514} 4515 4516SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4517 MVT VT1, MVT VT2, MVT VT3, 4518 SDValue Op1, SDValue Op2) { 4519 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4520 SDValue Ops[] = { Op1, Op2 }; 4521 return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode(); 4522} 4523 4524SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4525 MVT VT1, MVT VT2, MVT VT3, 4526 SDValue Op1, SDValue Op2, 4527 SDValue Op3) { 4528 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4529 SDValue Ops[] = { Op1, Op2, Op3 }; 4530 return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode(); 4531} 4532 4533SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4534 MVT VT1, MVT VT2, MVT VT3, 4535 const SDValue *Ops, unsigned NumOps) { 4536 const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3); 4537 return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode(); 4538} 4539 4540SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, 4541 MVT VT2, MVT VT3, MVT VT4, 4542 const SDValue *Ops, unsigned NumOps) { 4543 std::vector<MVT> VTList; 4544 VTList.push_back(VT1); 4545 VTList.push_back(VT2); 4546 VTList.push_back(VT3); 4547 VTList.push_back(VT4); 4548 const MVT *VTs = getNodeValueTypes(VTList); 4549 return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode(); 4550} 4551 4552SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, 4553 const std::vector<MVT> &ResultTys, 4554 const SDValue *Ops, unsigned NumOps) { 4555 const MVT *VTs = getNodeValueTypes(ResultTys); 4556 return getNode(~Opcode, dl, VTs, ResultTys.size(), 4557 Ops, NumOps).getNode(); 4558} 4559 4560/// getNodeIfExists - Get the specified node if it's already available, or 4561/// else return NULL. 4562SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, 4563 const SDValue *Ops, unsigned NumOps) { 4564 if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { 4565 FoldingSetNodeID ID; 4566 AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); 4567 void *IP = 0; 4568 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) 4569 return E; 4570 } 4571 return NULL; 4572} 4573 4574/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4575/// This can cause recursive merging of nodes in the DAG. 4576/// 4577/// This version assumes From has a single result value. 4578/// 4579void SelectionDAG::ReplaceAllUsesWith(SDValue FromN, SDValue To, 4580 DAGUpdateListener *UpdateListener) { 4581 SDNode *From = FromN.getNode(); 4582 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && 4583 "Cannot replace with this method!"); 4584 assert(From != To.getNode() && "Cannot replace uses of with self"); 4585 4586 // Iterate over all the existing uses of From. New uses will be added 4587 // to the beginning of the use list, which we avoid visiting. 4588 // This specifically avoids visiting uses of From that arise while the 4589 // replacement is happening, because any such uses would be the result 4590 // of CSE: If an existing node looks like From after one of its operands 4591 // is replaced by To, we don't want to replace of all its users with To 4592 // too. See PR3018 for more info. 4593 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4594 while (UI != UE) { 4595 SDNode *User = *UI; 4596 4597 // This node is about to morph, remove its old self from the CSE maps. 4598 RemoveNodeFromCSEMaps(User); 4599 4600 // A user can appear in a use list multiple times, and when this 4601 // happens the uses are usually next to each other in the list. 4602 // To help reduce the number of CSE recomputations, process all 4603 // the uses of this user that we can find this way. 4604 do { 4605 SDUse &Use = UI.getUse(); 4606 ++UI; 4607 Use.set(To); 4608 } while (UI != UE && *UI == User); 4609 4610 // Now that we have modified User, add it back to the CSE maps. If it 4611 // already exists there, recursively merge the results together. 4612 AddModifiedNodeToCSEMaps(User, UpdateListener); 4613 } 4614} 4615 4616/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4617/// This can cause recursive merging of nodes in the DAG. 4618/// 4619/// This version assumes From/To have matching types and numbers of result 4620/// values. 4621/// 4622void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To, 4623 DAGUpdateListener *UpdateListener) { 4624 assert(From->getVTList().VTs == To->getVTList().VTs && 4625 From->getNumValues() == To->getNumValues() && 4626 "Cannot use this version of ReplaceAllUsesWith!"); 4627 4628 // Handle the trivial case. 4629 if (From == To) 4630 return; 4631 4632 // Iterate over just the existing users of From. See the comments in 4633 // the ReplaceAllUsesWith above. 4634 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4635 while (UI != UE) { 4636 SDNode *User = *UI; 4637 4638 // This node is about to morph, remove its old self from the CSE maps. 4639 RemoveNodeFromCSEMaps(User); 4640 4641 // A user can appear in a use list multiple times, and when this 4642 // happens the uses are usually next to each other in the list. 4643 // To help reduce the number of CSE recomputations, process all 4644 // the uses of this user that we can find this way. 4645 do { 4646 SDUse &Use = UI.getUse(); 4647 ++UI; 4648 Use.setNode(To); 4649 } while (UI != UE && *UI == User); 4650 4651 // Now that we have modified User, add it back to the CSE maps. If it 4652 // already exists there, recursively merge the results together. 4653 AddModifiedNodeToCSEMaps(User, UpdateListener); 4654 } 4655} 4656 4657/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 4658/// This can cause recursive merging of nodes in the DAG. 4659/// 4660/// This version can replace From with any result values. To must match the 4661/// number and types of values returned by From. 4662void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 4663 const SDValue *To, 4664 DAGUpdateListener *UpdateListener) { 4665 if (From->getNumValues() == 1) // Handle the simple case efficiently. 4666 return ReplaceAllUsesWith(SDValue(From, 0), To[0], UpdateListener); 4667 4668 // Iterate over just the existing users of From. See the comments in 4669 // the ReplaceAllUsesWith above. 4670 SDNode::use_iterator UI = From->use_begin(), UE = From->use_end(); 4671 while (UI != UE) { 4672 SDNode *User = *UI; 4673 4674 // This node is about to morph, remove its old self from the CSE maps. 4675 RemoveNodeFromCSEMaps(User); 4676 4677 // A user can appear in a use list multiple times, and when this 4678 // happens the uses are usually next to each other in the list. 4679 // To help reduce the number of CSE recomputations, process all 4680 // the uses of this user that we can find this way. 4681 do { 4682 SDUse &Use = UI.getUse(); 4683 const SDValue &ToOp = To[Use.getResNo()]; 4684 ++UI; 4685 Use.set(ToOp); 4686 } while (UI != UE && *UI == User); 4687 4688 // Now that we have modified User, add it back to the CSE maps. If it 4689 // already exists there, recursively merge the results together. 4690 AddModifiedNodeToCSEMaps(User, UpdateListener); 4691 } 4692} 4693 4694/// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving 4695/// uses of other values produced by From.getNode() alone. The Deleted 4696/// vector is handled the same way as for ReplaceAllUsesWith. 4697void SelectionDAG::ReplaceAllUsesOfValueWith(SDValue From, SDValue To, 4698 DAGUpdateListener *UpdateListener){ 4699 // Handle the really simple, really trivial case efficiently. 4700 if (From == To) return; 4701 4702 // Handle the simple, trivial, case efficiently. 4703 if (From.getNode()->getNumValues() == 1) { 4704 ReplaceAllUsesWith(From, To, UpdateListener); 4705 return; 4706 } 4707 4708 // Iterate over just the existing users of From. See the comments in 4709 // the ReplaceAllUsesWith above. 4710 SDNode::use_iterator UI = From.getNode()->use_begin(), 4711 UE = From.getNode()->use_end(); 4712 while (UI != UE) { 4713 SDNode *User = *UI; 4714 bool UserRemovedFromCSEMaps = false; 4715 4716 // A user can appear in a use list multiple times, and when this 4717 // happens the uses are usually next to each other in the list. 4718 // To help reduce the number of CSE recomputations, process all 4719 // the uses of this user that we can find this way. 4720 do { 4721 SDUse &Use = UI.getUse(); 4722 4723 // Skip uses of different values from the same node. 4724 if (Use.getResNo() != From.getResNo()) { 4725 ++UI; 4726 continue; 4727 } 4728 4729 // If this node hasn't been modified yet, it's still in the CSE maps, 4730 // so remove its old self from the CSE maps. 4731 if (!UserRemovedFromCSEMaps) { 4732 RemoveNodeFromCSEMaps(User); 4733 UserRemovedFromCSEMaps = true; 4734 } 4735 4736 ++UI; 4737 Use.set(To); 4738 } while (UI != UE && *UI == User); 4739 4740 // We are iterating over all uses of the From node, so if a use 4741 // doesn't use the specific value, no changes are made. 4742 if (!UserRemovedFromCSEMaps) 4743 continue; 4744 4745 // Now that we have modified User, add it back to the CSE maps. If it 4746 // already exists there, recursively merge the results together. 4747 AddModifiedNodeToCSEMaps(User, UpdateListener); 4748 } 4749} 4750 4751namespace { 4752 /// UseMemo - This class is used by SelectionDAG::ReplaceAllUsesOfValuesWith 4753 /// to record information about a use. 4754 struct UseMemo { 4755 SDNode *User; 4756 unsigned Index; 4757 SDUse *Use; 4758 }; 4759 4760 /// operator< - Sort Memos by User. 4761 bool operator<(const UseMemo &L, const UseMemo &R) { 4762 return (intptr_t)L.User < (intptr_t)R.User; 4763 } 4764} 4765 4766/// ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving 4767/// uses of other values produced by From.getNode() alone. The same value 4768/// may appear in both the From and To list. The Deleted vector is 4769/// handled the same way as for ReplaceAllUsesWith. 4770void SelectionDAG::ReplaceAllUsesOfValuesWith(const SDValue *From, 4771 const SDValue *To, 4772 unsigned Num, 4773 DAGUpdateListener *UpdateListener){ 4774 // Handle the simple, trivial case efficiently. 4775 if (Num == 1) 4776 return ReplaceAllUsesOfValueWith(*From, *To, UpdateListener); 4777 4778 // Read up all the uses and make records of them. This helps 4779 // processing new uses that are introduced during the 4780 // replacement process. 4781 SmallVector<UseMemo, 4> Uses; 4782 for (unsigned i = 0; i != Num; ++i) { 4783 unsigned FromResNo = From[i].getResNo(); 4784 SDNode *FromNode = From[i].getNode(); 4785 for (SDNode::use_iterator UI = FromNode->use_begin(), 4786 E = FromNode->use_end(); UI != E; ++UI) { 4787 SDUse &Use = UI.getUse(); 4788 if (Use.getResNo() == FromResNo) { 4789 UseMemo Memo = { *UI, i, &Use }; 4790 Uses.push_back(Memo); 4791 } 4792 } 4793 } 4794 4795 // Sort the uses, so that all the uses from a given User are together. 4796 std::sort(Uses.begin(), Uses.end()); 4797 4798 for (unsigned UseIndex = 0, UseIndexEnd = Uses.size(); 4799 UseIndex != UseIndexEnd; ) { 4800 // We know that this user uses some value of From. If it is the right 4801 // value, update it. 4802 SDNode *User = Uses[UseIndex].User; 4803 4804 // This node is about to morph, remove its old self from the CSE maps. 4805 RemoveNodeFromCSEMaps(User); 4806 4807 // The Uses array is sorted, so all the uses for a given User 4808 // are next to each other in the list. 4809 // To help reduce the number of CSE recomputations, process all 4810 // the uses of this user that we can find this way. 4811 do { 4812 unsigned i = Uses[UseIndex].Index; 4813 SDUse &Use = *Uses[UseIndex].Use; 4814 ++UseIndex; 4815 4816 Use.set(To[i]); 4817 } while (UseIndex != UseIndexEnd && Uses[UseIndex].User == User); 4818 4819 // Now that we have modified User, add it back to the CSE maps. If it 4820 // already exists there, recursively merge the results together. 4821 AddModifiedNodeToCSEMaps(User, UpdateListener); 4822 } 4823} 4824 4825/// AssignTopologicalOrder - Assign a unique node id for each node in the DAG 4826/// based on their topological order. It returns the maximum id and a vector 4827/// of the SDNodes* in assigned order by reference. 4828unsigned SelectionDAG::AssignTopologicalOrder() { 4829 4830 unsigned DAGSize = 0; 4831 4832 // SortedPos tracks the progress of the algorithm. Nodes before it are 4833 // sorted, nodes after it are unsorted. When the algorithm completes 4834 // it is at the end of the list. 4835 allnodes_iterator SortedPos = allnodes_begin(); 4836 4837 // Visit all the nodes. Move nodes with no operands to the front of 4838 // the list immediately. Annotate nodes that do have operands with their 4839 // operand count. Before we do this, the Node Id fields of the nodes 4840 // may contain arbitrary values. After, the Node Id fields for nodes 4841 // before SortedPos will contain the topological sort index, and the 4842 // Node Id fields for nodes At SortedPos and after will contain the 4843 // count of outstanding operands. 4844 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ) { 4845 SDNode *N = I++; 4846 unsigned Degree = N->getNumOperands(); 4847 if (Degree == 0) { 4848 // A node with no uses, add it to the result array immediately. 4849 N->setNodeId(DAGSize++); 4850 allnodes_iterator Q = N; 4851 if (Q != SortedPos) 4852 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q)); 4853 ++SortedPos; 4854 } else { 4855 // Temporarily use the Node Id as scratch space for the degree count. 4856 N->setNodeId(Degree); 4857 } 4858 } 4859 4860 // Visit all the nodes. As we iterate, moves nodes into sorted order, 4861 // such that by the time the end is reached all nodes will be sorted. 4862 for (allnodes_iterator I = allnodes_begin(),E = allnodes_end(); I != E; ++I) { 4863 SDNode *N = I; 4864 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4865 UI != UE; ++UI) { 4866 SDNode *P = *UI; 4867 unsigned Degree = P->getNodeId(); 4868 --Degree; 4869 if (Degree == 0) { 4870 // All of P's operands are sorted, so P may sorted now. 4871 P->setNodeId(DAGSize++); 4872 if (P != SortedPos) 4873 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(P)); 4874 ++SortedPos; 4875 } else { 4876 // Update P's outstanding operand count. 4877 P->setNodeId(Degree); 4878 } 4879 } 4880 } 4881 4882 assert(SortedPos == AllNodes.end() && 4883 "Topological sort incomplete!"); 4884 assert(AllNodes.front().getOpcode() == ISD::EntryToken && 4885 "First node in topological sort is not the entry token!"); 4886 assert(AllNodes.front().getNodeId() == 0 && 4887 "First node in topological sort has non-zero id!"); 4888 assert(AllNodes.front().getNumOperands() == 0 && 4889 "First node in topological sort has operands!"); 4890 assert(AllNodes.back().getNodeId() == (int)DAGSize-1 && 4891 "Last node in topologic sort has unexpected id!"); 4892 assert(AllNodes.back().use_empty() && 4893 "Last node in topologic sort has users!"); 4894 assert(DAGSize == allnodes_size() && "Node count mismatch!"); 4895 return DAGSize; 4896} 4897 4898 4899 4900//===----------------------------------------------------------------------===// 4901// SDNode Class 4902//===----------------------------------------------------------------------===// 4903 4904HandleSDNode::~HandleSDNode() { 4905 DropOperands(); 4906} 4907 4908GlobalAddressSDNode::GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, 4909 MVT VT, int64_t o) 4910 : SDNode(isa<GlobalVariable>(GA) && 4911 cast<GlobalVariable>(GA)->isThreadLocal() ? 4912 // Thread Local 4913 (isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) : 4914 // Non Thread Local 4915 (isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress), 4916 getSDVTList(VT)), Offset(o) { 4917 TheGlobal = const_cast<GlobalValue*>(GA); 4918} 4919 4920MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt, 4921 const Value *srcValue, int SVO, 4922 unsigned alignment, bool vol) 4923 : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4924 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4925 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4926 assert(getAlignment() == alignment && "Alignment representation error!"); 4927 assert(isVolatile() == vol && "Volatile representation error!"); 4928} 4929 4930MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, 4931 unsigned NumOps, MVT memvt, const Value *srcValue, 4932 int SVO, unsigned alignment, bool vol) 4933 : SDNode(Opc, VTs, Ops, NumOps), 4934 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4935 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4936 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4937 assert(getAlignment() == alignment && "Alignment representation error!"); 4938 assert(isVolatile() == vol && "Volatile representation error!"); 4939} 4940 4941MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, 4942 const Value *srcValue, int SVO, 4943 unsigned alignment, bool vol) 4944 : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4945 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4946 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4947 assert(getAlignment() == alignment && "Alignment representation error!"); 4948 assert(isVolatile() == vol && "Volatile representation error!"); 4949} 4950 4951MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, 4952 const SDValue *Ops, 4953 unsigned NumOps, MVT memvt, const Value *srcValue, 4954 int SVO, unsigned alignment, bool vol) 4955 : SDNode(Opc, dl, VTs, Ops, NumOps), 4956 MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { 4957 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment); 4958 assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!"); 4959 assert(getAlignment() == alignment && "Alignment representation error!"); 4960 assert(isVolatile() == vol && "Volatile representation error!"); 4961} 4962 4963/// getMemOperand - Return a MachineMemOperand object describing the memory 4964/// reference performed by this memory reference. 4965MachineMemOperand MemSDNode::getMemOperand() const { 4966 int Flags = 0; 4967 if (isa<LoadSDNode>(this)) 4968 Flags = MachineMemOperand::MOLoad; 4969 else if (isa<StoreSDNode>(this)) 4970 Flags = MachineMemOperand::MOStore; 4971 else if (isa<AtomicSDNode>(this)) { 4972 Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 4973 } 4974 else { 4975 const MemIntrinsicSDNode* MemIntrinNode = dyn_cast<MemIntrinsicSDNode>(this); 4976 assert(MemIntrinNode && "Unknown MemSDNode opcode!"); 4977 if (MemIntrinNode->readMem()) Flags |= MachineMemOperand::MOLoad; 4978 if (MemIntrinNode->writeMem()) Flags |= MachineMemOperand::MOStore; 4979 } 4980 4981 int Size = (getMemoryVT().getSizeInBits() + 7) >> 3; 4982 if (isVolatile()) Flags |= MachineMemOperand::MOVolatile; 4983 4984 // Check if the memory reference references a frame index 4985 const FrameIndexSDNode *FI = 4986 dyn_cast<const FrameIndexSDNode>(getBasePtr().getNode()); 4987 if (!getSrcValue() && FI) 4988 return MachineMemOperand(PseudoSourceValue::getFixedStack(FI->getIndex()), 4989 Flags, 0, Size, getAlignment()); 4990 else 4991 return MachineMemOperand(getSrcValue(), Flags, getSrcValueOffset(), 4992 Size, getAlignment()); 4993} 4994 4995/// Profile - Gather unique data for the node. 4996/// 4997void SDNode::Profile(FoldingSetNodeID &ID) const { 4998 AddNodeIDNode(ID, this); 4999} 5000 5001/// getValueTypeList - Return a pointer to the specified value type. 5002/// 5003const MVT *SDNode::getValueTypeList(MVT VT) { 5004 if (VT.isExtended()) { 5005 static std::set<MVT, MVT::compareRawBits> EVTs; 5006 return &(*EVTs.insert(VT).first); 5007 } else { 5008 static MVT VTs[MVT::LAST_VALUETYPE]; 5009 VTs[VT.getSimpleVT()] = VT; 5010 return &VTs[VT.getSimpleVT()]; 5011 } 5012} 5013 5014/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 5015/// indicated value. This method ignores uses of other values defined by this 5016/// operation. 5017bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) const { 5018 assert(Value < getNumValues() && "Bad value!"); 5019 5020 // TODO: Only iterate over uses of a given value of the node 5021 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { 5022 if (UI.getUse().getResNo() == Value) { 5023 if (NUses == 0) 5024 return false; 5025 --NUses; 5026 } 5027 } 5028 5029 // Found exactly the right number of uses? 5030 return NUses == 0; 5031} 5032 5033 5034/// hasAnyUseOfValue - Return true if there are any use of the indicated 5035/// value. This method ignores uses of other values defined by this operation. 5036bool SDNode::hasAnyUseOfValue(unsigned Value) const { 5037 assert(Value < getNumValues() && "Bad value!"); 5038 5039 for (SDNode::use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) 5040 if (UI.getUse().getResNo() == Value) 5041 return true; 5042 5043 return false; 5044} 5045 5046 5047/// isOnlyUserOf - Return true if this node is the only use of N. 5048/// 5049bool SDNode::isOnlyUserOf(SDNode *N) const { 5050 bool Seen = false; 5051 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 5052 SDNode *User = *I; 5053 if (User == this) 5054 Seen = true; 5055 else 5056 return false; 5057 } 5058 5059 return Seen; 5060} 5061 5062/// isOperand - Return true if this node is an operand of N. 5063/// 5064bool SDValue::isOperandOf(SDNode *N) const { 5065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5066 if (*this == N->getOperand(i)) 5067 return true; 5068 return false; 5069} 5070 5071bool SDNode::isOperandOf(SDNode *N) const { 5072 for (unsigned i = 0, e = N->NumOperands; i != e; ++i) 5073 if (this == N->OperandList[i].getNode()) 5074 return true; 5075 return false; 5076} 5077 5078/// reachesChainWithoutSideEffects - Return true if this operand (which must 5079/// be a chain) reaches the specified operand without crossing any 5080/// side-effecting instructions. In practice, this looks through token 5081/// factors and non-volatile loads. In order to remain efficient, this only 5082/// looks a couple of nodes in, it does not do an exhaustive search. 5083bool SDValue::reachesChainWithoutSideEffects(SDValue Dest, 5084 unsigned Depth) const { 5085 if (*this == Dest) return true; 5086 5087 // Don't search too deeply, we just want to be able to see through 5088 // TokenFactor's etc. 5089 if (Depth == 0) return false; 5090 5091 // If this is a token factor, all inputs to the TF happen in parallel. If any 5092 // of the operands of the TF reach dest, then we can do the xform. 5093 if (getOpcode() == ISD::TokenFactor) { 5094 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5095 if (getOperand(i).reachesChainWithoutSideEffects(Dest, Depth-1)) 5096 return true; 5097 return false; 5098 } 5099 5100 // Loads don't have side effects, look through them. 5101 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(*this)) { 5102 if (!Ld->isVolatile()) 5103 return Ld->getChain().reachesChainWithoutSideEffects(Dest, Depth-1); 5104 } 5105 return false; 5106} 5107 5108 5109static void findPredecessor(SDNode *N, const SDNode *P, bool &found, 5110 SmallPtrSet<SDNode *, 32> &Visited) { 5111 if (found || !Visited.insert(N)) 5112 return; 5113 5114 for (unsigned i = 0, e = N->getNumOperands(); !found && i != e; ++i) { 5115 SDNode *Op = N->getOperand(i).getNode(); 5116 if (Op == P) { 5117 found = true; 5118 return; 5119 } 5120 findPredecessor(Op, P, found, Visited); 5121 } 5122} 5123 5124/// isPredecessorOf - Return true if this node is a predecessor of N. This node 5125/// is either an operand of N or it can be reached by recursively traversing 5126/// up the operands. 5127/// NOTE: this is an expensive method. Use it carefully. 5128bool SDNode::isPredecessorOf(SDNode *N) const { 5129 SmallPtrSet<SDNode *, 32> Visited; 5130 bool found = false; 5131 findPredecessor(N, this, found, Visited); 5132 return found; 5133} 5134 5135uint64_t SDNode::getConstantOperandVal(unsigned Num) const { 5136 assert(Num < NumOperands && "Invalid child # of SDNode!"); 5137 return cast<ConstantSDNode>(OperandList[Num])->getZExtValue(); 5138} 5139 5140std::string SDNode::getOperationName(const SelectionDAG *G) const { 5141 switch (getOpcode()) { 5142 default: 5143 if (getOpcode() < ISD::BUILTIN_OP_END) 5144 return "<<Unknown DAG Node>>"; 5145 if (isMachineOpcode()) { 5146 if (G) 5147 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 5148 if (getMachineOpcode() < TII->getNumOpcodes()) 5149 return TII->get(getMachineOpcode()).getName(); 5150 return "<<Unknown Machine Node>>"; 5151 } 5152 if (G) { 5153 const TargetLowering &TLI = G->getTargetLoweringInfo(); 5154 const char *Name = TLI.getTargetNodeName(getOpcode()); 5155 if (Name) return Name; 5156 return "<<Unknown Target Node>>"; 5157 } 5158 return "<<Unknown Node>>"; 5159 5160#ifndef NDEBUG 5161 case ISD::DELETED_NODE: 5162 return "<<Deleted Node!>>"; 5163#endif 5164 case ISD::PREFETCH: return "Prefetch"; 5165 case ISD::MEMBARRIER: return "MemBarrier"; 5166 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 5167 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 5168 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 5169 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 5170 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; 5171 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"; 5172 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor"; 5173 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; 5174 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin"; 5175 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax"; 5176 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin"; 5177 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax"; 5178 case ISD::PCMARKER: return "PCMarker"; 5179 case ISD::READCYCLECOUNTER: return "ReadCycleCounter"; 5180 case ISD::SRCVALUE: return "SrcValue"; 5181 case ISD::MEMOPERAND: return "MemOperand"; 5182 case ISD::EntryToken: return "EntryToken"; 5183 case ISD::TokenFactor: return "TokenFactor"; 5184 case ISD::AssertSext: return "AssertSext"; 5185 case ISD::AssertZext: return "AssertZext"; 5186 5187 case ISD::BasicBlock: return "BasicBlock"; 5188 case ISD::ARG_FLAGS: return "ArgFlags"; 5189 case ISD::VALUETYPE: return "ValueType"; 5190 case ISD::Register: return "Register"; 5191 5192 case ISD::Constant: return "Constant"; 5193 case ISD::ConstantFP: return "ConstantFP"; 5194 case ISD::GlobalAddress: return "GlobalAddress"; 5195 case ISD::GlobalTLSAddress: return "GlobalTLSAddress"; 5196 case ISD::FrameIndex: return "FrameIndex"; 5197 case ISD::JumpTable: return "JumpTable"; 5198 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE"; 5199 case ISD::RETURNADDR: return "RETURNADDR"; 5200 case ISD::FRAMEADDR: return "FRAMEADDR"; 5201 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET"; 5202 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR"; 5203 case ISD::EHSELECTION: return "EHSELECTION"; 5204 case ISD::EH_RETURN: return "EH_RETURN"; 5205 case ISD::ConstantPool: return "ConstantPool"; 5206 case ISD::ExternalSymbol: return "ExternalSymbol"; 5207 case ISD::INTRINSIC_WO_CHAIN: { 5208 unsigned IID = cast<ConstantSDNode>(getOperand(0))->getZExtValue(); 5209 return Intrinsic::getName((Intrinsic::ID)IID); 5210 } 5211 case ISD::INTRINSIC_VOID: 5212 case ISD::INTRINSIC_W_CHAIN: { 5213 unsigned IID = cast<ConstantSDNode>(getOperand(1))->getZExtValue(); 5214 return Intrinsic::getName((Intrinsic::ID)IID); 5215 } 5216 5217 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; 5218 case ISD::TargetConstant: return "TargetConstant"; 5219 case ISD::TargetConstantFP:return "TargetConstantFP"; 5220 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 5221 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress"; 5222 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 5223 case ISD::TargetJumpTable: return "TargetJumpTable"; 5224 case ISD::TargetConstantPool: return "TargetConstantPool"; 5225 case ISD::TargetExternalSymbol: return "TargetExternalSymbol"; 5226 5227 case ISD::CopyToReg: return "CopyToReg"; 5228 case ISD::CopyFromReg: return "CopyFromReg"; 5229 case ISD::UNDEF: return "undef"; 5230 case ISD::MERGE_VALUES: return "merge_values"; 5231 case ISD::INLINEASM: return "inlineasm"; 5232 case ISD::DBG_LABEL: return "dbg_label"; 5233 case ISD::EH_LABEL: return "eh_label"; 5234 case ISD::DECLARE: return "declare"; 5235 case ISD::HANDLENODE: return "handlenode"; 5236 case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; 5237 case ISD::CALL: return "call"; 5238 5239 // Unary operators 5240 case ISD::FABS: return "fabs"; 5241 case ISD::FNEG: return "fneg"; 5242 case ISD::FSQRT: return "fsqrt"; 5243 case ISD::FSIN: return "fsin"; 5244 case ISD::FCOS: return "fcos"; 5245 case ISD::FPOWI: return "fpowi"; 5246 case ISD::FPOW: return "fpow"; 5247 case ISD::FTRUNC: return "ftrunc"; 5248 case ISD::FFLOOR: return "ffloor"; 5249 case ISD::FCEIL: return "fceil"; 5250 case ISD::FRINT: return "frint"; 5251 case ISD::FNEARBYINT: return "fnearbyint"; 5252 5253 // Binary operators 5254 case ISD::ADD: return "add"; 5255 case ISD::SUB: return "sub"; 5256 case ISD::MUL: return "mul"; 5257 case ISD::MULHU: return "mulhu"; 5258 case ISD::MULHS: return "mulhs"; 5259 case ISD::SDIV: return "sdiv"; 5260 case ISD::UDIV: return "udiv"; 5261 case ISD::SREM: return "srem"; 5262 case ISD::UREM: return "urem"; 5263 case ISD::SMUL_LOHI: return "smul_lohi"; 5264 case ISD::UMUL_LOHI: return "umul_lohi"; 5265 case ISD::SDIVREM: return "sdivrem"; 5266 case ISD::UDIVREM: return "udivrem"; 5267 case ISD::AND: return "and"; 5268 case ISD::OR: return "or"; 5269 case ISD::XOR: return "xor"; 5270 case ISD::SHL: return "shl"; 5271 case ISD::SRA: return "sra"; 5272 case ISD::SRL: return "srl"; 5273 case ISD::ROTL: return "rotl"; 5274 case ISD::ROTR: return "rotr"; 5275 case ISD::FADD: return "fadd"; 5276 case ISD::FSUB: return "fsub"; 5277 case ISD::FMUL: return "fmul"; 5278 case ISD::FDIV: return "fdiv"; 5279 case ISD::FREM: return "frem"; 5280 case ISD::FCOPYSIGN: return "fcopysign"; 5281 case ISD::FGETSIGN: return "fgetsign"; 5282 5283 case ISD::SETCC: return "setcc"; 5284 case ISD::VSETCC: return "vsetcc"; 5285 case ISD::SELECT: return "select"; 5286 case ISD::SELECT_CC: return "select_cc"; 5287 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; 5288 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; 5289 case ISD::CONCAT_VECTORS: return "concat_vectors"; 5290 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; 5291 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; 5292 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; 5293 case ISD::CARRY_FALSE: return "carry_false"; 5294 case ISD::ADDC: return "addc"; 5295 case ISD::ADDE: return "adde"; 5296 case ISD::SADDO: return "saddo"; 5297 case ISD::UADDO: return "uaddo"; 5298 case ISD::SSUBO: return "ssubo"; 5299 case ISD::USUBO: return "usubo"; 5300 case ISD::SMULO: return "smulo"; 5301 case ISD::UMULO: return "umulo"; 5302 case ISD::SUBC: return "subc"; 5303 case ISD::SUBE: return "sube"; 5304 case ISD::SHL_PARTS: return "shl_parts"; 5305 case ISD::SRA_PARTS: return "sra_parts"; 5306 case ISD::SRL_PARTS: return "srl_parts"; 5307 5308 case ISD::EXTRACT_SUBREG: return "extract_subreg"; 5309 case ISD::INSERT_SUBREG: return "insert_subreg"; 5310 5311 // Conversion operators. 5312 case ISD::SIGN_EXTEND: return "sign_extend"; 5313 case ISD::ZERO_EXTEND: return "zero_extend"; 5314 case ISD::ANY_EXTEND: return "any_extend"; 5315 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 5316 case ISD::TRUNCATE: return "truncate"; 5317 case ISD::FP_ROUND: return "fp_round"; 5318 case ISD::FLT_ROUNDS_: return "flt_rounds"; 5319 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 5320 case ISD::FP_EXTEND: return "fp_extend"; 5321 5322 case ISD::SINT_TO_FP: return "sint_to_fp"; 5323 case ISD::UINT_TO_FP: return "uint_to_fp"; 5324 case ISD::FP_TO_SINT: return "fp_to_sint"; 5325 case ISD::FP_TO_UINT: return "fp_to_uint"; 5326 case ISD::BIT_CONVERT: return "bit_convert"; 5327 5328 case ISD::CONVERT_RNDSAT: { 5329 switch (cast<CvtRndSatSDNode>(this)->getCvtCode()) { 5330 default: assert(0 && "Unknown cvt code!"); 5331 case ISD::CVT_FF: return "cvt_ff"; 5332 case ISD::CVT_FS: return "cvt_fs"; 5333 case ISD::CVT_FU: return "cvt_fu"; 5334 case ISD::CVT_SF: return "cvt_sf"; 5335 case ISD::CVT_UF: return "cvt_uf"; 5336 case ISD::CVT_SS: return "cvt_ss"; 5337 case ISD::CVT_SU: return "cvt_su"; 5338 case ISD::CVT_US: return "cvt_us"; 5339 case ISD::CVT_UU: return "cvt_uu"; 5340 } 5341 } 5342 5343 // Control flow instructions 5344 case ISD::BR: return "br"; 5345 case ISD::BRIND: return "brind"; 5346 case ISD::BR_JT: return "br_jt"; 5347 case ISD::BRCOND: return "brcond"; 5348 case ISD::BR_CC: return "br_cc"; 5349 case ISD::RET: return "ret"; 5350 case ISD::CALLSEQ_START: return "callseq_start"; 5351 case ISD::CALLSEQ_END: return "callseq_end"; 5352 5353 // Other operators 5354 case ISD::LOAD: return "load"; 5355 case ISD::STORE: return "store"; 5356 case ISD::VAARG: return "vaarg"; 5357 case ISD::VACOPY: return "vacopy"; 5358 case ISD::VAEND: return "vaend"; 5359 case ISD::VASTART: return "vastart"; 5360 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 5361 case ISD::EXTRACT_ELEMENT: return "extract_element"; 5362 case ISD::BUILD_PAIR: return "build_pair"; 5363 case ISD::STACKSAVE: return "stacksave"; 5364 case ISD::STACKRESTORE: return "stackrestore"; 5365 case ISD::TRAP: return "trap"; 5366 5367 // Bit manipulation 5368 case ISD::BSWAP: return "bswap"; 5369 case ISD::CTPOP: return "ctpop"; 5370 case ISD::CTTZ: return "cttz"; 5371 case ISD::CTLZ: return "ctlz"; 5372 5373 // Debug info 5374 case ISD::DBG_STOPPOINT: return "dbg_stoppoint"; 5375 case ISD::DEBUG_LOC: return "debug_loc"; 5376 5377 // Trampolines 5378 case ISD::TRAMPOLINE: return "trampoline"; 5379 5380 case ISD::CONDCODE: 5381 switch (cast<CondCodeSDNode>(this)->get()) { 5382 default: assert(0 && "Unknown setcc condition!"); 5383 case ISD::SETOEQ: return "setoeq"; 5384 case ISD::SETOGT: return "setogt"; 5385 case ISD::SETOGE: return "setoge"; 5386 case ISD::SETOLT: return "setolt"; 5387 case ISD::SETOLE: return "setole"; 5388 case ISD::SETONE: return "setone"; 5389 5390 case ISD::SETO: return "seto"; 5391 case ISD::SETUO: return "setuo"; 5392 case ISD::SETUEQ: return "setue"; 5393 case ISD::SETUGT: return "setugt"; 5394 case ISD::SETUGE: return "setuge"; 5395 case ISD::SETULT: return "setult"; 5396 case ISD::SETULE: return "setule"; 5397 case ISD::SETUNE: return "setune"; 5398 5399 case ISD::SETEQ: return "seteq"; 5400 case ISD::SETGT: return "setgt"; 5401 case ISD::SETGE: return "setge"; 5402 case ISD::SETLT: return "setlt"; 5403 case ISD::SETLE: return "setle"; 5404 case ISD::SETNE: return "setne"; 5405 } 5406 } 5407} 5408 5409const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { 5410 switch (AM) { 5411 default: 5412 return ""; 5413 case ISD::PRE_INC: 5414 return "<pre-inc>"; 5415 case ISD::PRE_DEC: 5416 return "<pre-dec>"; 5417 case ISD::POST_INC: 5418 return "<post-inc>"; 5419 case ISD::POST_DEC: 5420 return "<post-dec>"; 5421 } 5422} 5423 5424std::string ISD::ArgFlagsTy::getArgFlagsString() { 5425 std::string S = "< "; 5426 5427 if (isZExt()) 5428 S += "zext "; 5429 if (isSExt()) 5430 S += "sext "; 5431 if (isInReg()) 5432 S += "inreg "; 5433 if (isSRet()) 5434 S += "sret "; 5435 if (isByVal()) 5436 S += "byval "; 5437 if (isNest()) 5438 S += "nest "; 5439 if (getByValAlign()) 5440 S += "byval-align:" + utostr(getByValAlign()) + " "; 5441 if (getOrigAlign()) 5442 S += "orig-align:" + utostr(getOrigAlign()) + " "; 5443 if (getByValSize()) 5444 S += "byval-size:" + utostr(getByValSize()) + " "; 5445 return S + ">"; 5446} 5447 5448void SDNode::dump() const { dump(0); } 5449void SDNode::dump(const SelectionDAG *G) const { 5450 print(errs(), G); 5451 errs().flush(); 5452} 5453 5454void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { 5455 OS << (void*)this << ": "; 5456 5457 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 5458 if (i) OS << ","; 5459 if (getValueType(i) == MVT::Other) 5460 OS << "ch"; 5461 else 5462 OS << getValueType(i).getMVTString(); 5463 } 5464 OS << " = " << getOperationName(G); 5465} 5466 5467void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { 5468 if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) { 5469 SDNode *Mask = getOperand(2).getNode(); 5470 OS << "<"; 5471 for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) { 5472 if (i) OS << ","; 5473 if (Mask->getOperand(i).getOpcode() == ISD::UNDEF) 5474 OS << "u"; 5475 else 5476 OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue(); 5477 } 5478 OS << ">"; 5479 } 5480 5481 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 5482 OS << '<' << CSDN->getAPIntValue() << '>'; 5483 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 5484 if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle) 5485 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>'; 5486 else if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEdouble) 5487 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>'; 5488 else { 5489 OS << "<APFloat("; 5490 CSDN->getValueAPF().bitcastToAPInt().dump(); 5491 OS << ")>"; 5492 } 5493 } else if (const GlobalAddressSDNode *GADN = 5494 dyn_cast<GlobalAddressSDNode>(this)) { 5495 int64_t offset = GADN->getOffset(); 5496 OS << '<'; 5497 WriteAsOperand(OS, GADN->getGlobal()); 5498 OS << '>'; 5499 if (offset > 0) 5500 OS << " + " << offset; 5501 else 5502 OS << " " << offset; 5503 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 5504 OS << "<" << FIDN->getIndex() << ">"; 5505 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) { 5506 OS << "<" << JTDN->getIndex() << ">"; 5507 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 5508 int offset = CP->getOffset(); 5509 if (CP->isMachineConstantPoolEntry()) 5510 OS << "<" << *CP->getMachineCPVal() << ">"; 5511 else 5512 OS << "<" << *CP->getConstVal() << ">"; 5513 if (offset > 0) 5514 OS << " + " << offset; 5515 else 5516 OS << " " << offset; 5517 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 5518 OS << "<"; 5519 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 5520 if (LBB) 5521 OS << LBB->getName() << " "; 5522 OS << (const void*)BBDN->getBasicBlock() << ">"; 5523 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 5524 if (G && R->getReg() && 5525 TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 5526 OS << " " << G->getTarget().getRegisterInfo()->getName(R->getReg()); 5527 } else { 5528 OS << " #" << R->getReg(); 5529 } 5530 } else if (const ExternalSymbolSDNode *ES = 5531 dyn_cast<ExternalSymbolSDNode>(this)) { 5532 OS << "'" << ES->getSymbol() << "'"; 5533 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 5534 if (M->getValue()) 5535 OS << "<" << M->getValue() << ">"; 5536 else 5537 OS << "<null>"; 5538 } else if (const MemOperandSDNode *M = dyn_cast<MemOperandSDNode>(this)) { 5539 if (M->MO.getValue()) 5540 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">"; 5541 else 5542 OS << "<null:" << M->MO.getOffset() << ">"; 5543 } else if (const ARG_FLAGSSDNode *N = dyn_cast<ARG_FLAGSSDNode>(this)) { 5544 OS << N->getArgFlags().getArgFlagsString(); 5545 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 5546 OS << ":" << N->getVT().getMVTString(); 5547 } 5548 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { 5549 const Value *SrcValue = LD->getSrcValue(); 5550 int SrcOffset = LD->getSrcValueOffset(); 5551 OS << " <"; 5552 if (SrcValue) 5553 OS << SrcValue; 5554 else 5555 OS << "null"; 5556 OS << ":" << SrcOffset << ">"; 5557 5558 bool doExt = true; 5559 switch (LD->getExtensionType()) { 5560 default: doExt = false; break; 5561 case ISD::EXTLOAD: OS << " <anyext "; break; 5562 case ISD::SEXTLOAD: OS << " <sext "; break; 5563 case ISD::ZEXTLOAD: OS << " <zext "; break; 5564 } 5565 if (doExt) 5566 OS << LD->getMemoryVT().getMVTString() << ">"; 5567 5568 const char *AM = getIndexedModeName(LD->getAddressingMode()); 5569 if (*AM) 5570 OS << " " << AM; 5571 if (LD->isVolatile()) 5572 OS << " <volatile>"; 5573 OS << " alignment=" << LD->getAlignment(); 5574 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) { 5575 const Value *SrcValue = ST->getSrcValue(); 5576 int SrcOffset = ST->getSrcValueOffset(); 5577 OS << " <"; 5578 if (SrcValue) 5579 OS << SrcValue; 5580 else 5581 OS << "null"; 5582 OS << ":" << SrcOffset << ">"; 5583 5584 if (ST->isTruncatingStore()) 5585 OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; 5586 5587 const char *AM = getIndexedModeName(ST->getAddressingMode()); 5588 if (*AM) 5589 OS << " " << AM; 5590 if (ST->isVolatile()) 5591 OS << " <volatile>"; 5592 OS << " alignment=" << ST->getAlignment(); 5593 } else if (const AtomicSDNode* AT = dyn_cast<AtomicSDNode>(this)) { 5594 const Value *SrcValue = AT->getSrcValue(); 5595 int SrcOffset = AT->getSrcValueOffset(); 5596 OS << " <"; 5597 if (SrcValue) 5598 OS << SrcValue; 5599 else 5600 OS << "null"; 5601 OS << ":" << SrcOffset << ">"; 5602 if (AT->isVolatile()) 5603 OS << " <volatile>"; 5604 OS << " alignment=" << AT->getAlignment(); 5605 } 5606} 5607 5608void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const { 5609 print_types(OS, G); 5610 OS << " "; 5611 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 5612 if (i) OS << ", "; 5613 OS << (void*)getOperand(i).getNode(); 5614 if (unsigned RN = getOperand(i).getResNo()) 5615 OS << ":" << RN; 5616 } 5617 print_details(OS, G); 5618} 5619 5620static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) { 5621 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 5622 if (N->getOperand(i).getNode()->hasOneUse()) 5623 DumpNodes(N->getOperand(i).getNode(), indent+2, G); 5624 else 5625 cerr << "\n" << std::string(indent+2, ' ') 5626 << (void*)N->getOperand(i).getNode() << ": <multiple use>"; 5627 5628 5629 cerr << "\n" << std::string(indent, ' '); 5630 N->dump(G); 5631} 5632 5633void SelectionDAG::dump() const { 5634 cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 5635 5636 for (allnodes_const_iterator I = allnodes_begin(), E = allnodes_end(); 5637 I != E; ++I) { 5638 const SDNode *N = I; 5639 if (!N->hasOneUse() && N != getRoot().getNode()) 5640 DumpNodes(N, 2, this); 5641 } 5642 5643 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this); 5644 5645 cerr << "\n\n"; 5646} 5647 5648void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const { 5649 print_types(OS, G); 5650 print_details(OS, G); 5651} 5652 5653typedef SmallPtrSet<const SDNode *, 128> VisitedSDNodeSet; 5654static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, 5655 const SelectionDAG *G, VisitedSDNodeSet &once) { 5656 if (!once.insert(N)) // If we've been here before, return now. 5657 return; 5658 // Dump the current SDNode, but don't end the line yet. 5659 OS << std::string(indent, ' '); 5660 N->printr(OS, G); 5661 // Having printed this SDNode, walk the children: 5662 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5663 const SDNode *child = N->getOperand(i).getNode(); 5664 if (i) OS << ","; 5665 OS << " "; 5666 if (child->getNumOperands() == 0) { 5667 // This child has no grandchildren; print it inline right here. 5668 child->printr(OS, G); 5669 once.insert(child); 5670 } else { // Just the address. FIXME: also print the child's opcode 5671 OS << (void*)child; 5672 if (unsigned RN = N->getOperand(i).getResNo()) 5673 OS << ":" << RN; 5674 } 5675 } 5676 OS << "\n"; 5677 // Dump children that have grandchildren on their own line(s). 5678 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5679 const SDNode *child = N->getOperand(i).getNode(); 5680 DumpNodesr(OS, child, indent+2, G, once); 5681 } 5682} 5683 5684void SDNode::dumpr() const { 5685 VisitedSDNodeSet once; 5686 DumpNodesr(errs(), this, 0, 0, once); 5687 errs().flush(); 5688} 5689 5690const Type *ConstantPoolSDNode::getType() const { 5691 if (isMachineConstantPoolEntry()) 5692 return Val.MachineCPVal->getType(); 5693 return Val.ConstVal->getType(); 5694} 5695