VirtRegMap.cpp revision 4daa9071ed1afde7fb03c7e0198101f4806b7d11
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the VirtRegMap class. 11// 12// It also contains implementations of the the Spiller interface, which, given a 13// virtual register map and a machine function, eliminates all virtual 14// references by replacing them with physical register references - adding spill 15// code as necessary. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "spiller" 20#include "VirtRegMap.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Target/TargetInstrInfo.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/ADT/BitVector.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include "llvm/ADT/SmallSet.h" 36#include <algorithm> 37using namespace llvm; 38 39STATISTIC(NumSpills , "Number of register spills"); 40STATISTIC(NumPSpills , "Number of physical register spills"); 41STATISTIC(NumReMats , "Number of re-materialization"); 42STATISTIC(NumDRM , "Number of re-materializable defs elided"); 43STATISTIC(NumStores , "Number of stores added"); 44STATISTIC(NumLoads , "Number of loads added"); 45STATISTIC(NumReused , "Number of values reused"); 46STATISTIC(NumDSE , "Number of dead stores elided"); 47STATISTIC(NumDCE , "Number of copies elided"); 48STATISTIC(NumDSS , "Number of dead spill slots removed"); 49STATISTIC(NumCommutes, "Number of instructions commuted"); 50 51namespace { 52 enum SpillerName { simple, local }; 53} 54 55static cl::opt<SpillerName> 56SpillerOpt("spiller", 57 cl::desc("Spiller to use: (default: local)"), 58 cl::Prefix, 59 cl::values(clEnumVal(simple, " simple spiller"), 60 clEnumVal(local, " local spiller"), 61 clEnumValEnd), 62 cl::init(local)); 63 64//===----------------------------------------------------------------------===// 65// VirtRegMap implementation 66//===----------------------------------------------------------------------===// 67 68VirtRegMap::VirtRegMap(MachineFunction &mf) 69 : TII(*mf.getTarget().getInstrInfo()), MF(mf), 70 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), 71 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), 72 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1), 73 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { 74 SpillSlotToUsesMap.resize(8); 75 ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1- 76 TargetRegisterInfo::FirstVirtualRegister); 77 grow(); 78} 79 80void VirtRegMap::grow() { 81 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); 82 Virt2PhysMap.grow(LastVirtReg); 83 Virt2StackSlotMap.grow(LastVirtReg); 84 Virt2ReMatIdMap.grow(LastVirtReg); 85 Virt2SplitMap.grow(LastVirtReg); 86 Virt2SplitKillMap.grow(LastVirtReg); 87 ReMatMap.grow(LastVirtReg); 88 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1); 89} 90 91int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 92 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 93 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 94 "attempt to assign stack slot to already spilled register"); 95 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); 96 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 97 RC->getAlignment()); 98 if (LowSpillSlot == NO_STACK_SLOT) 99 LowSpillSlot = SS; 100 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 101 HighSpillSlot = SS; 102 unsigned Idx = SS-LowSpillSlot; 103 while (Idx >= SpillSlotToUsesMap.size()) 104 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2); 105 Virt2StackSlotMap[virtReg] = SS; 106 ++NumSpills; 107 return SS; 108} 109 110void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { 111 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 112 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 113 "attempt to assign stack slot to already spilled register"); 114 assert((SS >= 0 || 115 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) && 116 "illegal fixed frame index"); 117 Virt2StackSlotMap[virtReg] = SS; 118} 119 120int VirtRegMap::assignVirtReMatId(unsigned virtReg) { 121 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 122 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 123 "attempt to assign re-mat id to already spilled register"); 124 Virt2ReMatIdMap[virtReg] = ReMatId; 125 return ReMatId++; 126} 127 128void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { 129 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 130 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 131 "attempt to assign re-mat id to already spilled register"); 132 Virt2ReMatIdMap[virtReg] = id; 133} 134 135int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { 136 std::map<const TargetRegisterClass*, int>::iterator I = 137 EmergencySpillSlots.find(RC); 138 if (I != EmergencySpillSlots.end()) 139 return I->second; 140 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 141 RC->getAlignment()); 142 if (LowSpillSlot == NO_STACK_SLOT) 143 LowSpillSlot = SS; 144 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 145 HighSpillSlot = SS; 146 EmergencySpillSlots[RC] = SS; 147 return SS; 148} 149 150void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) { 151 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) { 152 // If FI < LowSpillSlot, this stack reference was produced by 153 // instruction selection and is not a spill 154 if (FI >= LowSpillSlot) { 155 assert(FI >= 0 && "Spill slot index should not be negative!"); 156 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() 157 && "Invalid spill slot"); 158 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI); 159 } 160 } 161} 162 163void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 164 MachineInstr *NewMI, ModRef MRInfo) { 165 // Move previous memory references folded to new instruction. 166 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 167 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 168 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 169 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 170 MI2VirtMap.erase(I++); 171 } 172 173 // add new memory reference 174 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 175} 176 177void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { 178 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI); 179 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); 180} 181 182void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { 183 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 184 MachineOperand &MO = MI->getOperand(i); 185 if (!MO.isFI()) 186 continue; 187 int FI = MO.getIndex(); 188 if (MF.getFrameInfo()->isFixedObjectIndex(FI)) 189 continue; 190 // This stack reference was produced by instruction selection and 191 // is not a spill 192 if (FI < LowSpillSlot) 193 continue; 194 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() 195 && "Invalid spill slot"); 196 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI); 197 } 198 MI2VirtMap.erase(MI); 199 SpillPt2VirtMap.erase(MI); 200 RestorePt2VirtMap.erase(MI); 201 EmergencySpillMap.erase(MI); 202} 203 204void VirtRegMap::print(std::ostream &OS) const { 205 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); 206 207 OS << "********** REGISTER MAP **********\n"; 208 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 209 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { 210 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 211 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) 212 << "]\n"; 213 } 214 215 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 216 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) 217 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 218 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 219 OS << '\n'; 220} 221 222void VirtRegMap::dump() const { 223 print(cerr); 224} 225 226 227//===----------------------------------------------------------------------===// 228// Simple Spiller Implementation 229//===----------------------------------------------------------------------===// 230 231Spiller::~Spiller() {} 232 233namespace { 234 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { 235 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); 236 }; 237} 238 239bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 240 DOUT << "********** REWRITE MACHINE CODE **********\n"; 241 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; 242 const TargetMachine &TM = MF.getTarget(); 243 const TargetInstrInfo &TII = *TM.getInstrInfo(); 244 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 245 246 247 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 248 // each vreg once (in the case where a spilled vreg is used by multiple 249 // operands). This is always smaller than the number of operands to the 250 // current machine instr, so it should be small. 251 std::vector<unsigned> LoadedRegs; 252 253 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 254 MBBI != E; ++MBBI) { 255 DOUT << MBBI->getBasicBlock()->getName() << ":\n"; 256 MachineBasicBlock &MBB = *MBBI; 257 for (MachineBasicBlock::iterator MII = MBB.begin(), 258 E = MBB.end(); MII != E; ++MII) { 259 MachineInstr &MI = *MII; 260 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 261 MachineOperand &MO = MI.getOperand(i); 262 if (MO.isReg() && MO.getReg()) { 263 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 264 unsigned VirtReg = MO.getReg(); 265 unsigned SubIdx = MO.getSubReg(); 266 unsigned PhysReg = VRM.getPhys(VirtReg); 267 unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg; 268 if (!VRM.isAssignedReg(VirtReg)) { 269 int StackSlot = VRM.getStackSlot(VirtReg); 270 const TargetRegisterClass* RC = 271 MF.getRegInfo().getRegClass(VirtReg); 272 273 if (MO.isUse() && 274 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 275 == LoadedRegs.end()) { 276 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 277 MachineInstr *LoadMI = prior(MII); 278 VRM.addSpillSlotUse(StackSlot, LoadMI); 279 LoadedRegs.push_back(VirtReg); 280 ++NumLoads; 281 DOUT << '\t' << *LoadMI; 282 } 283 284 if (MO.isDef()) { 285 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true, 286 StackSlot, RC); 287 MachineInstr *StoreMI = next(MII); 288 VRM.addSpillSlotUse(StackSlot, StoreMI); 289 ++NumStores; 290 } 291 } 292 MF.getRegInfo().setPhysRegUsed(RReg); 293 MI.getOperand(i).setReg(RReg); 294 } else { 295 MF.getRegInfo().setPhysRegUsed(MO.getReg()); 296 } 297 } 298 } 299 300 DOUT << '\t' << MI; 301 LoadedRegs.clear(); 302 } 303 } 304 return true; 305} 306 307//===----------------------------------------------------------------------===// 308// Local Spiller Implementation 309//===----------------------------------------------------------------------===// 310 311namespace { 312 class AvailableSpills; 313 314 /// LocalSpiller - This spiller does a simple pass over the machine basic 315 /// block to attempt to keep spills in registers as much as possible for 316 /// blocks that have low register pressure (the vreg may be spilled due to 317 /// register pressure in other blocks). 318 class VISIBILITY_HIDDEN LocalSpiller : public Spiller { 319 MachineRegisterInfo *RegInfo; 320 const TargetRegisterInfo *TRI; 321 const TargetInstrInfo *TII; 322 DenseMap<MachineInstr*, unsigned> DistanceMap; 323 public: 324 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 325 RegInfo = &MF.getRegInfo(); 326 TRI = MF.getTarget().getRegisterInfo(); 327 TII = MF.getTarget().getInstrInfo(); 328 DOUT << "\n**** Local spiller rewriting function '" 329 << MF.getFunction()->getName() << "':\n"; 330 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" 331 " ****\n"; 332 DEBUG(MF.dump()); 333 334 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 335 MBB != E; ++MBB) 336 RewriteMBB(*MBB, VRM); 337 338 // Mark unused spill slots. 339 MachineFrameInfo *MFI = MF.getFrameInfo(); 340 int SS = VRM.getLowSpillSlot(); 341 if (SS != VirtRegMap::NO_STACK_SLOT) 342 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) 343 if (!VRM.isSpillSlotUsed(SS)) { 344 MFI->RemoveStackObject(SS); 345 ++NumDSS; 346 } 347 348 DOUT << "**** Post Machine Instrs ****\n"; 349 DEBUG(MF.dump()); 350 351 return true; 352 } 353 private: 354 void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, 355 unsigned Reg, BitVector &RegKills, 356 std::vector<MachineOperand*> &KillOps); 357 bool PrepForUnfoldOpti(MachineBasicBlock &MBB, 358 MachineBasicBlock::iterator &MII, 359 std::vector<MachineInstr*> &MaybeDeadStores, 360 AvailableSpills &Spills, BitVector &RegKills, 361 std::vector<MachineOperand*> &KillOps, 362 VirtRegMap &VRM); 363 bool CommuteToFoldReload(MachineBasicBlock &MBB, 364 MachineBasicBlock::iterator &MII, 365 unsigned VirtReg, unsigned SrcReg, int SS, 366 BitVector &RegKills, 367 std::vector<MachineOperand*> &KillOps, 368 const TargetRegisterInfo *TRI, 369 VirtRegMap &VRM); 370 void SpillRegToStackSlot(MachineBasicBlock &MBB, 371 MachineBasicBlock::iterator &MII, 372 int Idx, unsigned PhysReg, int StackSlot, 373 const TargetRegisterClass *RC, 374 bool isAvailable, MachineInstr *&LastStore, 375 AvailableSpills &Spills, 376 SmallSet<MachineInstr*, 4> &ReMatDefs, 377 BitVector &RegKills, 378 std::vector<MachineOperand*> &KillOps, 379 VirtRegMap &VRM); 380 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); 381 }; 382} 383 384/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from 385/// top down, keep track of which spills slots or remat are available in each 386/// register. 387/// 388/// Note that not all physregs are created equal here. In particular, some 389/// physregs are reloads that we are allowed to clobber or ignore at any time. 390/// Other physregs are values that the register allocated program is using that 391/// we cannot CHANGE, but we can read if we like. We keep track of this on a 392/// per-stack-slot / remat id basis as the low bit in the value of the 393/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks 394/// this bit and addAvailable sets it if. 395namespace { 396class VISIBILITY_HIDDEN AvailableSpills { 397 const TargetRegisterInfo *TRI; 398 const TargetInstrInfo *TII; 399 400 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled 401 // or remat'ed virtual register values that are still available, due to being 402 // loaded or stored to, but not invalidated yet. 403 std::map<int, unsigned> SpillSlotsOrReMatsAvailable; 404 405 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, 406 // indicating which stack slot values are currently held by a physreg. This 407 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a 408 // physreg is modified. 409 std::multimap<unsigned, int> PhysRegsAvailable; 410 411 void disallowClobberPhysRegOnly(unsigned PhysReg); 412 413 void ClobberPhysRegOnly(unsigned PhysReg); 414public: 415 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) 416 : TRI(tri), TII(tii) { 417 } 418 419 const TargetRegisterInfo *getRegInfo() const { return TRI; } 420 421 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is 422 /// available in a physical register, return that PhysReg, otherwise 423 /// return 0. 424 unsigned getSpillSlotOrReMatPhysReg(int Slot) const { 425 std::map<int, unsigned>::const_iterator I = 426 SpillSlotsOrReMatsAvailable.find(Slot); 427 if (I != SpillSlotsOrReMatsAvailable.end()) { 428 return I->second >> 1; // Remove the CanClobber bit. 429 } 430 return 0; 431 } 432 433 /// addAvailable - Mark that the specified stack slot / remat is available in 434 /// the specified physreg. If CanClobber is true, the physreg can be modified 435 /// at any time without changing the semantics of the program. 436 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, 437 bool CanClobber = true) { 438 // If this stack slot is thought to be available in some other physreg, 439 // remove its record. 440 ModifyStackSlotOrReMat(SlotOrReMat); 441 442 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); 443 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; 444 445 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 446 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; 447 else 448 DOUT << "Remembering SS#" << SlotOrReMat; 449 DOUT << " in physreg " << TRI->getName(Reg) << "\n"; 450 } 451 452 /// canClobberPhysReg - Return true if the spiller is allowed to change the 453 /// value of the specified stackslot register if it desires. The specified 454 /// stack slot must be available in a physreg for this query to make sense. 455 bool canClobberPhysReg(int SlotOrReMat) const { 456 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && 457 "Value not available!"); 458 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; 459 } 460 461 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified 462 /// stackslot register. The register is still available but is no longer 463 /// allowed to be modifed. 464 void disallowClobberPhysReg(unsigned PhysReg); 465 466 /// ClobberPhysReg - This is called when the specified physreg changes 467 /// value. We use this to invalidate any info about stuff that lives in 468 /// it and any of its aliases. 469 void ClobberPhysReg(unsigned PhysReg); 470 471 /// ModifyStackSlotOrReMat - This method is called when the value in a stack 472 /// slot changes. This removes information about which register the previous 473 /// value for this slot lives in (as the previous value is dead now). 474 void ModifyStackSlotOrReMat(int SlotOrReMat); 475}; 476} 477 478/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified 479/// stackslot register. The register is still available but is no longer 480/// allowed to be modifed. 481void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { 482 std::multimap<unsigned, int>::iterator I = 483 PhysRegsAvailable.lower_bound(PhysReg); 484 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 485 int SlotOrReMat = I->second; 486 I++; 487 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 488 "Bidirectional map mismatch!"); 489 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; 490 DOUT << "PhysReg " << TRI->getName(PhysReg) 491 << " copied, it is available for use but can no longer be modified\n"; 492 } 493} 494 495/// disallowClobberPhysReg - Unset the CanClobber bit of the specified 496/// stackslot register and its aliases. The register and its aliases may 497/// still available but is no longer allowed to be modifed. 498void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { 499 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 500 disallowClobberPhysRegOnly(*AS); 501 disallowClobberPhysRegOnly(PhysReg); 502} 503 504/// ClobberPhysRegOnly - This is called when the specified physreg changes 505/// value. We use this to invalidate any info about stuff we thing lives in it. 506void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { 507 std::multimap<unsigned, int>::iterator I = 508 PhysRegsAvailable.lower_bound(PhysReg); 509 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 510 int SlotOrReMat = I->second; 511 PhysRegsAvailable.erase(I++); 512 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 513 "Bidirectional map mismatch!"); 514 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); 515 DOUT << "PhysReg " << TRI->getName(PhysReg) 516 << " clobbered, invalidating "; 517 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 518 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; 519 else 520 DOUT << "SS#" << SlotOrReMat << "\n"; 521 } 522} 523 524/// ClobberPhysReg - This is called when the specified physreg changes 525/// value. We use this to invalidate any info about stuff we thing lives in 526/// it and any of its aliases. 527void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { 528 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 529 ClobberPhysRegOnly(*AS); 530 ClobberPhysRegOnly(PhysReg); 531} 532 533/// ModifyStackSlotOrReMat - This method is called when the value in a stack 534/// slot changes. This removes information about which register the previous 535/// value for this slot lives in (as the previous value is dead now). 536void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { 537 std::map<int, unsigned>::iterator It = 538 SpillSlotsOrReMatsAvailable.find(SlotOrReMat); 539 if (It == SpillSlotsOrReMatsAvailable.end()) return; 540 unsigned Reg = It->second >> 1; 541 SpillSlotsOrReMatsAvailable.erase(It); 542 543 // This register may hold the value of multiple stack slots, only remove this 544 // stack slot from the set of values the register contains. 545 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); 546 for (; ; ++I) { 547 assert(I != PhysRegsAvailable.end() && I->first == Reg && 548 "Map inverse broken!"); 549 if (I->second == SlotOrReMat) break; 550 } 551 PhysRegsAvailable.erase(I); 552} 553 554 555 556/// InvalidateKills - MI is going to be deleted. If any of its operands are 557/// marked kill, then invalidate the information. 558static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, 559 std::vector<MachineOperand*> &KillOps, 560 SmallVector<unsigned, 2> *KillRegs = NULL) { 561 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 562 MachineOperand &MO = MI.getOperand(i); 563 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 564 continue; 565 unsigned Reg = MO.getReg(); 566 if (TargetRegisterInfo::isVirtualRegister(Reg)) 567 continue; 568 if (KillRegs) 569 KillRegs->push_back(Reg); 570 assert(Reg < KillOps.size()); 571 if (KillOps[Reg] == &MO) { 572 RegKills.reset(Reg); 573 KillOps[Reg] = NULL; 574 } 575 } 576} 577 578/// InvalidateKill - A MI that defines the specified register is being deleted, 579/// invalidate the register kill information. 580static void InvalidateKill(unsigned Reg, BitVector &RegKills, 581 std::vector<MachineOperand*> &KillOps) { 582 if (RegKills[Reg]) { 583 KillOps[Reg]->setIsKill(false); 584 KillOps[Reg] = NULL; 585 RegKills.reset(Reg); 586 } 587} 588 589/// InvalidateRegDef - If the def operand of the specified def MI is now dead 590/// (since it's spill instruction is removed), mark it isDead. Also checks if 591/// the def MI has other definition operands that are not dead. Returns it by 592/// reference. 593static bool InvalidateRegDef(MachineBasicBlock::iterator I, 594 MachineInstr &NewDef, unsigned Reg, 595 bool &HasLiveDef) { 596 // Due to remat, it's possible this reg isn't being reused. That is, 597 // the def of this reg (by prev MI) is now dead. 598 MachineInstr *DefMI = I; 599 MachineOperand *DefOp = NULL; 600 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { 601 MachineOperand &MO = DefMI->getOperand(i); 602 if (MO.isReg() && MO.isDef()) { 603 if (MO.getReg() == Reg) 604 DefOp = &MO; 605 else if (!MO.isDead()) 606 HasLiveDef = true; 607 } 608 } 609 if (!DefOp) 610 return false; 611 612 bool FoundUse = false, Done = false; 613 MachineBasicBlock::iterator E = &NewDef; 614 ++I; ++E; 615 for (; !Done && I != E; ++I) { 616 MachineInstr *NMI = I; 617 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { 618 MachineOperand &MO = NMI->getOperand(j); 619 if (!MO.isReg() || MO.getReg() != Reg) 620 continue; 621 if (MO.isUse()) 622 FoundUse = true; 623 Done = true; // Stop after scanning all the operands of this MI. 624 } 625 } 626 if (!FoundUse) { 627 // Def is dead! 628 DefOp->setIsDead(); 629 return true; 630 } 631 return false; 632} 633 634/// UpdateKills - Track and update kill info. If a MI reads a register that is 635/// marked kill, then it must be due to register reuse. Transfer the kill info 636/// over. 637static void UpdateKills(MachineInstr &MI, BitVector &RegKills, 638 std::vector<MachineOperand*> &KillOps) { 639 const TargetInstrDesc &TID = MI.getDesc(); 640 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 641 MachineOperand &MO = MI.getOperand(i); 642 if (!MO.isReg() || !MO.isUse()) 643 continue; 644 unsigned Reg = MO.getReg(); 645 if (Reg == 0) 646 continue; 647 648 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) { 649 // That can't be right. Register is killed but not re-defined and it's 650 // being reused. Let's fix that. 651 KillOps[Reg]->setIsKill(false); 652 KillOps[Reg] = NULL; 653 RegKills.reset(Reg); 654 if (i < TID.getNumOperands() && 655 TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 656 // Unless it's a two-address operand, this is the new kill. 657 MO.setIsKill(); 658 } 659 if (MO.isKill()) { 660 RegKills.set(Reg); 661 KillOps[Reg] = &MO; 662 } 663 } 664 665 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 666 const MachineOperand &MO = MI.getOperand(i); 667 if (!MO.isReg() || !MO.isDef()) 668 continue; 669 unsigned Reg = MO.getReg(); 670 RegKills.reset(Reg); 671 KillOps[Reg] = NULL; 672 } 673} 674 675/// ReMaterialize - Re-materialize definition for Reg targetting DestReg. 676/// 677static void ReMaterialize(MachineBasicBlock &MBB, 678 MachineBasicBlock::iterator &MII, 679 unsigned DestReg, unsigned Reg, 680 const TargetInstrInfo *TII, 681 const TargetRegisterInfo *TRI, 682 VirtRegMap &VRM) { 683 TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg)); 684 MachineInstr *NewMI = prior(MII); 685 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { 686 MachineOperand &MO = NewMI->getOperand(i); 687 if (!MO.isReg() || MO.getReg() == 0) 688 continue; 689 unsigned VirtReg = MO.getReg(); 690 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) 691 continue; 692 assert(MO.isUse()); 693 unsigned SubIdx = MO.getSubReg(); 694 unsigned Phys = VRM.getPhys(VirtReg); 695 assert(Phys); 696 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 697 MO.setReg(RReg); 698 } 699 ++NumReMats; 700} 701 702 703// ReusedOp - For each reused operand, we keep track of a bit of information, in 704// case we need to rollback upon processing a new operand. See comments below. 705namespace { 706 struct ReusedOp { 707 // The MachineInstr operand that reused an available value. 708 unsigned Operand; 709 710 // StackSlotOrReMat - The spill slot or remat id of the value being reused. 711 unsigned StackSlotOrReMat; 712 713 // PhysRegReused - The physical register the value was available in. 714 unsigned PhysRegReused; 715 716 // AssignedPhysReg - The physreg that was assigned for use by the reload. 717 unsigned AssignedPhysReg; 718 719 // VirtReg - The virtual register itself. 720 unsigned VirtReg; 721 722 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, 723 unsigned vreg) 724 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), 725 AssignedPhysReg(apr), VirtReg(vreg) {} 726 }; 727 728 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that 729 /// is reused instead of reloaded. 730 class VISIBILITY_HIDDEN ReuseInfo { 731 MachineInstr &MI; 732 std::vector<ReusedOp> Reuses; 733 BitVector PhysRegsClobbered; 734 public: 735 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { 736 PhysRegsClobbered.resize(tri->getNumRegs()); 737 } 738 739 bool hasReuses() const { 740 return !Reuses.empty(); 741 } 742 743 /// addReuse - If we choose to reuse a virtual register that is already 744 /// available instead of reloading it, remember that we did so. 745 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, 746 unsigned PhysRegReused, unsigned AssignedPhysReg, 747 unsigned VirtReg) { 748 // If the reload is to the assigned register anyway, no undo will be 749 // required. 750 if (PhysRegReused == AssignedPhysReg) return; 751 752 // Otherwise, remember this. 753 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, 754 AssignedPhysReg, VirtReg)); 755 } 756 757 void markClobbered(unsigned PhysReg) { 758 PhysRegsClobbered.set(PhysReg); 759 } 760 761 bool isClobbered(unsigned PhysReg) const { 762 return PhysRegsClobbered.test(PhysReg); 763 } 764 765 /// GetRegForReload - We are about to emit a reload into PhysReg. If there 766 /// is some other operand that is using the specified register, either pick 767 /// a new register to use, or evict the previous reload and use this reg. 768 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 769 AvailableSpills &Spills, 770 std::vector<MachineInstr*> &MaybeDeadStores, 771 SmallSet<unsigned, 8> &Rejected, 772 BitVector &RegKills, 773 std::vector<MachineOperand*> &KillOps, 774 VirtRegMap &VRM) { 775 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget() 776 .getInstrInfo(); 777 778 if (Reuses.empty()) return PhysReg; // This is most often empty. 779 780 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { 781 ReusedOp &Op = Reuses[ro]; 782 // If we find some other reuse that was supposed to use this register 783 // exactly for its reload, we can change this reload to use ITS reload 784 // register. That is, unless its reload register has already been 785 // considered and subsequently rejected because it has also been reused 786 // by another operand. 787 if (Op.PhysRegReused == PhysReg && 788 Rejected.count(Op.AssignedPhysReg) == 0) { 789 // Yup, use the reload register that we didn't use before. 790 unsigned NewReg = Op.AssignedPhysReg; 791 Rejected.insert(PhysReg); 792 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, 793 RegKills, KillOps, VRM); 794 } else { 795 // Otherwise, we might also have a problem if a previously reused 796 // value aliases the new register. If so, codegen the previous reload 797 // and use this one. 798 unsigned PRRU = Op.PhysRegReused; 799 const TargetRegisterInfo *TRI = Spills.getRegInfo(); 800 if (TRI->areAliases(PRRU, PhysReg)) { 801 // Okay, we found out that an alias of a reused register 802 // was used. This isn't good because it means we have 803 // to undo a previous reuse. 804 MachineBasicBlock *MBB = MI->getParent(); 805 const TargetRegisterClass *AliasRC = 806 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); 807 808 // Copy Op out of the vector and remove it, we're going to insert an 809 // explicit load for it. 810 ReusedOp NewOp = Op; 811 Reuses.erase(Reuses.begin()+ro); 812 813 // Ok, we're going to try to reload the assigned physreg into the 814 // slot that we were supposed to in the first place. However, that 815 // register could hold a reuse. Check to see if it conflicts or 816 // would prefer us to use a different register. 817 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, 818 MI, Spills, MaybeDeadStores, 819 Rejected, RegKills, KillOps, VRM); 820 821 MachineBasicBlock::iterator MII = MI; 822 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { 823 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM); 824 } else { 825 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg, 826 NewOp.StackSlotOrReMat, AliasRC); 827 MachineInstr *LoadMI = prior(MII); 828 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI); 829 // Any stores to this stack slot are not dead anymore. 830 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; 831 ++NumLoads; 832 } 833 Spills.ClobberPhysReg(NewPhysReg); 834 Spills.ClobberPhysReg(NewOp.PhysRegReused); 835 836 unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg(); 837 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg; 838 MI->getOperand(NewOp.Operand).setReg(RReg); 839 840 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); 841 --MII; 842 UpdateKills(*MII, RegKills, KillOps); 843 DOUT << '\t' << *MII; 844 845 DOUT << "Reuse undone!\n"; 846 --NumReused; 847 848 // Finally, PhysReg is now available, go ahead and use it. 849 return PhysReg; 850 } 851 } 852 } 853 return PhysReg; 854 } 855 856 /// GetRegForReload - Helper for the above GetRegForReload(). Add a 857 /// 'Rejected' set to remember which registers have been considered and 858 /// rejected for the reload. This avoids infinite looping in case like 859 /// this: 860 /// t1 := op t2, t3 861 /// t2 <- assigned r0 for use by the reload but ended up reuse r1 862 /// t3 <- assigned r1 for use by the reload but ended up reuse r0 863 /// t1 <- desires r1 864 /// sees r1 is taken by t2, tries t2's reload register r0 865 /// sees r0 is taken by t3, tries t3's reload register r1 866 /// sees r1 is taken by t2, tries t2's reload register r0 ... 867 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 868 AvailableSpills &Spills, 869 std::vector<MachineInstr*> &MaybeDeadStores, 870 BitVector &RegKills, 871 std::vector<MachineOperand*> &KillOps, 872 VirtRegMap &VRM) { 873 SmallSet<unsigned, 8> Rejected; 874 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, 875 RegKills, KillOps, VRM); 876 } 877 }; 878} 879 880/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding 881/// instruction. e.g. 882/// xorl %edi, %eax 883/// movl %eax, -32(%ebp) 884/// movl -36(%ebp), %eax 885/// orl %eax, -32(%ebp) 886/// ==> 887/// xorl %edi, %eax 888/// orl -36(%ebp), %eax 889/// mov %eax, -32(%ebp) 890/// This enables unfolding optimization for a subsequent instruction which will 891/// also eliminate the newly introduced store instruction. 892bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, 893 MachineBasicBlock::iterator &MII, 894 std::vector<MachineInstr*> &MaybeDeadStores, 895 AvailableSpills &Spills, 896 BitVector &RegKills, 897 std::vector<MachineOperand*> &KillOps, 898 VirtRegMap &VRM) { 899 MachineFunction &MF = *MBB.getParent(); 900 MachineInstr &MI = *MII; 901 unsigned UnfoldedOpc = 0; 902 unsigned UnfoldPR = 0; 903 unsigned UnfoldVR = 0; 904 int FoldedSS = VirtRegMap::NO_STACK_SLOT; 905 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 906 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 907 // Only transform a MI that folds a single register. 908 if (UnfoldedOpc) 909 return false; 910 UnfoldVR = I->second.first; 911 VirtRegMap::ModRef MR = I->second.second; 912 // MI2VirtMap be can updated which invalidate the iterator. 913 // Increment the iterator first. 914 ++I; 915 if (VRM.isAssignedReg(UnfoldVR)) 916 continue; 917 // If this reference is not a use, any previous store is now dead. 918 // Otherwise, the store to this stack slot is not dead anymore. 919 FoldedSS = VRM.getStackSlot(UnfoldVR); 920 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; 921 if (DeadStore && (MR & VirtRegMap::isModRef)) { 922 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); 923 if (!PhysReg || !DeadStore->readsRegister(PhysReg)) 924 continue; 925 UnfoldPR = PhysReg; 926 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 927 false, true); 928 } 929 } 930 931 if (!UnfoldedOpc) 932 return false; 933 934 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 935 MachineOperand &MO = MI.getOperand(i); 936 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse()) 937 continue; 938 unsigned VirtReg = MO.getReg(); 939 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) 940 continue; 941 if (VRM.isAssignedReg(VirtReg)) { 942 unsigned PhysReg = VRM.getPhys(VirtReg); 943 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) 944 return false; 945 } else if (VRM.isReMaterialized(VirtReg)) 946 continue; 947 int SS = VRM.getStackSlot(VirtReg); 948 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 949 if (PhysReg) { 950 if (TRI->regsOverlap(PhysReg, UnfoldPR)) 951 return false; 952 continue; 953 } 954 if (VRM.hasPhys(VirtReg)) { 955 PhysReg = VRM.getPhys(VirtReg); 956 if (!TRI->regsOverlap(PhysReg, UnfoldPR)) 957 continue; 958 } 959 960 // Ok, we'll need to reload the value into a register which makes 961 // it impossible to perform the store unfolding optimization later. 962 // Let's see if it is possible to fold the load if the store is 963 // unfolded. This allows us to perform the store unfolding 964 // optimization. 965 SmallVector<MachineInstr*, 4> NewMIs; 966 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { 967 assert(NewMIs.size() == 1); 968 MachineInstr *NewMI = NewMIs.back(); 969 NewMIs.clear(); 970 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); 971 assert(Idx != -1); 972 SmallVector<unsigned, 2> Ops; 973 Ops.push_back(Idx); 974 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); 975 if (FoldedMI) { 976 VRM.addSpillSlotUse(SS, FoldedMI); 977 if (!VRM.hasPhys(UnfoldVR)) 978 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); 979 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 980 MII = MBB.insert(MII, FoldedMI); 981 InvalidateKills(MI, RegKills, KillOps); 982 VRM.RemoveMachineInstrFromMaps(&MI); 983 MBB.erase(&MI); 984 MF.DeleteMachineInstr(NewMI); 985 return true; 986 } 987 MF.DeleteMachineInstr(NewMI); 988 } 989 } 990 return false; 991} 992 993/// CommuteToFoldReload - 994/// Look for 995/// r1 = load fi#1 996/// r1 = op r1, r2<kill> 997/// store r1, fi#1 998/// 999/// If op is commutable and r2 is killed, then we can xform these to 1000/// r2 = op r2, fi#1 1001/// store r2, fi#1 1002bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB, 1003 MachineBasicBlock::iterator &MII, 1004 unsigned VirtReg, unsigned SrcReg, int SS, 1005 BitVector &RegKills, 1006 std::vector<MachineOperand*> &KillOps, 1007 const TargetRegisterInfo *TRI, 1008 VirtRegMap &VRM) { 1009 if (MII == MBB.begin() || !MII->killsRegister(SrcReg)) 1010 return false; 1011 1012 MachineFunction &MF = *MBB.getParent(); 1013 MachineInstr &MI = *MII; 1014 MachineBasicBlock::iterator DefMII = prior(MII); 1015 MachineInstr *DefMI = DefMII; 1016 const TargetInstrDesc &TID = DefMI->getDesc(); 1017 unsigned NewDstIdx; 1018 if (DefMII != MBB.begin() && 1019 TID.isCommutable() && 1020 TII->CommuteChangesDestination(DefMI, NewDstIdx)) { 1021 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 1022 unsigned NewReg = NewDstMO.getReg(); 1023 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg)) 1024 return false; 1025 MachineInstr *ReloadMI = prior(DefMII); 1026 int FrameIdx; 1027 unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx); 1028 if (DestReg != SrcReg || FrameIdx != SS) 1029 return false; 1030 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false); 1031 if (UseIdx == -1) 1032 return false; 1033 int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO); 1034 if (DefIdx == -1) 1035 return false; 1036 assert(DefMI->getOperand(DefIdx).isReg() && 1037 DefMI->getOperand(DefIdx).getReg() == SrcReg); 1038 1039 // Now commute def instruction. 1040 MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true); 1041 if (!CommutedMI) 1042 return false; 1043 SmallVector<unsigned, 2> Ops; 1044 Ops.push_back(NewDstIdx); 1045 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS); 1046 // Not needed since foldMemoryOperand returns new MI. 1047 MF.DeleteMachineInstr(CommutedMI); 1048 if (!FoldedMI) 1049 return false; 1050 1051 VRM.addSpillSlotUse(SS, FoldedMI); 1052 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 1053 // Insert new def MI and spill MI. 1054 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); 1055 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC); 1056 MII = prior(MII); 1057 MachineInstr *StoreMI = MII; 1058 VRM.addSpillSlotUse(SS, StoreMI); 1059 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1060 MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack. 1061 1062 // Delete all 3 old instructions. 1063 InvalidateKills(*ReloadMI, RegKills, KillOps); 1064 VRM.RemoveMachineInstrFromMaps(ReloadMI); 1065 MBB.erase(ReloadMI); 1066 InvalidateKills(*DefMI, RegKills, KillOps); 1067 VRM.RemoveMachineInstrFromMaps(DefMI); 1068 MBB.erase(DefMI); 1069 InvalidateKills(MI, RegKills, KillOps); 1070 VRM.RemoveMachineInstrFromMaps(&MI); 1071 MBB.erase(&MI); 1072 1073 ++NumCommutes; 1074 return true; 1075 } 1076 1077 return false; 1078} 1079 1080/// findSuperReg - Find the SubReg's super-register of given register class 1081/// where its SubIdx sub-register is SubReg. 1082static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, 1083 unsigned SubIdx, const TargetRegisterInfo *TRI) { 1084 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1085 I != E; ++I) { 1086 unsigned Reg = *I; 1087 if (TRI->getSubReg(Reg, SubIdx) == SubReg) 1088 return Reg; 1089 } 1090 return 0; 1091} 1092 1093/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if 1094/// the last store to the same slot is now dead. If so, remove the last store. 1095void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, 1096 MachineBasicBlock::iterator &MII, 1097 int Idx, unsigned PhysReg, int StackSlot, 1098 const TargetRegisterClass *RC, 1099 bool isAvailable, MachineInstr *&LastStore, 1100 AvailableSpills &Spills, 1101 SmallSet<MachineInstr*, 4> &ReMatDefs, 1102 BitVector &RegKills, 1103 std::vector<MachineOperand*> &KillOps, 1104 VirtRegMap &VRM) { 1105 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); 1106 MachineInstr *StoreMI = next(MII); 1107 VRM.addSpillSlotUse(StackSlot, StoreMI); 1108 DOUT << "Store:\t" << *StoreMI; 1109 1110 // If there is a dead store to this stack slot, nuke it now. 1111 if (LastStore) { 1112 DOUT << "Removed dead store:\t" << *LastStore; 1113 ++NumDSE; 1114 SmallVector<unsigned, 2> KillRegs; 1115 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); 1116 MachineBasicBlock::iterator PrevMII = LastStore; 1117 bool CheckDef = PrevMII != MBB.begin(); 1118 if (CheckDef) 1119 --PrevMII; 1120 VRM.RemoveMachineInstrFromMaps(LastStore); 1121 MBB.erase(LastStore); 1122 if (CheckDef) { 1123 // Look at defs of killed registers on the store. Mark the defs 1124 // as dead since the store has been deleted and they aren't 1125 // being reused. 1126 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { 1127 bool HasOtherDef = false; 1128 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) { 1129 MachineInstr *DeadDef = PrevMII; 1130 if (ReMatDefs.count(DeadDef) && !HasOtherDef) { 1131 // FIXME: This assumes a remat def does not have side 1132 // effects. 1133 VRM.RemoveMachineInstrFromMaps(DeadDef); 1134 MBB.erase(DeadDef); 1135 ++NumDRM; 1136 } 1137 } 1138 } 1139 } 1140 } 1141 1142 LastStore = next(MII); 1143 1144 // If the stack slot value was previously available in some other 1145 // register, change it now. Otherwise, make the register available, 1146 // in PhysReg. 1147 Spills.ModifyStackSlotOrReMat(StackSlot); 1148 Spills.ClobberPhysReg(PhysReg); 1149 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable); 1150 ++NumStores; 1151} 1152 1153/// TransferDeadness - A identity copy definition is dead and it's being 1154/// removed. Find the last def or use and mark it as dead / kill. 1155void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, 1156 unsigned Reg, BitVector &RegKills, 1157 std::vector<MachineOperand*> &KillOps) { 1158 int LastUDDist = -1; 1159 MachineInstr *LastUDMI = NULL; 1160 for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg), 1161 RE = RegInfo->reg_end(); RI != RE; ++RI) { 1162 MachineInstr *UDMI = &*RI; 1163 if (UDMI->getParent() != MBB) 1164 continue; 1165 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI); 1166 if (DI == DistanceMap.end() || DI->second > CurDist) 1167 continue; 1168 if ((int)DI->second < LastUDDist) 1169 continue; 1170 LastUDDist = DI->second; 1171 LastUDMI = UDMI; 1172 } 1173 1174 if (LastUDMI) { 1175 const TargetInstrDesc &TID = LastUDMI->getDesc(); 1176 MachineOperand *LastUD = NULL; 1177 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) { 1178 MachineOperand &MO = LastUDMI->getOperand(i); 1179 if (!MO.isReg() || MO.getReg() != Reg) 1180 continue; 1181 if (!LastUD || (LastUD->isUse() && MO.isDef())) 1182 LastUD = &MO; 1183 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) 1184 return; 1185 } 1186 if (LastUD->isDef()) 1187 LastUD->setIsDead(); 1188 else { 1189 LastUD->setIsKill(); 1190 RegKills.set(Reg); 1191 KillOps[Reg] = LastUD; 1192 } 1193 } 1194} 1195 1196/// rewriteMBB - Keep track of which spills are available even after the 1197/// register allocator is done with them. If possible, avid reloading vregs. 1198void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { 1199 DOUT << MBB.getBasicBlock()->getName() << ":\n"; 1200 1201 MachineFunction &MF = *MBB.getParent(); 1202 1203 // Spills - Keep track of which spilled values are available in physregs so 1204 // that we can choose to reuse the physregs instead of emitting reloads. 1205 AvailableSpills Spills(TRI, TII); 1206 1207 // MaybeDeadStores - When we need to write a value back into a stack slot, 1208 // keep track of the inserted store. If the stack slot value is never read 1209 // (because the value was used from some available register, for example), and 1210 // subsequently stored to, the original store is dead. This map keeps track 1211 // of inserted stores that are not used. If we see a subsequent store to the 1212 // same stack slot, the original store is deleted. 1213 std::vector<MachineInstr*> MaybeDeadStores; 1214 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); 1215 1216 // ReMatDefs - These are rematerializable def MIs which are not deleted. 1217 SmallSet<MachineInstr*, 4> ReMatDefs; 1218 1219 // Keep track of kill information. 1220 BitVector RegKills(TRI->getNumRegs()); 1221 std::vector<MachineOperand*> KillOps; 1222 KillOps.resize(TRI->getNumRegs(), NULL); 1223 1224 unsigned Dist = 0; 1225 DistanceMap.clear(); 1226 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 1227 MII != E; ) { 1228 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 1229 1230 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 1231 bool Erased = false; 1232 bool BackTracked = false; 1233 if (PrepForUnfoldOpti(MBB, MII, 1234 MaybeDeadStores, Spills, RegKills, KillOps, VRM)) 1235 NextMII = next(MII); 1236 1237 MachineInstr &MI = *MII; 1238 const TargetInstrDesc &TID = MI.getDesc(); 1239 1240 if (VRM.hasEmergencySpills(&MI)) { 1241 // Spill physical register(s) in the rare case the allocator has run out 1242 // of registers to allocate. 1243 SmallSet<int, 4> UsedSS; 1244 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI); 1245 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) { 1246 unsigned PhysReg = EmSpills[i]; 1247 const TargetRegisterClass *RC = 1248 TRI->getPhysicalRegisterRegClass(PhysReg); 1249 assert(RC && "Unable to determine register class!"); 1250 int SS = VRM.getEmergencySpillSlot(RC); 1251 if (UsedSS.count(SS)) 1252 assert(0 && "Need to spill more than one physical registers!"); 1253 UsedSS.insert(SS); 1254 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); 1255 MachineInstr *StoreMI = prior(MII); 1256 VRM.addSpillSlotUse(SS, StoreMI); 1257 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC); 1258 MachineInstr *LoadMI = next(MII); 1259 VRM.addSpillSlotUse(SS, LoadMI); 1260 ++NumPSpills; 1261 } 1262 NextMII = next(MII); 1263 } 1264 1265 // Insert restores here if asked to. 1266 if (VRM.isRestorePt(&MI)) { 1267 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI); 1268 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { 1269 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order. 1270 if (!VRM.getPreSplitReg(VirtReg)) 1271 continue; // Split interval spilled again. 1272 unsigned Phys = VRM.getPhys(VirtReg); 1273 RegInfo->setPhysRegUsed(Phys); 1274 if (VRM.isReMaterialized(VirtReg)) { 1275 ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM); 1276 } else { 1277 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1278 int SS = VRM.getStackSlot(VirtReg); 1279 TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC); 1280 MachineInstr *LoadMI = prior(MII); 1281 VRM.addSpillSlotUse(SS, LoadMI); 1282 ++NumLoads; 1283 } 1284 // This invalidates Phys. 1285 Spills.ClobberPhysReg(Phys); 1286 UpdateKills(*prior(MII), RegKills, KillOps); 1287 DOUT << '\t' << *prior(MII); 1288 } 1289 } 1290 1291 // Insert spills here if asked to. 1292 if (VRM.isSpillPt(&MI)) { 1293 std::vector<std::pair<unsigned,bool> > &SpillRegs = 1294 VRM.getSpillPtSpills(&MI); 1295 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { 1296 unsigned VirtReg = SpillRegs[i].first; 1297 bool isKill = SpillRegs[i].second; 1298 if (!VRM.getPreSplitReg(VirtReg)) 1299 continue; // Split interval spilled again. 1300 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1301 unsigned Phys = VRM.getPhys(VirtReg); 1302 int StackSlot = VRM.getStackSlot(VirtReg); 1303 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); 1304 MachineInstr *StoreMI = next(MII); 1305 VRM.addSpillSlotUse(StackSlot, StoreMI); 1306 DOUT << "Store:\t" << *StoreMI; 1307 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1308 } 1309 NextMII = next(MII); 1310 } 1311 1312 /// ReusedOperands - Keep track of operand reuse in case we need to undo 1313 /// reuse. 1314 ReuseInfo ReusedOperands(MI, TRI); 1315 SmallVector<unsigned, 4> VirtUseOps; 1316 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1317 MachineOperand &MO = MI.getOperand(i); 1318 if (!MO.isReg() || MO.getReg() == 0) 1319 continue; // Ignore non-register operands. 1320 1321 unsigned VirtReg = MO.getReg(); 1322 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { 1323 // Ignore physregs for spilling, but remember that it is used by this 1324 // function. 1325 RegInfo->setPhysRegUsed(VirtReg); 1326 continue; 1327 } 1328 1329 // We want to process implicit virtual register uses first. 1330 if (MO.isImplicit()) 1331 // If the virtual register is implicitly defined, emit a implicit_def 1332 // before so scavenger knows it's "defined". 1333 VirtUseOps.insert(VirtUseOps.begin(), i); 1334 else 1335 VirtUseOps.push_back(i); 1336 } 1337 1338 // Process all of the spilled uses and all non spilled reg references. 1339 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) { 1340 unsigned i = VirtUseOps[j]; 1341 MachineOperand &MO = MI.getOperand(i); 1342 unsigned VirtReg = MO.getReg(); 1343 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 1344 "Not a virtual register?"); 1345 1346 unsigned SubIdx = MO.getSubReg(); 1347 if (VRM.isAssignedReg(VirtReg)) { 1348 // This virtual register was assigned a physreg! 1349 unsigned Phys = VRM.getPhys(VirtReg); 1350 RegInfo->setPhysRegUsed(Phys); 1351 if (MO.isDef()) 1352 ReusedOperands.markClobbered(Phys); 1353 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 1354 MI.getOperand(i).setReg(RReg); 1355 if (VRM.isImplicitlyDefined(VirtReg)) 1356 BuildMI(MBB, &MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg); 1357 continue; 1358 } 1359 1360 // This virtual register is now known to be a spilled value. 1361 if (!MO.isUse()) 1362 continue; // Handle defs in the loop below (handle use&def here though) 1363 1364 bool DoReMat = VRM.isReMaterialized(VirtReg); 1365 int SSorRMId = DoReMat 1366 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); 1367 int ReuseSlot = SSorRMId; 1368 1369 // Check to see if this stack slot is available. 1370 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); 1371 1372 // If this is a sub-register use, make sure the reuse register is in the 1373 // right register class. For example, for x86 not all of the 32-bit 1374 // registers have accessible sub-registers. 1375 // Similarly so for EXTRACT_SUBREG. Consider this: 1376 // EDI = op 1377 // MOV32_mr fi#1, EDI 1378 // ... 1379 // = EXTRACT_SUBREG fi#1 1380 // fi#1 is available in EDI, but it cannot be reused because it's not in 1381 // the right register file. 1382 if (PhysReg && 1383 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { 1384 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1385 if (!RC->contains(PhysReg)) 1386 PhysReg = 0; 1387 } 1388 1389 if (PhysReg) { 1390 // This spilled operand might be part of a two-address operand. If this 1391 // is the case, then changing it will necessarily require changing the 1392 // def part of the instruction as well. However, in some cases, we 1393 // aren't allowed to modify the reused register. If none of these cases 1394 // apply, reuse it. 1395 bool CanReuse = true; 1396 int ti = TID.getOperandConstraint(i, TOI::TIED_TO); 1397 if (ti != -1 && 1398 MI.getOperand(ti).isReg() && 1399 MI.getOperand(ti).getReg() == VirtReg) { 1400 // Okay, we have a two address operand. We can reuse this physreg as 1401 // long as we are allowed to clobber the value and there isn't an 1402 // earlier def that has already clobbered the physreg. 1403 CanReuse = Spills.canClobberPhysReg(ReuseSlot) && 1404 !ReusedOperands.isClobbered(PhysReg); 1405 } 1406 1407 if (CanReuse) { 1408 // If this stack slot value is already available, reuse it! 1409 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1410 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1411 else 1412 DOUT << "Reusing SS#" << ReuseSlot; 1413 DOUT << " from physreg " 1414 << TRI->getName(PhysReg) << " for vreg" 1415 << VirtReg <<" instead of reloading into physreg " 1416 << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; 1417 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1418 MI.getOperand(i).setReg(RReg); 1419 1420 // The only technical detail we have is that we don't know that 1421 // PhysReg won't be clobbered by a reloaded stack slot that occurs 1422 // later in the instruction. In particular, consider 'op V1, V2'. 1423 // If V1 is available in physreg R0, we would choose to reuse it 1424 // here, instead of reloading it into the register the allocator 1425 // indicated (say R1). However, V2 might have to be reloaded 1426 // later, and it might indicate that it needs to live in R0. When 1427 // this occurs, we need to have information available that 1428 // indicates it is safe to use R1 for the reload instead of R0. 1429 // 1430 // To further complicate matters, we might conflict with an alias, 1431 // or R0 and R1 might not be compatible with each other. In this 1432 // case, we actually insert a reload for V1 in R1, ensuring that 1433 // we can get at R0 or its alias. 1434 ReusedOperands.addReuse(i, ReuseSlot, PhysReg, 1435 VRM.getPhys(VirtReg), VirtReg); 1436 if (ti != -1) 1437 // Only mark it clobbered if this is a use&def operand. 1438 ReusedOperands.markClobbered(PhysReg); 1439 ++NumReused; 1440 1441 if (MI.getOperand(i).isKill() && 1442 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { 1443 // This was the last use and the spilled value is still available 1444 // for reuse. That means the spill was unnecessary! 1445 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; 1446 if (DeadStore) { 1447 DOUT << "Removed dead store:\t" << *DeadStore; 1448 InvalidateKills(*DeadStore, RegKills, KillOps); 1449 VRM.RemoveMachineInstrFromMaps(DeadStore); 1450 MBB.erase(DeadStore); 1451 MaybeDeadStores[ReuseSlot] = NULL; 1452 ++NumDSE; 1453 } 1454 } 1455 continue; 1456 } // CanReuse 1457 1458 // Otherwise we have a situation where we have a two-address instruction 1459 // whose mod/ref operand needs to be reloaded. This reload is already 1460 // available in some register "PhysReg", but if we used PhysReg as the 1461 // operand to our 2-addr instruction, the instruction would modify 1462 // PhysReg. This isn't cool if something later uses PhysReg and expects 1463 // to get its initial value. 1464 // 1465 // To avoid this problem, and to avoid doing a load right after a store, 1466 // we emit a copy from PhysReg into the designated register for this 1467 // operand. 1468 unsigned DesignatedReg = VRM.getPhys(VirtReg); 1469 assert(DesignatedReg && "Must map virtreg to physreg!"); 1470 1471 // Note that, if we reused a register for a previous operand, the 1472 // register we want to reload into might not actually be 1473 // available. If this occurs, use the register indicated by the 1474 // reuser. 1475 if (ReusedOperands.hasReuses()) 1476 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, 1477 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1478 1479 // If the mapped designated register is actually the physreg we have 1480 // incoming, we don't need to inserted a dead copy. 1481 if (DesignatedReg == PhysReg) { 1482 // If this stack slot value is already available, reuse it! 1483 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1484 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1485 else 1486 DOUT << "Reusing SS#" << ReuseSlot; 1487 DOUT << " from physreg " << TRI->getName(PhysReg) 1488 << " for vreg" << VirtReg 1489 << " instead of reloading into same physreg.\n"; 1490 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1491 MI.getOperand(i).setReg(RReg); 1492 ReusedOperands.markClobbered(RReg); 1493 ++NumReused; 1494 continue; 1495 } 1496 1497 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1498 RegInfo->setPhysRegUsed(DesignatedReg); 1499 ReusedOperands.markClobbered(DesignatedReg); 1500 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); 1501 1502 MachineInstr *CopyMI = prior(MII); 1503 UpdateKills(*CopyMI, RegKills, KillOps); 1504 1505 // This invalidates DesignatedReg. 1506 Spills.ClobberPhysReg(DesignatedReg); 1507 1508 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); 1509 unsigned RReg = 1510 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; 1511 MI.getOperand(i).setReg(RReg); 1512 DOUT << '\t' << *prior(MII); 1513 ++NumReused; 1514 continue; 1515 } // if (PhysReg) 1516 1517 // Otherwise, reload it and remember that we have it. 1518 PhysReg = VRM.getPhys(VirtReg); 1519 assert(PhysReg && "Must map virtreg to physreg!"); 1520 1521 // Note that, if we reused a register for a previous operand, the 1522 // register we want to reload into might not actually be 1523 // available. If this occurs, use the register indicated by the 1524 // reuser. 1525 if (ReusedOperands.hasReuses()) 1526 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1527 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1528 1529 RegInfo->setPhysRegUsed(PhysReg); 1530 ReusedOperands.markClobbered(PhysReg); 1531 if (DoReMat) { 1532 ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM); 1533 } else { 1534 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1535 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); 1536 MachineInstr *LoadMI = prior(MII); 1537 VRM.addSpillSlotUse(SSorRMId, LoadMI); 1538 ++NumLoads; 1539 } 1540 // This invalidates PhysReg. 1541 Spills.ClobberPhysReg(PhysReg); 1542 1543 // Any stores to this stack slot are not dead anymore. 1544 if (!DoReMat) 1545 MaybeDeadStores[SSorRMId] = NULL; 1546 Spills.addAvailable(SSorRMId, &MI, PhysReg); 1547 // Assumes this is the last use. IsKill will be unset if reg is reused 1548 // unless it's a two-address operand. 1549 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 1550 MI.getOperand(i).setIsKill(); 1551 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1552 MI.getOperand(i).setReg(RReg); 1553 UpdateKills(*prior(MII), RegKills, KillOps); 1554 DOUT << '\t' << *prior(MII); 1555 } 1556 1557 DOUT << '\t' << MI; 1558 1559 1560 // If we have folded references to memory operands, make sure we clear all 1561 // physical registers that may contain the value of the spilled virtual 1562 // register 1563 SmallSet<int, 2> FoldedSS; 1564 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 1565 unsigned VirtReg = I->second.first; 1566 VirtRegMap::ModRef MR = I->second.second; 1567 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; 1568 1569 // MI2VirtMap be can updated which invalidate the iterator. 1570 // Increment the iterator first. 1571 ++I; 1572 int SS = VRM.getStackSlot(VirtReg); 1573 if (SS == VirtRegMap::NO_STACK_SLOT) 1574 continue; 1575 FoldedSS.insert(SS); 1576 DOUT << " - StackSlot: " << SS << "\n"; 1577 1578 // If this folded instruction is just a use, check to see if it's a 1579 // straight load from the virt reg slot. 1580 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { 1581 int FrameIdx; 1582 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); 1583 if (DestReg && FrameIdx == SS) { 1584 // If this spill slot is available, turn it into a copy (or nothing) 1585 // instead of leaving it as a load! 1586 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { 1587 DOUT << "Promoted Load To Copy: " << MI; 1588 if (DestReg != InReg) { 1589 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1590 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); 1591 MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg); 1592 unsigned SubIdx = DefMO->getSubReg(); 1593 // Revisit the copy so we make sure to notice the effects of the 1594 // operation on the destreg (either needing to RA it if it's 1595 // virtual or needing to clobber any values if it's physical). 1596 NextMII = &MI; 1597 --NextMII; // backtrack to the copy. 1598 // Propagate the sub-register index over. 1599 if (SubIdx) { 1600 DefMO = NextMII->findRegisterDefOperand(DestReg); 1601 DefMO->setSubReg(SubIdx); 1602 } 1603 BackTracked = true; 1604 } else { 1605 DOUT << "Removing now-noop copy: " << MI; 1606 // Unset last kill since it's being reused. 1607 InvalidateKill(InReg, RegKills, KillOps); 1608 } 1609 1610 InvalidateKills(MI, RegKills, KillOps); 1611 VRM.RemoveMachineInstrFromMaps(&MI); 1612 MBB.erase(&MI); 1613 Erased = true; 1614 goto ProcessNextInst; 1615 } 1616 } else { 1617 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1618 SmallVector<MachineInstr*, 4> NewMIs; 1619 if (PhysReg && 1620 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { 1621 MBB.insert(MII, NewMIs[0]); 1622 InvalidateKills(MI, RegKills, KillOps); 1623 VRM.RemoveMachineInstrFromMaps(&MI); 1624 MBB.erase(&MI); 1625 Erased = true; 1626 --NextMII; // backtrack to the unfolded instruction. 1627 BackTracked = true; 1628 goto ProcessNextInst; 1629 } 1630 } 1631 } 1632 1633 // If this reference is not a use, any previous store is now dead. 1634 // Otherwise, the store to this stack slot is not dead anymore. 1635 MachineInstr* DeadStore = MaybeDeadStores[SS]; 1636 if (DeadStore) { 1637 bool isDead = !(MR & VirtRegMap::isRef); 1638 MachineInstr *NewStore = NULL; 1639 if (MR & VirtRegMap::isModRef) { 1640 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1641 SmallVector<MachineInstr*, 4> NewMIs; 1642 // We can reuse this physreg as long as we are allowed to clobber 1643 // the value and there isn't an earlier def that has already clobbered 1644 // the physreg. 1645 if (PhysReg && 1646 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable! 1647 MachineOperand *KillOpnd = 1648 DeadStore->findRegisterUseOperand(PhysReg, true); 1649 // Note, if the store is storing a sub-register, it's possible the 1650 // super-register is needed below. 1651 if (KillOpnd && !KillOpnd->getSubReg() && 1652 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){ 1653 MBB.insert(MII, NewMIs[0]); 1654 NewStore = NewMIs[1]; 1655 MBB.insert(MII, NewStore); 1656 VRM.addSpillSlotUse(SS, NewStore); 1657 InvalidateKills(MI, RegKills, KillOps); 1658 VRM.RemoveMachineInstrFromMaps(&MI); 1659 MBB.erase(&MI); 1660 Erased = true; 1661 --NextMII; 1662 --NextMII; // backtrack to the unfolded instruction. 1663 BackTracked = true; 1664 isDead = true; 1665 } 1666 } 1667 } 1668 1669 if (isDead) { // Previous store is dead. 1670 // If we get here, the store is dead, nuke it now. 1671 DOUT << "Removed dead store:\t" << *DeadStore; 1672 InvalidateKills(*DeadStore, RegKills, KillOps); 1673 VRM.RemoveMachineInstrFromMaps(DeadStore); 1674 MBB.erase(DeadStore); 1675 if (!NewStore) 1676 ++NumDSE; 1677 } 1678 1679 MaybeDeadStores[SS] = NULL; 1680 if (NewStore) { 1681 // Treat this store as a spill merged into a copy. That makes the 1682 // stack slot value available. 1683 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod); 1684 goto ProcessNextInst; 1685 } 1686 } 1687 1688 // If the spill slot value is available, and this is a new definition of 1689 // the value, the value is not available anymore. 1690 if (MR & VirtRegMap::isMod) { 1691 // Notice that the value in this stack slot has been modified. 1692 Spills.ModifyStackSlotOrReMat(SS); 1693 1694 // If this is *just* a mod of the value, check to see if this is just a 1695 // store to the spill slot (i.e. the spill got merged into the copy). If 1696 // so, realize that the vreg is available now, and add the store to the 1697 // MaybeDeadStore info. 1698 int StackSlot; 1699 if (!(MR & VirtRegMap::isRef)) { 1700 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { 1701 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && 1702 "Src hasn't been allocated yet?"); 1703 1704 if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot, 1705 RegKills, KillOps, TRI, VRM)) { 1706 NextMII = next(MII); 1707 BackTracked = true; 1708 goto ProcessNextInst; 1709 } 1710 1711 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark 1712 // this as a potentially dead store in case there is a subsequent 1713 // store into the stack slot without a read from it. 1714 MaybeDeadStores[StackSlot] = &MI; 1715 1716 // If the stack slot value was previously available in some other 1717 // register, change it now. Otherwise, make the register 1718 // available in PhysReg. 1719 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*!clobber*/); 1720 } 1721 } 1722 } 1723 } 1724 1725 // Process all of the spilled defs. 1726 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1727 MachineOperand &MO = MI.getOperand(i); 1728 if (!(MO.isReg() && MO.getReg() && MO.isDef())) 1729 continue; 1730 1731 unsigned VirtReg = MO.getReg(); 1732 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { 1733 // Check to see if this is a noop copy. If so, eliminate the 1734 // instruction before considering the dest reg to be changed. 1735 unsigned Src, Dst; 1736 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1737 ++NumDCE; 1738 DOUT << "Removing now-noop copy: " << MI; 1739 SmallVector<unsigned, 2> KillRegs; 1740 InvalidateKills(MI, RegKills, KillOps, &KillRegs); 1741 if (MO.isDead() && !KillRegs.empty()) { 1742 // Source register or an implicit super-register use is killed. 1743 assert(KillRegs[0] == Dst || TRI->isSubRegister(KillRegs[0], Dst)); 1744 // Last def is now dead. 1745 TransferDeadness(&MBB, Dist, Src, RegKills, KillOps); 1746 } 1747 VRM.RemoveMachineInstrFromMaps(&MI); 1748 MBB.erase(&MI); 1749 Erased = true; 1750 Spills.disallowClobberPhysReg(VirtReg); 1751 goto ProcessNextInst; 1752 } 1753 1754 // If it's not a no-op copy, it clobbers the value in the destreg. 1755 Spills.ClobberPhysReg(VirtReg); 1756 ReusedOperands.markClobbered(VirtReg); 1757 1758 // Check to see if this instruction is a load from a stack slot into 1759 // a register. If so, this provides the stack slot value in the reg. 1760 int FrameIdx; 1761 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { 1762 assert(DestReg == VirtReg && "Unknown load situation!"); 1763 1764 // If it is a folded reference, then it's not safe to clobber. 1765 bool Folded = FoldedSS.count(FrameIdx); 1766 // Otherwise, if it wasn't available, remember that it is now! 1767 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); 1768 goto ProcessNextInst; 1769 } 1770 1771 continue; 1772 } 1773 1774 unsigned SubIdx = MO.getSubReg(); 1775 bool DoReMat = VRM.isReMaterialized(VirtReg); 1776 if (DoReMat) 1777 ReMatDefs.insert(&MI); 1778 1779 // The only vregs left are stack slot definitions. 1780 int StackSlot = VRM.getStackSlot(VirtReg); 1781 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1782 1783 // If this def is part of a two-address operand, make sure to execute 1784 // the store from the correct physical register. 1785 unsigned PhysReg; 1786 int TiedOp = MI.getDesc().findTiedToSrcOperand(i); 1787 if (TiedOp != -1) { 1788 PhysReg = MI.getOperand(TiedOp).getReg(); 1789 if (SubIdx) { 1790 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); 1791 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && 1792 "Can't find corresponding super-register!"); 1793 PhysReg = SuperReg; 1794 } 1795 } else { 1796 PhysReg = VRM.getPhys(VirtReg); 1797 if (ReusedOperands.isClobbered(PhysReg)) { 1798 // Another def has taken the assigned physreg. It must have been a 1799 // use&def which got it due to reuse. Undo the reuse! 1800 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1801 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1802 } 1803 } 1804 1805 assert(PhysReg && "VR not assigned a physical register?"); 1806 RegInfo->setPhysRegUsed(PhysReg); 1807 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1808 ReusedOperands.markClobbered(RReg); 1809 MI.getOperand(i).setReg(RReg); 1810 1811 if (!MO.isDead()) { 1812 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 1813 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true, 1814 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); 1815 NextMII = next(MII); 1816 1817 // Check to see if this is a noop copy. If so, eliminate the 1818 // instruction before considering the dest reg to be changed. 1819 { 1820 unsigned Src, Dst; 1821 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1822 ++NumDCE; 1823 DOUT << "Removing now-noop copy: " << MI; 1824 InvalidateKills(MI, RegKills, KillOps); 1825 VRM.RemoveMachineInstrFromMaps(&MI); 1826 MBB.erase(&MI); 1827 Erased = true; 1828 UpdateKills(*LastStore, RegKills, KillOps); 1829 goto ProcessNextInst; 1830 } 1831 } 1832 } 1833 } 1834 ProcessNextInst: 1835 DistanceMap.insert(std::make_pair(&MI, Dist++)); 1836 if (!Erased && !BackTracked) { 1837 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II) 1838 UpdateKills(*II, RegKills, KillOps); 1839 } 1840 MII = NextMII; 1841 } 1842} 1843 1844llvm::Spiller* llvm::createSpiller() { 1845 switch (SpillerOpt) { 1846 default: assert(0 && "Unreachable!"); 1847 case local: 1848 return new LocalSpiller(); 1849 case simple: 1850 return new SimpleSpiller(); 1851 } 1852} 1853