VirtRegMap.cpp revision 7ebc06bfd8df4cd7c477af1e5fec196c32efcfea
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the VirtRegMap class. 11// 12// It also contains implementations of the the Spiller interface, which, given a 13// virtual register map and a machine function, eliminates all virtual 14// references by replacing them with physical register references - adding spill 15// code as necessary. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "spiller" 20#include "VirtRegMap.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Target/TargetInstrInfo.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/ADT/BitVector.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/ADT/STLExtras.h" 34#include "llvm/ADT/SmallSet.h" 35#include <algorithm> 36using namespace llvm; 37 38STATISTIC(NumSpills, "Number of register spills"); 39STATISTIC(NumPSpills,"Number of physical register spills"); 40STATISTIC(NumReMats, "Number of re-materialization"); 41STATISTIC(NumDRM , "Number of re-materializable defs elided"); 42STATISTIC(NumStores, "Number of stores added"); 43STATISTIC(NumLoads , "Number of loads added"); 44STATISTIC(NumReused, "Number of values reused"); 45STATISTIC(NumDSE , "Number of dead stores elided"); 46STATISTIC(NumDCE , "Number of copies elided"); 47STATISTIC(NumDSS , "Number of dead spill slots removed"); 48 49namespace { 50 enum SpillerName { simple, local }; 51 52 static cl::opt<SpillerName> 53 SpillerOpt("spiller", 54 cl::desc("Spiller to use: (default: local)"), 55 cl::Prefix, 56 cl::values(clEnumVal(simple, " simple spiller"), 57 clEnumVal(local, " local spiller"), 58 clEnumValEnd), 59 cl::init(local)); 60} 61 62//===----------------------------------------------------------------------===// 63// VirtRegMap implementation 64//===----------------------------------------------------------------------===// 65 66VirtRegMap::VirtRegMap(MachineFunction &mf) 67 : TII(*mf.getTarget().getInstrInfo()), MF(mf), 68 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), 69 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), 70 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1), 71 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { 72 SpillSlotToUsesMap.resize(8); 73 ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1- 74 TargetRegisterInfo::FirstVirtualRegister); 75 grow(); 76} 77 78void VirtRegMap::grow() { 79 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); 80 Virt2PhysMap.grow(LastVirtReg); 81 Virt2StackSlotMap.grow(LastVirtReg); 82 Virt2ReMatIdMap.grow(LastVirtReg); 83 Virt2SplitMap.grow(LastVirtReg); 84 Virt2SplitKillMap.grow(LastVirtReg); 85 ReMatMap.grow(LastVirtReg); 86 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1); 87} 88 89int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 90 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 91 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 92 "attempt to assign stack slot to already spilled register"); 93 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); 94 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 95 RC->getAlignment()); 96 if (LowSpillSlot == NO_STACK_SLOT) 97 LowSpillSlot = SS; 98 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 99 HighSpillSlot = SS; 100 unsigned Idx = SS-LowSpillSlot; 101 while (Idx >= SpillSlotToUsesMap.size()) 102 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2); 103 Virt2StackSlotMap[virtReg] = SS; 104 ++NumSpills; 105 return SS; 106} 107 108void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { 109 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 110 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 111 "attempt to assign stack slot to already spilled register"); 112 assert((SS >= 0 || 113 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) && 114 "illegal fixed frame index"); 115 Virt2StackSlotMap[virtReg] = SS; 116} 117 118int VirtRegMap::assignVirtReMatId(unsigned virtReg) { 119 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 120 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 121 "attempt to assign re-mat id to already spilled register"); 122 Virt2ReMatIdMap[virtReg] = ReMatId; 123 return ReMatId++; 124} 125 126void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { 127 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 128 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 129 "attempt to assign re-mat id to already spilled register"); 130 Virt2ReMatIdMap[virtReg] = id; 131} 132 133int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { 134 std::map<const TargetRegisterClass*, int>::iterator I = 135 EmergencySpillSlots.find(RC); 136 if (I != EmergencySpillSlots.end()) 137 return I->second; 138 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 139 RC->getAlignment()); 140 if (LowSpillSlot == NO_STACK_SLOT) 141 LowSpillSlot = SS; 142 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 143 HighSpillSlot = SS; 144 I->second = SS; 145 return SS; 146} 147 148void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) { 149 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) { 150 assert(FI >= 0 && "Spill slot index should not be negative!"); 151 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI); 152 } 153} 154 155void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 156 MachineInstr *NewMI, ModRef MRInfo) { 157 // Move previous memory references folded to new instruction. 158 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 159 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 160 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 161 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 162 MI2VirtMap.erase(I++); 163 } 164 165 // add new memory reference 166 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 167} 168 169void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { 170 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI); 171 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); 172} 173 174void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { 175 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 176 MachineOperand &MO = MI->getOperand(i); 177 if (!MO.isFrameIndex()) 178 continue; 179 int FI = MO.getIndex(); 180 if (MF.getFrameInfo()->isFixedObjectIndex(FI)) 181 continue; 182 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI); 183 } 184 MI2VirtMap.erase(MI); 185 SpillPt2VirtMap.erase(MI); 186 RestorePt2VirtMap.erase(MI); 187 EmergencySpillMap.erase(MI); 188} 189 190void VirtRegMap::print(std::ostream &OS) const { 191 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); 192 193 OS << "********** REGISTER MAP **********\n"; 194 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 195 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { 196 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 197 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) 198 << "]\n"; 199 } 200 201 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 202 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) 203 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 204 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 205 OS << '\n'; 206} 207 208void VirtRegMap::dump() const { 209 print(cerr); 210} 211 212 213//===----------------------------------------------------------------------===// 214// Simple Spiller Implementation 215//===----------------------------------------------------------------------===// 216 217Spiller::~Spiller() {} 218 219namespace { 220 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { 221 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); 222 }; 223} 224 225bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 226 DOUT << "********** REWRITE MACHINE CODE **********\n"; 227 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; 228 const TargetMachine &TM = MF.getTarget(); 229 const TargetInstrInfo &TII = *TM.getInstrInfo(); 230 231 232 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 233 // each vreg once (in the case where a spilled vreg is used by multiple 234 // operands). This is always smaller than the number of operands to the 235 // current machine instr, so it should be small. 236 std::vector<unsigned> LoadedRegs; 237 238 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 239 MBBI != E; ++MBBI) { 240 DOUT << MBBI->getBasicBlock()->getName() << ":\n"; 241 MachineBasicBlock &MBB = *MBBI; 242 for (MachineBasicBlock::iterator MII = MBB.begin(), 243 E = MBB.end(); MII != E; ++MII) { 244 MachineInstr &MI = *MII; 245 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 246 MachineOperand &MO = MI.getOperand(i); 247 if (MO.isRegister() && MO.getReg()) { 248 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 249 unsigned VirtReg = MO.getReg(); 250 unsigned PhysReg = VRM.getPhys(VirtReg); 251 if (!VRM.isAssignedReg(VirtReg)) { 252 int StackSlot = VRM.getStackSlot(VirtReg); 253 const TargetRegisterClass* RC = 254 MF.getRegInfo().getRegClass(VirtReg); 255 256 if (MO.isUse() && 257 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 258 == LoadedRegs.end()) { 259 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 260 MachineInstr *LoadMI = prior(MII); 261 VRM.addSpillSlotUse(StackSlot, LoadMI); 262 LoadedRegs.push_back(VirtReg); 263 ++NumLoads; 264 DOUT << '\t' << *LoadMI; 265 } 266 267 if (MO.isDef()) { 268 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true, 269 StackSlot, RC); 270 MachineInstr *StoreMI = next(MII); 271 VRM.addSpillSlotUse(StackSlot, StoreMI); 272 ++NumStores; 273 } 274 } 275 MF.getRegInfo().setPhysRegUsed(PhysReg); 276 MI.getOperand(i).setReg(PhysReg); 277 } else { 278 MF.getRegInfo().setPhysRegUsed(MO.getReg()); 279 } 280 } 281 } 282 283 DOUT << '\t' << MI; 284 LoadedRegs.clear(); 285 } 286 } 287 return true; 288} 289 290//===----------------------------------------------------------------------===// 291// Local Spiller Implementation 292//===----------------------------------------------------------------------===// 293 294namespace { 295 class AvailableSpills; 296 297 /// LocalSpiller - This spiller does a simple pass over the machine basic 298 /// block to attempt to keep spills in registers as much as possible for 299 /// blocks that have low register pressure (the vreg may be spilled due to 300 /// register pressure in other blocks). 301 class VISIBILITY_HIDDEN LocalSpiller : public Spiller { 302 MachineRegisterInfo *RegInfo; 303 const TargetRegisterInfo *TRI; 304 const TargetInstrInfo *TII; 305 public: 306 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 307 RegInfo = &MF.getRegInfo(); 308 TRI = MF.getTarget().getRegisterInfo(); 309 TII = MF.getTarget().getInstrInfo(); 310 DOUT << "\n**** Local spiller rewriting function '" 311 << MF.getFunction()->getName() << "':\n"; 312 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" 313 " ****\n"; 314 DEBUG(MF.dump()); 315 316 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 317 MBB != E; ++MBB) 318 RewriteMBB(*MBB, VRM); 319 320 // Mark unused spill slots. 321 MachineFrameInfo *MFI = MF.getFrameInfo(); 322 int SS = VRM.getLowSpillSlot(); 323 if (SS != VirtRegMap::NO_STACK_SLOT) 324 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) 325 if (!VRM.isSpillSlotUsed(SS)) { 326 MFI->RemoveStackObject(SS); 327 ++NumDSS; 328 } 329 330 DOUT << "**** Post Machine Instrs ****\n"; 331 DEBUG(MF.dump()); 332 333 return true; 334 } 335 private: 336 bool PrepForUnfoldOpti(MachineBasicBlock &MBB, 337 MachineBasicBlock::iterator &MII, 338 std::vector<MachineInstr*> &MaybeDeadStores, 339 AvailableSpills &Spills, BitVector &RegKills, 340 std::vector<MachineOperand*> &KillOps, 341 VirtRegMap &VRM); 342 void SpillRegToStackSlot(MachineBasicBlock &MBB, 343 MachineBasicBlock::iterator &MII, 344 int Idx, unsigned PhysReg, int StackSlot, 345 const TargetRegisterClass *RC, 346 bool isAvailable, MachineInstr *&LastStore, 347 AvailableSpills &Spills, 348 SmallSet<MachineInstr*, 4> &ReMatDefs, 349 BitVector &RegKills, 350 std::vector<MachineOperand*> &KillOps, 351 VirtRegMap &VRM); 352 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); 353 }; 354} 355 356/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from 357/// top down, keep track of which spills slots or remat are available in each 358/// register. 359/// 360/// Note that not all physregs are created equal here. In particular, some 361/// physregs are reloads that we are allowed to clobber or ignore at any time. 362/// Other physregs are values that the register allocated program is using that 363/// we cannot CHANGE, but we can read if we like. We keep track of this on a 364/// per-stack-slot / remat id basis as the low bit in the value of the 365/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks 366/// this bit and addAvailable sets it if. 367namespace { 368class VISIBILITY_HIDDEN AvailableSpills { 369 const TargetRegisterInfo *TRI; 370 const TargetInstrInfo *TII; 371 372 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled 373 // or remat'ed virtual register values that are still available, due to being 374 // loaded or stored to, but not invalidated yet. 375 std::map<int, unsigned> SpillSlotsOrReMatsAvailable; 376 377 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, 378 // indicating which stack slot values are currently held by a physreg. This 379 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a 380 // physreg is modified. 381 std::multimap<unsigned, int> PhysRegsAvailable; 382 383 void disallowClobberPhysRegOnly(unsigned PhysReg); 384 385 void ClobberPhysRegOnly(unsigned PhysReg); 386public: 387 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) 388 : TRI(tri), TII(tii) { 389 } 390 391 const TargetRegisterInfo *getRegInfo() const { return TRI; } 392 393 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is 394 /// available in a physical register, return that PhysReg, otherwise 395 /// return 0. 396 unsigned getSpillSlotOrReMatPhysReg(int Slot) const { 397 std::map<int, unsigned>::const_iterator I = 398 SpillSlotsOrReMatsAvailable.find(Slot); 399 if (I != SpillSlotsOrReMatsAvailable.end()) { 400 return I->second >> 1; // Remove the CanClobber bit. 401 } 402 return 0; 403 } 404 405 /// addAvailable - Mark that the specified stack slot / remat is available in 406 /// the specified physreg. If CanClobber is true, the physreg can be modified 407 /// at any time without changing the semantics of the program. 408 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, 409 bool CanClobber = true) { 410 // If this stack slot is thought to be available in some other physreg, 411 // remove its record. 412 ModifyStackSlotOrReMat(SlotOrReMat); 413 414 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); 415 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; 416 417 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 418 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; 419 else 420 DOUT << "Remembering SS#" << SlotOrReMat; 421 DOUT << " in physreg " << TRI->getName(Reg) << "\n"; 422 } 423 424 /// canClobberPhysReg - Return true if the spiller is allowed to change the 425 /// value of the specified stackslot register if it desires. The specified 426 /// stack slot must be available in a physreg for this query to make sense. 427 bool canClobberPhysReg(int SlotOrReMat) const { 428 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && 429 "Value not available!"); 430 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; 431 } 432 433 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified 434 /// stackslot register. The register is still available but is no longer 435 /// allowed to be modifed. 436 void disallowClobberPhysReg(unsigned PhysReg); 437 438 /// ClobberPhysReg - This is called when the specified physreg changes 439 /// value. We use this to invalidate any info about stuff that lives in 440 /// it and any of its aliases. 441 void ClobberPhysReg(unsigned PhysReg); 442 443 /// ModifyStackSlotOrReMat - This method is called when the value in a stack 444 /// slot changes. This removes information about which register the previous 445 /// value for this slot lives in (as the previous value is dead now). 446 void ModifyStackSlotOrReMat(int SlotOrReMat); 447}; 448} 449 450/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified 451/// stackslot register. The register is still available but is no longer 452/// allowed to be modifed. 453void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { 454 std::multimap<unsigned, int>::iterator I = 455 PhysRegsAvailable.lower_bound(PhysReg); 456 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 457 int SlotOrReMat = I->second; 458 I++; 459 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 460 "Bidirectional map mismatch!"); 461 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; 462 DOUT << "PhysReg " << TRI->getName(PhysReg) 463 << " copied, it is available for use but can no longer be modified\n"; 464 } 465} 466 467/// disallowClobberPhysReg - Unset the CanClobber bit of the specified 468/// stackslot register and its aliases. The register and its aliases may 469/// still available but is no longer allowed to be modifed. 470void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { 471 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 472 disallowClobberPhysRegOnly(*AS); 473 disallowClobberPhysRegOnly(PhysReg); 474} 475 476/// ClobberPhysRegOnly - This is called when the specified physreg changes 477/// value. We use this to invalidate any info about stuff we thing lives in it. 478void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { 479 std::multimap<unsigned, int>::iterator I = 480 PhysRegsAvailable.lower_bound(PhysReg); 481 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 482 int SlotOrReMat = I->second; 483 PhysRegsAvailable.erase(I++); 484 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 485 "Bidirectional map mismatch!"); 486 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); 487 DOUT << "PhysReg " << TRI->getName(PhysReg) 488 << " clobbered, invalidating "; 489 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 490 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; 491 else 492 DOUT << "SS#" << SlotOrReMat << "\n"; 493 } 494} 495 496/// ClobberPhysReg - This is called when the specified physreg changes 497/// value. We use this to invalidate any info about stuff we thing lives in 498/// it and any of its aliases. 499void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { 500 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 501 ClobberPhysRegOnly(*AS); 502 ClobberPhysRegOnly(PhysReg); 503} 504 505/// ModifyStackSlotOrReMat - This method is called when the value in a stack 506/// slot changes. This removes information about which register the previous 507/// value for this slot lives in (as the previous value is dead now). 508void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { 509 std::map<int, unsigned>::iterator It = 510 SpillSlotsOrReMatsAvailable.find(SlotOrReMat); 511 if (It == SpillSlotsOrReMatsAvailable.end()) return; 512 unsigned Reg = It->second >> 1; 513 SpillSlotsOrReMatsAvailable.erase(It); 514 515 // This register may hold the value of multiple stack slots, only remove this 516 // stack slot from the set of values the register contains. 517 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); 518 for (; ; ++I) { 519 assert(I != PhysRegsAvailable.end() && I->first == Reg && 520 "Map inverse broken!"); 521 if (I->second == SlotOrReMat) break; 522 } 523 PhysRegsAvailable.erase(I); 524} 525 526 527 528/// InvalidateKills - MI is going to be deleted. If any of its operands are 529/// marked kill, then invalidate the information. 530static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, 531 std::vector<MachineOperand*> &KillOps, 532 SmallVector<unsigned, 2> *KillRegs = NULL) { 533 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 534 MachineOperand &MO = MI.getOperand(i); 535 if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) 536 continue; 537 unsigned Reg = MO.getReg(); 538 if (KillRegs) 539 KillRegs->push_back(Reg); 540 if (KillOps[Reg] == &MO) { 541 RegKills.reset(Reg); 542 KillOps[Reg] = NULL; 543 } 544 } 545} 546 547/// InvalidateKill - A MI that defines the specified register is being deleted, 548/// invalidate the register kill information. 549static void InvalidateKill(unsigned Reg, BitVector &RegKills, 550 std::vector<MachineOperand*> &KillOps) { 551 if (RegKills[Reg]) { 552 KillOps[Reg]->setIsKill(false); 553 KillOps[Reg] = NULL; 554 RegKills.reset(Reg); 555 } 556} 557 558/// InvalidateRegDef - If the def operand of the specified def MI is now dead 559/// (since it's spill instruction is removed), mark it isDead. Also checks if 560/// the def MI has other definition operands that are not dead. Returns it by 561/// reference. 562static bool InvalidateRegDef(MachineBasicBlock::iterator I, 563 MachineInstr &NewDef, unsigned Reg, 564 bool &HasLiveDef) { 565 // Due to remat, it's possible this reg isn't being reused. That is, 566 // the def of this reg (by prev MI) is now dead. 567 MachineInstr *DefMI = I; 568 MachineOperand *DefOp = NULL; 569 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { 570 MachineOperand &MO = DefMI->getOperand(i); 571 if (MO.isRegister() && MO.isDef()) { 572 if (MO.getReg() == Reg) 573 DefOp = &MO; 574 else if (!MO.isDead()) 575 HasLiveDef = true; 576 } 577 } 578 if (!DefOp) 579 return false; 580 581 bool FoundUse = false, Done = false; 582 MachineBasicBlock::iterator E = NewDef; 583 ++I; ++E; 584 for (; !Done && I != E; ++I) { 585 MachineInstr *NMI = I; 586 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { 587 MachineOperand &MO = NMI->getOperand(j); 588 if (!MO.isRegister() || MO.getReg() != Reg) 589 continue; 590 if (MO.isUse()) 591 FoundUse = true; 592 Done = true; // Stop after scanning all the operands of this MI. 593 } 594 } 595 if (!FoundUse) { 596 // Def is dead! 597 DefOp->setIsDead(); 598 return true; 599 } 600 return false; 601} 602 603/// UpdateKills - Track and update kill info. If a MI reads a register that is 604/// marked kill, then it must be due to register reuse. Transfer the kill info 605/// over. 606static void UpdateKills(MachineInstr &MI, BitVector &RegKills, 607 std::vector<MachineOperand*> &KillOps) { 608 const TargetInstrDesc &TID = MI.getDesc(); 609 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 610 MachineOperand &MO = MI.getOperand(i); 611 if (!MO.isRegister() || !MO.isUse()) 612 continue; 613 unsigned Reg = MO.getReg(); 614 if (Reg == 0) 615 continue; 616 617 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) { 618 // That can't be right. Register is killed but not re-defined and it's 619 // being reused. Let's fix that. 620 KillOps[Reg]->setIsKill(false); 621 KillOps[Reg] = NULL; 622 RegKills.reset(Reg); 623 if (i < TID.getNumOperands() && 624 TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 625 // Unless it's a two-address operand, this is the new kill. 626 MO.setIsKill(); 627 } 628 if (MO.isKill()) { 629 RegKills.set(Reg); 630 KillOps[Reg] = &MO; 631 } 632 } 633 634 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 635 const MachineOperand &MO = MI.getOperand(i); 636 if (!MO.isRegister() || !MO.isDef()) 637 continue; 638 unsigned Reg = MO.getReg(); 639 RegKills.reset(Reg); 640 KillOps[Reg] = NULL; 641 } 642} 643 644/// ReMaterialize - Re-materialize definition for Reg targetting DestReg. 645/// 646static void ReMaterialize(MachineBasicBlock &MBB, 647 MachineBasicBlock::iterator &MII, 648 unsigned DestReg, unsigned Reg, 649 const TargetInstrInfo *TII, 650 const TargetRegisterInfo *TRI, 651 VirtRegMap &VRM) { 652 TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg)); 653 MachineInstr *NewMI = prior(MII); 654 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { 655 MachineOperand &MO = NewMI->getOperand(i); 656 if (!MO.isRegister() || MO.getReg() == 0) 657 continue; 658 unsigned VirtReg = MO.getReg(); 659 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) 660 continue; 661 assert(MO.isUse()); 662 unsigned SubIdx = MO.getSubReg(); 663 unsigned Phys = VRM.getPhys(VirtReg); 664 assert(Phys); 665 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 666 MO.setReg(RReg); 667 } 668 ++NumReMats; 669} 670 671 672// ReusedOp - For each reused operand, we keep track of a bit of information, in 673// case we need to rollback upon processing a new operand. See comments below. 674namespace { 675 struct ReusedOp { 676 // The MachineInstr operand that reused an available value. 677 unsigned Operand; 678 679 // StackSlotOrReMat - The spill slot or remat id of the value being reused. 680 unsigned StackSlotOrReMat; 681 682 // PhysRegReused - The physical register the value was available in. 683 unsigned PhysRegReused; 684 685 // AssignedPhysReg - The physreg that was assigned for use by the reload. 686 unsigned AssignedPhysReg; 687 688 // VirtReg - The virtual register itself. 689 unsigned VirtReg; 690 691 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, 692 unsigned vreg) 693 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), 694 AssignedPhysReg(apr), VirtReg(vreg) {} 695 }; 696 697 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that 698 /// is reused instead of reloaded. 699 class VISIBILITY_HIDDEN ReuseInfo { 700 MachineInstr &MI; 701 std::vector<ReusedOp> Reuses; 702 BitVector PhysRegsClobbered; 703 public: 704 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { 705 PhysRegsClobbered.resize(tri->getNumRegs()); 706 } 707 708 bool hasReuses() const { 709 return !Reuses.empty(); 710 } 711 712 /// addReuse - If we choose to reuse a virtual register that is already 713 /// available instead of reloading it, remember that we did so. 714 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, 715 unsigned PhysRegReused, unsigned AssignedPhysReg, 716 unsigned VirtReg) { 717 // If the reload is to the assigned register anyway, no undo will be 718 // required. 719 if (PhysRegReused == AssignedPhysReg) return; 720 721 // Otherwise, remember this. 722 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, 723 AssignedPhysReg, VirtReg)); 724 } 725 726 void markClobbered(unsigned PhysReg) { 727 PhysRegsClobbered.set(PhysReg); 728 } 729 730 bool isClobbered(unsigned PhysReg) const { 731 return PhysRegsClobbered.test(PhysReg); 732 } 733 734 /// GetRegForReload - We are about to emit a reload into PhysReg. If there 735 /// is some other operand that is using the specified register, either pick 736 /// a new register to use, or evict the previous reload and use this reg. 737 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 738 AvailableSpills &Spills, 739 std::vector<MachineInstr*> &MaybeDeadStores, 740 SmallSet<unsigned, 8> &Rejected, 741 BitVector &RegKills, 742 std::vector<MachineOperand*> &KillOps, 743 VirtRegMap &VRM) { 744 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget() 745 .getInstrInfo(); 746 747 if (Reuses.empty()) return PhysReg; // This is most often empty. 748 749 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { 750 ReusedOp &Op = Reuses[ro]; 751 // If we find some other reuse that was supposed to use this register 752 // exactly for its reload, we can change this reload to use ITS reload 753 // register. That is, unless its reload register has already been 754 // considered and subsequently rejected because it has also been reused 755 // by another operand. 756 if (Op.PhysRegReused == PhysReg && 757 Rejected.count(Op.AssignedPhysReg) == 0) { 758 // Yup, use the reload register that we didn't use before. 759 unsigned NewReg = Op.AssignedPhysReg; 760 Rejected.insert(PhysReg); 761 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, 762 RegKills, KillOps, VRM); 763 } else { 764 // Otherwise, we might also have a problem if a previously reused 765 // value aliases the new register. If so, codegen the previous reload 766 // and use this one. 767 unsigned PRRU = Op.PhysRegReused; 768 const TargetRegisterInfo *TRI = Spills.getRegInfo(); 769 if (TRI->areAliases(PRRU, PhysReg)) { 770 // Okay, we found out that an alias of a reused register 771 // was used. This isn't good because it means we have 772 // to undo a previous reuse. 773 MachineBasicBlock *MBB = MI->getParent(); 774 const TargetRegisterClass *AliasRC = 775 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); 776 777 // Copy Op out of the vector and remove it, we're going to insert an 778 // explicit load for it. 779 ReusedOp NewOp = Op; 780 Reuses.erase(Reuses.begin()+ro); 781 782 // Ok, we're going to try to reload the assigned physreg into the 783 // slot that we were supposed to in the first place. However, that 784 // register could hold a reuse. Check to see if it conflicts or 785 // would prefer us to use a different register. 786 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, 787 MI, Spills, MaybeDeadStores, 788 Rejected, RegKills, KillOps, VRM); 789 790 MachineBasicBlock::iterator MII = MI; 791 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { 792 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM); 793 } else { 794 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg, 795 NewOp.StackSlotOrReMat, AliasRC); 796 MachineInstr *LoadMI = prior(MII); 797 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI); 798 // Any stores to this stack slot are not dead anymore. 799 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; 800 ++NumLoads; 801 } 802 Spills.ClobberPhysReg(NewPhysReg); 803 Spills.ClobberPhysReg(NewOp.PhysRegReused); 804 805 MI->getOperand(NewOp.Operand).setReg(NewPhysReg); 806 807 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); 808 --MII; 809 UpdateKills(*MII, RegKills, KillOps); 810 DOUT << '\t' << *MII; 811 812 DOUT << "Reuse undone!\n"; 813 --NumReused; 814 815 // Finally, PhysReg is now available, go ahead and use it. 816 return PhysReg; 817 } 818 } 819 } 820 return PhysReg; 821 } 822 823 /// GetRegForReload - Helper for the above GetRegForReload(). Add a 824 /// 'Rejected' set to remember which registers have been considered and 825 /// rejected for the reload. This avoids infinite looping in case like 826 /// this: 827 /// t1 := op t2, t3 828 /// t2 <- assigned r0 for use by the reload but ended up reuse r1 829 /// t3 <- assigned r1 for use by the reload but ended up reuse r0 830 /// t1 <- desires r1 831 /// sees r1 is taken by t2, tries t2's reload register r0 832 /// sees r0 is taken by t3, tries t3's reload register r1 833 /// sees r1 is taken by t2, tries t2's reload register r0 ... 834 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 835 AvailableSpills &Spills, 836 std::vector<MachineInstr*> &MaybeDeadStores, 837 BitVector &RegKills, 838 std::vector<MachineOperand*> &KillOps, 839 VirtRegMap &VRM) { 840 SmallSet<unsigned, 8> Rejected; 841 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, 842 RegKills, KillOps, VRM); 843 } 844 }; 845} 846 847/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding 848/// instruction. e.g. 849/// xorl %edi, %eax 850/// movl %eax, -32(%ebp) 851/// movl -36(%ebp), %eax 852/// orl %eax, -32(%ebp) 853/// ==> 854/// xorl %edi, %eax 855/// orl -36(%ebp), %eax 856/// mov %eax, -32(%ebp) 857/// This enables unfolding optimization for a subsequent instruction which will 858/// also eliminate the newly introduced store instruction. 859bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, 860 MachineBasicBlock::iterator &MII, 861 std::vector<MachineInstr*> &MaybeDeadStores, 862 AvailableSpills &Spills, 863 BitVector &RegKills, 864 std::vector<MachineOperand*> &KillOps, 865 VirtRegMap &VRM) { 866 MachineFunction &MF = *MBB.getParent(); 867 MachineInstr &MI = *MII; 868 unsigned UnfoldedOpc = 0; 869 unsigned UnfoldPR = 0; 870 unsigned UnfoldVR = 0; 871 int FoldedSS = VirtRegMap::NO_STACK_SLOT; 872 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 873 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 874 // Only transform a MI that folds a single register. 875 if (UnfoldedOpc) 876 return false; 877 UnfoldVR = I->second.first; 878 VirtRegMap::ModRef MR = I->second.second; 879 // MI2VirtMap be can updated which invalidate the iterator. 880 // Increment the iterator first. 881 ++I; 882 if (VRM.isAssignedReg(UnfoldVR)) 883 continue; 884 // If this reference is not a use, any previous store is now dead. 885 // Otherwise, the store to this stack slot is not dead anymore. 886 FoldedSS = VRM.getStackSlot(UnfoldVR); 887 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; 888 if (DeadStore && (MR & VirtRegMap::isModRef)) { 889 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); 890 if (!PhysReg || !DeadStore->readsRegister(PhysReg)) 891 continue; 892 UnfoldPR = PhysReg; 893 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 894 false, true); 895 } 896 } 897 898 if (!UnfoldedOpc) 899 return false; 900 901 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 902 MachineOperand &MO = MI.getOperand(i); 903 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) 904 continue; 905 unsigned VirtReg = MO.getReg(); 906 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) 907 continue; 908 if (VRM.isAssignedReg(VirtReg)) { 909 unsigned PhysReg = VRM.getPhys(VirtReg); 910 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) 911 return false; 912 } else if (VRM.isReMaterialized(VirtReg)) 913 continue; 914 int SS = VRM.getStackSlot(VirtReg); 915 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 916 if (PhysReg) { 917 if (TRI->regsOverlap(PhysReg, UnfoldPR)) 918 return false; 919 continue; 920 } 921 PhysReg = VRM.getPhys(VirtReg); 922 if (!TRI->regsOverlap(PhysReg, UnfoldPR)) 923 continue; 924 925 // Ok, we'll need to reload the value into a register which makes 926 // it impossible to perform the store unfolding optimization later. 927 // Let's see if it is possible to fold the load if the store is 928 // unfolded. This allows us to perform the store unfolding 929 // optimization. 930 SmallVector<MachineInstr*, 4> NewMIs; 931 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { 932 assert(NewMIs.size() == 1); 933 MachineInstr *NewMI = NewMIs.back(); 934 NewMIs.clear(); 935 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); 936 assert(Idx != -1); 937 SmallVector<unsigned, 2> Ops; 938 Ops.push_back(Idx); 939 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); 940 if (FoldedMI) { 941 VRM.addSpillSlotUse(SS, FoldedMI); 942 if (!VRM.hasPhys(UnfoldVR)) 943 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); 944 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 945 MII = MBB.insert(MII, FoldedMI); 946 VRM.RemoveMachineInstrFromMaps(&MI); 947 MBB.erase(&MI); 948 return true; 949 } 950 delete NewMI; 951 } 952 } 953 return false; 954} 955 956/// findSuperReg - Find the SubReg's super-register of given register class 957/// where its SubIdx sub-register is SubReg. 958static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, 959 unsigned SubIdx, const TargetRegisterInfo *TRI) { 960 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 961 I != E; ++I) { 962 unsigned Reg = *I; 963 if (TRI->getSubReg(Reg, SubIdx) == SubReg) 964 return Reg; 965 } 966 return 0; 967} 968 969/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if 970/// the last store to the same slot is now dead. If so, remove the last store. 971void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, 972 MachineBasicBlock::iterator &MII, 973 int Idx, unsigned PhysReg, int StackSlot, 974 const TargetRegisterClass *RC, 975 bool isAvailable, MachineInstr *&LastStore, 976 AvailableSpills &Spills, 977 SmallSet<MachineInstr*, 4> &ReMatDefs, 978 BitVector &RegKills, 979 std::vector<MachineOperand*> &KillOps, 980 VirtRegMap &VRM) { 981 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); 982 MachineInstr *StoreMI = next(MII); 983 VRM.addSpillSlotUse(StackSlot, StoreMI); 984 DOUT << "Store:\t" << *StoreMI; 985 986 // If there is a dead store to this stack slot, nuke it now. 987 if (LastStore) { 988 DOUT << "Removed dead store:\t" << *LastStore; 989 ++NumDSE; 990 SmallVector<unsigned, 2> KillRegs; 991 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); 992 MachineBasicBlock::iterator PrevMII = LastStore; 993 bool CheckDef = PrevMII != MBB.begin(); 994 if (CheckDef) 995 --PrevMII; 996 VRM.RemoveMachineInstrFromMaps(LastStore); 997 MBB.erase(LastStore); 998 if (CheckDef) { 999 // Look at defs of killed registers on the store. Mark the defs 1000 // as dead since the store has been deleted and they aren't 1001 // being reused. 1002 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { 1003 bool HasOtherDef = false; 1004 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) { 1005 MachineInstr *DeadDef = PrevMII; 1006 if (ReMatDefs.count(DeadDef) && !HasOtherDef) { 1007 // FIXME: This assumes a remat def does not have side 1008 // effects. 1009 VRM.RemoveMachineInstrFromMaps(DeadDef); 1010 MBB.erase(DeadDef); 1011 ++NumDRM; 1012 } 1013 } 1014 } 1015 } 1016 } 1017 1018 LastStore = next(MII); 1019 1020 // If the stack slot value was previously available in some other 1021 // register, change it now. Otherwise, make the register available, 1022 // in PhysReg. 1023 Spills.ModifyStackSlotOrReMat(StackSlot); 1024 Spills.ClobberPhysReg(PhysReg); 1025 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable); 1026 ++NumStores; 1027} 1028 1029/// rewriteMBB - Keep track of which spills are available even after the 1030/// register allocator is done with them. If possible, avid reloading vregs. 1031void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { 1032 DOUT << MBB.getBasicBlock()->getName() << ":\n"; 1033 1034 MachineFunction &MF = *MBB.getParent(); 1035 1036 // Spills - Keep track of which spilled values are available in physregs so 1037 // that we can choose to reuse the physregs instead of emitting reloads. 1038 AvailableSpills Spills(TRI, TII); 1039 1040 // MaybeDeadStores - When we need to write a value back into a stack slot, 1041 // keep track of the inserted store. If the stack slot value is never read 1042 // (because the value was used from some available register, for example), and 1043 // subsequently stored to, the original store is dead. This map keeps track 1044 // of inserted stores that are not used. If we see a subsequent store to the 1045 // same stack slot, the original store is deleted. 1046 std::vector<MachineInstr*> MaybeDeadStores; 1047 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); 1048 1049 // ReMatDefs - These are rematerializable def MIs which are not deleted. 1050 SmallSet<MachineInstr*, 4> ReMatDefs; 1051 1052 // Keep track of kill information. 1053 BitVector RegKills(TRI->getNumRegs()); 1054 std::vector<MachineOperand*> KillOps; 1055 KillOps.resize(TRI->getNumRegs(), NULL); 1056 1057 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 1058 MII != E; ) { 1059 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 1060 1061 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 1062 bool Erased = false; 1063 bool BackTracked = false; 1064 if (PrepForUnfoldOpti(MBB, MII, 1065 MaybeDeadStores, Spills, RegKills, KillOps, VRM)) 1066 NextMII = next(MII); 1067 1068 MachineInstr &MI = *MII; 1069 const TargetInstrDesc &TID = MI.getDesc(); 1070 1071 if (VRM.hasEmergencySpills(&MI)) { 1072 // Spill physical register(s) in the rare case the allocator has run out 1073 // of registers to allocate. 1074 SmallSet<int, 4> UsedSS; 1075 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI); 1076 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) { 1077 unsigned PhysReg = EmSpills[i]; 1078 const TargetRegisterClass *RC = 1079 TRI->getPhysicalRegisterRegClass(PhysReg); 1080 assert(RC && "Unable to determine register class!"); 1081 int SS = VRM.getEmergencySpillSlot(RC); 1082 if (UsedSS.count(SS)) 1083 assert(0 && "Need to spill more than one physical registers!"); 1084 UsedSS.insert(SS); 1085 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); 1086 MachineInstr *StoreMI = prior(MII); 1087 VRM.addSpillSlotUse(SS, StoreMI); 1088 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC); 1089 MachineInstr *LoadMI = next(MII); 1090 VRM.addSpillSlotUse(SS, LoadMI); 1091 ++NumPSpills; 1092 } 1093 NextMII = next(MII); 1094 } 1095 1096 // Insert restores here if asked to. 1097 if (VRM.isRestorePt(&MI)) { 1098 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI); 1099 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { 1100 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order. 1101 if (!VRM.getPreSplitReg(VirtReg)) 1102 continue; // Split interval spilled again. 1103 unsigned Phys = VRM.getPhys(VirtReg); 1104 RegInfo->setPhysRegUsed(Phys); 1105 if (VRM.isReMaterialized(VirtReg)) { 1106 ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM); 1107 } else { 1108 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1109 int SS = VRM.getStackSlot(VirtReg); 1110 TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC); 1111 MachineInstr *LoadMI = prior(MII); 1112 VRM.addSpillSlotUse(SS, LoadMI); 1113 ++NumLoads; 1114 } 1115 // This invalidates Phys. 1116 Spills.ClobberPhysReg(Phys); 1117 UpdateKills(*prior(MII), RegKills, KillOps); 1118 DOUT << '\t' << *prior(MII); 1119 } 1120 } 1121 1122 // Insert spills here if asked to. 1123 if (VRM.isSpillPt(&MI)) { 1124 std::vector<std::pair<unsigned,bool> > &SpillRegs = 1125 VRM.getSpillPtSpills(&MI); 1126 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { 1127 unsigned VirtReg = SpillRegs[i].first; 1128 bool isKill = SpillRegs[i].second; 1129 if (!VRM.getPreSplitReg(VirtReg)) 1130 continue; // Split interval spilled again. 1131 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1132 unsigned Phys = VRM.getPhys(VirtReg); 1133 int StackSlot = VRM.getStackSlot(VirtReg); 1134 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); 1135 MachineInstr *StoreMI = next(MII); 1136 VRM.addSpillSlotUse(StackSlot, StoreMI); 1137 DOUT << "Store:\t" << *StoreMI; 1138 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1139 } 1140 NextMII = next(MII); 1141 } 1142 1143 /// ReusedOperands - Keep track of operand reuse in case we need to undo 1144 /// reuse. 1145 ReuseInfo ReusedOperands(MI, TRI); 1146 SmallVector<unsigned, 4> VirtUseOps; 1147 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1148 MachineOperand &MO = MI.getOperand(i); 1149 if (!MO.isRegister() || MO.getReg() == 0) 1150 continue; // Ignore non-register operands. 1151 1152 unsigned VirtReg = MO.getReg(); 1153 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { 1154 // Ignore physregs for spilling, but remember that it is used by this 1155 // function. 1156 RegInfo->setPhysRegUsed(VirtReg); 1157 continue; 1158 } 1159 1160 // We want to process implicit virtual register uses first. 1161 if (MO.isImplicit()) 1162 // If the virtual register is implicitly defined, emit a implicit_def 1163 // before so scavenger knows it's "defined". 1164 VirtUseOps.insert(VirtUseOps.begin(), i); 1165 else 1166 VirtUseOps.push_back(i); 1167 } 1168 1169 // Process all of the spilled uses and all non spilled reg references. 1170 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) { 1171 unsigned i = VirtUseOps[j]; 1172 MachineOperand &MO = MI.getOperand(i); 1173 unsigned VirtReg = MO.getReg(); 1174 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 1175 "Not a virtual register?"); 1176 1177 unsigned SubIdx = MO.getSubReg(); 1178 if (VRM.isAssignedReg(VirtReg)) { 1179 // This virtual register was assigned a physreg! 1180 unsigned Phys = VRM.getPhys(VirtReg); 1181 RegInfo->setPhysRegUsed(Phys); 1182 if (MO.isDef()) 1183 ReusedOperands.markClobbered(Phys); 1184 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 1185 MI.getOperand(i).setReg(RReg); 1186 if (VRM.isImplicitlyDefined(VirtReg)) 1187 BuildMI(MBB, MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg); 1188 continue; 1189 } 1190 1191 // This virtual register is now known to be a spilled value. 1192 if (!MO.isUse()) 1193 continue; // Handle defs in the loop below (handle use&def here though) 1194 1195 bool DoReMat = VRM.isReMaterialized(VirtReg); 1196 int SSorRMId = DoReMat 1197 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); 1198 int ReuseSlot = SSorRMId; 1199 1200 // Check to see if this stack slot is available. 1201 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); 1202 1203 // If this is a sub-register use, make sure the reuse register is in the 1204 // right register class. For example, for x86 not all of the 32-bit 1205 // registers have accessible sub-registers. 1206 // Similarly so for EXTRACT_SUBREG. Consider this: 1207 // EDI = op 1208 // MOV32_mr fi#1, EDI 1209 // ... 1210 // = EXTRACT_SUBREG fi#1 1211 // fi#1 is available in EDI, but it cannot be reused because it's not in 1212 // the right register file. 1213 if (PhysReg && 1214 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { 1215 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1216 if (!RC->contains(PhysReg)) 1217 PhysReg = 0; 1218 } 1219 1220 if (PhysReg) { 1221 // This spilled operand might be part of a two-address operand. If this 1222 // is the case, then changing it will necessarily require changing the 1223 // def part of the instruction as well. However, in some cases, we 1224 // aren't allowed to modify the reused register. If none of these cases 1225 // apply, reuse it. 1226 bool CanReuse = true; 1227 int ti = TID.getOperandConstraint(i, TOI::TIED_TO); 1228 if (ti != -1 && 1229 MI.getOperand(ti).isRegister() && 1230 MI.getOperand(ti).getReg() == VirtReg) { 1231 // Okay, we have a two address operand. We can reuse this physreg as 1232 // long as we are allowed to clobber the value and there isn't an 1233 // earlier def that has already clobbered the physreg. 1234 CanReuse = Spills.canClobberPhysReg(ReuseSlot) && 1235 !ReusedOperands.isClobbered(PhysReg); 1236 } 1237 1238 if (CanReuse) { 1239 // If this stack slot value is already available, reuse it! 1240 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1241 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1242 else 1243 DOUT << "Reusing SS#" << ReuseSlot; 1244 DOUT << " from physreg " 1245 << TRI->getName(PhysReg) << " for vreg" 1246 << VirtReg <<" instead of reloading into physreg " 1247 << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; 1248 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1249 MI.getOperand(i).setReg(RReg); 1250 1251 // The only technical detail we have is that we don't know that 1252 // PhysReg won't be clobbered by a reloaded stack slot that occurs 1253 // later in the instruction. In particular, consider 'op V1, V2'. 1254 // If V1 is available in physreg R0, we would choose to reuse it 1255 // here, instead of reloading it into the register the allocator 1256 // indicated (say R1). However, V2 might have to be reloaded 1257 // later, and it might indicate that it needs to live in R0. When 1258 // this occurs, we need to have information available that 1259 // indicates it is safe to use R1 for the reload instead of R0. 1260 // 1261 // To further complicate matters, we might conflict with an alias, 1262 // or R0 and R1 might not be compatible with each other. In this 1263 // case, we actually insert a reload for V1 in R1, ensuring that 1264 // we can get at R0 or its alias. 1265 ReusedOperands.addReuse(i, ReuseSlot, PhysReg, 1266 VRM.getPhys(VirtReg), VirtReg); 1267 if (ti != -1) 1268 // Only mark it clobbered if this is a use&def operand. 1269 ReusedOperands.markClobbered(PhysReg); 1270 ++NumReused; 1271 1272 if (MI.getOperand(i).isKill() && 1273 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { 1274 // This was the last use and the spilled value is still available 1275 // for reuse. That means the spill was unnecessary! 1276 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; 1277 if (DeadStore) { 1278 DOUT << "Removed dead store:\t" << *DeadStore; 1279 InvalidateKills(*DeadStore, RegKills, KillOps); 1280 VRM.RemoveMachineInstrFromMaps(DeadStore); 1281 MBB.erase(DeadStore); 1282 MaybeDeadStores[ReuseSlot] = NULL; 1283 ++NumDSE; 1284 } 1285 } 1286 continue; 1287 } // CanReuse 1288 1289 // Otherwise we have a situation where we have a two-address instruction 1290 // whose mod/ref operand needs to be reloaded. This reload is already 1291 // available in some register "PhysReg", but if we used PhysReg as the 1292 // operand to our 2-addr instruction, the instruction would modify 1293 // PhysReg. This isn't cool if something later uses PhysReg and expects 1294 // to get its initial value. 1295 // 1296 // To avoid this problem, and to avoid doing a load right after a store, 1297 // we emit a copy from PhysReg into the designated register for this 1298 // operand. 1299 unsigned DesignatedReg = VRM.getPhys(VirtReg); 1300 assert(DesignatedReg && "Must map virtreg to physreg!"); 1301 1302 // Note that, if we reused a register for a previous operand, the 1303 // register we want to reload into might not actually be 1304 // available. If this occurs, use the register indicated by the 1305 // reuser. 1306 if (ReusedOperands.hasReuses()) 1307 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, 1308 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1309 1310 // If the mapped designated register is actually the physreg we have 1311 // incoming, we don't need to inserted a dead copy. 1312 if (DesignatedReg == PhysReg) { 1313 // If this stack slot value is already available, reuse it! 1314 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1315 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1316 else 1317 DOUT << "Reusing SS#" << ReuseSlot; 1318 DOUT << " from physreg " << TRI->getName(PhysReg) 1319 << " for vreg" << VirtReg 1320 << " instead of reloading into same physreg.\n"; 1321 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1322 MI.getOperand(i).setReg(RReg); 1323 ReusedOperands.markClobbered(RReg); 1324 ++NumReused; 1325 continue; 1326 } 1327 1328 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1329 RegInfo->setPhysRegUsed(DesignatedReg); 1330 ReusedOperands.markClobbered(DesignatedReg); 1331 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); 1332 1333 MachineInstr *CopyMI = prior(MII); 1334 UpdateKills(*CopyMI, RegKills, KillOps); 1335 1336 // This invalidates DesignatedReg. 1337 Spills.ClobberPhysReg(DesignatedReg); 1338 1339 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); 1340 unsigned RReg = 1341 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; 1342 MI.getOperand(i).setReg(RReg); 1343 DOUT << '\t' << *prior(MII); 1344 ++NumReused; 1345 continue; 1346 } // if (PhysReg) 1347 1348 // Otherwise, reload it and remember that we have it. 1349 PhysReg = VRM.getPhys(VirtReg); 1350 assert(PhysReg && "Must map virtreg to physreg!"); 1351 1352 // Note that, if we reused a register for a previous operand, the 1353 // register we want to reload into might not actually be 1354 // available. If this occurs, use the register indicated by the 1355 // reuser. 1356 if (ReusedOperands.hasReuses()) 1357 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1358 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1359 1360 RegInfo->setPhysRegUsed(PhysReg); 1361 ReusedOperands.markClobbered(PhysReg); 1362 if (DoReMat) { 1363 ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM); 1364 } else { 1365 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1366 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); 1367 MachineInstr *LoadMI = prior(MII); 1368 VRM.addSpillSlotUse(SSorRMId, LoadMI); 1369 ++NumLoads; 1370 } 1371 // This invalidates PhysReg. 1372 Spills.ClobberPhysReg(PhysReg); 1373 1374 // Any stores to this stack slot are not dead anymore. 1375 if (!DoReMat) 1376 MaybeDeadStores[SSorRMId] = NULL; 1377 Spills.addAvailable(SSorRMId, &MI, PhysReg); 1378 // Assumes this is the last use. IsKill will be unset if reg is reused 1379 // unless it's a two-address operand. 1380 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 1381 MI.getOperand(i).setIsKill(); 1382 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1383 MI.getOperand(i).setReg(RReg); 1384 UpdateKills(*prior(MII), RegKills, KillOps); 1385 DOUT << '\t' << *prior(MII); 1386 } 1387 1388 DOUT << '\t' << MI; 1389 1390 1391 // If we have folded references to memory operands, make sure we clear all 1392 // physical registers that may contain the value of the spilled virtual 1393 // register 1394 SmallSet<int, 2> FoldedSS; 1395 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 1396 unsigned VirtReg = I->second.first; 1397 VirtRegMap::ModRef MR = I->second.second; 1398 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; 1399 1400 // MI2VirtMap be can updated which invalidate the iterator. 1401 // Increment the iterator first. 1402 ++I; 1403 int SS = VRM.getStackSlot(VirtReg); 1404 if (SS == VirtRegMap::NO_STACK_SLOT) 1405 continue; 1406 FoldedSS.insert(SS); 1407 DOUT << " - StackSlot: " << SS << "\n"; 1408 1409 // If this folded instruction is just a use, check to see if it's a 1410 // straight load from the virt reg slot. 1411 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { 1412 int FrameIdx; 1413 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); 1414 if (DestReg && FrameIdx == SS) { 1415 // If this spill slot is available, turn it into a copy (or nothing) 1416 // instead of leaving it as a load! 1417 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { 1418 DOUT << "Promoted Load To Copy: " << MI; 1419 if (DestReg != InReg) { 1420 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1421 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); 1422 // Revisit the copy so we make sure to notice the effects of the 1423 // operation on the destreg (either needing to RA it if it's 1424 // virtual or needing to clobber any values if it's physical). 1425 NextMII = &MI; 1426 --NextMII; // backtrack to the copy. 1427 BackTracked = true; 1428 } else { 1429 DOUT << "Removing now-noop copy: " << MI; 1430 // Unset last kill since it's being reused. 1431 InvalidateKill(InReg, RegKills, KillOps); 1432 } 1433 1434 VRM.RemoveMachineInstrFromMaps(&MI); 1435 MBB.erase(&MI); 1436 Erased = true; 1437 goto ProcessNextInst; 1438 } 1439 } else { 1440 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1441 SmallVector<MachineInstr*, 4> NewMIs; 1442 if (PhysReg && 1443 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { 1444 MBB.insert(MII, NewMIs[0]); 1445 VRM.RemoveMachineInstrFromMaps(&MI); 1446 MBB.erase(&MI); 1447 Erased = true; 1448 --NextMII; // backtrack to the unfolded instruction. 1449 BackTracked = true; 1450 goto ProcessNextInst; 1451 } 1452 } 1453 } 1454 1455 // If this reference is not a use, any previous store is now dead. 1456 // Otherwise, the store to this stack slot is not dead anymore. 1457 MachineInstr* DeadStore = MaybeDeadStores[SS]; 1458 if (DeadStore) { 1459 bool isDead = !(MR & VirtRegMap::isRef); 1460 MachineInstr *NewStore = NULL; 1461 if (MR & VirtRegMap::isModRef) { 1462 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1463 SmallVector<MachineInstr*, 4> NewMIs; 1464 // We can reuse this physreg as long as we are allowed to clobber 1465 // the value and there isn't an earlier def that has already clobbered 1466 // the physreg. 1467 if (PhysReg && 1468 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable! 1469 MachineOperand *KillOpnd = 1470 DeadStore->findRegisterUseOperand(PhysReg, true); 1471 // Note, if the store is storing a sub-register, it's possible the 1472 // super-register is needed below. 1473 if (KillOpnd && !KillOpnd->getSubReg() && 1474 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){ 1475 MBB.insert(MII, NewMIs[0]); 1476 NewStore = NewMIs[1]; 1477 MBB.insert(MII, NewStore); 1478 VRM.addSpillSlotUse(SS, NewStore); 1479 VRM.RemoveMachineInstrFromMaps(&MI); 1480 MBB.erase(&MI); 1481 Erased = true; 1482 --NextMII; 1483 --NextMII; // backtrack to the unfolded instruction. 1484 BackTracked = true; 1485 isDead = true; 1486 } 1487 } 1488 } 1489 1490 if (isDead) { // Previous store is dead. 1491 // If we get here, the store is dead, nuke it now. 1492 DOUT << "Removed dead store:\t" << *DeadStore; 1493 InvalidateKills(*DeadStore, RegKills, KillOps); 1494 VRM.RemoveMachineInstrFromMaps(DeadStore); 1495 MBB.erase(DeadStore); 1496 if (!NewStore) 1497 ++NumDSE; 1498 } 1499 1500 MaybeDeadStores[SS] = NULL; 1501 if (NewStore) { 1502 // Treat this store as a spill merged into a copy. That makes the 1503 // stack slot value available. 1504 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod); 1505 goto ProcessNextInst; 1506 } 1507 } 1508 1509 // If the spill slot value is available, and this is a new definition of 1510 // the value, the value is not available anymore. 1511 if (MR & VirtRegMap::isMod) { 1512 // Notice that the value in this stack slot has been modified. 1513 Spills.ModifyStackSlotOrReMat(SS); 1514 1515 // If this is *just* a mod of the value, check to see if this is just a 1516 // store to the spill slot (i.e. the spill got merged into the copy). If 1517 // so, realize that the vreg is available now, and add the store to the 1518 // MaybeDeadStore info. 1519 int StackSlot; 1520 if (!(MR & VirtRegMap::isRef)) { 1521 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { 1522 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && 1523 "Src hasn't been allocated yet?"); 1524 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark 1525 // this as a potentially dead store in case there is a subsequent 1526 // store into the stack slot without a read from it. 1527 MaybeDeadStores[StackSlot] = &MI; 1528 1529 // If the stack slot value was previously available in some other 1530 // register, change it now. Otherwise, make the register available, 1531 // in PhysReg. 1532 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); 1533 } 1534 } 1535 } 1536 } 1537 1538 // Process all of the spilled defs. 1539 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1540 MachineOperand &MO = MI.getOperand(i); 1541 if (!(MO.isRegister() && MO.getReg() && MO.isDef())) 1542 continue; 1543 1544 unsigned VirtReg = MO.getReg(); 1545 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { 1546 // Check to see if this is a noop copy. If so, eliminate the 1547 // instruction before considering the dest reg to be changed. 1548 unsigned Src, Dst; 1549 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1550 ++NumDCE; 1551 DOUT << "Removing now-noop copy: " << MI; 1552 VRM.RemoveMachineInstrFromMaps(&MI); 1553 MBB.erase(&MI); 1554 Erased = true; 1555 Spills.disallowClobberPhysReg(VirtReg); 1556 goto ProcessNextInst; 1557 } 1558 1559 // If it's not a no-op copy, it clobbers the value in the destreg. 1560 Spills.ClobberPhysReg(VirtReg); 1561 ReusedOperands.markClobbered(VirtReg); 1562 1563 // Check to see if this instruction is a load from a stack slot into 1564 // a register. If so, this provides the stack slot value in the reg. 1565 int FrameIdx; 1566 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { 1567 assert(DestReg == VirtReg && "Unknown load situation!"); 1568 1569 // If it is a folded reference, then it's not safe to clobber. 1570 bool Folded = FoldedSS.count(FrameIdx); 1571 // Otherwise, if it wasn't available, remember that it is now! 1572 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); 1573 goto ProcessNextInst; 1574 } 1575 1576 continue; 1577 } 1578 1579 unsigned SubIdx = MO.getSubReg(); 1580 bool DoReMat = VRM.isReMaterialized(VirtReg); 1581 if (DoReMat) 1582 ReMatDefs.insert(&MI); 1583 1584 // The only vregs left are stack slot definitions. 1585 int StackSlot = VRM.getStackSlot(VirtReg); 1586 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1587 1588 // If this def is part of a two-address operand, make sure to execute 1589 // the store from the correct physical register. 1590 unsigned PhysReg; 1591 int TiedOp = MI.getDesc().findTiedToSrcOperand(i); 1592 if (TiedOp != -1) { 1593 PhysReg = MI.getOperand(TiedOp).getReg(); 1594 if (SubIdx) { 1595 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); 1596 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && 1597 "Can't find corresponding super-register!"); 1598 PhysReg = SuperReg; 1599 } 1600 } else { 1601 PhysReg = VRM.getPhys(VirtReg); 1602 if (ReusedOperands.isClobbered(PhysReg)) { 1603 // Another def has taken the assigned physreg. It must have been a 1604 // use&def which got it due to reuse. Undo the reuse! 1605 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1606 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1607 } 1608 } 1609 1610 assert(PhysReg && "VR not assigned a physical register?"); 1611 RegInfo->setPhysRegUsed(PhysReg); 1612 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1613 ReusedOperands.markClobbered(RReg); 1614 MI.getOperand(i).setReg(RReg); 1615 1616 if (!MO.isDead()) { 1617 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 1618 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true, 1619 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); 1620 NextMII = next(MII); 1621 1622 // Check to see if this is a noop copy. If so, eliminate the 1623 // instruction before considering the dest reg to be changed. 1624 { 1625 unsigned Src, Dst; 1626 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1627 ++NumDCE; 1628 DOUT << "Removing now-noop copy: " << MI; 1629 VRM.RemoveMachineInstrFromMaps(&MI); 1630 MBB.erase(&MI); 1631 Erased = true; 1632 UpdateKills(*LastStore, RegKills, KillOps); 1633 goto ProcessNextInst; 1634 } 1635 } 1636 } 1637 } 1638 ProcessNextInst: 1639 if (!Erased && !BackTracked) { 1640 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II) 1641 UpdateKills(*II, RegKills, KillOps); 1642 } 1643 MII = NextMII; 1644 } 1645} 1646 1647llvm::Spiller* llvm::createSpiller() { 1648 switch (SpillerOpt) { 1649 default: assert(0 && "Unreachable!"); 1650 case local: 1651 return new LocalSpiller(); 1652 case simple: 1653 return new SimpleSpiller(); 1654 } 1655} 1656