ARMBaseRegisterInfo.cpp revision 391f228e7e00f62b79ad483b801f5f58f046b7ea 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43static cl::opt<bool>
44ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
45          cl::desc("Force use of virtual base registers for stack load/store"));
46static cl::opt<bool>
47EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
48          cl::desc("Enable pre-regalloc stack frame index allocation"));
49}
50
51using namespace llvm;
52
53static cl::opt<bool>
54EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57
58ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
59                                         const ARMSubtarget &sti)
60  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
61    TII(tii), STI(sti),
62    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
63    BasePtr(ARM::R6) {
64}
65
66const unsigned*
67ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68  static const unsigned CalleeSavedRegs[] = {
69    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
70    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
71
72    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
73    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
74    0
75  };
76
77  static const unsigned DarwinCalleeSavedRegs[] = {
78    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
79    // register.
80    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
81    ARM::R11, ARM::R10, ARM::R8,
82
83    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
84    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
85    0
86  };
87  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
88}
89
90BitVector ARMBaseRegisterInfo::
91getReservedRegs(const MachineFunction &MF) const {
92  // FIXME: avoid re-calculating this everytime.
93  BitVector Reserved(getNumRegs());
94  Reserved.set(ARM::SP);
95  Reserved.set(ARM::PC);
96  Reserved.set(ARM::FPSCR);
97  if (hasFP(MF))
98    Reserved.set(FramePtr);
99  if (hasBasePointer(MF))
100    Reserved.set(BasePtr);
101  // Some targets reserve R9.
102  if (STI.isR9Reserved())
103    Reserved.set(ARM::R9);
104  return Reserved;
105}
106
107bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
108                                        unsigned Reg) const {
109  switch (Reg) {
110  default: break;
111  case ARM::SP:
112  case ARM::PC:
113    return true;
114  case ARM::R6:
115    if (hasBasePointer(MF))
116      return true;
117    break;
118  case ARM::R7:
119  case ARM::R11:
120    if (FramePtr == Reg && hasFP(MF))
121      return true;
122    break;
123  case ARM::R9:
124    return STI.isR9Reserved();
125  }
126
127  return false;
128}
129
130const TargetRegisterClass *
131ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
132                                              const TargetRegisterClass *B,
133                                              unsigned SubIdx) const {
134  switch (SubIdx) {
135  default: return 0;
136  case ARM::ssub_0:
137  case ARM::ssub_1:
138  case ARM::ssub_2:
139  case ARM::ssub_3: {
140    // S sub-registers.
141    if (A->getSize() == 8) {
142      if (B == &ARM::SPR_8RegClass)
143        return &ARM::DPR_8RegClass;
144      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
145      if (A == &ARM::DPR_8RegClass)
146        return A;
147      return &ARM::DPR_VFP2RegClass;
148    }
149
150    if (A->getSize() == 16) {
151      if (B == &ARM::SPR_8RegClass)
152        return &ARM::QPR_8RegClass;
153      return &ARM::QPR_VFP2RegClass;
154    }
155
156    if (A->getSize() == 32) {
157      if (B == &ARM::SPR_8RegClass)
158        return 0;  // Do not allow coalescing!
159      return &ARM::QQPR_VFP2RegClass;
160    }
161
162    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
163    return 0;  // Do not allow coalescing!
164  }
165  case ARM::dsub_0:
166  case ARM::dsub_1:
167  case ARM::dsub_2:
168  case ARM::dsub_3: {
169    // D sub-registers.
170    if (A->getSize() == 16) {
171      if (B == &ARM::DPR_VFP2RegClass)
172        return &ARM::QPR_VFP2RegClass;
173      if (B == &ARM::DPR_8RegClass)
174        return 0;  // Do not allow coalescing!
175      return A;
176    }
177
178    if (A->getSize() == 32) {
179      if (B == &ARM::DPR_VFP2RegClass)
180        return &ARM::QQPR_VFP2RegClass;
181      if (B == &ARM::DPR_8RegClass)
182        return 0;  // Do not allow coalescing!
183      return A;
184    }
185
186    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
187    if (B != &ARM::DPRRegClass)
188      return 0;  // Do not allow coalescing!
189    return A;
190  }
191  case ARM::dsub_4:
192  case ARM::dsub_5:
193  case ARM::dsub_6:
194  case ARM::dsub_7: {
195    // D sub-registers of QQQQ registers.
196    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
197      return A;
198    return 0;  // Do not allow coalescing!
199  }
200
201  case ARM::qsub_0:
202  case ARM::qsub_1: {
203    // Q sub-registers.
204    if (A->getSize() == 32) {
205      if (B == &ARM::QPR_VFP2RegClass)
206        return &ARM::QQPR_VFP2RegClass;
207      if (B == &ARM::QPR_8RegClass)
208        return 0;  // Do not allow coalescing!
209      return A;
210    }
211
212    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
213    if (B == &ARM::QPRRegClass)
214      return A;
215    return 0;  // Do not allow coalescing!
216  }
217  case ARM::qsub_2:
218  case ARM::qsub_3: {
219    // Q sub-registers of QQQQ registers.
220    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
221      return A;
222    return 0;  // Do not allow coalescing!
223  }
224  }
225  return 0;
226}
227
228bool
229ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
230                                          SmallVectorImpl<unsigned> &SubIndices,
231                                          unsigned &NewSubIdx) const {
232
233  unsigned Size = RC->getSize() * 8;
234  if (Size < 6)
235    return 0;
236
237  NewSubIdx = 0;  // Whole register.
238  unsigned NumRegs = SubIndices.size();
239  if (NumRegs == 8) {
240    // 8 D registers -> 1 QQQQ register.
241    return (Size == 512 &&
242            SubIndices[0] == ARM::dsub_0 &&
243            SubIndices[1] == ARM::dsub_1 &&
244            SubIndices[2] == ARM::dsub_2 &&
245            SubIndices[3] == ARM::dsub_3 &&
246            SubIndices[4] == ARM::dsub_4 &&
247            SubIndices[5] == ARM::dsub_5 &&
248            SubIndices[6] == ARM::dsub_6 &&
249            SubIndices[7] == ARM::dsub_7);
250  } else if (NumRegs == 4) {
251    if (SubIndices[0] == ARM::qsub_0) {
252      // 4 Q registers -> 1 QQQQ register.
253      return (Size == 512 &&
254              SubIndices[1] == ARM::qsub_1 &&
255              SubIndices[2] == ARM::qsub_2 &&
256              SubIndices[3] == ARM::qsub_3);
257    } else if (SubIndices[0] == ARM::dsub_0) {
258      // 4 D registers -> 1 QQ register.
259      if (Size >= 256 &&
260          SubIndices[1] == ARM::dsub_1 &&
261          SubIndices[2] == ARM::dsub_2 &&
262          SubIndices[3] == ARM::dsub_3) {
263        if (Size == 512)
264          NewSubIdx = ARM::qqsub_0;
265        return true;
266      }
267    } else if (SubIndices[0] == ARM::dsub_4) {
268      // 4 D registers -> 1 QQ register (2nd).
269      if (Size == 512 &&
270          SubIndices[1] == ARM::dsub_5 &&
271          SubIndices[2] == ARM::dsub_6 &&
272          SubIndices[3] == ARM::dsub_7) {
273        NewSubIdx = ARM::qqsub_1;
274        return true;
275      }
276    } else if (SubIndices[0] == ARM::ssub_0) {
277      // 4 S registers -> 1 Q register.
278      if (Size >= 128 &&
279          SubIndices[1] == ARM::ssub_1 &&
280          SubIndices[2] == ARM::ssub_2 &&
281          SubIndices[3] == ARM::ssub_3) {
282        if (Size >= 256)
283          NewSubIdx = ARM::qsub_0;
284        return true;
285      }
286    }
287  } else if (NumRegs == 2) {
288    if (SubIndices[0] == ARM::qsub_0) {
289      // 2 Q registers -> 1 QQ register.
290      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
291        if (Size == 512)
292          NewSubIdx = ARM::qqsub_0;
293        return true;
294      }
295    } else if (SubIndices[0] == ARM::qsub_2) {
296      // 2 Q registers -> 1 QQ register (2nd).
297      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
298        NewSubIdx = ARM::qqsub_1;
299        return true;
300      }
301    } else if (SubIndices[0] == ARM::dsub_0) {
302      // 2 D registers -> 1 Q register.
303      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
304        if (Size >= 256)
305          NewSubIdx = ARM::qsub_0;
306        return true;
307      }
308    } else if (SubIndices[0] == ARM::dsub_2) {
309      // 2 D registers -> 1 Q register (2nd).
310      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
311        NewSubIdx = ARM::qsub_1;
312        return true;
313      }
314    } else if (SubIndices[0] == ARM::dsub_4) {
315      // 2 D registers -> 1 Q register (3rd).
316      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
317        NewSubIdx = ARM::qsub_2;
318        return true;
319      }
320    } else if (SubIndices[0] == ARM::dsub_6) {
321      // 2 D registers -> 1 Q register (3rd).
322      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
323        NewSubIdx = ARM::qsub_3;
324        return true;
325      }
326    } else if (SubIndices[0] == ARM::ssub_0) {
327      // 2 S registers -> 1 D register.
328      if (SubIndices[1] == ARM::ssub_1) {
329        if (Size >= 128)
330          NewSubIdx = ARM::dsub_0;
331        return true;
332      }
333    } else if (SubIndices[0] == ARM::ssub_2) {
334      // 2 S registers -> 1 D register (2nd).
335      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
336        NewSubIdx = ARM::dsub_1;
337        return true;
338      }
339    }
340  }
341  return false;
342}
343
344
345const TargetRegisterClass *
346ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
347  return ARM::GPRRegisterClass;
348}
349
350/// getAllocationOrder - Returns the register allocation order for a specified
351/// register class in the form of a pair of TargetRegisterClass iterators.
352std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
353ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
354                                        unsigned HintType, unsigned HintReg,
355                                        const MachineFunction &MF) const {
356  // Alternative register allocation orders when favoring even / odd registers
357  // of register pairs.
358
359  // No FP, R9 is available.
360  static const unsigned GPREven1[] = {
361    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
362    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
363    ARM::R9, ARM::R11
364  };
365  static const unsigned GPROdd1[] = {
366    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
367    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
368    ARM::R8, ARM::R10
369  };
370
371  // FP is R7, R9 is available.
372  static const unsigned GPREven2[] = {
373    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
374    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
375    ARM::R9, ARM::R11
376  };
377  static const unsigned GPROdd2[] = {
378    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
379    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
380    ARM::R8, ARM::R10
381  };
382
383  // FP is R11, R9 is available.
384  static const unsigned GPREven3[] = {
385    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
386    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
387    ARM::R9
388  };
389  static const unsigned GPROdd3[] = {
390    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
391    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
392    ARM::R8
393  };
394
395  // No FP, R9 is not available.
396  static const unsigned GPREven4[] = {
397    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
398    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
399    ARM::R11
400  };
401  static const unsigned GPROdd4[] = {
402    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
403    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
404    ARM::R10
405  };
406
407  // FP is R7, R9 is not available.
408  static const unsigned GPREven5[] = {
409    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
410    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
411    ARM::R11
412  };
413  static const unsigned GPROdd5[] = {
414    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
415    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
416    ARM::R10
417  };
418
419  // FP is R11, R9 is not available.
420  static const unsigned GPREven6[] = {
421    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
422    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
423  };
424  static const unsigned GPROdd6[] = {
425    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
426    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
427  };
428
429
430  if (HintType == ARMRI::RegPairEven) {
431    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
432      // It's no longer possible to fulfill this hint. Return the default
433      // allocation order.
434      return std::make_pair(RC->allocation_order_begin(MF),
435                            RC->allocation_order_end(MF));
436
437    if (!hasFP(MF)) {
438      if (!STI.isR9Reserved())
439        return std::make_pair(GPREven1,
440                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
441      else
442        return std::make_pair(GPREven4,
443                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
444    } else if (FramePtr == ARM::R7) {
445      if (!STI.isR9Reserved())
446        return std::make_pair(GPREven2,
447                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
448      else
449        return std::make_pair(GPREven5,
450                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
451    } else { // FramePtr == ARM::R11
452      if (!STI.isR9Reserved())
453        return std::make_pair(GPREven3,
454                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
455      else
456        return std::make_pair(GPREven6,
457                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
458    }
459  } else if (HintType == ARMRI::RegPairOdd) {
460    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
461      // It's no longer possible to fulfill this hint. Return the default
462      // allocation order.
463      return std::make_pair(RC->allocation_order_begin(MF),
464                            RC->allocation_order_end(MF));
465
466    if (!hasFP(MF)) {
467      if (!STI.isR9Reserved())
468        return std::make_pair(GPROdd1,
469                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
470      else
471        return std::make_pair(GPROdd4,
472                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
473    } else if (FramePtr == ARM::R7) {
474      if (!STI.isR9Reserved())
475        return std::make_pair(GPROdd2,
476                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
477      else
478        return std::make_pair(GPROdd5,
479                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
480    } else { // FramePtr == ARM::R11
481      if (!STI.isR9Reserved())
482        return std::make_pair(GPROdd3,
483                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
484      else
485        return std::make_pair(GPROdd6,
486                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
487    }
488  }
489  return std::make_pair(RC->allocation_order_begin(MF),
490                        RC->allocation_order_end(MF));
491}
492
493/// ResolveRegAllocHint - Resolves the specified register allocation hint
494/// to a physical register. Returns the physical register if it is successful.
495unsigned
496ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
497                                         const MachineFunction &MF) const {
498  if (Reg == 0 || !isPhysicalRegister(Reg))
499    return 0;
500  if (Type == 0)
501    return Reg;
502  else if (Type == (unsigned)ARMRI::RegPairOdd)
503    // Odd register.
504    return getRegisterPairOdd(Reg, MF);
505  else if (Type == (unsigned)ARMRI::RegPairEven)
506    // Even register.
507    return getRegisterPairEven(Reg, MF);
508  return 0;
509}
510
511void
512ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
513                                        MachineFunction &MF) const {
514  MachineRegisterInfo *MRI = &MF.getRegInfo();
515  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
516  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
517       Hint.first == (unsigned)ARMRI::RegPairEven) &&
518      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
519    // If 'Reg' is one of the even / odd register pair and it's now changed
520    // (e.g. coalesced) into a different register. The other register of the
521    // pair allocation hint must be updated to reflect the relationship
522    // change.
523    unsigned OtherReg = Hint.second;
524    Hint = MRI->getRegAllocationHint(OtherReg);
525    if (Hint.second == Reg)
526      // Make sure the pair has not already divorced.
527      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
528  }
529}
530
531/// hasFP - Return true if the specified function should have a dedicated frame
532/// pointer register.  This is true if the function has variable sized allocas
533/// or if frame pointer elimination is disabled.
534///
535bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
536  // Mac OS X requires FP not to be clobbered for backtracing purpose.
537  if (STI.isTargetDarwin())
538    return true;
539
540  const MachineFrameInfo *MFI = MF.getFrameInfo();
541  // Always eliminate non-leaf frame pointers.
542  return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
543          needsStackRealignment(MF) ||
544          MFI->hasVarSizedObjects() ||
545          MFI->isFrameAddressTaken());
546}
547
548bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
549  const MachineFrameInfo *MFI = MF.getFrameInfo();
550  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
551
552  if (!EnableBasePointer)
553    return false;
554
555  if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
556    return true;
557
558  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
559  // negative range for ldr/str (255), and thumb1 is positive offsets only.
560  // It's going to be better to use the SP or Base Pointer instead. When there
561  // are variable sized objects, we can't reference off of the SP, so we
562  // reserve a Base Pointer.
563  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
564    // Conservatively estimate whether the negative offset from the frame
565    // pointer will be sufficient to reach. If a function has a smallish
566    // frame, it's less likely to have lots of spills and callee saved
567    // space, so it's all more likely to be within range of the frame pointer.
568    // If it's wrong, the scavenger will still enable access to work, it just
569    // won't be optimal.
570    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
571      return false;
572    return true;
573  }
574
575  return false;
576}
577
578bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
579  const MachineFrameInfo *MFI = MF.getFrameInfo();
580  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
581  // We can't realign the stack if:
582  // 1. Dynamic stack realignment is explicitly disabled,
583  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
584  // 3. There are VLAs in the function and the base pointer is disabled.
585  return (RealignStack && !AFI->isThumb1OnlyFunction() &&
586          (!MFI->hasVarSizedObjects() || EnableBasePointer));
587}
588
589bool ARMBaseRegisterInfo::
590needsStackRealignment(const MachineFunction &MF) const {
591  const MachineFrameInfo *MFI = MF.getFrameInfo();
592  const Function *F = MF.getFunction();
593  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
594  bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
595                               F->hasFnAttr(Attribute::StackAlignment));
596
597  return requiresRealignment && canRealignStack(MF);
598}
599
600bool ARMBaseRegisterInfo::
601cannotEliminateFrame(const MachineFunction &MF) const {
602  const MachineFrameInfo *MFI = MF.getFrameInfo();
603  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
604    return true;
605  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
606    || needsStackRealignment(MF);
607}
608
609/// estimateStackSize - Estimate and return the size of the frame.
610static unsigned estimateStackSize(MachineFunction &MF) {
611  const MachineFrameInfo *FFI = MF.getFrameInfo();
612  int Offset = 0;
613  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
614    int FixedOff = -FFI->getObjectOffset(i);
615    if (FixedOff > Offset) Offset = FixedOff;
616  }
617  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
618    if (FFI->isDeadObjectIndex(i))
619      continue;
620    Offset += FFI->getObjectSize(i);
621    unsigned Align = FFI->getObjectAlignment(i);
622    // Adjust to alignment boundary
623    Offset = (Offset+Align-1)/Align*Align;
624  }
625  return (unsigned)Offset;
626}
627
628/// estimateRSStackSizeLimit - Look at each instruction that references stack
629/// frames and return the stack size limit beyond which some of these
630/// instructions will require a scratch register during their expansion later.
631unsigned
632ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
633  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
634  unsigned Limit = (1 << 12) - 1;
635  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
636    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
637         I != E; ++I) {
638      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
639        if (!I->getOperand(i).isFI()) continue;
640
641        // When using ADDri to get the address of a stack object, 255 is the
642        // largest offset guaranteed to fit in the immediate offset.
643        if (I->getOpcode() == ARM::ADDri) {
644          Limit = std::min(Limit, (1U << 8) - 1);
645          break;
646        }
647
648        // Otherwise check the addressing mode.
649        switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
650        case ARMII::AddrMode3:
651        case ARMII::AddrModeT2_i8:
652          Limit = std::min(Limit, (1U << 8) - 1);
653          break;
654        case ARMII::AddrMode5:
655        case ARMII::AddrModeT2_i8s4:
656          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
657          break;
658        case ARMII::AddrModeT2_i12:
659          // i12 supports only positive offset so these will be converted to
660          // i8 opcodes. See llvm::rewriteT2FrameIndex.
661          if (hasFP(MF) && AFI->hasStackFrame())
662            Limit = std::min(Limit, (1U << 8) - 1);
663          break;
664        case ARMII::AddrMode4:
665        case ARMII::AddrMode6:
666          // Addressing modes 4 & 6 (load/store) instructions can't encode an
667          // immediate offset for stack references.
668          return 0;
669        default:
670          break;
671        }
672        break; // At most one FI per instruction
673      }
674    }
675  }
676
677  return Limit;
678}
679
680static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
681                                       const ARMBaseInstrInfo &TII) {
682  unsigned FnSize = 0;
683  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
684       MBBI != E; ++MBBI) {
685    const MachineBasicBlock &MBB = *MBBI;
686    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
687         I != E; ++I)
688      FnSize += TII.GetInstSizeInBytes(I);
689  }
690  return FnSize;
691}
692
693void
694ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
695                                                       RegScavenger *RS) const {
696  // This tells PEI to spill the FP as if it is any other callee-save register
697  // to take advantage the eliminateFrameIndex machinery. This also ensures it
698  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
699  // to combine multiple loads / stores.
700  bool CanEliminateFrame = true;
701  bool CS1Spilled = false;
702  bool LRSpilled = false;
703  unsigned NumGPRSpills = 0;
704  SmallVector<unsigned, 4> UnspilledCS1GPRs;
705  SmallVector<unsigned, 4> UnspilledCS2GPRs;
706  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
707  MachineFrameInfo *MFI = MF.getFrameInfo();
708
709  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
710  // scratch register.
711  // FIXME: It will be better just to find spare register here.
712  if (needsStackRealignment(MF) &&
713      AFI->isThumb2Function())
714    MF.getRegInfo().setPhysRegUsed(ARM::R4);
715
716  // Spill LR if Thumb1 function uses variable length argument lists.
717  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
718    MF.getRegInfo().setPhysRegUsed(ARM::LR);
719
720  // Spill the BasePtr if it's used.
721  if (hasBasePointer(MF))
722    MF.getRegInfo().setPhysRegUsed(BasePtr);
723
724  // Don't spill FP if the frame can be eliminated. This is determined
725  // by scanning the callee-save registers to see if any is used.
726  const unsigned *CSRegs = getCalleeSavedRegs();
727  for (unsigned i = 0; CSRegs[i]; ++i) {
728    unsigned Reg = CSRegs[i];
729    bool Spilled = false;
730    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
731      AFI->setCSRegisterIsSpilled(Reg);
732      Spilled = true;
733      CanEliminateFrame = false;
734    } else {
735      // Check alias registers too.
736      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
737        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
738          Spilled = true;
739          CanEliminateFrame = false;
740        }
741      }
742    }
743
744    if (!ARM::GPRRegisterClass->contains(Reg))
745      continue;
746
747    if (Spilled) {
748      NumGPRSpills++;
749
750      if (!STI.isTargetDarwin()) {
751        if (Reg == ARM::LR)
752          LRSpilled = true;
753        CS1Spilled = true;
754        continue;
755      }
756
757      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
758      switch (Reg) {
759      case ARM::LR:
760        LRSpilled = true;
761        // Fallthrough
762      case ARM::R4:
763      case ARM::R5:
764      case ARM::R6:
765      case ARM::R7:
766        CS1Spilled = true;
767        break;
768      default:
769        break;
770      }
771    } else {
772      if (!STI.isTargetDarwin()) {
773        UnspilledCS1GPRs.push_back(Reg);
774        continue;
775      }
776
777      switch (Reg) {
778      case ARM::R4:
779      case ARM::R5:
780      case ARM::R6:
781      case ARM::R7:
782      case ARM::LR:
783        UnspilledCS1GPRs.push_back(Reg);
784        break;
785      default:
786        UnspilledCS2GPRs.push_back(Reg);
787        break;
788      }
789    }
790  }
791
792  bool ForceLRSpill = false;
793  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
794    unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
795    // Force LR to be spilled if the Thumb function size is > 2048. This enables
796    // use of BL to implement far jump. If it turns out that it's not needed
797    // then the branch fix up path will undo it.
798    if (FnSize >= (1 << 11)) {
799      CanEliminateFrame = false;
800      ForceLRSpill = true;
801    }
802  }
803
804  // If any of the stack slot references may be out of range of an immediate
805  // offset, make sure a register (or a spill slot) is available for the
806  // register scavenger. Note that if we're indexing off the frame pointer, the
807  // effective stack size is 4 bytes larger since the FP points to the stack
808  // slot of the previous FP. Also, if we have variable sized objects in the
809  // function, stack slot references will often be negative, and some of
810  // our instructions are positive-offset only, so conservatively consider
811  // that case to want a spill slot (or register) as well. Similarly, if
812  // the function adjusts the stack pointer during execution and the
813  // adjustments aren't already part of our stack size estimate, our offset
814  // calculations may be off, so be conservative.
815  // FIXME: We could add logic to be more precise about negative offsets
816  //        and which instructions will need a scratch register for them. Is it
817  //        worth the effort and added fragility?
818  bool BigStack =
819    (RS &&
820     (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
821      estimateRSStackSizeLimit(MF)))
822    || MFI->hasVarSizedObjects()
823    || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
824
825  bool ExtraCSSpill = false;
826  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
827    AFI->setHasStackFrame(true);
828
829    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
830    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
831    if (!LRSpilled && CS1Spilled) {
832      MF.getRegInfo().setPhysRegUsed(ARM::LR);
833      AFI->setCSRegisterIsSpilled(ARM::LR);
834      NumGPRSpills++;
835      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
836                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
837      ForceLRSpill = false;
838      ExtraCSSpill = true;
839    }
840
841    if (hasFP(MF)) {
842      MF.getRegInfo().setPhysRegUsed(FramePtr);
843      NumGPRSpills++;
844    }
845
846    // If stack and double are 8-byte aligned and we are spilling an odd number
847    // of GPRs, spill one extra callee save GPR so we won't have to pad between
848    // the integer and double callee save areas.
849    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
850    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
851      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
852        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
853          unsigned Reg = UnspilledCS1GPRs[i];
854          // Don't spill high register if the function is thumb1
855          if (!AFI->isThumb1OnlyFunction() ||
856              isARMLowRegister(Reg) || Reg == ARM::LR) {
857            MF.getRegInfo().setPhysRegUsed(Reg);
858            AFI->setCSRegisterIsSpilled(Reg);
859            if (!isReservedReg(MF, Reg))
860              ExtraCSSpill = true;
861            break;
862          }
863        }
864      } else if (!UnspilledCS2GPRs.empty() &&
865                 !AFI->isThumb1OnlyFunction()) {
866        unsigned Reg = UnspilledCS2GPRs.front();
867        MF.getRegInfo().setPhysRegUsed(Reg);
868        AFI->setCSRegisterIsSpilled(Reg);
869        if (!isReservedReg(MF, Reg))
870          ExtraCSSpill = true;
871      }
872    }
873
874    // Estimate if we might need to scavenge a register at some point in order
875    // to materialize a stack offset. If so, either spill one additional
876    // callee-saved register or reserve a special spill slot to facilitate
877    // register scavenging. Thumb1 needs a spill slot for stack pointer
878    // adjustments also, even when the frame itself is small.
879    if (BigStack && !ExtraCSSpill) {
880      // If any non-reserved CS register isn't spilled, just spill one or two
881      // extra. That should take care of it!
882      unsigned NumExtras = TargetAlign / 4;
883      SmallVector<unsigned, 2> Extras;
884      while (NumExtras && !UnspilledCS1GPRs.empty()) {
885        unsigned Reg = UnspilledCS1GPRs.back();
886        UnspilledCS1GPRs.pop_back();
887        if (!isReservedReg(MF, Reg) &&
888            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
889             Reg == ARM::LR)) {
890          Extras.push_back(Reg);
891          NumExtras--;
892        }
893      }
894      // For non-Thumb1 functions, also check for hi-reg CS registers
895      if (!AFI->isThumb1OnlyFunction()) {
896        while (NumExtras && !UnspilledCS2GPRs.empty()) {
897          unsigned Reg = UnspilledCS2GPRs.back();
898          UnspilledCS2GPRs.pop_back();
899          if (!isReservedReg(MF, Reg)) {
900            Extras.push_back(Reg);
901            NumExtras--;
902          }
903        }
904      }
905      if (Extras.size() && NumExtras == 0) {
906        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
907          MF.getRegInfo().setPhysRegUsed(Extras[i]);
908          AFI->setCSRegisterIsSpilled(Extras[i]);
909        }
910      } else if (!AFI->isThumb1OnlyFunction()) {
911        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
912        // closest to SP or frame pointer.
913        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
914        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
915                                                           RC->getAlignment(),
916                                                           false));
917      }
918    }
919  }
920
921  if (ForceLRSpill) {
922    MF.getRegInfo().setPhysRegUsed(ARM::LR);
923    AFI->setCSRegisterIsSpilled(ARM::LR);
924    AFI->setLRIsSpilledForFarJump(true);
925  }
926}
927
928unsigned ARMBaseRegisterInfo::getRARegister() const {
929  return ARM::LR;
930}
931
932unsigned
933ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
934  if (hasFP(MF))
935    return FramePtr;
936  return ARM::SP;
937}
938
939// Provide a base+offset reference to an FI slot for debug info. It's the
940// same as what we use for resolving the code-gen references for now.
941// FIXME: This can go wrong when references are SP-relative and simple call
942//        frames aren't used.
943int
944ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
945                                            unsigned &FrameReg) const {
946  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
947}
948
949int
950ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
951                                                int FI,
952                                                unsigned &FrameReg,
953                                                int SPAdj) const {
954  const MachineFrameInfo *MFI = MF.getFrameInfo();
955  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
956  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
957  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
958  bool isFixed = MFI->isFixedObjectIndex(FI);
959
960  FrameReg = ARM::SP;
961  Offset += SPAdj;
962  if (AFI->isGPRCalleeSavedArea1Frame(FI))
963    return Offset - AFI->getGPRCalleeSavedArea1Offset();
964  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
965    return Offset - AFI->getGPRCalleeSavedArea2Offset();
966  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
967    return Offset - AFI->getDPRCalleeSavedAreaOffset();
968
969  // When dynamically realigning the stack, use the frame pointer for
970  // parameters, and the stack/base pointer for locals.
971  if (needsStackRealignment(MF)) {
972    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
973    if (isFixed) {
974      FrameReg = getFrameRegister(MF);
975      Offset = FPOffset;
976    } else if (MFI->hasVarSizedObjects()) {
977      assert(hasBasePointer(MF) &&
978             "VLAs and dynamic stack alignment, but missing base pointer!");
979      FrameReg = BasePtr;
980    }
981    return Offset;
982  }
983
984  // If there is a frame pointer, use it when we can.
985  if (hasFP(MF) && AFI->hasStackFrame()) {
986    // Use frame pointer to reference fixed objects. Use it for locals if
987    // there are VLAs (and thus the SP isn't reliable as a base).
988    if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
989      FrameReg = getFrameRegister(MF);
990      return FPOffset;
991    } else if (MFI->hasVarSizedObjects()) {
992      assert(hasBasePointer(MF) && "missing base pointer!");
993      // Try to use the frame pointer if we can, else use the base pointer
994      // since it's available. This is handy for the emergency spill slot, in
995      // particular.
996      if (AFI->isThumb2Function()) {
997        if (FPOffset >= -255 && FPOffset < 0) {
998          FrameReg = getFrameRegister(MF);
999          return FPOffset;
1000        }
1001      } else
1002        FrameReg = BasePtr;
1003    } else if (AFI->isThumb2Function()) {
1004      // In Thumb2 mode, the negative offset is very limited. Try to avoid
1005      // out of range references.
1006      if (FPOffset >= -255 && FPOffset < 0) {
1007        FrameReg = getFrameRegister(MF);
1008        return FPOffset;
1009      }
1010    } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1011      // Otherwise, use SP or FP, whichever is closer to the stack slot.
1012      FrameReg = getFrameRegister(MF);
1013      return FPOffset;
1014    }
1015  }
1016  // Use the base pointer if we have one.
1017  if (hasBasePointer(MF))
1018    FrameReg = BasePtr;
1019  return Offset;
1020}
1021
1022int
1023ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1024                                         int FI) const {
1025  unsigned FrameReg;
1026  return getFrameIndexReference(MF, FI, FrameReg);
1027}
1028
1029unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1030  llvm_unreachable("What is the exception register");
1031  return 0;
1032}
1033
1034unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1035  llvm_unreachable("What is the exception handler register");
1036  return 0;
1037}
1038
1039int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1040  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1041}
1042
1043unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1044                                              const MachineFunction &MF) const {
1045  switch (Reg) {
1046  default: break;
1047  // Return 0 if either register of the pair is a special register.
1048  // So no R12, etc.
1049  case ARM::R1:
1050    return ARM::R0;
1051  case ARM::R3:
1052    return ARM::R2;
1053  case ARM::R5:
1054    return ARM::R4;
1055  case ARM::R7:
1056    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1057      ? 0 : ARM::R6;
1058  case ARM::R9:
1059    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1060  case ARM::R11:
1061    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1062
1063  case ARM::S1:
1064    return ARM::S0;
1065  case ARM::S3:
1066    return ARM::S2;
1067  case ARM::S5:
1068    return ARM::S4;
1069  case ARM::S7:
1070    return ARM::S6;
1071  case ARM::S9:
1072    return ARM::S8;
1073  case ARM::S11:
1074    return ARM::S10;
1075  case ARM::S13:
1076    return ARM::S12;
1077  case ARM::S15:
1078    return ARM::S14;
1079  case ARM::S17:
1080    return ARM::S16;
1081  case ARM::S19:
1082    return ARM::S18;
1083  case ARM::S21:
1084    return ARM::S20;
1085  case ARM::S23:
1086    return ARM::S22;
1087  case ARM::S25:
1088    return ARM::S24;
1089  case ARM::S27:
1090    return ARM::S26;
1091  case ARM::S29:
1092    return ARM::S28;
1093  case ARM::S31:
1094    return ARM::S30;
1095
1096  case ARM::D1:
1097    return ARM::D0;
1098  case ARM::D3:
1099    return ARM::D2;
1100  case ARM::D5:
1101    return ARM::D4;
1102  case ARM::D7:
1103    return ARM::D6;
1104  case ARM::D9:
1105    return ARM::D8;
1106  case ARM::D11:
1107    return ARM::D10;
1108  case ARM::D13:
1109    return ARM::D12;
1110  case ARM::D15:
1111    return ARM::D14;
1112  case ARM::D17:
1113    return ARM::D16;
1114  case ARM::D19:
1115    return ARM::D18;
1116  case ARM::D21:
1117    return ARM::D20;
1118  case ARM::D23:
1119    return ARM::D22;
1120  case ARM::D25:
1121    return ARM::D24;
1122  case ARM::D27:
1123    return ARM::D26;
1124  case ARM::D29:
1125    return ARM::D28;
1126  case ARM::D31:
1127    return ARM::D30;
1128  }
1129
1130  return 0;
1131}
1132
1133unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1134                                             const MachineFunction &MF) const {
1135  switch (Reg) {
1136  default: break;
1137  // Return 0 if either register of the pair is a special register.
1138  // So no R12, etc.
1139  case ARM::R0:
1140    return ARM::R1;
1141  case ARM::R2:
1142    return ARM::R3;
1143  case ARM::R4:
1144    return ARM::R5;
1145  case ARM::R6:
1146    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1147      ? 0 : ARM::R7;
1148  case ARM::R8:
1149    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1150  case ARM::R10:
1151    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1152
1153  case ARM::S0:
1154    return ARM::S1;
1155  case ARM::S2:
1156    return ARM::S3;
1157  case ARM::S4:
1158    return ARM::S5;
1159  case ARM::S6:
1160    return ARM::S7;
1161  case ARM::S8:
1162    return ARM::S9;
1163  case ARM::S10:
1164    return ARM::S11;
1165  case ARM::S12:
1166    return ARM::S13;
1167  case ARM::S14:
1168    return ARM::S15;
1169  case ARM::S16:
1170    return ARM::S17;
1171  case ARM::S18:
1172    return ARM::S19;
1173  case ARM::S20:
1174    return ARM::S21;
1175  case ARM::S22:
1176    return ARM::S23;
1177  case ARM::S24:
1178    return ARM::S25;
1179  case ARM::S26:
1180    return ARM::S27;
1181  case ARM::S28:
1182    return ARM::S29;
1183  case ARM::S30:
1184    return ARM::S31;
1185
1186  case ARM::D0:
1187    return ARM::D1;
1188  case ARM::D2:
1189    return ARM::D3;
1190  case ARM::D4:
1191    return ARM::D5;
1192  case ARM::D6:
1193    return ARM::D7;
1194  case ARM::D8:
1195    return ARM::D9;
1196  case ARM::D10:
1197    return ARM::D11;
1198  case ARM::D12:
1199    return ARM::D13;
1200  case ARM::D14:
1201    return ARM::D15;
1202  case ARM::D16:
1203    return ARM::D17;
1204  case ARM::D18:
1205    return ARM::D19;
1206  case ARM::D20:
1207    return ARM::D21;
1208  case ARM::D22:
1209    return ARM::D23;
1210  case ARM::D24:
1211    return ARM::D25;
1212  case ARM::D26:
1213    return ARM::D27;
1214  case ARM::D28:
1215    return ARM::D29;
1216  case ARM::D30:
1217    return ARM::D31;
1218  }
1219
1220  return 0;
1221}
1222
1223/// emitLoadConstPool - Emits a load from constpool to materialize the
1224/// specified immediate.
1225void ARMBaseRegisterInfo::
1226emitLoadConstPool(MachineBasicBlock &MBB,
1227                  MachineBasicBlock::iterator &MBBI,
1228                  DebugLoc dl,
1229                  unsigned DestReg, unsigned SubIdx, int Val,
1230                  ARMCC::CondCodes Pred,
1231                  unsigned PredReg) const {
1232  MachineFunction &MF = *MBB.getParent();
1233  MachineConstantPool *ConstantPool = MF.getConstantPool();
1234  const Constant *C =
1235        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1236  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1237
1238  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1239    .addReg(DestReg, getDefRegState(true), SubIdx)
1240    .addConstantPoolIndex(Idx)
1241    .addImm(0).addImm(Pred).addReg(PredReg);
1242}
1243
1244bool ARMBaseRegisterInfo::
1245requiresRegisterScavenging(const MachineFunction &MF) const {
1246  return true;
1247}
1248
1249bool ARMBaseRegisterInfo::
1250requiresFrameIndexScavenging(const MachineFunction &MF) const {
1251  return true;
1252}
1253
1254bool ARMBaseRegisterInfo::
1255requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1256  return EnableLocalStackAlloc;
1257}
1258
1259// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1260// not required, we reserve argument space for call sites in the function
1261// immediately on entry to the current function. This eliminates the need for
1262// add/sub sp brackets around call sites. Returns true if the call frame is
1263// included as part of the stack frame.
1264bool ARMBaseRegisterInfo::
1265hasReservedCallFrame(const MachineFunction &MF) const {
1266  const MachineFrameInfo *FFI = MF.getFrameInfo();
1267  unsigned CFSize = FFI->getMaxCallFrameSize();
1268  // It's not always a good idea to include the call frame as part of the
1269  // stack frame. ARM (especially Thumb) has small immediate offset to
1270  // address the stack frame. So a large call frame can cause poor codegen
1271  // and may even makes it impossible to scavenge a register.
1272  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1273    return false;
1274
1275  return !MF.getFrameInfo()->hasVarSizedObjects();
1276}
1277
1278// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1279// call frame pseudos can be simplified. Unlike most targets, having a FP
1280// is not sufficient here since we still may reference some objects via SP
1281// even when FP is available in Thumb2 mode.
1282bool ARMBaseRegisterInfo::
1283canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1284  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1285}
1286
1287static void
1288emitSPUpdate(bool isARM,
1289             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1290             DebugLoc dl, const ARMBaseInstrInfo &TII,
1291             int NumBytes,
1292             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1293  if (isARM)
1294    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1295                            Pred, PredReg, TII);
1296  else
1297    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1298                           Pred, PredReg, TII);
1299}
1300
1301
1302void ARMBaseRegisterInfo::
1303eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1304                              MachineBasicBlock::iterator I) const {
1305  if (!hasReservedCallFrame(MF)) {
1306    // If we have alloca, convert as follows:
1307    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1308    // ADJCALLSTACKUP   -> add, sp, sp, amount
1309    MachineInstr *Old = I;
1310    DebugLoc dl = Old->getDebugLoc();
1311    unsigned Amount = Old->getOperand(0).getImm();
1312    if (Amount != 0) {
1313      // We need to keep the stack aligned properly.  To do this, we round the
1314      // amount of space needed for the outgoing arguments up to the next
1315      // alignment boundary.
1316      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1317      Amount = (Amount+Align-1)/Align*Align;
1318
1319      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1320      assert(!AFI->isThumb1OnlyFunction() &&
1321             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1322      bool isARM = !AFI->isThumbFunction();
1323
1324      // Replace the pseudo instruction with a new instruction...
1325      unsigned Opc = Old->getOpcode();
1326      int PIdx = Old->findFirstPredOperandIdx();
1327      ARMCC::CondCodes Pred = (PIdx == -1)
1328        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1329      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1330        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1331        unsigned PredReg = Old->getOperand(2).getReg();
1332        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1333      } else {
1334        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1335        unsigned PredReg = Old->getOperand(3).getReg();
1336        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1337        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1338      }
1339    }
1340  }
1341  MBB.erase(I);
1342}
1343
1344int64_t ARMBaseRegisterInfo::
1345getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1346  const TargetInstrDesc &Desc = MI->getDesc();
1347  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1348  int64_t InstrOffs = 0;;
1349  int Scale = 1;
1350  unsigned ImmIdx = 0;
1351  switch (AddrMode) {
1352  case ARMII::AddrModeT2_i8:
1353  case ARMII::AddrModeT2_i12:
1354  case ARMII::AddrMode_i12:
1355    InstrOffs = MI->getOperand(Idx+1).getImm();
1356    Scale = 1;
1357    break;
1358  case ARMII::AddrMode5: {
1359    // VFP address mode.
1360    const MachineOperand &OffOp = MI->getOperand(Idx+1);
1361    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1362    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1363      InstrOffs = -InstrOffs;
1364    Scale = 4;
1365    break;
1366  }
1367  case ARMII::AddrMode2: {
1368    ImmIdx = Idx+2;
1369    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1370    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1371      InstrOffs = -InstrOffs;
1372    break;
1373  }
1374  case ARMII::AddrMode3: {
1375    ImmIdx = Idx+2;
1376    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1377    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1378      InstrOffs = -InstrOffs;
1379    break;
1380  }
1381  case ARMII::AddrModeT1_s: {
1382    ImmIdx = Idx+1;
1383    InstrOffs = MI->getOperand(ImmIdx).getImm();
1384    Scale = 4;
1385    break;
1386  }
1387  default:
1388    llvm_unreachable("Unsupported addressing mode!");
1389    break;
1390  }
1391
1392  return InstrOffs * Scale;
1393}
1394
1395/// needsFrameBaseReg - Returns true if the instruction's frame index
1396/// reference would be better served by a base register other than FP
1397/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1398/// references it should create new base registers for.
1399bool ARMBaseRegisterInfo::
1400needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1401  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1402    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1403  }
1404
1405  // It's the load/store FI references that cause issues, as it can be difficult
1406  // to materialize the offset if it won't fit in the literal field. Estimate
1407  // based on the size of the local frame and some conservative assumptions
1408  // about the rest of the stack frame (note, this is pre-regalloc, so
1409  // we don't know everything for certain yet) whether this offset is likely
1410  // to be out of range of the immediate. Return true if so.
1411
1412  // We only generate virtual base registers for loads and stores, so
1413  // return false for everything else.
1414  unsigned Opc = MI->getOpcode();
1415  switch (Opc) {
1416  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1417  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1418  case ARM::t2LDRi12: case ARM::t2LDRi8:
1419  case ARM::t2STRi12: case ARM::t2STRi8:
1420  case ARM::VLDRS: case ARM::VLDRD:
1421  case ARM::VSTRS: case ARM::VSTRD:
1422  case ARM::tSTRspi: case ARM::tLDRspi:
1423    if (ForceAllBaseRegAlloc)
1424      return true;
1425    break;
1426  default:
1427    return false;
1428  }
1429
1430  // Without a virtual base register, if the function has variable sized
1431  // objects, all fixed-size local references will be via the frame pointer,
1432  // Approximate the offset and see if it's legal for the instruction.
1433  // Note that the incoming offset is based on the SP value at function entry,
1434  // so it'll be negative.
1435  MachineFunction &MF = *MI->getParent()->getParent();
1436  MachineFrameInfo *MFI = MF.getFrameInfo();
1437  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1438
1439  // Estimate an offset from the frame pointer.
1440  // Conservatively assume all callee-saved registers get pushed. R4-R6
1441  // will be earlier than the FP, so we ignore those.
1442  // R7, LR
1443  int64_t FPOffset = Offset - 8;
1444  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1445  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1446    FPOffset -= 80;
1447  // Estimate an offset from the stack pointer.
1448  // The incoming offset is relating to the SP at the start of the function,
1449  // but when we access the local it'll be relative to the SP after local
1450  // allocation, so adjust our SP-relative offset by that allocation size.
1451  Offset = -Offset;
1452  Offset += MFI->getLocalFrameSize();
1453  // Assume that we'll have at least some spill slots allocated.
1454  // FIXME: This is a total SWAG number. We should run some statistics
1455  //        and pick a real one.
1456  Offset += 128; // 128 bytes of spill slots
1457
1458  // If there is a frame pointer, try using it.
1459  // The FP is only available if there is no dynamic realignment. We
1460  // don't know for sure yet whether we'll need that, so we guess based
1461  // on whether there are any local variables that would trigger it.
1462  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1463  if (hasFP(MF) &&
1464      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1465    if (isFrameOffsetLegal(MI, FPOffset))
1466      return false;
1467  }
1468  // If we can reference via the stack pointer, try that.
1469  // FIXME: This (and the code that resolves the references) can be improved
1470  //        to only disallow SP relative references in the live range of
1471  //        the VLA(s). In practice, it's unclear how much difference that
1472  //        would make, but it may be worth doing.
1473  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1474    return false;
1475
1476  // The offset likely isn't legal, we want to allocate a virtual base register.
1477  return true;
1478}
1479
1480/// materializeFrameBaseRegister - Insert defining instruction(s) for
1481/// BaseReg to be a pointer to FrameIdx before insertion point I.
1482void ARMBaseRegisterInfo::
1483materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1484                             int FrameIdx, int64_t Offset) const {
1485  ARMFunctionInfo *AFI =
1486    I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1487  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1488    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1489
1490  MachineInstrBuilder MIB =
1491    BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1492    .addFrameIndex(FrameIdx).addImm(Offset);
1493  if (!AFI->isThumb1OnlyFunction())
1494    AddDefaultCC(AddDefaultPred(MIB));
1495}
1496
1497void
1498ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1499                                       unsigned BaseReg, int64_t Offset) const {
1500  MachineInstr &MI = *I;
1501  MachineBasicBlock &MBB = *MI.getParent();
1502  MachineFunction &MF = *MBB.getParent();
1503  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1504  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1505  unsigned i = 0;
1506
1507  assert(!AFI->isThumb1OnlyFunction() &&
1508         "This resolveFrameIndex does not support Thumb1!");
1509
1510  while (!MI.getOperand(i).isFI()) {
1511    ++i;
1512    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1513  }
1514  bool Done = false;
1515  if (!AFI->isThumbFunction())
1516    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1517  else {
1518    assert(AFI->isThumb2Function());
1519    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1520  }
1521  assert (Done && "Unable to resolve frame index!");
1522}
1523
1524bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1525                                             int64_t Offset) const {
1526  const TargetInstrDesc &Desc = MI->getDesc();
1527  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1528  unsigned i = 0;
1529
1530  while (!MI->getOperand(i).isFI()) {
1531    ++i;
1532    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1533  }
1534
1535  // AddrMode4 and AddrMode6 cannot handle any offset.
1536  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1537    return Offset == 0;
1538
1539  unsigned NumBits = 0;
1540  unsigned Scale = 1;
1541  bool isSigned = true;
1542  switch (AddrMode) {
1543  case ARMII::AddrModeT2_i8:
1544  case ARMII::AddrModeT2_i12:
1545    // i8 supports only negative, and i12 supports only positive, so
1546    // based on Offset sign, consider the appropriate instruction
1547    Scale = 1;
1548    if (Offset < 0) {
1549      NumBits = 8;
1550      Offset = -Offset;
1551    } else {
1552      NumBits = 12;
1553    }
1554    break;
1555  case ARMII::AddrMode5:
1556    // VFP address mode.
1557    NumBits = 8;
1558    Scale = 4;
1559    break;
1560  case ARMII::AddrMode_i12:
1561  case ARMII::AddrMode2:
1562    NumBits = 12;
1563    break;
1564  case ARMII::AddrMode3:
1565    NumBits = 8;
1566    break;
1567  case ARMII::AddrModeT1_s:
1568    NumBits = 5;
1569    Scale = 4;
1570    isSigned = false;
1571    break;
1572  default:
1573    llvm_unreachable("Unsupported addressing mode!");
1574    break;
1575  }
1576
1577  Offset += getFrameIndexInstrOffset(MI, i);
1578  // Make sure the offset is encodable for instructions that scale the
1579  // immediate.
1580  if ((Offset & (Scale-1)) != 0)
1581    return false;
1582
1583  if (isSigned && Offset < 0)
1584    Offset = -Offset;
1585
1586  unsigned Mask = (1 << NumBits) - 1;
1587  if ((unsigned)Offset <= Mask * Scale)
1588    return true;
1589
1590  return false;
1591}
1592
1593void
1594ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1595                                         int SPAdj, RegScavenger *RS) const {
1596  unsigned i = 0;
1597  MachineInstr &MI = *II;
1598  MachineBasicBlock &MBB = *MI.getParent();
1599  MachineFunction &MF = *MBB.getParent();
1600  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1601  assert(!AFI->isThumb1OnlyFunction() &&
1602         "This eliminateFrameIndex does not support Thumb1!");
1603
1604  while (!MI.getOperand(i).isFI()) {
1605    ++i;
1606    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1607  }
1608
1609  int FrameIndex = MI.getOperand(i).getIndex();
1610  unsigned FrameReg;
1611
1612  int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1613
1614  // Special handling of dbg_value instructions.
1615  if (MI.isDebugValue()) {
1616    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1617    MI.getOperand(i+1).ChangeToImmediate(Offset);
1618    return;
1619  }
1620
1621  // Modify MI as necessary to handle as much of 'Offset' as possible
1622  bool Done = false;
1623  if (!AFI->isThumbFunction())
1624    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1625  else {
1626    assert(AFI->isThumb2Function());
1627    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1628  }
1629  if (Done)
1630    return;
1631
1632  // If we get here, the immediate doesn't fit into the instruction.  We folded
1633  // as much as possible above, handle the rest, providing a register that is
1634  // SP+LargeImm.
1635  assert((Offset ||
1636          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1637          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1638         "This code isn't needed if offset already handled!");
1639
1640  unsigned ScratchReg = 0;
1641  int PIdx = MI.findFirstPredOperandIdx();
1642  ARMCC::CondCodes Pred = (PIdx == -1)
1643    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1644  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1645  if (Offset == 0)
1646    // Must be addrmode4/6.
1647    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1648  else {
1649    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1650    if (!AFI->isThumbFunction())
1651      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1652                              Offset, Pred, PredReg, TII);
1653    else {
1654      assert(AFI->isThumb2Function());
1655      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1656                             Offset, Pred, PredReg, TII);
1657    }
1658    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1659  }
1660}
1661
1662/// Move iterator past the next bunch of callee save load / store ops for
1663/// the particular spill area (1: integer area 1, 2: integer area 2,
1664/// 3: fp area, 0: don't care).
1665static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1666                                   MachineBasicBlock::iterator &MBBI,
1667                                   int Opc1, int Opc2, unsigned Area,
1668                                   const ARMSubtarget &STI) {
1669  while (MBBI != MBB.end() &&
1670         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2))) {
1671
1672    if (Area == 3) {
1673      bool Done = false;
1674      unsigned Category = 0;
1675      switch (MBBI->getOperand(0).getReg()) {
1676      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1677      case ARM::LR:
1678        Category = 1;
1679        break;
1680      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1681        Category = STI.isTargetDarwin() ? 2 : 1;
1682        break;
1683      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1684      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1685        Category = 3;
1686        break;
1687      default:
1688        Done = true;
1689        break;
1690      }
1691      if (Done || Category != Area)
1692        break;
1693    }
1694
1695    ++MBBI;
1696  }
1697}
1698
1699void ARMBaseRegisterInfo::
1700emitPrologue(MachineFunction &MF) const {
1701  MachineBasicBlock &MBB = MF.front();
1702  MachineBasicBlock::iterator MBBI = MBB.begin();
1703  MachineFrameInfo  *MFI = MF.getFrameInfo();
1704  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1705  assert(!AFI->isThumb1OnlyFunction() &&
1706         "This emitPrologue does not support Thumb1!");
1707  bool isARM = !AFI->isThumbFunction();
1708  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1709  unsigned NumBytes = MFI->getStackSize();
1710  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1711  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1712
1713  // Determine the sizes of each callee-save spill areas and record which frame
1714  // belongs to which callee-save spill areas.
1715  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1716  int FramePtrSpillFI = 0;
1717
1718  // Allocate the vararg register save area. This is not counted in NumBytes.
1719  if (VARegSaveSize)
1720    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1721
1722  if (!AFI->hasStackFrame()) {
1723    if (NumBytes != 0)
1724      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1725    return;
1726  }
1727
1728  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1729    unsigned Reg = CSI[i].getReg();
1730    int FI = CSI[i].getFrameIdx();
1731    switch (Reg) {
1732    case ARM::R4:
1733    case ARM::R5:
1734    case ARM::R6:
1735    case ARM::R7:
1736    case ARM::LR:
1737      if (Reg == FramePtr)
1738        FramePtrSpillFI = FI;
1739      AFI->addGPRCalleeSavedArea1Frame(FI);
1740      GPRCS1Size += 4;
1741      break;
1742    case ARM::R8:
1743    case ARM::R9:
1744    case ARM::R10:
1745    case ARM::R11:
1746      if (Reg == FramePtr)
1747        FramePtrSpillFI = FI;
1748      if (STI.isTargetDarwin()) {
1749        AFI->addGPRCalleeSavedArea2Frame(FI);
1750        GPRCS2Size += 4;
1751      } else {
1752        AFI->addGPRCalleeSavedArea1Frame(FI);
1753        GPRCS1Size += 4;
1754      }
1755      break;
1756    default:
1757      AFI->addDPRCalleeSavedAreaFrame(FI);
1758      DPRCSSize += 8;
1759    }
1760  }
1761
1762  movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 1, STI);
1763
1764  // Set FP to point to the stack slot that contains the previous FP.
1765  // For Darwin, FP is R7, which has now been stored in spill area 1.
1766  // Otherwise, if this is not Darwin, all the callee-saved registers go
1767  // into spill area 1, including the FP in R11.  In either case, it is
1768  // now safe to emit this assignment.
1769  bool HasFP = hasFP(MF);
1770  if (HasFP) {
1771    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1772    MachineInstrBuilder MIB =
1773      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1774      .addFrameIndex(FramePtrSpillFI).addImm(0);
1775    AddDefaultCC(AddDefaultPred(MIB));
1776  }
1777
1778  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1779  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1780
1781  // Build the new SUBri to adjust SP for FP callee-save spill area.
1782  movePastCSLoadStoreOps(MBB, MBBI, ARM::tPUSH, 0, 2, STI);
1783  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1784
1785  // Determine starting offsets of spill areas.
1786  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1787  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1788  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1789  if (HasFP)
1790    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1791                                NumBytes);
1792  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1793  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1794  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1795
1796  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1797  NumBytes = DPRCSOffset;
1798  if (NumBytes) {
1799    // Adjust SP after all the callee-save spills.
1800    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1801    if (HasFP)
1802      AFI->setShouldRestoreSPFromFP(true);
1803  }
1804
1805  if (STI.isTargetELF() && hasFP(MF)) {
1806    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1807                             AFI->getFramePtrSpillOffset());
1808    AFI->setShouldRestoreSPFromFP(true);
1809  }
1810
1811  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1812  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1813  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1814
1815  // If we need dynamic stack realignment, do it here. Be paranoid and make
1816  // sure if we also have VLAs, we have a base pointer for frame access.
1817  if (needsStackRealignment(MF)) {
1818    unsigned MaxAlign = MFI->getMaxAlignment();
1819    assert (!AFI->isThumb1OnlyFunction());
1820    if (!AFI->isThumbFunction()) {
1821      // Emit bic sp, sp, MaxAlign
1822      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1823                                          TII.get(ARM::BICri), ARM::SP)
1824                                  .addReg(ARM::SP, RegState::Kill)
1825                                  .addImm(MaxAlign-1)));
1826    } else {
1827      // We cannot use sp as source/dest register here, thus we're emitting the
1828      // following sequence:
1829      // mov r4, sp
1830      // bic r4, r4, MaxAlign
1831      // mov sp, r4
1832      // FIXME: It will be better just to find spare register here.
1833      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1834        .addReg(ARM::SP, RegState::Kill);
1835      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1836                                          TII.get(ARM::t2BICri), ARM::R4)
1837                                  .addReg(ARM::R4, RegState::Kill)
1838                                  .addImm(MaxAlign-1)));
1839      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1840        .addReg(ARM::R4, RegState::Kill);
1841    }
1842
1843    AFI->setShouldRestoreSPFromFP(true);
1844  }
1845
1846  // If we need a base pointer, set it up here. It's whatever the value
1847  // of the stack pointer is at this point. Any variable size objects
1848  // will be allocated after this, so we can still use the base pointer
1849  // to reference locals.
1850  if (hasBasePointer(MF)) {
1851    if (isARM)
1852      BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr)
1853        .addReg(ARM::SP)
1854        .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1855    else
1856      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
1857        .addReg(ARM::SP);
1858  }
1859
1860  // If the frame has variable sized objects then the epilogue must restore
1861  // the sp from fp.
1862  if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1863    AFI->setShouldRestoreSPFromFP(true);
1864}
1865
1866static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1867  for (unsigned i = 0; CSRegs[i]; ++i)
1868    if (Reg == CSRegs[i])
1869      return true;
1870  return false;
1871}
1872
1873static bool isCSRestore(MachineInstr *MI,
1874                        const ARMBaseInstrInfo &TII,
1875                        const unsigned *CSRegs) {
1876
1877  // Integer spill area is handled with pop.
1878  if (MI->getOpcode() == ARM::tRestore ||
1879      MI->getOpcode() == ARM::tPOP) {
1880    // The first two operands are predicates. The last two are
1881    // imp-def and imp-use of SP. Check everything in between.
1882    for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i)
1883      if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
1884        return false;
1885      return true;
1886  }
1887
1888  // Or if this is a fp reg spill.
1889  if (MI->getOpcode() == (int)ARM::VLDRD &&
1890      MI->getOperand(1).isFI() &&
1891      isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
1892    return true;
1893
1894  return false;
1895}
1896
1897void ARMBaseRegisterInfo::
1898emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1899  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1900  assert(MBBI->getDesc().isReturn() &&
1901         "Can only insert epilog into returning blocks");
1902  unsigned RetOpcode = MBBI->getOpcode();
1903  DebugLoc dl = MBBI->getDebugLoc();
1904  MachineFrameInfo *MFI = MF.getFrameInfo();
1905  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1906  assert(!AFI->isThumb1OnlyFunction() &&
1907         "This emitEpilogue does not support Thumb1!");
1908  bool isARM = !AFI->isThumbFunction();
1909
1910  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1911  int NumBytes = (int)MFI->getStackSize();
1912
1913  if (!AFI->hasStackFrame()) {
1914    if (NumBytes != 0)
1915      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1916  } else {
1917    // Unwind MBBI to point to first LDR / VLDRD.
1918    const unsigned *CSRegs = getCalleeSavedRegs();
1919    if (MBBI != MBB.begin()) {
1920      do
1921        --MBBI;
1922      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1923      if (!isCSRestore(MBBI, TII, CSRegs))
1924        ++MBBI;
1925    }
1926
1927    // Move SP to start of FP callee save spill area.
1928    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1929                 AFI->getGPRCalleeSavedArea2Size() +
1930                 AFI->getDPRCalleeSavedAreaSize());
1931
1932    // Reset SP based on frame pointer only if the stack frame extends beyond
1933    // frame pointer stack slot or target is ELF and the function has FP.
1934    if (AFI->shouldRestoreSPFromFP()) {
1935      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1936      if (NumBytes) {
1937        if (isARM)
1938          emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1939                                  ARMCC::AL, 0, TII);
1940        else
1941          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1942                                 ARMCC::AL, 0, TII);
1943      } else {
1944        // Thumb2 or ARM.
1945        if (isARM)
1946          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1947            .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1948        else
1949          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1950            .addReg(FramePtr);
1951      }
1952    } else if (NumBytes)
1953      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1954
1955    // Move SP to start of integer callee save spill area 2.
1956    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1957    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1958
1959    // Move SP to start of integer callee save spill area 1.
1960    movePastCSLoadStoreOps(MBB, MBBI, ARM::tPOP, 0, 2, STI);
1961    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1962  }
1963
1964  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1965      RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1966    // Tail call return: adjust the stack pointer and jump to callee.
1967    MBBI = prior(MBB.end());
1968    MachineOperand &JumpTarget = MBBI->getOperand(0);
1969
1970    // Jump to label or value in register.
1971    if (RetOpcode == ARM::TCRETURNdi) {
1972      BuildMI(MBB, MBBI, dl,
1973            TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1974        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1975                         JumpTarget.getTargetFlags());
1976    } else if (RetOpcode == ARM::TCRETURNdiND) {
1977      BuildMI(MBB, MBBI, dl,
1978            TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1979        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1980                         JumpTarget.getTargetFlags());
1981    } else if (RetOpcode == ARM::TCRETURNri) {
1982      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1983        addReg(JumpTarget.getReg(), RegState::Kill);
1984    } else if (RetOpcode == ARM::TCRETURNriND) {
1985      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1986        addReg(JumpTarget.getReg(), RegState::Kill);
1987    }
1988
1989    MachineInstr *NewMI = prior(MBBI);
1990    for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1991      NewMI->addOperand(MBBI->getOperand(i));
1992
1993    // Delete the pseudo instruction TCRETURN.
1994    MBB.erase(MBBI);
1995  }
1996
1997  if (VARegSaveSize)
1998    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1999}
2000
2001#include "ARMGenRegisterInfo.inc"
2002