ARMBaseRegisterInfo.cpp revision b000d683c822bab7bed608937048b24b4b6db551 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46}
47
48using namespace llvm;
49
50unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
51                                                   bool *isSPVFP) {
52  if (isSPVFP)
53    *isSPVFP = false;
54
55  using namespace ARM;
56  switch (RegEnum) {
57  default:
58    llvm_unreachable("Unknown ARM register!");
59  case R0:  case D0:  case Q0:  return 0;
60  case R1:  case D1:  case Q1:  return 1;
61  case R2:  case D2:  case Q2:  return 2;
62  case R3:  case D3:  case Q3:  return 3;
63  case R4:  case D4:  case Q4:  return 4;
64  case R5:  case D5:  case Q5:  return 5;
65  case R6:  case D6:  case Q6:  return 6;
66  case R7:  case D7:  case Q7:  return 7;
67  case R8:  case D8:  case Q8:  return 8;
68  case R9:  case D9:  case Q9:  return 9;
69  case R10: case D10: case Q10: return 10;
70  case R11: case D11: case Q11: return 11;
71  case R12: case D12: case Q12: return 12;
72  case SP:  case D13: case Q13: return 13;
73  case LR:  case D14: case Q14: return 14;
74  case PC:  case D15: case Q15: return 15;
75
76  case D16: return 16;
77  case D17: return 17;
78  case D18: return 18;
79  case D19: return 19;
80  case D20: return 20;
81  case D21: return 21;
82  case D22: return 22;
83  case D23: return 23;
84  case D24: return 24;
85  case D25: return 25;
86  case D26: return 26;
87  case D27: return 27;
88  case D28: return 28;
89  case D29: return 29;
90  case D30: return 30;
91  case D31: return 31;
92
93  case S0: case S1: case S2: case S3:
94  case S4: case S5: case S6: case S7:
95  case S8: case S9: case S10: case S11:
96  case S12: case S13: case S14: case S15:
97  case S16: case S17: case S18: case S19:
98  case S20: case S21: case S22: case S23:
99  case S24: case S25: case S26: case S27:
100  case S28: case S29: case S30: case S31: {
101    if (isSPVFP)
102      *isSPVFP = true;
103    switch (RegEnum) {
104    default: return 0; // Avoid compile time warning.
105    case S0: return 0;
106    case S1: return 1;
107    case S2: return 2;
108    case S3: return 3;
109    case S4: return 4;
110    case S5: return 5;
111    case S6: return 6;
112    case S7: return 7;
113    case S8: return 8;
114    case S9: return 9;
115    case S10: return 10;
116    case S11: return 11;
117    case S12: return 12;
118    case S13: return 13;
119    case S14: return 14;
120    case S15: return 15;
121    case S16: return 16;
122    case S17: return 17;
123    case S18: return 18;
124    case S19: return 19;
125    case S20: return 20;
126    case S21: return 21;
127    case S22: return 22;
128    case S23: return 23;
129    case S24: return 24;
130    case S25: return 25;
131    case S26: return 26;
132    case S27: return 27;
133    case S28: return 28;
134    case S29: return 29;
135    case S30: return 30;
136    case S31: return 31;
137    }
138  }
139  }
140}
141
142ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143                                         const ARMSubtarget &sti)
144  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
145    TII(tii), STI(sti),
146    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
147}
148
149const unsigned*
150ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151  static const unsigned CalleeSavedRegs[] = {
152    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
154
155    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
157    0
158  };
159
160  static const unsigned DarwinCalleeSavedRegs[] = {
161    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
162    // register.
163    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
164    ARM::R11, ARM::R10, ARM::R8,
165
166    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
168    0
169  };
170  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
171}
172
173BitVector ARMBaseRegisterInfo::
174getReservedRegs(const MachineFunction &MF) const {
175  // FIXME: avoid re-calculating this everytime.
176  BitVector Reserved(getNumRegs());
177  Reserved.set(ARM::SP);
178  Reserved.set(ARM::PC);
179  Reserved.set(ARM::FPSCR);
180  if (STI.isTargetDarwin() || hasFP(MF))
181    Reserved.set(FramePtr);
182  // Some targets reserve R9.
183  if (STI.isR9Reserved())
184    Reserved.set(ARM::R9);
185  return Reserved;
186}
187
188bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
189                                        unsigned Reg) const {
190  switch (Reg) {
191  default: break;
192  case ARM::SP:
193  case ARM::PC:
194    return true;
195  case ARM::R7:
196  case ARM::R11:
197    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
198      return true;
199    break;
200  case ARM::R9:
201    return STI.isR9Reserved();
202  }
203
204  return false;
205}
206
207const TargetRegisterClass *
208ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
209                                              const TargetRegisterClass *B,
210                                              unsigned SubIdx) const {
211  switch (SubIdx) {
212  default: return 0;
213  case ARM::ssub_0:
214  case ARM::ssub_1:
215  case ARM::ssub_2:
216  case ARM::ssub_3: {
217    // S sub-registers.
218    if (A->getSize() == 8) {
219      if (B == &ARM::SPR_8RegClass)
220        return &ARM::DPR_8RegClass;
221      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
222      if (A == &ARM::DPR_8RegClass)
223        return A;
224      return &ARM::DPR_VFP2RegClass;
225    }
226
227    if (A->getSize() == 16) {
228      if (B == &ARM::SPR_8RegClass)
229        return &ARM::QPR_8RegClass;
230      return &ARM::QPR_VFP2RegClass;
231    }
232
233    if (A->getSize() == 32) {
234      if (B == &ARM::SPR_8RegClass)
235        return 0;  // Do not allow coalescing!
236      return &ARM::QQPR_VFP2RegClass;
237    }
238
239    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
240    return 0;  // Do not allow coalescing!
241  }
242  case ARM::dsub_0:
243  case ARM::dsub_1:
244  case ARM::dsub_2:
245  case ARM::dsub_3: {
246    // D sub-registers.
247    if (A->getSize() == 16) {
248      if (B == &ARM::DPR_VFP2RegClass)
249        return &ARM::QPR_VFP2RegClass;
250      if (B == &ARM::DPR_8RegClass)
251        return 0;  // Do not allow coalescing!
252      return A;
253    }
254
255    if (A->getSize() == 32) {
256      if (B == &ARM::DPR_VFP2RegClass)
257        return &ARM::QQPR_VFP2RegClass;
258      if (B == &ARM::DPR_8RegClass)
259        return 0;  // Do not allow coalescing!
260      return A;
261    }
262
263    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
264    if (B != &ARM::DPRRegClass)
265      return 0;  // Do not allow coalescing!
266    return A;
267  }
268  case ARM::dsub_4:
269  case ARM::dsub_5:
270  case ARM::dsub_6:
271  case ARM::dsub_7: {
272    // D sub-registers of QQQQ registers.
273    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
274      return A;
275    return 0;  // Do not allow coalescing!
276  }
277
278  case ARM::qsub_0:
279  case ARM::qsub_1: {
280    // Q sub-registers.
281    if (A->getSize() == 32) {
282      if (B == &ARM::QPR_VFP2RegClass)
283        return &ARM::QQPR_VFP2RegClass;
284      if (B == &ARM::QPR_8RegClass)
285        return 0;  // Do not allow coalescing!
286      return A;
287    }
288
289    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
290    if (B == &ARM::QPRRegClass)
291      return A;
292    return 0;  // Do not allow coalescing!
293  }
294  case ARM::qsub_2:
295  case ARM::qsub_3: {
296    // Q sub-registers of QQQQ registers.
297    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
298      return A;
299    return 0;  // Do not allow coalescing!
300  }
301  }
302  return 0;
303}
304
305bool
306ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
307                                          SmallVectorImpl<unsigned> &SubIndices,
308                                          unsigned &NewSubIdx) const {
309
310  unsigned Size = RC->getSize() * 8;
311  if (Size < 6)
312    return 0;
313
314  NewSubIdx = 0;  // Whole register.
315  unsigned NumRegs = SubIndices.size();
316  if (NumRegs == 8) {
317    // 8 D registers -> 1 QQQQ register.
318    return (Size == 512 &&
319            SubIndices[0] == ARM::dsub_0 &&
320            SubIndices[1] == ARM::dsub_1 &&
321            SubIndices[2] == ARM::dsub_2 &&
322            SubIndices[3] == ARM::dsub_3 &&
323            SubIndices[4] == ARM::dsub_4 &&
324            SubIndices[5] == ARM::dsub_5 &&
325            SubIndices[6] == ARM::dsub_6 &&
326            SubIndices[7] == ARM::dsub_7);
327  } else if (NumRegs == 4) {
328    if (SubIndices[0] == ARM::qsub_0) {
329      // 4 Q registers -> 1 QQQQ register.
330      return (Size == 512 &&
331              SubIndices[1] == ARM::qsub_1 &&
332              SubIndices[2] == ARM::qsub_2 &&
333              SubIndices[3] == ARM::qsub_3);
334    } else if (SubIndices[0] == ARM::dsub_0) {
335      // 4 D registers -> 1 QQ register.
336      if (Size >= 256 &&
337          SubIndices[1] == ARM::dsub_1 &&
338          SubIndices[2] == ARM::dsub_2 &&
339          SubIndices[3] == ARM::dsub_3) {
340        if (Size == 512)
341          NewSubIdx = ARM::qqsub_0;
342        return true;
343      }
344    } else if (SubIndices[0] == ARM::dsub_4) {
345      // 4 D registers -> 1 QQ register (2nd).
346      if (Size == 512 &&
347          SubIndices[1] == ARM::dsub_5 &&
348          SubIndices[2] == ARM::dsub_6 &&
349          SubIndices[3] == ARM::dsub_7) {
350        NewSubIdx = ARM::qqsub_1;
351        return true;
352      }
353    } else if (SubIndices[0] == ARM::ssub_0) {
354      // 4 S registers -> 1 Q register.
355      if (Size >= 128 &&
356          SubIndices[1] == ARM::ssub_1 &&
357          SubIndices[2] == ARM::ssub_2 &&
358          SubIndices[3] == ARM::ssub_3) {
359        if (Size >= 256)
360          NewSubIdx = ARM::qsub_0;
361        return true;
362      }
363    }
364  } else if (NumRegs == 2) {
365    if (SubIndices[0] == ARM::qsub_0) {
366      // 2 Q registers -> 1 QQ register.
367      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
368        if (Size == 512)
369          NewSubIdx = ARM::qqsub_0;
370        return true;
371      }
372    } else if (SubIndices[0] == ARM::qsub_2) {
373      // 2 Q registers -> 1 QQ register (2nd).
374      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
375        NewSubIdx = ARM::qqsub_1;
376        return true;
377      }
378    } else if (SubIndices[0] == ARM::dsub_0) {
379      // 2 D registers -> 1 Q register.
380      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
381        if (Size >= 256)
382          NewSubIdx = ARM::qsub_0;
383        return true;
384      }
385    } else if (SubIndices[0] == ARM::dsub_2) {
386      // 2 D registers -> 1 Q register (2nd).
387      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
388        NewSubIdx = ARM::qsub_1;
389        return true;
390      }
391    } else if (SubIndices[0] == ARM::dsub_4) {
392      // 2 D registers -> 1 Q register (3rd).
393      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
394        NewSubIdx = ARM::qsub_2;
395        return true;
396      }
397    } else if (SubIndices[0] == ARM::dsub_6) {
398      // 2 D registers -> 1 Q register (3rd).
399      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
400        NewSubIdx = ARM::qsub_3;
401        return true;
402      }
403    } else if (SubIndices[0] == ARM::ssub_0) {
404      // 2 S registers -> 1 D register.
405      if (SubIndices[1] == ARM::ssub_1) {
406        if (Size >= 128)
407          NewSubIdx = ARM::dsub_0;
408        return true;
409      }
410    } else if (SubIndices[0] == ARM::ssub_2) {
411      // 2 S registers -> 1 D register (2nd).
412      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
413        NewSubIdx = ARM::dsub_1;
414        return true;
415      }
416    }
417  }
418  return false;
419}
420
421
422const TargetRegisterClass *
423ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
424  return ARM::GPRRegisterClass;
425}
426
427/// getAllocationOrder - Returns the register allocation order for a specified
428/// register class in the form of a pair of TargetRegisterClass iterators.
429std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
430ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
431                                        unsigned HintType, unsigned HintReg,
432                                        const MachineFunction &MF) const {
433  // Alternative register allocation orders when favoring even / odd registers
434  // of register pairs.
435
436  // No FP, R9 is available.
437  static const unsigned GPREven1[] = {
438    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
439    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
440    ARM::R9, ARM::R11
441  };
442  static const unsigned GPROdd1[] = {
443    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
444    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
445    ARM::R8, ARM::R10
446  };
447
448  // FP is R7, R9 is available.
449  static const unsigned GPREven2[] = {
450    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
451    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
452    ARM::R9, ARM::R11
453  };
454  static const unsigned GPROdd2[] = {
455    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
456    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
457    ARM::R8, ARM::R10
458  };
459
460  // FP is R11, R9 is available.
461  static const unsigned GPREven3[] = {
462    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
463    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
464    ARM::R9
465  };
466  static const unsigned GPROdd3[] = {
467    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
468    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
469    ARM::R8
470  };
471
472  // No FP, R9 is not available.
473  static const unsigned GPREven4[] = {
474    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
475    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
476    ARM::R11
477  };
478  static const unsigned GPROdd4[] = {
479    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
480    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
481    ARM::R10
482  };
483
484  // FP is R7, R9 is not available.
485  static const unsigned GPREven5[] = {
486    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
487    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
488    ARM::R11
489  };
490  static const unsigned GPROdd5[] = {
491    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
492    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
493    ARM::R10
494  };
495
496  // FP is R11, R9 is not available.
497  static const unsigned GPREven6[] = {
498    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
499    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
500  };
501  static const unsigned GPROdd6[] = {
502    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
503    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
504  };
505
506
507  if (HintType == ARMRI::RegPairEven) {
508    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
509      // It's no longer possible to fulfill this hint. Return the default
510      // allocation order.
511      return std::make_pair(RC->allocation_order_begin(MF),
512                            RC->allocation_order_end(MF));
513
514    if (!STI.isTargetDarwin() && !hasFP(MF)) {
515      if (!STI.isR9Reserved())
516        return std::make_pair(GPREven1,
517                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
518      else
519        return std::make_pair(GPREven4,
520                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
521    } else if (FramePtr == ARM::R7) {
522      if (!STI.isR9Reserved())
523        return std::make_pair(GPREven2,
524                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
525      else
526        return std::make_pair(GPREven5,
527                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
528    } else { // FramePtr == ARM::R11
529      if (!STI.isR9Reserved())
530        return std::make_pair(GPREven3,
531                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
532      else
533        return std::make_pair(GPREven6,
534                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
535    }
536  } else if (HintType == ARMRI::RegPairOdd) {
537    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
538      // It's no longer possible to fulfill this hint. Return the default
539      // allocation order.
540      return std::make_pair(RC->allocation_order_begin(MF),
541                            RC->allocation_order_end(MF));
542
543    if (!STI.isTargetDarwin() && !hasFP(MF)) {
544      if (!STI.isR9Reserved())
545        return std::make_pair(GPROdd1,
546                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
547      else
548        return std::make_pair(GPROdd4,
549                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
550    } else if (FramePtr == ARM::R7) {
551      if (!STI.isR9Reserved())
552        return std::make_pair(GPROdd2,
553                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
554      else
555        return std::make_pair(GPROdd5,
556                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
557    } else { // FramePtr == ARM::R11
558      if (!STI.isR9Reserved())
559        return std::make_pair(GPROdd3,
560                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
561      else
562        return std::make_pair(GPROdd6,
563                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
564    }
565  }
566  return std::make_pair(RC->allocation_order_begin(MF),
567                        RC->allocation_order_end(MF));
568}
569
570/// ResolveRegAllocHint - Resolves the specified register allocation hint
571/// to a physical register. Returns the physical register if it is successful.
572unsigned
573ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
574                                         const MachineFunction &MF) const {
575  if (Reg == 0 || !isPhysicalRegister(Reg))
576    return 0;
577  if (Type == 0)
578    return Reg;
579  else if (Type == (unsigned)ARMRI::RegPairOdd)
580    // Odd register.
581    return getRegisterPairOdd(Reg, MF);
582  else if (Type == (unsigned)ARMRI::RegPairEven)
583    // Even register.
584    return getRegisterPairEven(Reg, MF);
585  return 0;
586}
587
588void
589ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
590                                        MachineFunction &MF) const {
591  MachineRegisterInfo *MRI = &MF.getRegInfo();
592  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
593  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
594       Hint.first == (unsigned)ARMRI::RegPairEven) &&
595      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
596    // If 'Reg' is one of the even / odd register pair and it's now changed
597    // (e.g. coalesced) into a different register. The other register of the
598    // pair allocation hint must be updated to reflect the relationship
599    // change.
600    unsigned OtherReg = Hint.second;
601    Hint = MRI->getRegAllocationHint(OtherReg);
602    if (Hint.second == Reg)
603      // Make sure the pair has not already divorced.
604      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
605  }
606}
607
608/// hasFP - Return true if the specified function should have a dedicated frame
609/// pointer register.  This is true if the function has variable sized allocas
610/// or if frame pointer elimination is disabled.
611///
612bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
613  const MachineFrameInfo *MFI = MF.getFrameInfo();
614  // Always eliminate non-leaf frame pointers.
615  return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
616          needsStackRealignment(MF) ||
617          MFI->hasVarSizedObjects() ||
618          MFI->isFrameAddressTaken());
619}
620
621bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
622  const MachineFrameInfo *MFI = MF.getFrameInfo();
623  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
624  return (RealignStack &&
625          !AFI->isThumb1OnlyFunction() &&
626          !MFI->hasVarSizedObjects());
627}
628
629bool ARMBaseRegisterInfo::
630needsStackRealignment(const MachineFunction &MF) const {
631  const MachineFrameInfo *MFI = MF.getFrameInfo();
632  const Function *F = MF.getFunction();
633  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
634  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
635  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
636                               F->hasFnAttr(Attribute::StackAlignment));
637
638  // FIXME: Currently we don't support stack realignment for functions with
639  //        variable-sized allocas.
640  // FIXME: It's more complicated than this...
641  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
642    report_fatal_error(
643      "Stack realignment in presense of dynamic allocas is not supported");
644
645  // FIXME: This probably isn't the right place for this.
646  if (0 && requiresRealignment && AFI->isThumb1OnlyFunction())
647    report_fatal_error(
648      "Stack realignment in thumb1 functions is not supported");
649
650  return requiresRealignment && canRealignStack(MF);
651}
652
653bool ARMBaseRegisterInfo::
654cannotEliminateFrame(const MachineFunction &MF) const {
655  const MachineFrameInfo *MFI = MF.getFrameInfo();
656  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
657    return true;
658  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
659    || needsStackRealignment(MF);
660}
661
662/// estimateStackSize - Estimate and return the size of the frame.
663static unsigned estimateStackSize(MachineFunction &MF) {
664  const MachineFrameInfo *FFI = MF.getFrameInfo();
665  int Offset = 0;
666  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
667    int FixedOff = -FFI->getObjectOffset(i);
668    if (FixedOff > Offset) Offset = FixedOff;
669  }
670  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
671    if (FFI->isDeadObjectIndex(i))
672      continue;
673    Offset += FFI->getObjectSize(i);
674    unsigned Align = FFI->getObjectAlignment(i);
675    // Adjust to alignment boundary
676    Offset = (Offset+Align-1)/Align*Align;
677  }
678  return (unsigned)Offset;
679}
680
681/// estimateRSStackSizeLimit - Look at each instruction that references stack
682/// frames and return the stack size limit beyond which some of these
683/// instructions will require a scratch register during their expansion later.
684unsigned
685ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
686  unsigned Limit = (1 << 12) - 1;
687  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
688    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
689         I != E; ++I) {
690      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
691        if (!I->getOperand(i).isFI()) continue;
692
693        // When using ADDri to get the address of a stack object, 255 is the
694        // largest offset guaranteed to fit in the immediate offset.
695        if (I->getOpcode() == ARM::ADDri) {
696          Limit = std::min(Limit, (1U << 8) - 1);
697          break;
698        }
699
700        // Otherwise check the addressing mode.
701        switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
702        case ARMII::AddrMode3:
703        case ARMII::AddrModeT2_i8:
704          Limit = std::min(Limit, (1U << 8) - 1);
705          break;
706        case ARMII::AddrMode5:
707        case ARMII::AddrModeT2_i8s4:
708          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
709          break;
710        case ARMII::AddrModeT2_i12:
711          if (hasFP(MF)) Limit = std::min(Limit, (1U << 8) - 1);
712          break;
713        case ARMII::AddrMode6:
714          // Addressing mode 6 (load/store) instructions can't encode an
715          // immediate offset for stack references.
716          return 0;
717        default:
718          break;
719        }
720        break; // At most one FI per instruction
721      }
722    }
723  }
724
725  return Limit;
726}
727
728static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
729                                       const ARMBaseInstrInfo &TII) {
730  unsigned FnSize = 0;
731  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
732       MBBI != E; ++MBBI) {
733    const MachineBasicBlock &MBB = *MBBI;
734    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
735         I != E; ++I)
736      FnSize += TII.GetInstSizeInBytes(I);
737  }
738  return FnSize;
739}
740
741void
742ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
743                                                       RegScavenger *RS) const {
744  // This tells PEI to spill the FP as if it is any other callee-save register
745  // to take advantage the eliminateFrameIndex machinery. This also ensures it
746  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
747  // to combine multiple loads / stores.
748  bool CanEliminateFrame = true;
749  bool CS1Spilled = false;
750  bool LRSpilled = false;
751  unsigned NumGPRSpills = 0;
752  SmallVector<unsigned, 4> UnspilledCS1GPRs;
753  SmallVector<unsigned, 4> UnspilledCS2GPRs;
754  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
755  MachineFrameInfo *MFI = MF.getFrameInfo();
756
757  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
758  // scratch register.
759  // FIXME: It will be better just to find spare register here.
760  if (needsStackRealignment(MF) &&
761      AFI->isThumb2Function())
762    MF.getRegInfo().setPhysRegUsed(ARM::R4);
763
764  // Spill LR if Thumb1 function uses variable length argument lists.
765  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
766    MF.getRegInfo().setPhysRegUsed(ARM::LR);
767
768  // Don't spill FP if the frame can be eliminated. This is determined
769  // by scanning the callee-save registers to see if any is used.
770  const unsigned *CSRegs = getCalleeSavedRegs();
771  for (unsigned i = 0; CSRegs[i]; ++i) {
772    unsigned Reg = CSRegs[i];
773    bool Spilled = false;
774    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
775      AFI->setCSRegisterIsSpilled(Reg);
776      Spilled = true;
777      CanEliminateFrame = false;
778    } else {
779      // Check alias registers too.
780      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
781        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
782          Spilled = true;
783          CanEliminateFrame = false;
784        }
785      }
786    }
787
788    if (!ARM::GPRRegisterClass->contains(Reg))
789      continue;
790
791    if (Spilled) {
792      NumGPRSpills++;
793
794      if (!STI.isTargetDarwin()) {
795        if (Reg == ARM::LR)
796          LRSpilled = true;
797        CS1Spilled = true;
798        continue;
799      }
800
801      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
802      switch (Reg) {
803      case ARM::LR:
804        LRSpilled = true;
805        // Fallthrough
806      case ARM::R4:
807      case ARM::R5:
808      case ARM::R6:
809      case ARM::R7:
810        CS1Spilled = true;
811        break;
812      default:
813        break;
814      }
815    } else {
816      if (!STI.isTargetDarwin()) {
817        UnspilledCS1GPRs.push_back(Reg);
818        continue;
819      }
820
821      switch (Reg) {
822      case ARM::R4:
823      case ARM::R5:
824      case ARM::R6:
825      case ARM::R7:
826      case ARM::LR:
827        UnspilledCS1GPRs.push_back(Reg);
828        break;
829      default:
830        UnspilledCS2GPRs.push_back(Reg);
831        break;
832      }
833    }
834  }
835
836  bool ForceLRSpill = false;
837  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
838    unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
839    // Force LR to be spilled if the Thumb function size is > 2048. This enables
840    // use of BL to implement far jump. If it turns out that it's not needed
841    // then the branch fix up path will undo it.
842    if (FnSize >= (1 << 11)) {
843      CanEliminateFrame = false;
844      ForceLRSpill = true;
845    }
846  }
847
848  // If any of the stack slot references may be out of range of an immediate
849  // offset, make sure a register (or a spill slot) is available for the
850  // register scavenger. Note that if we're indexing off the frame pointer, the
851  // effective stack size is 4 bytes larger since the FP points to the stack
852  // slot of the previous FP. Also, if we have variable sized objects in the
853  // function, stack slot references will often be negative, and some of
854  // our instructions are positive-offset only, so conservatively consider
855  // that case to want a spill slot (or register) as well. Similarly, if
856  // the function adjusts the stack pointer during execution and the
857  // adjustments aren't already part of our stack size estimate, our offset
858  // calculations may be off, so be conservative.
859  // FIXME: We could add logic to be more precise about negative offsets
860  //        and which instructions will need a scratch register for them. Is it
861  //        worth the effort and added fragility?
862  bool BigStack =
863    (RS && (estimateStackSize(MF) + (hasFP(MF) ? 4:0) >=
864            estimateRSStackSizeLimit(MF)))
865    || MFI->hasVarSizedObjects()
866    || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
867
868  bool ExtraCSSpill = false;
869  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
870    AFI->setHasStackFrame(true);
871
872    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
873    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
874    if (!LRSpilled && CS1Spilled) {
875      MF.getRegInfo().setPhysRegUsed(ARM::LR);
876      AFI->setCSRegisterIsSpilled(ARM::LR);
877      NumGPRSpills++;
878      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
879                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
880      ForceLRSpill = false;
881      ExtraCSSpill = true;
882    }
883
884    // Darwin ABI requires FP to point to the stack slot that contains the
885    // previous FP.
886    if (STI.isTargetDarwin() || hasFP(MF)) {
887      MF.getRegInfo().setPhysRegUsed(FramePtr);
888      NumGPRSpills++;
889    }
890
891    // If stack and double are 8-byte aligned and we are spilling an odd number
892    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
893    // the integer and double callee save areas.
894    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
895    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
896      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
897        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
898          unsigned Reg = UnspilledCS1GPRs[i];
899          // Don't spill high register if the function is thumb1
900          if (!AFI->isThumb1OnlyFunction() ||
901              isARMLowRegister(Reg) || Reg == ARM::LR) {
902            MF.getRegInfo().setPhysRegUsed(Reg);
903            AFI->setCSRegisterIsSpilled(Reg);
904            if (!isReservedReg(MF, Reg))
905              ExtraCSSpill = true;
906            break;
907          }
908        }
909      } else if (!UnspilledCS2GPRs.empty() &&
910                 !AFI->isThumb1OnlyFunction()) {
911        unsigned Reg = UnspilledCS2GPRs.front();
912        MF.getRegInfo().setPhysRegUsed(Reg);
913        AFI->setCSRegisterIsSpilled(Reg);
914        if (!isReservedReg(MF, Reg))
915          ExtraCSSpill = true;
916      }
917    }
918
919    // Estimate if we might need to scavenge a register at some point in order
920    // to materialize a stack offset. If so, either spill one additional
921    // callee-saved register or reserve a special spill slot to facilitate
922    // register scavenging. Thumb1 needs a spill slot for stack pointer
923    // adjustments also, even when the frame itself is small.
924    if (BigStack && !ExtraCSSpill) {
925      // If any non-reserved CS register isn't spilled, just spill one or two
926      // extra. That should take care of it!
927      unsigned NumExtras = TargetAlign / 4;
928      SmallVector<unsigned, 2> Extras;
929      while (NumExtras && !UnspilledCS1GPRs.empty()) {
930        unsigned Reg = UnspilledCS1GPRs.back();
931        UnspilledCS1GPRs.pop_back();
932        if (!isReservedReg(MF, Reg) &&
933            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
934             Reg == ARM::LR)) {
935          Extras.push_back(Reg);
936          NumExtras--;
937        }
938      }
939      // For non-Thumb1 functions, also check for hi-reg CS registers
940      if (!AFI->isThumb1OnlyFunction()) {
941        while (NumExtras && !UnspilledCS2GPRs.empty()) {
942          unsigned Reg = UnspilledCS2GPRs.back();
943          UnspilledCS2GPRs.pop_back();
944          if (!isReservedReg(MF, Reg)) {
945            Extras.push_back(Reg);
946            NumExtras--;
947          }
948        }
949      }
950      if (Extras.size() && NumExtras == 0) {
951        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
952          MF.getRegInfo().setPhysRegUsed(Extras[i]);
953          AFI->setCSRegisterIsSpilled(Extras[i]);
954        }
955      } else if (!AFI->isThumb1OnlyFunction()) {
956        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
957        // closest to SP or frame pointer.
958        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
959        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
960                                                           RC->getAlignment(),
961                                                           false));
962      }
963    }
964  }
965
966  if (ForceLRSpill) {
967    MF.getRegInfo().setPhysRegUsed(ARM::LR);
968    AFI->setCSRegisterIsSpilled(ARM::LR);
969    AFI->setLRIsSpilledForFarJump(true);
970  }
971}
972
973unsigned ARMBaseRegisterInfo::getRARegister() const {
974  return ARM::LR;
975}
976
977unsigned
978ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
979  if (STI.isTargetDarwin() || hasFP(MF))
980    return FramePtr;
981  return ARM::SP;
982}
983
984// Provide a base+offset reference to an FI slot for debug info. It's the
985// same as what we use for resolving the code-gen references for now.
986// FIXME: This can go wrong when references are SP-relative and simple call
987//        frames aren't used.
988int
989ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
990                                            unsigned &FrameReg) const {
991  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
992}
993
994int
995ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
996                                                int FI,
997                                                unsigned &FrameReg,
998                                                int SPAdj) const {
999  const MachineFrameInfo *MFI = MF.getFrameInfo();
1000  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1001  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
1002  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1003  bool isFixed = MFI->isFixedObjectIndex(FI);
1004
1005  FrameReg = ARM::SP;
1006  Offset += SPAdj;
1007  if (AFI->isGPRCalleeSavedArea1Frame(FI))
1008    return Offset - AFI->getGPRCalleeSavedArea1Offset();
1009  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
1010    return Offset - AFI->getGPRCalleeSavedArea2Offset();
1011  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1012    return Offset - AFI->getDPRCalleeSavedAreaOffset();
1013
1014  // When dynamically realigning the stack, use the frame pointer for
1015  // parameters, and the stack pointer for locals.
1016  if (needsStackRealignment(MF)) {
1017    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1018    if (isFixed) {
1019      FrameReg = getFrameRegister(MF);
1020      Offset = FPOffset;
1021    }
1022    return Offset;
1023  }
1024
1025  // If there is a frame pointer, use it when we can.
1026  if (hasFP(MF) && AFI->hasStackFrame()) {
1027    // Use frame pointer to reference fixed objects. Use it for locals if
1028    // there are VLAs (and thus the SP isn't reliable as a base).
1029    if (isFixed || MFI->hasVarSizedObjects()) {
1030      FrameReg = getFrameRegister(MF);
1031      Offset = FPOffset;
1032    } else if (AFI->isThumb2Function()) {
1033      // In Thumb2 mode, the negative offset is very limited. Try to avoid
1034      // out of range references.
1035      if (FPOffset >= -255 && FPOffset < 0) {
1036        FrameReg = getFrameRegister(MF);
1037        Offset = FPOffset;
1038      }
1039    } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1040      // Otherwise, use SP or FP, whichever is closer to the stack slot.
1041      FrameReg = getFrameRegister(MF);
1042      Offset = FPOffset;
1043    }
1044  }
1045  return Offset;
1046}
1047
1048int
1049ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1050                                         int FI) const {
1051  unsigned FrameReg;
1052  return getFrameIndexReference(MF, FI, FrameReg);
1053}
1054
1055unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1056  llvm_unreachable("What is the exception register");
1057  return 0;
1058}
1059
1060unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1061  llvm_unreachable("What is the exception handler register");
1062  return 0;
1063}
1064
1065int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1066  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1067}
1068
1069unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1070                                              const MachineFunction &MF) const {
1071  switch (Reg) {
1072  default: break;
1073  // Return 0 if either register of the pair is a special register.
1074  // So no R12, etc.
1075  case ARM::R1:
1076    return ARM::R0;
1077  case ARM::R3:
1078    return ARM::R2;
1079  case ARM::R5:
1080    return ARM::R4;
1081  case ARM::R7:
1082    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
1083  case ARM::R9:
1084    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1085  case ARM::R11:
1086    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1087
1088  case ARM::S1:
1089    return ARM::S0;
1090  case ARM::S3:
1091    return ARM::S2;
1092  case ARM::S5:
1093    return ARM::S4;
1094  case ARM::S7:
1095    return ARM::S6;
1096  case ARM::S9:
1097    return ARM::S8;
1098  case ARM::S11:
1099    return ARM::S10;
1100  case ARM::S13:
1101    return ARM::S12;
1102  case ARM::S15:
1103    return ARM::S14;
1104  case ARM::S17:
1105    return ARM::S16;
1106  case ARM::S19:
1107    return ARM::S18;
1108  case ARM::S21:
1109    return ARM::S20;
1110  case ARM::S23:
1111    return ARM::S22;
1112  case ARM::S25:
1113    return ARM::S24;
1114  case ARM::S27:
1115    return ARM::S26;
1116  case ARM::S29:
1117    return ARM::S28;
1118  case ARM::S31:
1119    return ARM::S30;
1120
1121  case ARM::D1:
1122    return ARM::D0;
1123  case ARM::D3:
1124    return ARM::D2;
1125  case ARM::D5:
1126    return ARM::D4;
1127  case ARM::D7:
1128    return ARM::D6;
1129  case ARM::D9:
1130    return ARM::D8;
1131  case ARM::D11:
1132    return ARM::D10;
1133  case ARM::D13:
1134    return ARM::D12;
1135  case ARM::D15:
1136    return ARM::D14;
1137  case ARM::D17:
1138    return ARM::D16;
1139  case ARM::D19:
1140    return ARM::D18;
1141  case ARM::D21:
1142    return ARM::D20;
1143  case ARM::D23:
1144    return ARM::D22;
1145  case ARM::D25:
1146    return ARM::D24;
1147  case ARM::D27:
1148    return ARM::D26;
1149  case ARM::D29:
1150    return ARM::D28;
1151  case ARM::D31:
1152    return ARM::D30;
1153  }
1154
1155  return 0;
1156}
1157
1158unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1159                                             const MachineFunction &MF) const {
1160  switch (Reg) {
1161  default: break;
1162  // Return 0 if either register of the pair is a special register.
1163  // So no R12, etc.
1164  case ARM::R0:
1165    return ARM::R1;
1166  case ARM::R2:
1167    return ARM::R3;
1168  case ARM::R4:
1169    return ARM::R5;
1170  case ARM::R6:
1171    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
1172  case ARM::R8:
1173    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1174  case ARM::R10:
1175    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1176
1177  case ARM::S0:
1178    return ARM::S1;
1179  case ARM::S2:
1180    return ARM::S3;
1181  case ARM::S4:
1182    return ARM::S5;
1183  case ARM::S6:
1184    return ARM::S7;
1185  case ARM::S8:
1186    return ARM::S9;
1187  case ARM::S10:
1188    return ARM::S11;
1189  case ARM::S12:
1190    return ARM::S13;
1191  case ARM::S14:
1192    return ARM::S15;
1193  case ARM::S16:
1194    return ARM::S17;
1195  case ARM::S18:
1196    return ARM::S19;
1197  case ARM::S20:
1198    return ARM::S21;
1199  case ARM::S22:
1200    return ARM::S23;
1201  case ARM::S24:
1202    return ARM::S25;
1203  case ARM::S26:
1204    return ARM::S27;
1205  case ARM::S28:
1206    return ARM::S29;
1207  case ARM::S30:
1208    return ARM::S31;
1209
1210  case ARM::D0:
1211    return ARM::D1;
1212  case ARM::D2:
1213    return ARM::D3;
1214  case ARM::D4:
1215    return ARM::D5;
1216  case ARM::D6:
1217    return ARM::D7;
1218  case ARM::D8:
1219    return ARM::D9;
1220  case ARM::D10:
1221    return ARM::D11;
1222  case ARM::D12:
1223    return ARM::D13;
1224  case ARM::D14:
1225    return ARM::D15;
1226  case ARM::D16:
1227    return ARM::D17;
1228  case ARM::D18:
1229    return ARM::D19;
1230  case ARM::D20:
1231    return ARM::D21;
1232  case ARM::D22:
1233    return ARM::D23;
1234  case ARM::D24:
1235    return ARM::D25;
1236  case ARM::D26:
1237    return ARM::D27;
1238  case ARM::D28:
1239    return ARM::D29;
1240  case ARM::D30:
1241    return ARM::D31;
1242  }
1243
1244  return 0;
1245}
1246
1247/// emitLoadConstPool - Emits a load from constpool to materialize the
1248/// specified immediate.
1249void ARMBaseRegisterInfo::
1250emitLoadConstPool(MachineBasicBlock &MBB,
1251                  MachineBasicBlock::iterator &MBBI,
1252                  DebugLoc dl,
1253                  unsigned DestReg, unsigned SubIdx, int Val,
1254                  ARMCC::CondCodes Pred,
1255                  unsigned PredReg) const {
1256  MachineFunction &MF = *MBB.getParent();
1257  MachineConstantPool *ConstantPool = MF.getConstantPool();
1258  const Constant *C =
1259        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1260  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1261
1262  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1263    .addReg(DestReg, getDefRegState(true), SubIdx)
1264    .addConstantPoolIndex(Idx)
1265    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1266}
1267
1268bool ARMBaseRegisterInfo::
1269requiresRegisterScavenging(const MachineFunction &MF) const {
1270  return true;
1271}
1272
1273bool ARMBaseRegisterInfo::
1274requiresFrameIndexScavenging(const MachineFunction &MF) const {
1275  return true;
1276}
1277
1278// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1279// not required, we reserve argument space for call sites in the function
1280// immediately on entry to the current function. This eliminates the need for
1281// add/sub sp brackets around call sites. Returns true if the call frame is
1282// included as part of the stack frame.
1283bool ARMBaseRegisterInfo::
1284hasReservedCallFrame(const MachineFunction &MF) const {
1285  const MachineFrameInfo *FFI = MF.getFrameInfo();
1286  unsigned CFSize = FFI->getMaxCallFrameSize();
1287  // It's not always a good idea to include the call frame as part of the
1288  // stack frame. ARM (especially Thumb) has small immediate offset to
1289  // address the stack frame. So a large call frame can cause poor codegen
1290  // and may even makes it impossible to scavenge a register.
1291  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1292    return false;
1293
1294  return !MF.getFrameInfo()->hasVarSizedObjects();
1295}
1296
1297// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1298// call frame pseudos can be simplified. Unlike most targets, having a FP
1299// is not sufficient here since we still may reference some objects via SP
1300// even when FP is available in Thumb2 mode.
1301bool ARMBaseRegisterInfo::
1302canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1303  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1304}
1305
1306static void
1307emitSPUpdate(bool isARM,
1308             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1309             DebugLoc dl, const ARMBaseInstrInfo &TII,
1310             int NumBytes,
1311             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1312  if (isARM)
1313    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1314                            Pred, PredReg, TII);
1315  else
1316    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1317                           Pred, PredReg, TII);
1318}
1319
1320
1321void ARMBaseRegisterInfo::
1322eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1323                              MachineBasicBlock::iterator I) const {
1324  if (!hasReservedCallFrame(MF)) {
1325    // If we have alloca, convert as follows:
1326    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1327    // ADJCALLSTACKUP   -> add, sp, sp, amount
1328    MachineInstr *Old = I;
1329    DebugLoc dl = Old->getDebugLoc();
1330    unsigned Amount = Old->getOperand(0).getImm();
1331    if (Amount != 0) {
1332      // We need to keep the stack aligned properly.  To do this, we round the
1333      // amount of space needed for the outgoing arguments up to the next
1334      // alignment boundary.
1335      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1336      Amount = (Amount+Align-1)/Align*Align;
1337
1338      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1339      assert(!AFI->isThumb1OnlyFunction() &&
1340             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1341      bool isARM = !AFI->isThumbFunction();
1342
1343      // Replace the pseudo instruction with a new instruction...
1344      unsigned Opc = Old->getOpcode();
1345      int PIdx = Old->findFirstPredOperandIdx();
1346      ARMCC::CondCodes Pred = (PIdx == -1)
1347        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1348      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1349        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1350        unsigned PredReg = Old->getOperand(2).getReg();
1351        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1352      } else {
1353        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1354        unsigned PredReg = Old->getOperand(3).getReg();
1355        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1356        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1357      }
1358    }
1359  }
1360  MBB.erase(I);
1361}
1362
1363unsigned
1364ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1365                                         int SPAdj, FrameIndexValue *Value,
1366                                         RegScavenger *RS) const {
1367  unsigned i = 0;
1368  MachineInstr &MI = *II;
1369  MachineBasicBlock &MBB = *MI.getParent();
1370  MachineFunction &MF = *MBB.getParent();
1371  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1372  assert(!AFI->isThumb1OnlyFunction() &&
1373         "This eliminateFrameIndex does not support Thumb1!");
1374
1375  while (!MI.getOperand(i).isFI()) {
1376    ++i;
1377    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1378  }
1379
1380  int FrameIndex = MI.getOperand(i).getIndex();
1381  unsigned FrameReg;
1382
1383  int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1384
1385  // Special handling of dbg_value instructions.
1386  if (MI.isDebugValue()) {
1387    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1388    MI.getOperand(i+1).ChangeToImmediate(Offset);
1389    return 0;
1390  }
1391
1392  // Modify MI as necessary to handle as much of 'Offset' as possible
1393  bool Done = false;
1394  if (!AFI->isThumbFunction())
1395    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1396  else {
1397    assert(AFI->isThumb2Function());
1398    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1399  }
1400  if (Done)
1401    return 0;
1402
1403  // If we get here, the immediate doesn't fit into the instruction.  We folded
1404  // as much as possible above, handle the rest, providing a register that is
1405  // SP+LargeImm.
1406  assert((Offset ||
1407          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1408          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1409         "This code isn't needed if offset already handled!");
1410
1411  unsigned ScratchReg = 0;
1412  int PIdx = MI.findFirstPredOperandIdx();
1413  ARMCC::CondCodes Pred = (PIdx == -1)
1414    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1415  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1416  if (Offset == 0)
1417    // Must be addrmode4/6.
1418    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1419  else {
1420    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1421    if (Value) {
1422      Value->first = FrameReg; // use the frame register as a kind indicator
1423      Value->second = Offset;
1424    }
1425    if (!AFI->isThumbFunction())
1426      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1427                              Offset, Pred, PredReg, TII);
1428    else {
1429      assert(AFI->isThumb2Function());
1430      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1431                             Offset, Pred, PredReg, TII);
1432    }
1433    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1434    if (!ReuseFrameIndexVals)
1435      ScratchReg = 0;
1436  }
1437  return ScratchReg;
1438}
1439
1440/// Move iterator past the next bunch of callee save load / store ops for
1441/// the particular spill area (1: integer area 1, 2: integer area 2,
1442/// 3: fp area, 0: don't care).
1443static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1444                                   MachineBasicBlock::iterator &MBBI,
1445                                   int Opc1, int Opc2, unsigned Area,
1446                                   const ARMSubtarget &STI) {
1447  while (MBBI != MBB.end() &&
1448         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1449         MBBI->getOperand(1).isFI()) {
1450    if (Area != 0) {
1451      bool Done = false;
1452      unsigned Category = 0;
1453      switch (MBBI->getOperand(0).getReg()) {
1454      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1455      case ARM::LR:
1456        Category = 1;
1457        break;
1458      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1459        Category = STI.isTargetDarwin() ? 2 : 1;
1460        break;
1461      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1462      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1463        Category = 3;
1464        break;
1465      default:
1466        Done = true;
1467        break;
1468      }
1469      if (Done || Category != Area)
1470        break;
1471    }
1472
1473    ++MBBI;
1474  }
1475}
1476
1477void ARMBaseRegisterInfo::
1478emitPrologue(MachineFunction &MF) const {
1479  MachineBasicBlock &MBB = MF.front();
1480  MachineBasicBlock::iterator MBBI = MBB.begin();
1481  MachineFrameInfo  *MFI = MF.getFrameInfo();
1482  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1483  assert(!AFI->isThumb1OnlyFunction() &&
1484         "This emitPrologue does not support Thumb1!");
1485  bool isARM = !AFI->isThumbFunction();
1486  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1487  unsigned NumBytes = MFI->getStackSize();
1488  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1489  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1490
1491  // Determine the sizes of each callee-save spill areas and record which frame
1492  // belongs to which callee-save spill areas.
1493  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1494  int FramePtrSpillFI = 0;
1495
1496  // Allocate the vararg register save area. This is not counted in NumBytes.
1497  if (VARegSaveSize)
1498    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1499
1500  if (!AFI->hasStackFrame()) {
1501    if (NumBytes != 0)
1502      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1503    return;
1504  }
1505
1506  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1507    unsigned Reg = CSI[i].getReg();
1508    int FI = CSI[i].getFrameIdx();
1509    switch (Reg) {
1510    case ARM::R4:
1511    case ARM::R5:
1512    case ARM::R6:
1513    case ARM::R7:
1514    case ARM::LR:
1515      if (Reg == FramePtr)
1516        FramePtrSpillFI = FI;
1517      AFI->addGPRCalleeSavedArea1Frame(FI);
1518      GPRCS1Size += 4;
1519      break;
1520    case ARM::R8:
1521    case ARM::R9:
1522    case ARM::R10:
1523    case ARM::R11:
1524      if (Reg == FramePtr)
1525        FramePtrSpillFI = FI;
1526      if (STI.isTargetDarwin()) {
1527        AFI->addGPRCalleeSavedArea2Frame(FI);
1528        GPRCS2Size += 4;
1529      } else {
1530        AFI->addGPRCalleeSavedArea1Frame(FI);
1531        GPRCS1Size += 4;
1532      }
1533      break;
1534    default:
1535      AFI->addDPRCalleeSavedAreaFrame(FI);
1536      DPRCSSize += 8;
1537    }
1538  }
1539
1540  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1541  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1542  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1543
1544  // Set FP to point to the stack slot that contains the previous FP.
1545  // For Darwin, FP is R7, which has now been stored in spill area 1.
1546  // Otherwise, if this is not Darwin, all the callee-saved registers go
1547  // into spill area 1, including the FP in R11.  In either case, it is
1548  // now safe to emit this assignment.
1549  if (STI.isTargetDarwin() || hasFP(MF)) {
1550    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1551    MachineInstrBuilder MIB =
1552      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1553      .addFrameIndex(FramePtrSpillFI).addImm(0);
1554    AddDefaultCC(AddDefaultPred(MIB));
1555  }
1556
1557  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1558  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1559
1560  // Build the new SUBri to adjust SP for FP callee-save spill area.
1561  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1562  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1563
1564  // Determine starting offsets of spill areas.
1565  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1566  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1567  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1568  if (STI.isTargetDarwin() || hasFP(MF))
1569    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1570                                NumBytes);
1571  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1572  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1573  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1574
1575  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1576  NumBytes = DPRCSOffset;
1577  if (NumBytes) {
1578    // Adjust SP after all the callee-save spills.
1579    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1580  }
1581
1582  if (STI.isTargetELF() && hasFP(MF)) {
1583    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1584                             AFI->getFramePtrSpillOffset());
1585  }
1586
1587  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1588  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1589  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1590
1591  // If we need dynamic stack realignment, do it here.
1592  if (needsStackRealignment(MF)) {
1593    unsigned MaxAlign = MFI->getMaxAlignment();
1594    assert (!AFI->isThumb1OnlyFunction());
1595    if (!AFI->isThumbFunction()) {
1596      // Emit bic sp, sp, MaxAlign
1597      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1598                                          TII.get(ARM::BICri), ARM::SP)
1599                                  .addReg(ARM::SP, RegState::Kill)
1600                                  .addImm(MaxAlign-1)));
1601    } else {
1602      // We cannot use sp as source/dest register here, thus we're emitting the
1603      // following sequence:
1604      // mov r4, sp
1605      // bic r4, r4, MaxAlign
1606      // mov sp, r4
1607      // FIXME: It will be better just to find spare register here.
1608      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1609        .addReg(ARM::SP, RegState::Kill);
1610      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1611                                          TII.get(ARM::t2BICri), ARM::R4)
1612                                  .addReg(ARM::R4, RegState::Kill)
1613                                  .addImm(MaxAlign-1)));
1614      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1615        .addReg(ARM::R4, RegState::Kill);
1616    }
1617  }
1618}
1619
1620static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1621  for (unsigned i = 0; CSRegs[i]; ++i)
1622    if (Reg == CSRegs[i])
1623      return true;
1624  return false;
1625}
1626
1627static bool isCSRestore(MachineInstr *MI,
1628                        const ARMBaseInstrInfo &TII,
1629                        const unsigned *CSRegs) {
1630  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1631           MI->getOpcode() == (int)ARM::LDR ||
1632           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1633          MI->getOperand(1).isFI() &&
1634          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1635}
1636
1637void ARMBaseRegisterInfo::
1638emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1639  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1640  assert(MBBI->getDesc().isReturn() &&
1641         "Can only insert epilog into returning blocks");
1642  unsigned RetOpcode = MBBI->getOpcode();
1643  DebugLoc dl = MBBI->getDebugLoc();
1644  MachineFrameInfo *MFI = MF.getFrameInfo();
1645  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1646  assert(!AFI->isThumb1OnlyFunction() &&
1647         "This emitEpilogue does not support Thumb1!");
1648  bool isARM = !AFI->isThumbFunction();
1649
1650  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1651  int NumBytes = (int)MFI->getStackSize();
1652
1653  if (!AFI->hasStackFrame()) {
1654    if (NumBytes != 0)
1655      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1656  } else {
1657    // Unwind MBBI to point to first LDR / VLDRD.
1658    const unsigned *CSRegs = getCalleeSavedRegs();
1659    if (MBBI != MBB.begin()) {
1660      do
1661        --MBBI;
1662      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1663      if (!isCSRestore(MBBI, TII, CSRegs))
1664        ++MBBI;
1665    }
1666
1667    // Move SP to start of FP callee save spill area.
1668    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1669                 AFI->getGPRCalleeSavedArea2Size() +
1670                 AFI->getDPRCalleeSavedAreaSize());
1671
1672    // Darwin ABI requires FP to point to the stack slot that contains the
1673    // previous FP.
1674    bool HasFP = hasFP(MF);
1675    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1676      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1677      // Reset SP based on frame pointer only if the stack frame extends beyond
1678      // frame pointer stack slot or target is ELF and the function has FP.
1679      if (HasFP ||
1680          AFI->getGPRCalleeSavedArea2Size() ||
1681          AFI->getDPRCalleeSavedAreaSize()  ||
1682          AFI->getDPRCalleeSavedAreaOffset()) {
1683        if (NumBytes) {
1684          if (isARM)
1685            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1686                                    ARMCC::AL, 0, TII);
1687          else
1688            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1689                                    ARMCC::AL, 0, TII);
1690        } else {
1691          // Thumb2 or ARM.
1692          if (isARM)
1693            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1694              .addReg(FramePtr)
1695              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1696          else
1697            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1698              .addReg(FramePtr);
1699        }
1700      }
1701    } else if (NumBytes)
1702      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1703
1704    // Move SP to start of integer callee save spill area 2.
1705    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1706    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1707
1708    // Move SP to start of integer callee save spill area 1.
1709    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1710    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1711
1712    // Move SP to SP upon entry to the function.
1713    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1714    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1715  }
1716
1717  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1718      RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1719    // Tail call return: adjust the stack pointer and jump to callee.
1720    MBBI = prior(MBB.end());
1721    MachineOperand &JumpTarget = MBBI->getOperand(0);
1722
1723    // Jump to label or value in register.
1724    if (RetOpcode == ARM::TCRETURNdi) {
1725      BuildMI(MBB, MBBI, dl,
1726            TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1727        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1728                         JumpTarget.getTargetFlags());
1729    } else if (RetOpcode == ARM::TCRETURNdiND) {
1730      BuildMI(MBB, MBBI, dl,
1731            TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1732        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1733                         JumpTarget.getTargetFlags());
1734    } else if (RetOpcode == ARM::TCRETURNri) {
1735      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1736        addReg(JumpTarget.getReg(), RegState::Kill);
1737    } else if (RetOpcode == ARM::TCRETURNriND) {
1738      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1739        addReg(JumpTarget.getReg(), RegState::Kill);
1740    }
1741
1742    MachineInstr *NewMI = prior(MBBI);
1743    for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1744      NewMI->addOperand(MBBI->getOperand(i));
1745
1746    // Delete the pseudo instruction TCRETURN.
1747    MBB.erase(MBBI);
1748  }
1749
1750  if (VARegSaveSize)
1751    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1752}
1753
1754#include "ARMGenRegisterInfo.inc"
1755