ARMBaseRegisterInfo.cpp revision ca7943226e1d58f4f3ae936f93aa03c2a72289ae
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMBaseRegisterInfo.h" 18#include "ARMInstrInfo.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMSubtarget.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/RegisterScavenging.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetFrameInfo.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include "llvm/ADT/BitVector.h" 38#include "llvm/ADT/SmallVector.h" 39using namespace llvm; 40 41unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 42 bool *isSPVFP) { 43 if (isSPVFP) 44 *isSPVFP = false; 45 46 using namespace ARM; 47 switch (RegEnum) { 48 default: 49 llvm_unreachable("Unknown ARM register!"); 50 case R0: case D0: case Q0: return 0; 51 case R1: case D1: case Q1: return 1; 52 case R2: case D2: case Q2: return 2; 53 case R3: case D3: case Q3: return 3; 54 case R4: case D4: case Q4: return 4; 55 case R5: case D5: case Q5: return 5; 56 case R6: case D6: case Q6: return 6; 57 case R7: case D7: case Q7: return 7; 58 case R8: case D8: case Q8: return 8; 59 case R9: case D9: case Q9: return 9; 60 case R10: case D10: case Q10: return 10; 61 case R11: case D11: case Q11: return 11; 62 case R12: case D12: case Q12: return 12; 63 case SP: case D13: case Q13: return 13; 64 case LR: case D14: case Q14: return 14; 65 case PC: case D15: case Q15: return 15; 66 67 case D16: return 16; 68 case D17: return 17; 69 case D18: return 18; 70 case D19: return 19; 71 case D20: return 20; 72 case D21: return 21; 73 case D22: return 22; 74 case D23: return 23; 75 case D24: return 24; 76 case D25: return 25; 77 case D26: return 27; 78 case D27: return 27; 79 case D28: return 28; 80 case D29: return 29; 81 case D30: return 30; 82 case D31: return 31; 83 84 case S0: case S1: case S2: case S3: 85 case S4: case S5: case S6: case S7: 86 case S8: case S9: case S10: case S11: 87 case S12: case S13: case S14: case S15: 88 case S16: case S17: case S18: case S19: 89 case S20: case S21: case S22: case S23: 90 case S24: case S25: case S26: case S27: 91 case S28: case S29: case S30: case S31: { 92 if (isSPVFP) 93 *isSPVFP = true; 94 switch (RegEnum) { 95 default: return 0; // Avoid compile time warning. 96 case S0: return 0; 97 case S1: return 1; 98 case S2: return 2; 99 case S3: return 3; 100 case S4: return 4; 101 case S5: return 5; 102 case S6: return 6; 103 case S7: return 7; 104 case S8: return 8; 105 case S9: return 9; 106 case S10: return 10; 107 case S11: return 11; 108 case S12: return 12; 109 case S13: return 13; 110 case S14: return 14; 111 case S15: return 15; 112 case S16: return 16; 113 case S17: return 17; 114 case S18: return 18; 115 case S19: return 19; 116 case S20: return 20; 117 case S21: return 21; 118 case S22: return 22; 119 case S23: return 23; 120 case S24: return 24; 121 case S25: return 25; 122 case S26: return 26; 123 case S27: return 27; 124 case S28: return 28; 125 case S29: return 29; 126 case S30: return 30; 127 case S31: return 31; 128 } 129 } 130 } 131} 132 133ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 134 const ARMSubtarget &sti) 135 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 136 TII(tii), STI(sti), 137 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 138} 139 140const unsigned* 141ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 142 static const unsigned CalleeSavedRegs[] = { 143 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 144 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 145 146 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 147 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 148 0 149 }; 150 151 static const unsigned DarwinCalleeSavedRegs[] = { 152 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 153 // register. 154 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 155 ARM::R11, ARM::R10, ARM::R8, 156 157 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 158 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 159 0 160 }; 161 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 162} 163 164const TargetRegisterClass* const * 165ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 166 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 167 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 168 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 169 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 170 171 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 172 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 173 0 174 }; 175 176 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 179 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 180 181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 182 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 183 0 184 }; 185 186 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 188 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 189 &ARM::GPRRegClass, &ARM::GPRRegClass, 190 191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 192 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 193 0 194 }; 195 196 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 197 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, 198 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, 199 &ARM::GPRRegClass, &ARM::GPRRegClass, 200 201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 202 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 203 0 204 }; 205 206 if (STI.isThumb1Only()) { 207 return STI.isTargetDarwin() 208 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 209 } 210 return STI.isTargetDarwin() 211 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 212} 213 214BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 215 // FIXME: avoid re-calculating this everytime. 216 BitVector Reserved(getNumRegs()); 217 Reserved.set(ARM::SP); 218 Reserved.set(ARM::PC); 219 if (STI.isTargetDarwin() || hasFP(MF)) 220 Reserved.set(FramePtr); 221 // Some targets reserve R9. 222 if (STI.isR9Reserved()) 223 Reserved.set(ARM::R9); 224 return Reserved; 225} 226 227bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 228 unsigned Reg) const { 229 switch (Reg) { 230 default: break; 231 case ARM::SP: 232 case ARM::PC: 233 return true; 234 case ARM::R7: 235 case ARM::R11: 236 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 237 return true; 238 break; 239 case ARM::R9: 240 return STI.isR9Reserved(); 241 } 242 243 return false; 244} 245 246const TargetRegisterClass * 247ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 248 return &ARM::GPRRegClass; 249} 250 251/// getAllocationOrder - Returns the register allocation order for a specified 252/// register class in the form of a pair of TargetRegisterClass iterators. 253std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 254ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 255 unsigned HintType, unsigned HintReg, 256 const MachineFunction &MF) const { 257 // Alternative register allocation orders when favoring even / odd registers 258 // of register pairs. 259 260 // No FP, R9 is available. 261 static const unsigned GPREven1[] = { 262 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 263 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 264 ARM::R9, ARM::R11 265 }; 266 static const unsigned GPROdd1[] = { 267 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 268 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 269 ARM::R8, ARM::R10 270 }; 271 272 // FP is R7, R9 is available. 273 static const unsigned GPREven2[] = { 274 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 275 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 276 ARM::R9, ARM::R11 277 }; 278 static const unsigned GPROdd2[] = { 279 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 280 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 281 ARM::R8, ARM::R10 282 }; 283 284 // FP is R11, R9 is available. 285 static const unsigned GPREven3[] = { 286 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 287 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 288 ARM::R9 289 }; 290 static const unsigned GPROdd3[] = { 291 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 292 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 293 ARM::R8 294 }; 295 296 // No FP, R9 is not available. 297 static const unsigned GPREven4[] = { 298 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 299 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 300 ARM::R11 301 }; 302 static const unsigned GPROdd4[] = { 303 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 304 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 305 ARM::R10 306 }; 307 308 // FP is R7, R9 is not available. 309 static const unsigned GPREven5[] = { 310 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 311 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 312 ARM::R11 313 }; 314 static const unsigned GPROdd5[] = { 315 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 316 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 317 ARM::R10 318 }; 319 320 // FP is R11, R9 is not available. 321 static const unsigned GPREven6[] = { 322 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 323 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 324 }; 325 static const unsigned GPROdd6[] = { 326 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 327 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 328 }; 329 330 331 if (HintType == ARMRI::RegPairEven) { 332 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 333 // It's no longer possible to fulfill this hint. Return the default 334 // allocation order. 335 return std::make_pair(RC->allocation_order_begin(MF), 336 RC->allocation_order_end(MF)); 337 338 if (!STI.isTargetDarwin() && !hasFP(MF)) { 339 if (!STI.isR9Reserved()) 340 return std::make_pair(GPREven1, 341 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 342 else 343 return std::make_pair(GPREven4, 344 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 345 } else if (FramePtr == ARM::R7) { 346 if (!STI.isR9Reserved()) 347 return std::make_pair(GPREven2, 348 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 349 else 350 return std::make_pair(GPREven5, 351 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 352 } else { // FramePtr == ARM::R11 353 if (!STI.isR9Reserved()) 354 return std::make_pair(GPREven3, 355 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 356 else 357 return std::make_pair(GPREven6, 358 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 359 } 360 } else if (HintType == ARMRI::RegPairOdd) { 361 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 362 // It's no longer possible to fulfill this hint. Return the default 363 // allocation order. 364 return std::make_pair(RC->allocation_order_begin(MF), 365 RC->allocation_order_end(MF)); 366 367 if (!STI.isTargetDarwin() && !hasFP(MF)) { 368 if (!STI.isR9Reserved()) 369 return std::make_pair(GPROdd1, 370 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 371 else 372 return std::make_pair(GPROdd4, 373 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 374 } else if (FramePtr == ARM::R7) { 375 if (!STI.isR9Reserved()) 376 return std::make_pair(GPROdd2, 377 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 378 else 379 return std::make_pair(GPROdd5, 380 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 381 } else { // FramePtr == ARM::R11 382 if (!STI.isR9Reserved()) 383 return std::make_pair(GPROdd3, 384 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 385 else 386 return std::make_pair(GPROdd6, 387 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 388 } 389 } 390 return std::make_pair(RC->allocation_order_begin(MF), 391 RC->allocation_order_end(MF)); 392} 393 394/// ResolveRegAllocHint - Resolves the specified register allocation hint 395/// to a physical register. Returns the physical register if it is successful. 396unsigned 397ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 398 const MachineFunction &MF) const { 399 if (Reg == 0 || !isPhysicalRegister(Reg)) 400 return 0; 401 if (Type == 0) 402 return Reg; 403 else if (Type == (unsigned)ARMRI::RegPairOdd) 404 // Odd register. 405 return getRegisterPairOdd(Reg, MF); 406 else if (Type == (unsigned)ARMRI::RegPairEven) 407 // Even register. 408 return getRegisterPairEven(Reg, MF); 409 return 0; 410} 411 412void 413ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 414 MachineFunction &MF) const { 415 MachineRegisterInfo *MRI = &MF.getRegInfo(); 416 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 417 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 418 Hint.first == (unsigned)ARMRI::RegPairEven) && 419 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 420 // If 'Reg' is one of the even / odd register pair and it's now changed 421 // (e.g. coalesced) into a different register. The other register of the 422 // pair allocation hint must be updated to reflect the relationship 423 // change. 424 unsigned OtherReg = Hint.second; 425 Hint = MRI->getRegAllocationHint(OtherReg); 426 if (Hint.second == Reg) 427 // Make sure the pair has not already divorced. 428 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 429 } 430} 431 432/// hasFP - Return true if the specified function should have a dedicated frame 433/// pointer register. This is true if the function has variable sized allocas 434/// or if frame pointer elimination is disabled. 435/// 436bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 437 const MachineFrameInfo *MFI = MF.getFrameInfo(); 438 return (NoFramePointerElim || 439 MFI->hasVarSizedObjects() || 440 MFI->isFrameAddressTaken()); 441} 442 443bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 444 const MachineFrameInfo *MFI = MF.getFrameInfo(); 445 if (NoFramePointerElim && MFI->hasCalls()) 446 return true; 447 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 448} 449 450/// estimateStackSize - Estimate and return the size of the frame. 451static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 452 const MachineFrameInfo *FFI = MF.getFrameInfo(); 453 int Offset = 0; 454 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 455 int FixedOff = -FFI->getObjectOffset(i); 456 if (FixedOff > Offset) Offset = FixedOff; 457 } 458 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 459 if (FFI->isDeadObjectIndex(i)) 460 continue; 461 Offset += FFI->getObjectSize(i); 462 unsigned Align = FFI->getObjectAlignment(i); 463 // Adjust to alignment boundary 464 Offset = (Offset+Align-1)/Align*Align; 465 } 466 return (unsigned)Offset; 467} 468 469/// estimateRSStackSizeLimit - Look at each instruction that references stack 470/// frames and return the stack size limit beyond which some of these 471/// instructions will require scratch register during their expansion later. 472unsigned 473ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 474 unsigned Limit = (1 << 12) - 1; 475 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 476 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 477 I != E; ++I) { 478 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 479 if (!I->getOperand(i).isFI()) continue; 480 481 const TargetInstrDesc &Desc = TII.get(I->getOpcode()); 482 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 483 if (AddrMode == ARMII::AddrMode3 || 484 AddrMode == ARMII::AddrModeT2_i8) 485 return (1 << 8) - 1; 486 487 if (AddrMode == ARMII::AddrMode5 || 488 AddrMode == ARMII::AddrModeT2_i8s4) 489 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 490 491 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF)) 492 // When the stack offset is negative, we will end up using 493 // the i8 instructions instead. 494 return (1 << 8) - 1; 495 break; // At most one FI per instruction 496 } 497 } 498 } 499 500 return Limit; 501} 502 503void 504ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 505 RegScavenger *RS) const { 506 // This tells PEI to spill the FP as if it is any other callee-save register 507 // to take advantage the eliminateFrameIndex machinery. This also ensures it 508 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 509 // to combine multiple loads / stores. 510 bool CanEliminateFrame = true; 511 bool CS1Spilled = false; 512 bool LRSpilled = false; 513 unsigned NumGPRSpills = 0; 514 SmallVector<unsigned, 4> UnspilledCS1GPRs; 515 SmallVector<unsigned, 4> UnspilledCS2GPRs; 516 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 517 518 // Don't spill FP if the frame can be eliminated. This is determined 519 // by scanning the callee-save registers to see if any is used. 520 const unsigned *CSRegs = getCalleeSavedRegs(); 521 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 522 for (unsigned i = 0; CSRegs[i]; ++i) { 523 unsigned Reg = CSRegs[i]; 524 bool Spilled = false; 525 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 526 AFI->setCSRegisterIsSpilled(Reg); 527 Spilled = true; 528 CanEliminateFrame = false; 529 } else { 530 // Check alias registers too. 531 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 532 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 533 Spilled = true; 534 CanEliminateFrame = false; 535 } 536 } 537 } 538 539 if (CSRegClasses[i] == &ARM::GPRRegClass) { 540 if (Spilled) { 541 NumGPRSpills++; 542 543 if (!STI.isTargetDarwin()) { 544 if (Reg == ARM::LR) 545 LRSpilled = true; 546 CS1Spilled = true; 547 continue; 548 } 549 550 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 551 switch (Reg) { 552 case ARM::LR: 553 LRSpilled = true; 554 // Fallthrough 555 case ARM::R4: 556 case ARM::R5: 557 case ARM::R6: 558 case ARM::R7: 559 CS1Spilled = true; 560 break; 561 default: 562 break; 563 } 564 } else { 565 if (!STI.isTargetDarwin()) { 566 UnspilledCS1GPRs.push_back(Reg); 567 continue; 568 } 569 570 switch (Reg) { 571 case ARM::R4: 572 case ARM::R5: 573 case ARM::R6: 574 case ARM::R7: 575 case ARM::LR: 576 UnspilledCS1GPRs.push_back(Reg); 577 break; 578 default: 579 UnspilledCS2GPRs.push_back(Reg); 580 break; 581 } 582 } 583 } 584 } 585 586 bool ForceLRSpill = false; 587 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 588 unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 589 // Force LR to be spilled if the Thumb function size is > 2048. This enables 590 // use of BL to implement far jump. If it turns out that it's not needed 591 // then the branch fix up path will undo it. 592 if (FnSize >= (1 << 11)) { 593 CanEliminateFrame = false; 594 ForceLRSpill = true; 595 } 596 } 597 598 bool ExtraCSSpill = false; 599 if (!CanEliminateFrame || cannotEliminateFrame(MF)) { 600 AFI->setHasStackFrame(true); 601 602 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 603 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 604 if (!LRSpilled && CS1Spilled) { 605 MF.getRegInfo().setPhysRegUsed(ARM::LR); 606 AFI->setCSRegisterIsSpilled(ARM::LR); 607 NumGPRSpills++; 608 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 609 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 610 ForceLRSpill = false; 611 ExtraCSSpill = true; 612 } 613 614 // Darwin ABI requires FP to point to the stack slot that contains the 615 // previous FP. 616 if (STI.isTargetDarwin() || hasFP(MF)) { 617 MF.getRegInfo().setPhysRegUsed(FramePtr); 618 NumGPRSpills++; 619 } 620 621 // If stack and double are 8-byte aligned and we are spilling an odd number 622 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 623 // the integer and double callee save areas. 624 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 625 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 626 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 627 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 628 unsigned Reg = UnspilledCS1GPRs[i]; 629 // Don't spill high register if the function is thumb1 630 if (!AFI->isThumb1OnlyFunction() || 631 isARMLowRegister(Reg) || Reg == ARM::LR) { 632 MF.getRegInfo().setPhysRegUsed(Reg); 633 AFI->setCSRegisterIsSpilled(Reg); 634 if (!isReservedReg(MF, Reg)) 635 ExtraCSSpill = true; 636 break; 637 } 638 } 639 } else if (!UnspilledCS2GPRs.empty() && 640 !AFI->isThumb1OnlyFunction()) { 641 unsigned Reg = UnspilledCS2GPRs.front(); 642 MF.getRegInfo().setPhysRegUsed(Reg); 643 AFI->setCSRegisterIsSpilled(Reg); 644 if (!isReservedReg(MF, Reg)) 645 ExtraCSSpill = true; 646 } 647 } 648 649 // Estimate if we might need to scavenge a register at some point in order 650 // to materialize a stack offset. If so, either spill one additional 651 // callee-saved register or reserve a special spill slot to facilitate 652 // register scavenging. 653 if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) { 654 MachineFrameInfo *MFI = MF.getFrameInfo(); 655 if (estimateStackSize(MF, MFI) >= estimateRSStackSizeLimit(MF)) { 656 // If any non-reserved CS register isn't spilled, just spill one or two 657 // extra. That should take care of it! 658 unsigned NumExtras = TargetAlign / 4; 659 SmallVector<unsigned, 2> Extras; 660 while (NumExtras && !UnspilledCS1GPRs.empty()) { 661 unsigned Reg = UnspilledCS1GPRs.back(); 662 UnspilledCS1GPRs.pop_back(); 663 if (!isReservedReg(MF, Reg)) { 664 Extras.push_back(Reg); 665 NumExtras--; 666 } 667 } 668 while (NumExtras && !UnspilledCS2GPRs.empty()) { 669 unsigned Reg = UnspilledCS2GPRs.back(); 670 UnspilledCS2GPRs.pop_back(); 671 if (!isReservedReg(MF, Reg)) { 672 Extras.push_back(Reg); 673 NumExtras--; 674 } 675 } 676 if (Extras.size() && NumExtras == 0) { 677 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 678 MF.getRegInfo().setPhysRegUsed(Extras[i]); 679 AFI->setCSRegisterIsSpilled(Extras[i]); 680 } 681 } else { 682 // Reserve a slot closest to SP or frame pointer. 683 const TargetRegisterClass *RC = &ARM::GPRRegClass; 684 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 685 RC->getAlignment())); 686 } 687 } 688 } 689 } 690 691 if (ForceLRSpill) { 692 MF.getRegInfo().setPhysRegUsed(ARM::LR); 693 AFI->setCSRegisterIsSpilled(ARM::LR); 694 AFI->setLRIsSpilledForFarJump(true); 695 } 696} 697 698unsigned ARMBaseRegisterInfo::getRARegister() const { 699 return ARM::LR; 700} 701 702unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { 703 if (STI.isTargetDarwin() || hasFP(MF)) 704 return FramePtr; 705 return ARM::SP; 706} 707 708unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 709 llvm_unreachable("What is the exception register"); 710 return 0; 711} 712 713unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 714 llvm_unreachable("What is the exception handler register"); 715 return 0; 716} 717 718int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 719 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 720} 721 722unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 723 const MachineFunction &MF) const { 724 switch (Reg) { 725 default: break; 726 // Return 0 if either register of the pair is a special register. 727 // So no R12, etc. 728 case ARM::R1: 729 return ARM::R0; 730 case ARM::R3: 731 // FIXME! 732 return STI.isThumb1Only() ? 0 : ARM::R2; 733 case ARM::R5: 734 return ARM::R4; 735 case ARM::R7: 736 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 737 case ARM::R9: 738 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 739 case ARM::R11: 740 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 741 742 case ARM::S1: 743 return ARM::S0; 744 case ARM::S3: 745 return ARM::S2; 746 case ARM::S5: 747 return ARM::S4; 748 case ARM::S7: 749 return ARM::S6; 750 case ARM::S9: 751 return ARM::S8; 752 case ARM::S11: 753 return ARM::S10; 754 case ARM::S13: 755 return ARM::S12; 756 case ARM::S15: 757 return ARM::S14; 758 case ARM::S17: 759 return ARM::S16; 760 case ARM::S19: 761 return ARM::S18; 762 case ARM::S21: 763 return ARM::S20; 764 case ARM::S23: 765 return ARM::S22; 766 case ARM::S25: 767 return ARM::S24; 768 case ARM::S27: 769 return ARM::S26; 770 case ARM::S29: 771 return ARM::S28; 772 case ARM::S31: 773 return ARM::S30; 774 775 case ARM::D1: 776 return ARM::D0; 777 case ARM::D3: 778 return ARM::D2; 779 case ARM::D5: 780 return ARM::D4; 781 case ARM::D7: 782 return ARM::D6; 783 case ARM::D9: 784 return ARM::D8; 785 case ARM::D11: 786 return ARM::D10; 787 case ARM::D13: 788 return ARM::D12; 789 case ARM::D15: 790 return ARM::D14; 791 case ARM::D17: 792 return ARM::D16; 793 case ARM::D19: 794 return ARM::D18; 795 case ARM::D21: 796 return ARM::D20; 797 case ARM::D23: 798 return ARM::D22; 799 case ARM::D25: 800 return ARM::D24; 801 case ARM::D27: 802 return ARM::D26; 803 case ARM::D29: 804 return ARM::D28; 805 case ARM::D31: 806 return ARM::D30; 807 } 808 809 return 0; 810} 811 812unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 813 const MachineFunction &MF) const { 814 switch (Reg) { 815 default: break; 816 // Return 0 if either register of the pair is a special register. 817 // So no R12, etc. 818 case ARM::R0: 819 return ARM::R1; 820 case ARM::R2: 821 // FIXME! 822 return STI.isThumb1Only() ? 0 : ARM::R3; 823 case ARM::R4: 824 return ARM::R5; 825 case ARM::R6: 826 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 827 case ARM::R8: 828 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 829 case ARM::R10: 830 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 831 832 case ARM::S0: 833 return ARM::S1; 834 case ARM::S2: 835 return ARM::S3; 836 case ARM::S4: 837 return ARM::S5; 838 case ARM::S6: 839 return ARM::S7; 840 case ARM::S8: 841 return ARM::S9; 842 case ARM::S10: 843 return ARM::S11; 844 case ARM::S12: 845 return ARM::S13; 846 case ARM::S14: 847 return ARM::S15; 848 case ARM::S16: 849 return ARM::S17; 850 case ARM::S18: 851 return ARM::S19; 852 case ARM::S20: 853 return ARM::S21; 854 case ARM::S22: 855 return ARM::S23; 856 case ARM::S24: 857 return ARM::S25; 858 case ARM::S26: 859 return ARM::S27; 860 case ARM::S28: 861 return ARM::S29; 862 case ARM::S30: 863 return ARM::S31; 864 865 case ARM::D0: 866 return ARM::D1; 867 case ARM::D2: 868 return ARM::D3; 869 case ARM::D4: 870 return ARM::D5; 871 case ARM::D6: 872 return ARM::D7; 873 case ARM::D8: 874 return ARM::D9; 875 case ARM::D10: 876 return ARM::D11; 877 case ARM::D12: 878 return ARM::D13; 879 case ARM::D14: 880 return ARM::D15; 881 case ARM::D16: 882 return ARM::D17; 883 case ARM::D18: 884 return ARM::D19; 885 case ARM::D20: 886 return ARM::D21; 887 case ARM::D22: 888 return ARM::D23; 889 case ARM::D24: 890 return ARM::D25; 891 case ARM::D26: 892 return ARM::D27; 893 case ARM::D28: 894 return ARM::D29; 895 case ARM::D30: 896 return ARM::D31; 897 } 898 899 return 0; 900} 901 902/// emitLoadConstPool - Emits a load from constpool to materialize the 903/// specified immediate. 904void ARMBaseRegisterInfo:: 905emitLoadConstPool(MachineBasicBlock &MBB, 906 MachineBasicBlock::iterator &MBBI, 907 DebugLoc dl, 908 unsigned DestReg, unsigned SubIdx, int Val, 909 ARMCC::CondCodes Pred, 910 unsigned PredReg) const { 911 MachineFunction &MF = *MBB.getParent(); 912 MachineConstantPool *ConstantPool = MF.getConstantPool(); 913 Constant *C = 914 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 915 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 916 917 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 918 .addReg(DestReg, getDefRegState(true), SubIdx) 919 .addConstantPoolIndex(Idx) 920 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 921} 922 923bool ARMBaseRegisterInfo:: 924requiresRegisterScavenging(const MachineFunction &MF) const { 925 return true; 926} 927 928// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 929// not required, we reserve argument space for call sites in the function 930// immediately on entry to the current function. This eliminates the need for 931// add/sub sp brackets around call sites. Returns true if the call frame is 932// included as part of the stack frame. 933bool ARMBaseRegisterInfo:: 934hasReservedCallFrame(MachineFunction &MF) const { 935 const MachineFrameInfo *FFI = MF.getFrameInfo(); 936 unsigned CFSize = FFI->getMaxCallFrameSize(); 937 // It's not always a good idea to include the call frame as part of the 938 // stack frame. ARM (especially Thumb) has small immediate offset to 939 // address the stack frame. So a large call frame can cause poor codegen 940 // and may even makes it impossible to scavenge a register. 941 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 942 return false; 943 944 return !MF.getFrameInfo()->hasVarSizedObjects(); 945} 946 947static void 948emitSPUpdate(bool isARM, 949 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 950 DebugLoc dl, const ARMBaseInstrInfo &TII, 951 int NumBytes, 952 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 953 if (isARM) 954 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 955 Pred, PredReg, TII); 956 else 957 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 958 Pred, PredReg, TII); 959} 960 961 962void ARMBaseRegisterInfo:: 963eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 964 MachineBasicBlock::iterator I) const { 965 if (!hasReservedCallFrame(MF)) { 966 // If we have alloca, convert as follows: 967 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 968 // ADJCALLSTACKUP -> add, sp, sp, amount 969 MachineInstr *Old = I; 970 DebugLoc dl = Old->getDebugLoc(); 971 unsigned Amount = Old->getOperand(0).getImm(); 972 if (Amount != 0) { 973 // We need to keep the stack aligned properly. To do this, we round the 974 // amount of space needed for the outgoing arguments up to the next 975 // alignment boundary. 976 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 977 Amount = (Amount+Align-1)/Align*Align; 978 979 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 980 assert(!AFI->isThumb1OnlyFunction() && 981 "This eliminateCallFramePseudoInstr does not suppor Thumb1!"); 982 bool isARM = !AFI->isThumbFunction(); 983 984 // Replace the pseudo instruction with a new instruction... 985 unsigned Opc = Old->getOpcode(); 986 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm(); 987 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN? 988 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 989 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 990 unsigned PredReg = Old->getOperand(2).getReg(); 991 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 992 } else { 993 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 994 unsigned PredReg = Old->getOperand(3).getReg(); 995 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 996 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 997 } 998 } 999 } 1000 MBB.erase(I); 1001} 1002 1003/// findScratchRegister - Find a 'free' ARM register. If register scavenger 1004/// is not being used, R12 is available. Otherwise, try for a call-clobbered 1005/// register first and then a spilled callee-saved register if that fails. 1006static 1007unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 1008 ARMFunctionInfo *AFI) { 1009 unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12; 1010 assert(!AFI->isThumb1OnlyFunction()); 1011 return Reg; 1012} 1013 1014void 1015ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1016 int SPAdj, RegScavenger *RS) const { 1017 unsigned i = 0; 1018 MachineInstr &MI = *II; 1019 MachineBasicBlock &MBB = *MI.getParent(); 1020 MachineFunction &MF = *MBB.getParent(); 1021 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1022 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1023 assert(!AFI->isThumb1OnlyFunction() && 1024 "This eliminateFrameIndex does not suppor Thumb1!"); 1025 1026 while (!MI.getOperand(i).isFI()) { 1027 ++i; 1028 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1029 } 1030 1031 unsigned FrameReg = ARM::SP; 1032 int FrameIndex = MI.getOperand(i).getIndex(); 1033 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj; 1034 1035 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 1036 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 1037 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 1038 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 1039 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 1040 Offset -= AFI->getDPRCalleeSavedAreaOffset(); 1041 else if (hasFP(MF) && AFI->hasStackFrame()) { 1042 assert(SPAdj == 0 && "Unexpected stack offset!"); 1043 // Use frame pointer to reference fixed objects unless this is a 1044 // frameless function, 1045 FrameReg = getFrameRegister(MF); 1046 Offset -= AFI->getFramePtrSpillOffset(); 1047 } 1048 1049 // modify MI as necessary to handle as much of 'Offset' as possible 1050 bool Done = false; 1051 if (!AFI->isThumbFunction()) 1052 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 1053 else { 1054 assert(AFI->isThumb2Function()); 1055 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 1056 } 1057 if (Done) 1058 return; 1059 1060 const TargetInstrDesc &Desc = MI.getDesc(); 1061 1062 // If we get here, the immediate doesn't fit into the instruction. We folded 1063 // as much as possible above, handle the rest, providing a register that is 1064 // SP+LargeImm. 1065 assert((Offset || (Desc.TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && 1066 "This code isn't needed if offset already handled!"); 1067 1068 // Insert a set of r12 with the full address: r12 = sp + offset 1069 // If the offset we have is too large to fit into the instruction, we need 1070 // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1071 // out of 'Offset'. 1072 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 1073 if (ScratchReg == 0) 1074 // No register is "free". Scavenge a register. 1075 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 1076 int PIdx = MI.findFirstPredOperandIdx(); 1077 ARMCC::CondCodes Pred = (PIdx == -1) 1078 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1079 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1080 if (Offset == 0) 1081 // Must be addrmode4. 1082 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1083 else { 1084 if (!AFI->isThumbFunction()) 1085 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1086 Offset, Pred, PredReg, TII); 1087 else { 1088 assert(AFI->isThumb2Function()); 1089 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1090 Offset, Pred, PredReg, TII); 1091 } 1092 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1093 } 1094} 1095 1096/// Move iterator pass the next bunch of callee save load / store ops for 1097/// the particular spill area (1: integer area 1, 2: integer area 2, 1098/// 3: fp area, 0: don't care). 1099static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1100 MachineBasicBlock::iterator &MBBI, 1101 int Opc1, int Opc2, unsigned Area, 1102 const ARMSubtarget &STI) { 1103 while (MBBI != MBB.end() && 1104 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 1105 MBBI->getOperand(1).isFI()) { 1106 if (Area != 0) { 1107 bool Done = false; 1108 unsigned Category = 0; 1109 switch (MBBI->getOperand(0).getReg()) { 1110 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1111 case ARM::LR: 1112 Category = 1; 1113 break; 1114 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1115 Category = STI.isTargetDarwin() ? 2 : 1; 1116 break; 1117 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1118 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1119 Category = 3; 1120 break; 1121 default: 1122 Done = true; 1123 break; 1124 } 1125 if (Done || Category != Area) 1126 break; 1127 } 1128 1129 ++MBBI; 1130 } 1131} 1132 1133void ARMBaseRegisterInfo:: 1134emitPrologue(MachineFunction &MF) const { 1135 MachineBasicBlock &MBB = MF.front(); 1136 MachineBasicBlock::iterator MBBI = MBB.begin(); 1137 MachineFrameInfo *MFI = MF.getFrameInfo(); 1138 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1139 assert(!AFI->isThumb1OnlyFunction() && 1140 "This emitPrologue does not suppor Thumb1!"); 1141 bool isARM = !AFI->isThumbFunction(); 1142 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1143 unsigned NumBytes = MFI->getStackSize(); 1144 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1145 DebugLoc dl = (MBBI != MBB.end() ? 1146 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1147 1148 // Determine the sizes of each callee-save spill areas and record which frame 1149 // belongs to which callee-save spill areas. 1150 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1151 int FramePtrSpillFI = 0; 1152 1153 if (VARegSaveSize) 1154 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1155 1156 if (!AFI->hasStackFrame()) { 1157 if (NumBytes != 0) 1158 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1159 return; 1160 } 1161 1162 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1163 unsigned Reg = CSI[i].getReg(); 1164 int FI = CSI[i].getFrameIdx(); 1165 switch (Reg) { 1166 case ARM::R4: 1167 case ARM::R5: 1168 case ARM::R6: 1169 case ARM::R7: 1170 case ARM::LR: 1171 if (Reg == FramePtr) 1172 FramePtrSpillFI = FI; 1173 AFI->addGPRCalleeSavedArea1Frame(FI); 1174 GPRCS1Size += 4; 1175 break; 1176 case ARM::R8: 1177 case ARM::R9: 1178 case ARM::R10: 1179 case ARM::R11: 1180 if (Reg == FramePtr) 1181 FramePtrSpillFI = FI; 1182 if (STI.isTargetDarwin()) { 1183 AFI->addGPRCalleeSavedArea2Frame(FI); 1184 GPRCS2Size += 4; 1185 } else { 1186 AFI->addGPRCalleeSavedArea1Frame(FI); 1187 GPRCS1Size += 4; 1188 } 1189 break; 1190 default: 1191 AFI->addDPRCalleeSavedAreaFrame(FI); 1192 DPRCSSize += 8; 1193 } 1194 } 1195 1196 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1197 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 1198 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1199 1200 // Darwin ABI requires FP to point to the stack slot that contains the 1201 // previous FP. 1202 if (STI.isTargetDarwin() || hasFP(MF)) { 1203 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1204 MachineInstrBuilder MIB = 1205 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1206 .addFrameIndex(FramePtrSpillFI).addImm(0); 1207 AddDefaultCC(AddDefaultPred(MIB)); 1208 } 1209 1210 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1211 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1212 1213 // Build the new SUBri to adjust SP for FP callee-save spill area. 1214 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 1215 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1216 1217 // Determine starting offsets of spill areas. 1218 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1219 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1220 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1221 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1222 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1223 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1224 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1225 1226 NumBytes = DPRCSOffset; 1227 if (NumBytes) { 1228 // Insert it after all the callee-save spills. 1229 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI); 1230 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1231 } 1232 1233 if (STI.isTargetELF() && hasFP(MF)) { 1234 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1235 AFI->getFramePtrSpillOffset()); 1236 } 1237 1238 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1239 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1240 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1241} 1242 1243static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1244 for (unsigned i = 0; CSRegs[i]; ++i) 1245 if (Reg == CSRegs[i]) 1246 return true; 1247 return false; 1248} 1249 1250static bool isCSRestore(MachineInstr *MI, 1251 const ARMBaseInstrInfo &TII, 1252 const unsigned *CSRegs) { 1253 return ((MI->getOpcode() == (int)ARM::FLDD || 1254 MI->getOpcode() == (int)ARM::LDR || 1255 MI->getOpcode() == (int)ARM::t2LDRi12) && 1256 MI->getOperand(1).isFI() && 1257 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1258} 1259 1260void ARMBaseRegisterInfo:: 1261emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1262 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1263 assert(MBBI->getDesc().isReturn() && 1264 "Can only insert epilog into returning blocks"); 1265 DebugLoc dl = MBBI->getDebugLoc(); 1266 MachineFrameInfo *MFI = MF.getFrameInfo(); 1267 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1268 assert(!AFI->isThumb1OnlyFunction() && 1269 "This emitEpilogue does not suppor Thumb1!"); 1270 bool isARM = !AFI->isThumbFunction(); 1271 1272 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1273 int NumBytes = (int)MFI->getStackSize(); 1274 1275 if (!AFI->hasStackFrame()) { 1276 if (NumBytes != 0) 1277 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1278 } else { 1279 // Unwind MBBI to point to first LDR / FLDD. 1280 const unsigned *CSRegs = getCalleeSavedRegs(); 1281 if (MBBI != MBB.begin()) { 1282 do 1283 --MBBI; 1284 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 1285 if (!isCSRestore(MBBI, TII, CSRegs)) 1286 ++MBBI; 1287 } 1288 1289 // Move SP to start of FP callee save spill area. 1290 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1291 AFI->getGPRCalleeSavedArea2Size() + 1292 AFI->getDPRCalleeSavedAreaSize()); 1293 1294 // Darwin ABI requires FP to point to the stack slot that contains the 1295 // previous FP. 1296 bool HasFP = hasFP(MF); 1297 if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1298 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1299 // Reset SP based on frame pointer only if the stack frame extends beyond 1300 // frame pointer stack slot or target is ELF and the function has FP. 1301 if (HasFP || 1302 AFI->getGPRCalleeSavedArea2Size() || 1303 AFI->getDPRCalleeSavedAreaSize() || 1304 AFI->getDPRCalleeSavedAreaOffset()) { 1305 if (NumBytes) { 1306 if (isARM) 1307 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1308 ARMCC::AL, 0, TII); 1309 else 1310 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1311 ARMCC::AL, 0, TII); 1312 } else { 1313 // Thumb2 or ARM. 1314 if (isARM) 1315 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1316 .addReg(FramePtr) 1317 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1318 else 1319 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1320 .addReg(FramePtr); 1321 } 1322 } 1323 } else if (NumBytes) 1324 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1325 1326 // Move SP to start of integer callee save spill area 2. 1327 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI); 1328 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1329 1330 // Move SP to start of integer callee save spill area 1. 1331 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 1332 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1333 1334 // Move SP to SP upon entry to the function. 1335 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 1336 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1337 } 1338 1339 if (VARegSaveSize) 1340 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1341} 1342 1343#include "ARMGenRegisterInfo.inc" 1344