ARMBaseRegisterInfo.cpp revision ee42fd309ee6a8febfafb97c2f3b6f2069758c5e 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/SmallVector.h"
39using namespace llvm;
40
41unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
42                                                   bool *isSPVFP) {
43  if (isSPVFP)
44    *isSPVFP = false;
45
46  using namespace ARM;
47  switch (RegEnum) {
48  default:
49    llvm_unreachable("Unknown ARM register!");
50  case R0:  case D0:  case Q0:  return 0;
51  case R1:  case D1:  case Q1:  return 1;
52  case R2:  case D2:  case Q2:  return 2;
53  case R3:  case D3:  case Q3:  return 3;
54  case R4:  case D4:  case Q4:  return 4;
55  case R5:  case D5:  case Q5:  return 5;
56  case R6:  case D6:  case Q6:  return 6;
57  case R7:  case D7:  case Q7:  return 7;
58  case R8:  case D8:  case Q8:  return 8;
59  case R9:  case D9:  case Q9:  return 9;
60  case R10: case D10: case Q10: return 10;
61  case R11: case D11: case Q11: return 11;
62  case R12: case D12: case Q12: return 12;
63  case SP:  case D13: case Q13: return 13;
64  case LR:  case D14: case Q14: return 14;
65  case PC:  case D15: case Q15: return 15;
66
67  case D16: return 16;
68  case D17: return 17;
69  case D18: return 18;
70  case D19: return 19;
71  case D20: return 20;
72  case D21: return 21;
73  case D22: return 22;
74  case D23: return 23;
75  case D24: return 24;
76  case D25: return 25;
77  case D26: return 27;
78  case D27: return 27;
79  case D28: return 28;
80  case D29: return 29;
81  case D30: return 30;
82  case D31: return 31;
83
84  case S0: case S1: case S2: case S3:
85  case S4: case S5: case S6: case S7:
86  case S8: case S9: case S10: case S11:
87  case S12: case S13: case S14: case S15:
88  case S16: case S17: case S18: case S19:
89  case S20: case S21: case S22: case S23:
90  case S24: case S25: case S26: case S27:
91  case S28: case S29: case S30: case S31: {
92    if (isSPVFP)
93      *isSPVFP = true;
94    switch (RegEnum) {
95    default: return 0; // Avoid compile time warning.
96    case S0: return 0;
97    case S1: return 1;
98    case S2: return 2;
99    case S3: return 3;
100    case S4: return 4;
101    case S5: return 5;
102    case S6: return 6;
103    case S7: return 7;
104    case S8: return 8;
105    case S9: return 9;
106    case S10: return 10;
107    case S11: return 11;
108    case S12: return 12;
109    case S13: return 13;
110    case S14: return 14;
111    case S15: return 15;
112    case S16: return 16;
113    case S17: return 17;
114    case S18: return 18;
115    case S19: return 19;
116    case S20: return 20;
117    case S21: return 21;
118    case S22: return 22;
119    case S23: return 23;
120    case S24: return 24;
121    case S25: return 25;
122    case S26: return 26;
123    case S27: return 27;
124    case S28: return 28;
125    case S29: return 29;
126    case S30: return 30;
127    case S31: return 31;
128    }
129  }
130  }
131}
132
133ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
134                                         const ARMSubtarget &sti)
135  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
136    TII(tii), STI(sti),
137    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
138}
139
140const unsigned*
141ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
142  static const unsigned CalleeSavedRegs[] = {
143    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
144    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
145
146    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
147    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
148    0
149  };
150
151  static const unsigned DarwinCalleeSavedRegs[] = {
152    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
153    // register.
154    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
155    ARM::R11, ARM::R10, ARM::R8,
156
157    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
158    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
159    0
160  };
161  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
162}
163
164const TargetRegisterClass* const *
165ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
166  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
167    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
168    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
169    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
170
171    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
172    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
173    0
174  };
175
176  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
177    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
179    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
180
181    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
183    0
184  };
185
186  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
189    &ARM::GPRRegClass, &ARM::GPRRegClass,
190
191    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
193    0
194  };
195
196  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
197    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
198    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
199    &ARM::GPRRegClass,  &ARM::GPRRegClass,
200
201    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
203    0
204  };
205
206  if (STI.isThumb1Only()) {
207    return STI.isTargetDarwin()
208      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
209  }
210  return STI.isTargetDarwin()
211    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
212}
213
214BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
215  // FIXME: avoid re-calculating this everytime.
216  BitVector Reserved(getNumRegs());
217  Reserved.set(ARM::SP);
218  Reserved.set(ARM::PC);
219  if (STI.isTargetDarwin() || hasFP(MF))
220    Reserved.set(FramePtr);
221  // Some targets reserve R9.
222  if (STI.isR9Reserved())
223    Reserved.set(ARM::R9);
224  return Reserved;
225}
226
227bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
228                                        unsigned Reg) const {
229  switch (Reg) {
230  default: break;
231  case ARM::SP:
232  case ARM::PC:
233    return true;
234  case ARM::R7:
235  case ARM::R11:
236    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
237      return true;
238    break;
239  case ARM::R9:
240    return STI.isR9Reserved();
241  }
242
243  return false;
244}
245
246const TargetRegisterClass *
247ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
248  return &ARM::GPRRegClass;
249}
250
251/// getAllocationOrder - Returns the register allocation order for a specified
252/// register class in the form of a pair of TargetRegisterClass iterators.
253std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
254ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
255                                        unsigned HintType, unsigned HintReg,
256                                        const MachineFunction &MF) const {
257  // Alternative register allocation orders when favoring even / odd registers
258  // of register pairs.
259
260  // No FP, R9 is available.
261  static const unsigned GPREven1[] = {
262    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
263    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
264    ARM::R9, ARM::R11
265  };
266  static const unsigned GPROdd1[] = {
267    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
268    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
269    ARM::R8, ARM::R10
270  };
271
272  // FP is R7, R9 is available.
273  static const unsigned GPREven2[] = {
274    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
275    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
276    ARM::R9, ARM::R11
277  };
278  static const unsigned GPROdd2[] = {
279    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
280    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
281    ARM::R8, ARM::R10
282  };
283
284  // FP is R11, R9 is available.
285  static const unsigned GPREven3[] = {
286    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
287    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
288    ARM::R9
289  };
290  static const unsigned GPROdd3[] = {
291    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
292    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
293    ARM::R8
294  };
295
296  // No FP, R9 is not available.
297  static const unsigned GPREven4[] = {
298    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
299    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
300    ARM::R11
301  };
302  static const unsigned GPROdd4[] = {
303    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
304    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
305    ARM::R10
306  };
307
308  // FP is R7, R9 is not available.
309  static const unsigned GPREven5[] = {
310    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
311    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
312    ARM::R11
313  };
314  static const unsigned GPROdd5[] = {
315    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
316    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
317    ARM::R10
318  };
319
320  // FP is R11, R9 is not available.
321  static const unsigned GPREven6[] = {
322    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
323    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
324  };
325  static const unsigned GPROdd6[] = {
326    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
327    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
328  };
329
330
331  if (HintType == ARMRI::RegPairEven) {
332    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
333      // It's no longer possible to fulfill this hint. Return the default
334      // allocation order.
335      return std::make_pair(RC->allocation_order_begin(MF),
336                            RC->allocation_order_end(MF));
337
338    if (!STI.isTargetDarwin() && !hasFP(MF)) {
339      if (!STI.isR9Reserved())
340        return std::make_pair(GPREven1,
341                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
342      else
343        return std::make_pair(GPREven4,
344                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
345    } else if (FramePtr == ARM::R7) {
346      if (!STI.isR9Reserved())
347        return std::make_pair(GPREven2,
348                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
349      else
350        return std::make_pair(GPREven5,
351                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
352    } else { // FramePtr == ARM::R11
353      if (!STI.isR9Reserved())
354        return std::make_pair(GPREven3,
355                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
356      else
357        return std::make_pair(GPREven6,
358                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
359    }
360  } else if (HintType == ARMRI::RegPairOdd) {
361    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
362      // It's no longer possible to fulfill this hint. Return the default
363      // allocation order.
364      return std::make_pair(RC->allocation_order_begin(MF),
365                            RC->allocation_order_end(MF));
366
367    if (!STI.isTargetDarwin() && !hasFP(MF)) {
368      if (!STI.isR9Reserved())
369        return std::make_pair(GPROdd1,
370                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
371      else
372        return std::make_pair(GPROdd4,
373                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
374    } else if (FramePtr == ARM::R7) {
375      if (!STI.isR9Reserved())
376        return std::make_pair(GPROdd2,
377                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
378      else
379        return std::make_pair(GPROdd5,
380                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
381    } else { // FramePtr == ARM::R11
382      if (!STI.isR9Reserved())
383        return std::make_pair(GPROdd3,
384                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
385      else
386        return std::make_pair(GPROdd6,
387                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
388    }
389  }
390  return std::make_pair(RC->allocation_order_begin(MF),
391                        RC->allocation_order_end(MF));
392}
393
394/// ResolveRegAllocHint - Resolves the specified register allocation hint
395/// to a physical register. Returns the physical register if it is successful.
396unsigned
397ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
398                                         const MachineFunction &MF) const {
399  if (Reg == 0 || !isPhysicalRegister(Reg))
400    return 0;
401  if (Type == 0)
402    return Reg;
403  else if (Type == (unsigned)ARMRI::RegPairOdd)
404    // Odd register.
405    return getRegisterPairOdd(Reg, MF);
406  else if (Type == (unsigned)ARMRI::RegPairEven)
407    // Even register.
408    return getRegisterPairEven(Reg, MF);
409  return 0;
410}
411
412void
413ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
414                                        MachineFunction &MF) const {
415  MachineRegisterInfo *MRI = &MF.getRegInfo();
416  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
417  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
418       Hint.first == (unsigned)ARMRI::RegPairEven) &&
419      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
420    // If 'Reg' is one of the even / odd register pair and it's now changed
421    // (e.g. coalesced) into a different register. The other register of the
422    // pair allocation hint must be updated to reflect the relationship
423    // change.
424    unsigned OtherReg = Hint.second;
425    Hint = MRI->getRegAllocationHint(OtherReg);
426    if (Hint.second == Reg)
427      // Make sure the pair has not already divorced.
428      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
429  }
430}
431
432/// hasFP - Return true if the specified function should have a dedicated frame
433/// pointer register.  This is true if the function has variable sized allocas
434/// or if frame pointer elimination is disabled.
435///
436bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
437  const MachineFrameInfo *MFI = MF.getFrameInfo();
438  return (NoFramePointerElim ||
439          MFI->hasVarSizedObjects() ||
440          MFI->isFrameAddressTaken());
441}
442
443/// estimateStackSize - Estimate and return the size of the frame.
444static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
445  const MachineFrameInfo *FFI = MF.getFrameInfo();
446  int Offset = 0;
447  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
448    int FixedOff = -FFI->getObjectOffset(i);
449    if (FixedOff > Offset) Offset = FixedOff;
450  }
451  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
452    if (FFI->isDeadObjectIndex(i))
453      continue;
454    Offset += FFI->getObjectSize(i);
455    unsigned Align = FFI->getObjectAlignment(i);
456    // Adjust to alignment boundary
457    Offset = (Offset+Align-1)/Align*Align;
458  }
459  return (unsigned)Offset;
460}
461
462/// estimateRSStackSizeLimit - Look at each instruction that references stack
463/// frames and return the stack size limit beyond which some of these
464/// instructions will require scratch register during their expansion later.
465unsigned
466ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
467  unsigned Limit = (1 << 12) - 1;
468  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
469    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
470         I != E; ++I) {
471      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
472        if (!I->getOperand(i).isFI()) continue;
473
474        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
475        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
476        if (AddrMode == ARMII::AddrMode3 ||
477            AddrMode == ARMII::AddrModeT2_i8)
478          return (1 << 8) - 1;
479
480        if (AddrMode == ARMII::AddrMode5 ||
481            AddrMode == ARMII::AddrModeT2_i8s4)
482          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
483
484        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
485          // When the stack offset is negative, we will end up using
486          // the i8 instructions instead.
487          return (1 << 8) - 1;
488        break; // At most one FI per instruction
489      }
490    }
491  }
492
493  return Limit;
494}
495
496void
497ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
498                                                          RegScavenger *RS) const {
499  // This tells PEI to spill the FP as if it is any other callee-save register
500  // to take advantage the eliminateFrameIndex machinery. This also ensures it
501  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
502  // to combine multiple loads / stores.
503  bool CanEliminateFrame = true;
504  bool CS1Spilled = false;
505  bool LRSpilled = false;
506  unsigned NumGPRSpills = 0;
507  SmallVector<unsigned, 4> UnspilledCS1GPRs;
508  SmallVector<unsigned, 4> UnspilledCS2GPRs;
509  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
510
511  // Don't spill FP if the frame can be eliminated. This is determined
512  // by scanning the callee-save registers to see if any is used.
513  const unsigned *CSRegs = getCalleeSavedRegs();
514  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
515  for (unsigned i = 0; CSRegs[i]; ++i) {
516    unsigned Reg = CSRegs[i];
517    bool Spilled = false;
518    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
519      AFI->setCSRegisterIsSpilled(Reg);
520      Spilled = true;
521      CanEliminateFrame = false;
522    } else {
523      // Check alias registers too.
524      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
525        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
526          Spilled = true;
527          CanEliminateFrame = false;
528        }
529      }
530    }
531
532    if (CSRegClasses[i] == &ARM::GPRRegClass) {
533      if (Spilled) {
534        NumGPRSpills++;
535
536        if (!STI.isTargetDarwin()) {
537          if (Reg == ARM::LR)
538            LRSpilled = true;
539          CS1Spilled = true;
540          continue;
541        }
542
543        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
544        switch (Reg) {
545        case ARM::LR:
546          LRSpilled = true;
547          // Fallthrough
548        case ARM::R4:
549        case ARM::R5:
550        case ARM::R6:
551        case ARM::R7:
552          CS1Spilled = true;
553          break;
554        default:
555          break;
556        }
557      } else {
558        if (!STI.isTargetDarwin()) {
559          UnspilledCS1GPRs.push_back(Reg);
560          continue;
561        }
562
563        switch (Reg) {
564        case ARM::R4:
565        case ARM::R5:
566        case ARM::R6:
567        case ARM::R7:
568        case ARM::LR:
569          UnspilledCS1GPRs.push_back(Reg);
570          break;
571        default:
572          UnspilledCS2GPRs.push_back(Reg);
573          break;
574        }
575      }
576    }
577  }
578
579  bool ForceLRSpill = false;
580  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
581    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
582    // Force LR to be spilled if the Thumb function size is > 2048. This enables
583    // use of BL to implement far jump. If it turns out that it's not needed
584    // then the branch fix up path will undo it.
585    if (FnSize >= (1 << 11)) {
586      CanEliminateFrame = false;
587      ForceLRSpill = true;
588    }
589  }
590
591  bool ExtraCSSpill = false;
592  if (!CanEliminateFrame || hasFP(MF)) {
593    AFI->setHasStackFrame(true);
594
595    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
596    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
597    if (!LRSpilled && CS1Spilled) {
598      MF.getRegInfo().setPhysRegUsed(ARM::LR);
599      AFI->setCSRegisterIsSpilled(ARM::LR);
600      NumGPRSpills++;
601      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
602                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
603      ForceLRSpill = false;
604      ExtraCSSpill = true;
605    }
606
607    // Darwin ABI requires FP to point to the stack slot that contains the
608    // previous FP.
609    if (STI.isTargetDarwin() || hasFP(MF)) {
610      MF.getRegInfo().setPhysRegUsed(FramePtr);
611      NumGPRSpills++;
612    }
613
614    // If stack and double are 8-byte aligned and we are spilling an odd number
615    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
616    // the integer and double callee save areas.
617    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
618    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
619      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
620        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
621          unsigned Reg = UnspilledCS1GPRs[i];
622          // Don't spill high register if the function is thumb1
623          if (!AFI->isThumb1OnlyFunction() ||
624              isARMLowRegister(Reg) || Reg == ARM::LR) {
625            MF.getRegInfo().setPhysRegUsed(Reg);
626            AFI->setCSRegisterIsSpilled(Reg);
627            if (!isReservedReg(MF, Reg))
628              ExtraCSSpill = true;
629            break;
630          }
631        }
632      } else if (!UnspilledCS2GPRs.empty() &&
633                 !AFI->isThumb1OnlyFunction()) {
634        unsigned Reg = UnspilledCS2GPRs.front();
635        MF.getRegInfo().setPhysRegUsed(Reg);
636        AFI->setCSRegisterIsSpilled(Reg);
637        if (!isReservedReg(MF, Reg))
638          ExtraCSSpill = true;
639      }
640    }
641
642    // Estimate if we might need to scavenge a register at some point in order
643    // to materialize a stack offset. If so, either spill one additional
644    // callee-saved register or reserve a special spill slot to facilitate
645    // register scavenging.
646    if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
647      MachineFrameInfo  *MFI = MF.getFrameInfo();
648      if (estimateStackSize(MF, MFI) >= estimateRSStackSizeLimit(MF)) {
649        // If any non-reserved CS register isn't spilled, just spill one or two
650        // extra. That should take care of it!
651        unsigned NumExtras = TargetAlign / 4;
652        SmallVector<unsigned, 2> Extras;
653        while (NumExtras && !UnspilledCS1GPRs.empty()) {
654          unsigned Reg = UnspilledCS1GPRs.back();
655          UnspilledCS1GPRs.pop_back();
656          if (!isReservedReg(MF, Reg)) {
657            Extras.push_back(Reg);
658            NumExtras--;
659          }
660        }
661        while (NumExtras && !UnspilledCS2GPRs.empty()) {
662          unsigned Reg = UnspilledCS2GPRs.back();
663          UnspilledCS2GPRs.pop_back();
664          if (!isReservedReg(MF, Reg)) {
665            Extras.push_back(Reg);
666            NumExtras--;
667          }
668        }
669        if (Extras.size() && NumExtras == 0) {
670          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
671            MF.getRegInfo().setPhysRegUsed(Extras[i]);
672            AFI->setCSRegisterIsSpilled(Extras[i]);
673          }
674        } else {
675          // Reserve a slot closest to SP or frame pointer.
676          const TargetRegisterClass *RC = &ARM::GPRRegClass;
677          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
678                                                           RC->getAlignment()));
679        }
680      }
681    }
682  }
683
684  if (ForceLRSpill) {
685    MF.getRegInfo().setPhysRegUsed(ARM::LR);
686    AFI->setCSRegisterIsSpilled(ARM::LR);
687    AFI->setLRIsSpilledForFarJump(true);
688  }
689}
690
691unsigned ARMBaseRegisterInfo::getRARegister() const {
692  return ARM::LR;
693}
694
695unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
696  if (STI.isTargetDarwin() || hasFP(MF))
697    return FramePtr;
698  return ARM::SP;
699}
700
701unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
702  llvm_unreachable("What is the exception register");
703  return 0;
704}
705
706unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
707  llvm_unreachable("What is the exception handler register");
708  return 0;
709}
710
711int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
712  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
713}
714
715unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
716                                               const MachineFunction &MF) const {
717  switch (Reg) {
718  default: break;
719  // Return 0 if either register of the pair is a special register.
720  // So no R12, etc.
721  case ARM::R1:
722    return ARM::R0;
723  case ARM::R3:
724    // FIXME!
725    return STI.isThumb1Only() ? 0 : ARM::R2;
726  case ARM::R5:
727    return ARM::R4;
728  case ARM::R7:
729    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
730  case ARM::R9:
731    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
732  case ARM::R11:
733    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
734
735  case ARM::S1:
736    return ARM::S0;
737  case ARM::S3:
738    return ARM::S2;
739  case ARM::S5:
740    return ARM::S4;
741  case ARM::S7:
742    return ARM::S6;
743  case ARM::S9:
744    return ARM::S8;
745  case ARM::S11:
746    return ARM::S10;
747  case ARM::S13:
748    return ARM::S12;
749  case ARM::S15:
750    return ARM::S14;
751  case ARM::S17:
752    return ARM::S16;
753  case ARM::S19:
754    return ARM::S18;
755  case ARM::S21:
756    return ARM::S20;
757  case ARM::S23:
758    return ARM::S22;
759  case ARM::S25:
760    return ARM::S24;
761  case ARM::S27:
762    return ARM::S26;
763  case ARM::S29:
764    return ARM::S28;
765  case ARM::S31:
766    return ARM::S30;
767
768  case ARM::D1:
769    return ARM::D0;
770  case ARM::D3:
771    return ARM::D2;
772  case ARM::D5:
773    return ARM::D4;
774  case ARM::D7:
775    return ARM::D6;
776  case ARM::D9:
777    return ARM::D8;
778  case ARM::D11:
779    return ARM::D10;
780  case ARM::D13:
781    return ARM::D12;
782  case ARM::D15:
783    return ARM::D14;
784  case ARM::D17:
785    return ARM::D16;
786  case ARM::D19:
787    return ARM::D18;
788  case ARM::D21:
789    return ARM::D20;
790  case ARM::D23:
791    return ARM::D22;
792  case ARM::D25:
793    return ARM::D24;
794  case ARM::D27:
795    return ARM::D26;
796  case ARM::D29:
797    return ARM::D28;
798  case ARM::D31:
799    return ARM::D30;
800  }
801
802  return 0;
803}
804
805unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
806                                             const MachineFunction &MF) const {
807  switch (Reg) {
808  default: break;
809  // Return 0 if either register of the pair is a special register.
810  // So no R12, etc.
811  case ARM::R0:
812    return ARM::R1;
813  case ARM::R2:
814    // FIXME!
815    return STI.isThumb1Only() ? 0 : ARM::R3;
816  case ARM::R4:
817    return ARM::R5;
818  case ARM::R6:
819    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
820  case ARM::R8:
821    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
822  case ARM::R10:
823    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
824
825  case ARM::S0:
826    return ARM::S1;
827  case ARM::S2:
828    return ARM::S3;
829  case ARM::S4:
830    return ARM::S5;
831  case ARM::S6:
832    return ARM::S7;
833  case ARM::S8:
834    return ARM::S9;
835  case ARM::S10:
836    return ARM::S11;
837  case ARM::S12:
838    return ARM::S13;
839  case ARM::S14:
840    return ARM::S15;
841  case ARM::S16:
842    return ARM::S17;
843  case ARM::S18:
844    return ARM::S19;
845  case ARM::S20:
846    return ARM::S21;
847  case ARM::S22:
848    return ARM::S23;
849  case ARM::S24:
850    return ARM::S25;
851  case ARM::S26:
852    return ARM::S27;
853  case ARM::S28:
854    return ARM::S29;
855  case ARM::S30:
856    return ARM::S31;
857
858  case ARM::D0:
859    return ARM::D1;
860  case ARM::D2:
861    return ARM::D3;
862  case ARM::D4:
863    return ARM::D5;
864  case ARM::D6:
865    return ARM::D7;
866  case ARM::D8:
867    return ARM::D9;
868  case ARM::D10:
869    return ARM::D11;
870  case ARM::D12:
871    return ARM::D13;
872  case ARM::D14:
873    return ARM::D15;
874  case ARM::D16:
875    return ARM::D17;
876  case ARM::D18:
877    return ARM::D19;
878  case ARM::D20:
879    return ARM::D21;
880  case ARM::D22:
881    return ARM::D23;
882  case ARM::D24:
883    return ARM::D25;
884  case ARM::D26:
885    return ARM::D27;
886  case ARM::D28:
887    return ARM::D29;
888  case ARM::D30:
889    return ARM::D31;
890  }
891
892  return 0;
893}
894
895/// emitLoadConstPool - Emits a load from constpool to materialize the
896/// specified immediate.
897void ARMBaseRegisterInfo::
898emitLoadConstPool(MachineBasicBlock &MBB,
899                  MachineBasicBlock::iterator &MBBI,
900                  DebugLoc dl,
901                  unsigned DestReg, unsigned SubIdx, int Val,
902                  ARMCC::CondCodes Pred,
903                  unsigned PredReg) const {
904  MachineFunction &MF = *MBB.getParent();
905  MachineConstantPool *ConstantPool = MF.getConstantPool();
906  Constant *C = ConstantInt::get(Type::Int32Ty, Val);
907  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
908
909  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
910    .addReg(DestReg, getDefRegState(true), SubIdx)
911    .addConstantPoolIndex(Idx)
912    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
913}
914
915bool ARMBaseRegisterInfo::
916requiresRegisterScavenging(const MachineFunction &MF) const {
917  return true;
918}
919
920// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
921// not required, we reserve argument space for call sites in the function
922// immediately on entry to the current function. This eliminates the need for
923// add/sub sp brackets around call sites. Returns true if the call frame is
924// included as part of the stack frame.
925bool ARMBaseRegisterInfo::
926hasReservedCallFrame(MachineFunction &MF) const {
927  const MachineFrameInfo *FFI = MF.getFrameInfo();
928  unsigned CFSize = FFI->getMaxCallFrameSize();
929  // It's not always a good idea to include the call frame as part of the
930  // stack frame. ARM (especially Thumb) has small immediate offset to
931  // address the stack frame. So a large call frame can cause poor codegen
932  // and may even makes it impossible to scavenge a register.
933  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
934    return false;
935
936  return !MF.getFrameInfo()->hasVarSizedObjects();
937}
938
939static void
940emitSPUpdate(bool isARM,
941             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
942             DebugLoc dl, const ARMBaseInstrInfo &TII,
943             int NumBytes,
944             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
945  if (isARM)
946    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
947                            Pred, PredReg, TII);
948  else
949    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
950                           Pred, PredReg, TII);
951}
952
953
954void ARMBaseRegisterInfo::
955eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
956                              MachineBasicBlock::iterator I) const {
957  if (!hasReservedCallFrame(MF)) {
958    // If we have alloca, convert as follows:
959    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
960    // ADJCALLSTACKUP   -> add, sp, sp, amount
961    MachineInstr *Old = I;
962    DebugLoc dl = Old->getDebugLoc();
963    unsigned Amount = Old->getOperand(0).getImm();
964    if (Amount != 0) {
965      // We need to keep the stack aligned properly.  To do this, we round the
966      // amount of space needed for the outgoing arguments up to the next
967      // alignment boundary.
968      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
969      Amount = (Amount+Align-1)/Align*Align;
970
971      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
972      assert(!AFI->isThumb1OnlyFunction() &&
973             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
974      bool isARM = !AFI->isThumbFunction();
975
976      // Replace the pseudo instruction with a new instruction...
977      unsigned Opc = Old->getOpcode();
978      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
979      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
980      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
981        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
982        unsigned PredReg = Old->getOperand(2).getReg();
983        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
984      } else {
985        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
986        unsigned PredReg = Old->getOperand(3).getReg();
987        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
988        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
989      }
990    }
991  }
992  MBB.erase(I);
993}
994
995/// findScratchRegister - Find a 'free' ARM register. If register scavenger
996/// is not being used, R12 is available. Otherwise, try for a call-clobbered
997/// register first and then a spilled callee-saved register if that fails.
998static
999unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
1000                             ARMFunctionInfo *AFI) {
1001  unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
1002  assert(!AFI->isThumb1OnlyFunction());
1003  if (Reg == 0)
1004    // Try a already spilled CS register.
1005    Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
1006
1007  return Reg;
1008}
1009
1010void
1011ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1012                                         int SPAdj, RegScavenger *RS) const {
1013  unsigned i = 0;
1014  MachineInstr &MI = *II;
1015  MachineBasicBlock &MBB = *MI.getParent();
1016  MachineFunction &MF = *MBB.getParent();
1017  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1018  assert(!AFI->isThumb1OnlyFunction() &&
1019         "This eliminateFrameIndex does not suppor Thumb1!");
1020
1021  while (!MI.getOperand(i).isFI()) {
1022    ++i;
1023    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1024  }
1025
1026  unsigned FrameReg = ARM::SP;
1027  int FrameIndex = MI.getOperand(i).getIndex();
1028  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1029               MF.getFrameInfo()->getStackSize() + SPAdj;
1030
1031  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1032    Offset -= AFI->getGPRCalleeSavedArea1Offset();
1033  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1034    Offset -= AFI->getGPRCalleeSavedArea2Offset();
1035  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1036    Offset -= AFI->getDPRCalleeSavedAreaOffset();
1037  else if (hasFP(MF)) {
1038    assert(SPAdj == 0 && "Unexpected");
1039    // There is alloca()'s in this function, must reference off the frame
1040    // pointer instead.
1041    FrameReg = getFrameRegister(MF);
1042    Offset -= AFI->getFramePtrSpillOffset();
1043  }
1044
1045  // modify MI as necessary to handle as much of 'Offset' as possible
1046  if (!AFI->isThumbFunction())
1047    Offset = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1048  else {
1049    assert(AFI->isThumb2Function());
1050    Offset = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1051  }
1052  if (Offset == 0)
1053    return;
1054
1055  // If we get here, the immediate doesn't fit into the instruction.  We folded
1056  // as much as possible above, handle the rest, providing a register that is
1057  // SP+LargeImm.
1058  assert(Offset && "This code isn't needed if offset already handled!");
1059
1060  // Insert a set of r12 with the full address: r12 = sp + offset
1061  // If the offset we have is too large to fit into the instruction, we need
1062  // to form it with a series of ADDri's.  Do this by taking 8-bit chunks
1063  // out of 'Offset'.
1064  unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1065  if (ScratchReg == 0)
1066    // No register is "free". Scavenge a register.
1067    ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1068  int PIdx = MI.findFirstPredOperandIdx();
1069  ARMCC::CondCodes Pred = (PIdx == -1)
1070    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1071  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1072  if (!AFI->isThumbFunction())
1073    emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1074                            Offset, Pred, PredReg, TII);
1075  else {
1076    assert(AFI->isThumb2Function());
1077    emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1078                           Offset, Pred, PredReg, TII);
1079  }
1080  MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1081}
1082
1083/// Move iterator pass the next bunch of callee save load / store ops for
1084/// the particular spill area (1: integer area 1, 2: integer area 2,
1085/// 3: fp area, 0: don't care).
1086static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1087                                   MachineBasicBlock::iterator &MBBI,
1088                                   int Opc1, int Opc2, unsigned Area,
1089                                   const ARMSubtarget &STI) {
1090  while (MBBI != MBB.end() &&
1091         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1092         MBBI->getOperand(1).isFI()) {
1093    if (Area != 0) {
1094      bool Done = false;
1095      unsigned Category = 0;
1096      switch (MBBI->getOperand(0).getReg()) {
1097      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1098      case ARM::LR:
1099        Category = 1;
1100        break;
1101      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1102        Category = STI.isTargetDarwin() ? 2 : 1;
1103        break;
1104      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1105      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1106        Category = 3;
1107        break;
1108      default:
1109        Done = true;
1110        break;
1111      }
1112      if (Done || Category != Area)
1113        break;
1114    }
1115
1116    ++MBBI;
1117  }
1118}
1119
1120void ARMBaseRegisterInfo::
1121emitPrologue(MachineFunction &MF) const {
1122  MachineBasicBlock &MBB = MF.front();
1123  MachineBasicBlock::iterator MBBI = MBB.begin();
1124  MachineFrameInfo  *MFI = MF.getFrameInfo();
1125  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1126  assert(!AFI->isThumb1OnlyFunction() &&
1127         "This emitPrologue does not suppor Thumb1!");
1128  bool isARM = !AFI->isThumbFunction();
1129  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1130  unsigned NumBytes = MFI->getStackSize();
1131  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1132  DebugLoc dl = (MBBI != MBB.end() ?
1133                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1134
1135  // Determine the sizes of each callee-save spill areas and record which frame
1136  // belongs to which callee-save spill areas.
1137  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1138  int FramePtrSpillFI = 0;
1139
1140  if (VARegSaveSize)
1141    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1142
1143  if (!AFI->hasStackFrame()) {
1144    if (NumBytes != 0)
1145      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1146    return;
1147  }
1148
1149  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1150    unsigned Reg = CSI[i].getReg();
1151    int FI = CSI[i].getFrameIdx();
1152    switch (Reg) {
1153    case ARM::R4:
1154    case ARM::R5:
1155    case ARM::R6:
1156    case ARM::R7:
1157    case ARM::LR:
1158      if (Reg == FramePtr)
1159        FramePtrSpillFI = FI;
1160      AFI->addGPRCalleeSavedArea1Frame(FI);
1161      GPRCS1Size += 4;
1162      break;
1163    case ARM::R8:
1164    case ARM::R9:
1165    case ARM::R10:
1166    case ARM::R11:
1167      if (Reg == FramePtr)
1168        FramePtrSpillFI = FI;
1169      if (STI.isTargetDarwin()) {
1170        AFI->addGPRCalleeSavedArea2Frame(FI);
1171        GPRCS2Size += 4;
1172      } else {
1173        AFI->addGPRCalleeSavedArea1Frame(FI);
1174        GPRCS1Size += 4;
1175      }
1176      break;
1177    default:
1178      AFI->addDPRCalleeSavedAreaFrame(FI);
1179      DPRCSSize += 8;
1180    }
1181  }
1182
1183  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1184  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1185  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1186
1187  // Darwin ABI requires FP to point to the stack slot that contains the
1188  // previous FP.
1189  if (STI.isTargetDarwin() || hasFP(MF)) {
1190    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1191    MachineInstrBuilder MIB =
1192      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1193      .addFrameIndex(FramePtrSpillFI).addImm(0);
1194    AddDefaultCC(AddDefaultPred(MIB));
1195  }
1196
1197  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1198  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1199
1200  // Build the new SUBri to adjust SP for FP callee-save spill area.
1201  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1202  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1203
1204  // Determine starting offsets of spill areas.
1205  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1206  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1207  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1208  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1209  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1210  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1211  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1212
1213  NumBytes = DPRCSOffset;
1214  if (NumBytes) {
1215    // Insert it after all the callee-save spills.
1216    movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1217    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1218  }
1219
1220  if (STI.isTargetELF() && hasFP(MF)) {
1221    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1222                             AFI->getFramePtrSpillOffset());
1223  }
1224
1225  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1226  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1227  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1228}
1229
1230static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1231  for (unsigned i = 0; CSRegs[i]; ++i)
1232    if (Reg == CSRegs[i])
1233      return true;
1234  return false;
1235}
1236
1237static bool isCSRestore(MachineInstr *MI,
1238                        const ARMBaseInstrInfo &TII,
1239                        const unsigned *CSRegs) {
1240  return ((MI->getOpcode() == (int)ARM::FLDD ||
1241           MI->getOpcode() == (int)ARM::LDR ||
1242           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1243          MI->getOperand(1).isFI() &&
1244          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1245}
1246
1247void ARMBaseRegisterInfo::
1248emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1249  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1250  assert(MBBI->getDesc().isReturn() &&
1251         "Can only insert epilog into returning blocks");
1252  DebugLoc dl = MBBI->getDebugLoc();
1253  MachineFrameInfo *MFI = MF.getFrameInfo();
1254  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1255  assert(!AFI->isThumb1OnlyFunction() &&
1256         "This emitEpilogue does not suppor Thumb1!");
1257  bool isARM = !AFI->isThumbFunction();
1258
1259  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1260  int NumBytes = (int)MFI->getStackSize();
1261
1262  if (!AFI->hasStackFrame()) {
1263    if (NumBytes != 0)
1264      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1265  } else {
1266    // Unwind MBBI to point to first LDR / FLDD.
1267    const unsigned *CSRegs = getCalleeSavedRegs();
1268    if (MBBI != MBB.begin()) {
1269      do
1270        --MBBI;
1271      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1272      if (!isCSRestore(MBBI, TII, CSRegs))
1273        ++MBBI;
1274    }
1275
1276    // Move SP to start of FP callee save spill area.
1277    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1278                 AFI->getGPRCalleeSavedArea2Size() +
1279                 AFI->getDPRCalleeSavedAreaSize());
1280
1281    // Darwin ABI requires FP to point to the stack slot that contains the
1282    // previous FP.
1283    if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1284      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1285      // Reset SP based on frame pointer only if the stack frame extends beyond
1286      // frame pointer stack slot or target is ELF and the function has FP.
1287      if (AFI->getGPRCalleeSavedArea2Size() ||
1288          AFI->getDPRCalleeSavedAreaSize()  ||
1289          AFI->getDPRCalleeSavedAreaOffset()||
1290          hasFP(MF)) {
1291        if (NumBytes) {
1292          unsigned SUBriOpc = isARM ? ARM::SUBri : ARM::t2SUBri;
1293          BuildMI(MBB, MBBI, dl, TII.get(SUBriOpc), ARM::SP)
1294            .addReg(FramePtr)
1295            .addImm(NumBytes)
1296            .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1297        } else {
1298          // Thumb2 or ARM.
1299          unsigned MOVrOpc = isARM ? ARM::MOVr : ARM::t2MOVr;
1300          BuildMI(MBB, MBBI, dl, TII.get(MOVrOpc), ARM::SP)
1301            .addReg(FramePtr)
1302            .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1303        }
1304      }
1305    } else if (NumBytes)
1306      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1307
1308    // Move SP to start of integer callee save spill area 2.
1309    movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1310    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1311
1312    // Move SP to start of integer callee save spill area 1.
1313    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1314    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1315
1316    // Move SP to SP upon entry to the function.
1317    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1318    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1319  }
1320
1321  if (VARegSaveSize)
1322    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1323}
1324
1325#include "ARMGenRegisterInfo.inc"
1326