ARMISelDAGToDAG.cpp revision 0e5e3aacbe5dc069187b94896f5844f8dfbb44c5 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMTargetMachine.h"
16#include "llvm/CallingConv.h"
17#include "llvm/DerivedTypes.h"
18#include "llvm/Function.h"
19#include "llvm/Constants.h"
20#include "llvm/Intrinsics.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/SelectionDAG.h"
25#include "llvm/CodeGen/SelectionDAGISel.h"
26#include "llvm/CodeGen/SSARegMap.h"
27#include "llvm/Target/TargetLowering.h"
28#include "llvm/Support/Debug.h"
29#include <iostream>
30#include <vector>
31using namespace llvm;
32
33namespace {
34  class ARMTargetLowering : public TargetLowering {
35    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
36  public:
37    ARMTargetLowering(TargetMachine &TM);
38    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
39    virtual const char *getTargetNodeName(unsigned Opcode) const;
40  };
41
42}
43
44ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
45  : TargetLowering(TM) {
46  addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
47  addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass);
48  addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass);
49
50  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
51
52  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
53  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
54
55  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
56  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
57
58  setOperationAction(ISD::RET,           MVT::Other, Custom);
59  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
60  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
61
62  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
63  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
64  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
65
66  setOperationAction(ISD::SELECT, MVT::i32, Expand);
67
68  setOperationAction(ISD::SETCC, MVT::i32, Expand);
69  setOperationAction(ISD::SETCC, MVT::f32, Expand);
70  setOperationAction(ISD::SETCC, MVT::f64, Expand);
71
72  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
73
74  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
75
76  setOperationAction(ISD::BRIND, MVT::i32, Expand);
77  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
78  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
79  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
80
81  setOperationAction(ISD::BRCOND,        MVT::Other, Expand);
82
83  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
84  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
85  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
86  setOperationAction(ISD::SDIV,      MVT::i32, Expand);
87  setOperationAction(ISD::UDIV,      MVT::i32, Expand);
88  setOperationAction(ISD::SREM,      MVT::i32, Expand);
89  setOperationAction(ISD::UREM,      MVT::i32, Expand);
90
91  setOperationAction(ISD::VASTART,       MVT::Other, Custom);
92  setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
93  setOperationAction(ISD::VAEND,         MVT::Other, Expand);
94
95  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
96  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
97
98  setSchedulingPreference(SchedulingForRegPressure);
99  computeRegisterProperties();
100}
101
102namespace llvm {
103  namespace ARMISD {
104    enum NodeType {
105      // Start the numbering where the builting ops and target ops leave off.
106      FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
107      /// CALL - A direct function call.
108      CALL,
109
110      /// Return with a flag operand.
111      RET_FLAG,
112
113      CMP,
114
115      SELECT,
116
117      BR,
118
119      FSITOS,
120      FTOSIS,
121
122      FSITOD,
123      FTOSID,
124
125      FUITOS,
126      FTOUIS,
127
128      FUITOD,
129      FTOUID,
130
131      FMRRD,
132
133      FMDRR,
134
135      FMSTAT
136    };
137  }
138}
139
140/// DAGFPCCToARMCC - Convert a DAG fp condition code to an ARM CC
141// Unordered = !N & !Z & C & V = V
142// Ordered   =  N | Z | !C | !V = N | Z | !V
143static ARMCC::CondCodes DAGFPCCToARMCC(ISD::CondCode CC) {
144  switch (CC) {
145  default:
146    assert(0 && "Unknown fp condition code!");
147// SETOEQ = (N | Z | !V) & Z = Z                               = EQ
148  case ISD::SETEQ:
149  case ISD::SETOEQ: return ARMCC::EQ;
150// SETOGT = (N | Z | !V) & !N & !Z = !V &!N &!Z = (N = V) & !Z = GT
151  case ISD::SETGT:
152  case ISD::SETOGT: return ARMCC::GT;
153// SETOGE = (N | Z | !V) & !N = (Z | !V) & !N = !V & !N        = GE
154  case ISD::SETGE:
155  case ISD::SETOGE: return ARMCC::GE;
156// SETOLT = (N | Z | !V) & N = N                               = MI
157  case ISD::SETLT:
158  case ISD::SETOLT: return ARMCC::MI;
159// SETOLE = (N | Z | !V) & (N | Z) = N | Z = !C | Z            = LS
160  case ISD::SETLE:
161  case ISD::SETOLE: return ARMCC::LS;
162// SETONE = (N | Z | !V) & !Z = (N | !V) & Z = !V & Z = Z      = NE
163  case ISD::SETNE:
164  case ISD::SETONE: return ARMCC::NE;
165// SETO   = N | Z | !V = Z | !V = !V                           = VC
166  case ISD::SETO:   return ARMCC::VC;
167// SETUO  = V                                                  = VS
168  case ISD::SETUO:  return ARMCC::VS;
169// SETUEQ = V | Z                                              = ??
170// SETUGT = V | (!Z & !N) = !Z & !N = !Z & C                   = HI
171  case ISD::SETUGT: return ARMCC::HI;
172// SETUGE = V | !N = !N                                        = PL
173  case ISD::SETUGE: return ARMCC::PL;
174// SETULT = V | N                                              = ??
175// SETULE = V | Z | N                                          = ??
176// SETUNE = V | !Z = !Z                                        = NE
177  case ISD::SETUNE: return ARMCC::NE;
178  }
179}
180
181/// DAGIntCCToARMCC - Convert a DAG integer condition code to an ARM CC
182static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) {
183  switch (CC) {
184  default:
185    assert(0 && "Unknown integer condition code!");
186  case ISD::SETEQ:  return ARMCC::EQ;
187  case ISD::SETNE:  return ARMCC::NE;
188  case ISD::SETLT:  return ARMCC::LT;
189  case ISD::SETLE:  return ARMCC::LE;
190  case ISD::SETGT:  return ARMCC::GT;
191  case ISD::SETGE:  return ARMCC::GE;
192  case ISD::SETULT: return ARMCC::CC;
193  case ISD::SETULE: return ARMCC::LS;
194  case ISD::SETUGT: return ARMCC::HI;
195  case ISD::SETUGE: return ARMCC::CS;
196  }
197}
198
199const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
200  switch (Opcode) {
201  default: return 0;
202  case ARMISD::CALL:          return "ARMISD::CALL";
203  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
204  case ARMISD::SELECT:        return "ARMISD::SELECT";
205  case ARMISD::CMP:           return "ARMISD::CMP";
206  case ARMISD::BR:            return "ARMISD::BR";
207  case ARMISD::FSITOS:        return "ARMISD::FSITOS";
208  case ARMISD::FTOSIS:        return "ARMISD::FTOSIS";
209  case ARMISD::FSITOD:        return "ARMISD::FSITOD";
210  case ARMISD::FTOSID:        return "ARMISD::FTOSID";
211  case ARMISD::FUITOS:        return "ARMISD::FUITOS";
212  case ARMISD::FTOUIS:        return "ARMISD::FTOUIS";
213  case ARMISD::FUITOD:        return "ARMISD::FUITOD";
214  case ARMISD::FTOUID:        return "ARMISD::FTOUID";
215  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
216  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
217  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
218  }
219}
220
221class ArgumentLayout {
222  std::vector<bool>           is_reg;
223  std::vector<unsigned>       pos;
224  std::vector<MVT::ValueType> types;
225public:
226  ArgumentLayout(const std::vector<MVT::ValueType> &Types) {
227    types = Types;
228
229    unsigned      RegNum = 0;
230    unsigned StackOffset = 0;
231    for(std::vector<MVT::ValueType>::const_iterator I = Types.begin();
232        I != Types.end();
233        ++I) {
234      MVT::ValueType VT = *I;
235      assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
236      unsigned     size = MVT::getSizeInBits(VT)/32;
237
238      RegNum = ((RegNum + size - 1) / size) * size;
239      if (RegNum < 4) {
240        pos.push_back(RegNum);
241        is_reg.push_back(true);
242        RegNum += size;
243      } else {
244        unsigned bytes = size * 32/8;
245        StackOffset = ((StackOffset + bytes - 1) / bytes) * bytes;
246        pos.push_back(StackOffset);
247        is_reg.push_back(false);
248        StackOffset += bytes;
249      }
250    }
251  }
252  unsigned getRegisterNum(unsigned argNum) {
253    assert(isRegister(argNum));
254    return pos[argNum];
255  }
256  unsigned getOffset(unsigned argNum) {
257    assert(isOffset(argNum));
258    return pos[argNum];
259  }
260  unsigned isRegister(unsigned argNum) {
261    assert(argNum < is_reg.size());
262    return is_reg[argNum];
263  }
264  unsigned isOffset(unsigned argNum) {
265    return !isRegister(argNum);
266  }
267  MVT::ValueType getType(unsigned argNum) {
268    assert(argNum < types.size());
269    return types[argNum];
270  }
271  unsigned getStackSize(void) {
272    int last = is_reg.size() - 1;
273    if (last < 0)
274      return 0;
275    if (isRegister(last))
276      return 0;
277    return getOffset(last) + MVT::getSizeInBits(getType(last))/8;
278  }
279  int lastRegArg(void) {
280    int size = is_reg.size();
281    int last = 0;
282    while(last < size && isRegister(last))
283      last++;
284    last--;
285    return last;
286  }
287  int lastRegNum(void) {
288    int            l = lastRegArg();
289    if (l < 0)
290      return -1;
291    unsigned       r = getRegisterNum(l);
292    MVT::ValueType t = getType(l);
293    assert(t == MVT::i32 || t == MVT::f32 || t == MVT::f64);
294    if (t == MVT::f64)
295      return r + 1;
296    return r;
297  }
298};
299
300// This transforms a ISD::CALL node into a
301// callseq_star <- ARMISD:CALL <- callseq_end
302// chain
303static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
304  SDOperand Chain    = Op.getOperand(0);
305  unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
306  assert((CallConv == CallingConv::C ||
307          CallConv == CallingConv::Fast)
308         && "unknown calling convention");
309  bool isVarArg      = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
310  bool isTailCall    = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
311  SDOperand Callee   = Op.getOperand(4);
312  unsigned NumOps    = (Op.getNumOperands() - 5) / 2;
313  SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32);
314  static const unsigned regs[] = {
315    ARM::R0, ARM::R1, ARM::R2, ARM::R3
316  };
317
318  std::vector<MVT::ValueType> Types;
319  for (unsigned i = 0; i < NumOps; ++i) {
320    MVT::ValueType VT = Op.getOperand(5+2*i).getValueType();
321    Types.push_back(VT);
322  }
323  ArgumentLayout Layout(Types);
324
325  unsigned NumBytes = Layout.getStackSize();
326
327  Chain = DAG.getCALLSEQ_START(Chain,
328                               DAG.getConstant(NumBytes, MVT::i32));
329
330  //Build a sequence of stores
331  std::vector<SDOperand> MemOpChains;
332  for (unsigned i = Layout.lastRegArg() + 1; i < NumOps; ++i) {
333    SDOperand      Arg = Op.getOperand(5+2*i);
334    unsigned ArgOffset = Layout.getOffset(i);
335    SDOperand   PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
336    PtrOff             = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
337    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
338  }
339  if (!MemOpChains.empty())
340    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
341                        &MemOpChains[0], MemOpChains.size());
342
343  // If the callee is a GlobalAddress node (quite common, every direct call is)
344  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
345  // Likewise ExternalSymbol -> TargetExternalSymbol.
346  assert(Callee.getValueType() == MVT::i32);
347  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
348    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
349  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
350    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
351
352  // If this is a direct call, pass the chain and the callee.
353  assert (Callee.Val);
354  std::vector<SDOperand> Ops;
355  Ops.push_back(Chain);
356  Ops.push_back(Callee);
357
358  // Build a sequence of copy-to-reg nodes chained together with token chain
359  // and flag operands which copy the outgoing args into the appropriate regs.
360  SDOperand InFlag;
361  for (int i = 0, e = Layout.lastRegArg(); i <= e; ++i) {
362    SDOperand     Arg = Op.getOperand(5+2*i);
363    unsigned   RegNum = Layout.getRegisterNum(i);
364    unsigned     Reg1 = regs[RegNum];
365    MVT::ValueType VT = Layout.getType(i);
366    assert(VT == Arg.getValueType());
367    assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
368
369    // Add argument register to the end of the list so that it is known live
370    // into the call.
371    Ops.push_back(DAG.getRegister(Reg1, MVT::i32));
372    if (VT == MVT::f64) {
373      unsigned    Reg2 = regs[RegNum + 1];
374      SDOperand SDReg1 = DAG.getRegister(Reg1, MVT::i32);
375      SDOperand SDReg2 = DAG.getRegister(Reg2, MVT::i32);
376
377      Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
378      SDVTList    VTs = DAG.getVTList(MVT::Other, MVT::Flag);
379      SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg, InFlag};
380      Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, InFlag.Val ? 5 : 4);
381    } else {
382      if (VT == MVT::f32)
383        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);
384      Chain = DAG.getCopyToReg(Chain, Reg1, Arg, InFlag);
385    }
386    InFlag = Chain.getValue(1);
387  }
388
389  std::vector<MVT::ValueType> NodeTys;
390  NodeTys.push_back(MVT::Other);   // Returns a chain
391  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
392
393  unsigned CallOpc = ARMISD::CALL;
394  if (InFlag.Val)
395    Ops.push_back(InFlag);
396  Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
397  InFlag = Chain.getValue(1);
398
399  std::vector<SDOperand> ResultVals;
400  NodeTys.clear();
401
402  // If the call has results, copy the values out of the ret val registers.
403  MVT::ValueType VT = Op.Val->getValueType(0);
404  if (VT != MVT::Other) {
405    assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
406
407    SDOperand Value1 = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
408    Chain            = Value1.getValue(1);
409    InFlag           = Value1.getValue(2);
410    NodeTys.push_back(VT);
411    if (VT == MVT::i32) {
412      ResultVals.push_back(Value1);
413      if (Op.Val->getValueType(1) == MVT::i32) {
414        SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag);
415        Chain            = Value2.getValue(1);
416        ResultVals.push_back(Value2);
417        NodeTys.push_back(VT);
418      }
419    }
420    if (VT == MVT::f32) {
421      SDOperand Value = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Value1);
422      ResultVals.push_back(Value);
423    }
424    if (VT == MVT::f64) {
425      SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag);
426      Chain            = Value2.getValue(1);
427      SDOperand Value  = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2);
428      ResultVals.push_back(Value);
429    }
430  }
431
432  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
433                      DAG.getConstant(NumBytes, MVT::i32));
434  NodeTys.push_back(MVT::Other);
435
436  if (ResultVals.empty())
437    return Chain;
438
439  ResultVals.push_back(Chain);
440  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
441                              ResultVals.size());
442  return Res.getValue(Op.ResNo);
443}
444
445static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
446  SDOperand Copy;
447  SDOperand Chain = Op.getOperand(0);
448  SDOperand    R0 = DAG.getRegister(ARM::R0, MVT::i32);
449  SDOperand    R1 = DAG.getRegister(ARM::R1, MVT::i32);
450
451  switch(Op.getNumOperands()) {
452  default:
453    assert(0 && "Do not know how to return this many arguments!");
454    abort();
455  case 1: {
456    SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
457    return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
458  }
459  case 3: {
460    SDOperand Val = Op.getOperand(1);
461    assert(Val.getValueType() == MVT::i32 ||
462	   Val.getValueType() == MVT::f32 ||
463	   Val.getValueType() == MVT::f64);
464
465    if (Val.getValueType() == MVT::f64) {
466      SDVTList    VTs = DAG.getVTList(MVT::Other, MVT::Flag);
467      SDOperand Ops[] = {Chain, R0, R1, Val};
468      Copy  = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
469    } else {
470      if (Val.getValueType() == MVT::f32)
471	Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
472      Copy = DAG.getCopyToReg(Chain, R0, Val, SDOperand());
473    }
474
475    if (DAG.getMachineFunction().liveout_empty()) {
476      DAG.getMachineFunction().addLiveOut(ARM::R0);
477      if (Val.getValueType() == MVT::f64)
478        DAG.getMachineFunction().addLiveOut(ARM::R1);
479    }
480    break;
481  }
482  case 5:
483    Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
484    Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
485    // If we haven't noted the R0+R1 are live out, do so now.
486    if (DAG.getMachineFunction().liveout_empty()) {
487      DAG.getMachineFunction().addLiveOut(ARM::R0);
488      DAG.getMachineFunction().addLiveOut(ARM::R1);
489    }
490    break;
491  }
492
493  //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
494  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
495}
496
497static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
498  MVT::ValueType PtrVT = Op.getValueType();
499  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
500  Constant *C = CP->getConstVal();
501  SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
502
503  return CPI;
504}
505
506static SDOperand LowerGlobalAddress(SDOperand Op,
507				    SelectionDAG &DAG) {
508  GlobalValue  *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
509  int alignment = 2;
510  SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment);
511  return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr, NULL, 0);
512}
513
514static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
515                              unsigned VarArgsFrameIndex) {
516  // vastart just stores the address of the VarArgsFrameIndex slot into the
517  // memory location argument.
518  MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
519  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
520  SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
521  return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
522                      SV->getOffset());
523}
524
525static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
526				       int &VarArgsFrameIndex) {
527  MachineFunction   &MF = DAG.getMachineFunction();
528  MachineFrameInfo *MFI = MF.getFrameInfo();
529  SSARegMap     *RegMap = MF.getSSARegMap();
530  unsigned      NumArgs = Op.Val->getNumValues()-1;
531  SDOperand        Root = Op.getOperand(0);
532  bool         isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
533  static const unsigned REGS[] = {
534    ARM::R0, ARM::R1, ARM::R2, ARM::R3
535  };
536
537  std::vector<MVT::ValueType> Types(Op.Val->value_begin(), Op.Val->value_end() - 1);
538  ArgumentLayout Layout(Types);
539
540  std::vector<SDOperand> ArgValues;
541  for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) {
542    MVT::ValueType VT = Types[ArgNo];
543
544    SDOperand Value;
545    if (Layout.isRegister(ArgNo)) {
546      assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
547      unsigned  RegNum = Layout.getRegisterNum(ArgNo);
548      unsigned    Reg1 = REGS[RegNum];
549      unsigned   VReg1 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
550      SDOperand Value1 = DAG.getCopyFromReg(Root, VReg1, MVT::i32);
551      MF.addLiveIn(Reg1, VReg1);
552      if (VT == MVT::f64) {
553        unsigned    Reg2 = REGS[RegNum + 1];
554        unsigned   VReg2 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
555        SDOperand Value2 = DAG.getCopyFromReg(Root, VReg2, MVT::i32);
556        MF.addLiveIn(Reg2, VReg2);
557        Value            = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2);
558      } else {
559        Value = Value1;
560        if (VT == MVT::f32)
561          Value = DAG.getNode(ISD::BIT_CONVERT, VT, Value);
562      }
563    } else {
564      // If the argument is actually used, emit a load from the right stack
565      // slot.
566      if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
567        unsigned Offset = Layout.getOffset(ArgNo);
568        unsigned   Size = MVT::getSizeInBits(VT)/8;
569        int          FI = MFI->CreateFixedObject(Size, Offset);
570        SDOperand   FIN = DAG.getFrameIndex(FI, VT);
571        Value = DAG.getLoad(VT, Root, FIN, NULL, 0);
572      } else {
573        Value = DAG.getNode(ISD::UNDEF, VT);
574      }
575    }
576    ArgValues.push_back(Value);
577  }
578
579  unsigned NextRegNum = Layout.lastRegNum() + 1;
580
581  if (isVarArg) {
582    //If this function is vararg we must store the remaing
583    //registers so that they can be acessed with va_start
584    VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
585                                               -16 + NextRegNum * 4);
586
587    SmallVector<SDOperand, 4> MemOps;
588    for (unsigned RegNo = NextRegNum; RegNo < 4; ++RegNo) {
589      int RegOffset = - (4 - RegNo) * 4;
590      int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
591				      RegOffset);
592      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
593
594      unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
595      MF.addLiveIn(REGS[RegNo], VReg);
596
597      SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
598      SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
599      MemOps.push_back(Store);
600    }
601    Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
602  }
603
604  ArgValues.push_back(Root);
605
606  // Return the new list of results.
607  std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
608                                    Op.Val->value_end());
609  return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
610}
611
612static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS,
613                        SelectionDAG &DAG) {
614  MVT::ValueType vt = LHS.getValueType();
615  assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
616
617  SDOperand Cmp = DAG.getNode(ARMISD::CMP,  MVT::Flag, LHS, RHS);
618
619  if (vt != MVT::i32)
620    Cmp = DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
621  return Cmp;
622}
623
624static SDOperand GetARMCC(ISD::CondCode CC, MVT::ValueType vt,
625                          SelectionDAG &DAG) {
626  assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
627  if (vt == MVT::i32)
628    return DAG.getConstant(DAGIntCCToARMCC(CC), MVT::i32);
629  else
630    return DAG.getConstant(DAGFPCCToARMCC(CC), MVT::i32);
631}
632
633static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
634  SDOperand LHS = Op.getOperand(0);
635  SDOperand RHS = Op.getOperand(1);
636  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
637  SDOperand TrueVal = Op.getOperand(2);
638  SDOperand FalseVal = Op.getOperand(3);
639  SDOperand      Cmp = GetCMP(CC, LHS, RHS, DAG);
640  SDOperand    ARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
641  return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
642}
643
644static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
645  SDOperand  Chain = Op.getOperand(0);
646  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
647  SDOperand    LHS = Op.getOperand(2);
648  SDOperand    RHS = Op.getOperand(3);
649  SDOperand   Dest = Op.getOperand(4);
650  SDOperand    Cmp = GetCMP(CC, LHS, RHS, DAG);
651  SDOperand  ARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
652  return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
653}
654
655static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
656  SDOperand IntVal  = Op.getOperand(0);
657  assert(IntVal.getValueType() == MVT::i32);
658  MVT::ValueType vt = Op.getValueType();
659  assert(vt == MVT::f32 ||
660         vt == MVT::f64);
661
662  SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
663  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FSITOS : ARMISD::FSITOD;
664  return DAG.getNode(op, vt, Tmp);
665}
666
667static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
668  assert(Op.getValueType() == MVT::i32);
669  SDOperand FloatVal = Op.getOperand(0);
670  MVT::ValueType  vt = FloatVal.getValueType();
671  assert(vt == MVT::f32 || vt == MVT::f64);
672
673  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOSIS : ARMISD::FTOSID;
674  SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal);
675  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp);
676}
677
678static SDOperand LowerUINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
679  SDOperand IntVal  = Op.getOperand(0);
680  assert(IntVal.getValueType() == MVT::i32);
681  MVT::ValueType vt = Op.getValueType();
682  assert(vt == MVT::f32 ||
683         vt == MVT::f64);
684
685  SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
686  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FUITOS : ARMISD::FUITOD;
687  return DAG.getNode(op, vt, Tmp);
688}
689
690static SDOperand LowerFP_TO_UINT(SDOperand Op, SelectionDAG &DAG) {
691  assert(Op.getValueType() == MVT::i32);
692  SDOperand FloatVal = Op.getOperand(0);
693  MVT::ValueType  vt = FloatVal.getValueType();
694  assert(vt == MVT::f32 || vt == MVT::f64);
695
696  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOUIS : ARMISD::FTOUID;
697  SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal);
698  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp);
699}
700
701SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
702  switch (Op.getOpcode()) {
703  default:
704    assert(0 && "Should not custom lower this!");
705    abort();
706  case ISD::ConstantPool:
707    return LowerConstantPool(Op, DAG);
708  case ISD::GlobalAddress:
709    return LowerGlobalAddress(Op, DAG);
710  case ISD::FP_TO_SINT:
711    return LowerFP_TO_SINT(Op, DAG);
712  case ISD::SINT_TO_FP:
713    return LowerSINT_TO_FP(Op, DAG);
714  case ISD::FP_TO_UINT:
715    return LowerFP_TO_UINT(Op, DAG);
716  case ISD::UINT_TO_FP:
717    return LowerUINT_TO_FP(Op, DAG);
718  case ISD::FORMAL_ARGUMENTS:
719    return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
720  case ISD::CALL:
721    return LowerCALL(Op, DAG);
722  case ISD::RET:
723    return LowerRET(Op, DAG);
724  case ISD::SELECT_CC:
725    return LowerSELECT_CC(Op, DAG);
726  case ISD::BR_CC:
727    return LowerBR_CC(Op, DAG);
728  case ISD::VASTART:
729    return LowerVASTART(Op, DAG, VarArgsFrameIndex);
730  }
731}
732
733//===----------------------------------------------------------------------===//
734// Instruction Selector Implementation
735//===----------------------------------------------------------------------===//
736
737//===--------------------------------------------------------------------===//
738/// ARMDAGToDAGISel - ARM specific code to select ARM machine
739/// instructions for SelectionDAG operations.
740///
741namespace {
742class ARMDAGToDAGISel : public SelectionDAGISel {
743  ARMTargetLowering Lowering;
744
745public:
746  ARMDAGToDAGISel(TargetMachine &TM)
747    : SelectionDAGISel(Lowering), Lowering(TM) {
748  }
749
750  SDNode *Select(SDOperand Op);
751  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
752  bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
753  bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
754		       SDOperand &ShiftType);
755  bool SelectAddrMode5(SDOperand N, SDOperand &Arg, SDOperand &Offset);
756
757  // Include the pieces autogenerated from the target description.
758#include "ARMGenDAGISel.inc"
759};
760
761void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
762  DEBUG(BB->dump());
763
764  DAG.setRoot(SelectRoot(DAG.getRoot()));
765  DAG.RemoveDeadNodes();
766
767  ScheduleAndEmitDAG(DAG);
768}
769
770static bool isInt12Immediate(SDNode *N, short &Imm) {
771  if (N->getOpcode() != ISD::Constant)
772    return false;
773
774  int32_t t = cast<ConstantSDNode>(N)->getValue();
775  int max = 1<<12;
776  int min = -max;
777  if (t > min && t < max) {
778    Imm = t;
779    return true;
780  }
781  else
782    return false;
783}
784
785static bool isInt12Immediate(SDOperand Op, short &Imm) {
786  return isInt12Immediate(Op.Val, Imm);
787}
788
789static uint32_t rotateL(uint32_t x) {
790  uint32_t bit31 = (x & (1 << 31)) >> 31;
791  uint32_t     t = x << 1;
792  return t | bit31;
793}
794
795static bool isUInt8Immediate(uint32_t x) {
796  return x < (1 << 8);
797}
798
799static bool isRotInt8Immediate(uint32_t x) {
800  int r;
801  for (r = 0; r < 16; r++) {
802    if (isUInt8Immediate(x))
803      return true;
804    x = rotateL(rotateL(x));
805  }
806  return false;
807}
808
809bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
810				      SDOperand &Arg,
811				      SDOperand &Shift,
812				      SDOperand &ShiftType) {
813  switch(N.getOpcode()) {
814  case ISD::Constant: {
815    uint32_t val = cast<ConstantSDNode>(N)->getValue();
816    if(!isRotInt8Immediate(val)) {
817      Constant    *C = ConstantInt::get(Type::UIntTy, val);
818      int  alignment = 2;
819      SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
820      SDOperand    Z = CurDAG->getTargetConstant(0,     MVT::i32);
821      SDNode      *n = CurDAG->getTargetNode(ARM::ldr,  MVT::i32, Z, Addr);
822      Arg            = SDOperand(n, 0);
823    } else
824      Arg            = CurDAG->getTargetConstant(val,    MVT::i32);
825
826    Shift     = CurDAG->getTargetConstant(0,             MVT::i32);
827    ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
828    return true;
829  }
830  case ISD::SRA:
831    Arg       = N.getOperand(0);
832    Shift     = N.getOperand(1);
833    ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32);
834    return true;
835  case ISD::SRL:
836    Arg       = N.getOperand(0);
837    Shift     = N.getOperand(1);
838    ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32);
839    return true;
840  case ISD::SHL:
841    Arg       = N.getOperand(0);
842    Shift     = N.getOperand(1);
843    ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
844    return true;
845  }
846
847  Arg       = N;
848  Shift     = CurDAG->getTargetConstant(0, MVT::i32);
849  ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
850  return true;
851}
852
853bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg,
854                                      SDOperand &Offset) {
855  //TODO: detect offset
856  Offset = CurDAG->getTargetConstant(0, MVT::i32);
857  Arg    = N;
858  return true;
859}
860
861//register plus/minus 12 bit offset
862bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
863				    SDOperand &Base) {
864  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
865    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
866    Offset = CurDAG->getTargetConstant(0, MVT::i32);
867    return true;
868  }
869  if (N.getOpcode() == ISD::ADD) {
870    short imm = 0;
871    if (isInt12Immediate(N.getOperand(1), imm)) {
872      Offset = CurDAG->getTargetConstant(imm, MVT::i32);
873      if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
874	Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
875      } else {
876	Base = N.getOperand(0);
877      }
878      return true; // [r+i]
879    }
880  }
881
882  Offset = CurDAG->getTargetConstant(0, MVT::i32);
883  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
884    Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
885  }
886  else
887    Base = N;
888  return true;      //any address fits in a register
889}
890
891SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
892  SDNode *N = Op.Val;
893
894  switch (N->getOpcode()) {
895  default:
896    return SelectCode(Op);
897    break;
898  }
899  return NULL;
900}
901
902}  // end anonymous namespace
903
904/// createARMISelDag - This pass converts a legalized DAG into a
905/// ARM-specific DAG, ready for instruction scheduling.
906///
907FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
908  return new ARMDAGToDAGISel(TM);
909}
910