ARMISelDAGToDAG.cpp revision 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(true));
49
50static cl::opt<bool>
51DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
52  cl::desc("Enable / disable ARM integer abs transform"),
53  cl::init(false));
54
55//===--------------------------------------------------------------------===//
56/// ARMDAGToDAGISel - ARM specific code to select ARM machine
57/// instructions for SelectionDAG operations.
58///
59namespace {
60
61enum AddrMode2Type {
62  AM2_BASE, // Simple AM2 (+-imm12)
63  AM2_SHOP  // Shifter-op AM2
64};
65
66class ARMDAGToDAGISel : public SelectionDAGISel {
67  ARMBaseTargetMachine &TM;
68  const ARMBaseInstrInfo *TII;
69
70  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
71  /// make the right decision when generating code for different targets.
72  const ARMSubtarget *Subtarget;
73
74public:
75  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
76                           CodeGenOpt::Level OptLevel)
77    : SelectionDAGISel(tm, OptLevel), TM(tm),
78      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
79      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
80  }
81
82  virtual const char *getPassName() const {
83    return "ARM Instruction Selection";
84  }
85
86  /// getI32Imm - Return a target constant of type i32 with the specified
87  /// value.
88  inline SDValue getI32Imm(unsigned Imm) {
89    return CurDAG->getTargetConstant(Imm, MVT::i32);
90  }
91
92  SDNode *Select(SDNode *N);
93
94
95  bool hasNoVMLxHazardUse(SDNode *N) const;
96  bool isShifterOpProfitable(const SDValue &Shift,
97                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
98  bool SelectRegShifterOperand(SDValue N, SDValue &A,
99                               SDValue &B, SDValue &C,
100                               bool CheckProfitability = true);
101  bool SelectImmShifterOperand(SDValue N, SDValue &A,
102                               SDValue &B, bool CheckProfitability = true);
103  bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
104                                    SDValue &B, SDValue &C) {
105    // Don't apply the profitability check
106    return SelectRegShifterOperand(N, A, B, C, false);
107  }
108  bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
109                                    SDValue &B) {
110    // Don't apply the profitability check
111    return SelectImmShifterOperand(N, A, B, false);
112  }
113
114  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116
117  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
118                                      SDValue &Offset, SDValue &Opc);
119  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
120                           SDValue &Opc) {
121    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
122  }
123
124  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
125                           SDValue &Opc) {
126    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
127  }
128
129  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
130                       SDValue &Opc) {
131    SelectAddrMode2Worker(N, Base, Offset, Opc);
132//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
133    // This always matches one way or another.
134    return true;
135  }
136
137  bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
138                             SDValue &Offset, SDValue &Opc);
139  bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
140                             SDValue &Offset, SDValue &Opc);
141  bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142                             SDValue &Offset, SDValue &Opc);
143  bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
144  bool SelectAddrMode3(SDValue N, SDValue &Base,
145                       SDValue &Offset, SDValue &Opc);
146  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
147                             SDValue &Offset, SDValue &Opc);
148  bool SelectAddrMode5(SDValue N, SDValue &Base,
149                       SDValue &Offset);
150  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151  bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
152
153  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
154
155  // Thumb Addressing Modes:
156  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
157  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
158                             unsigned Scale);
159  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
160  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
161  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
162  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
163                                SDValue &OffImm);
164  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
165                                 SDValue &OffImm);
166  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
167                                 SDValue &OffImm);
168  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
169                                 SDValue &OffImm);
170  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
171
172  // Thumb 2 Addressing Modes:
173  bool SelectT2ShifterOperandReg(SDValue N,
174                                 SDValue &BaseReg, SDValue &Opc);
175  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
176  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
177                            SDValue &OffImm);
178  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
179                                 SDValue &OffImm);
180  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
181                             SDValue &OffReg, SDValue &ShImm);
182
183  inline bool is_so_imm(unsigned Imm) const {
184    return ARM_AM::getSOImmVal(Imm) != -1;
185  }
186
187  inline bool is_so_imm_not(unsigned Imm) const {
188    return ARM_AM::getSOImmVal(~Imm) != -1;
189  }
190
191  inline bool is_t2_so_imm(unsigned Imm) const {
192    return ARM_AM::getT2SOImmVal(Imm) != -1;
193  }
194
195  inline bool is_t2_so_imm_not(unsigned Imm) const {
196    return ARM_AM::getT2SOImmVal(~Imm) != -1;
197  }
198
199  // Include the pieces autogenerated from the target description.
200#include "ARMGenDAGISel.inc"
201
202private:
203  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
204  /// ARM.
205  SDNode *SelectARMIndexedLoad(SDNode *N);
206  SDNode *SelectT2IndexedLoad(SDNode *N);
207
208  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
209  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
210  /// loads of D registers and even subregs and odd subregs of Q registers.
211  /// For NumVecs <= 2, QOpcodes1 is not used.
212  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
213                    unsigned *DOpcodes,
214                    unsigned *QOpcodes0, unsigned *QOpcodes1);
215
216  /// SelectVST - Select NEON store intrinsics.  NumVecs should
217  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
218  /// stores of D registers and even subregs and odd subregs of Q registers.
219  /// For NumVecs <= 2, QOpcodes1 is not used.
220  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
221                    unsigned *DOpcodes,
222                    unsigned *QOpcodes0, unsigned *QOpcodes1);
223
224  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
225  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
226  /// load/store of D registers and Q registers.
227  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
228                          bool isUpdating, unsigned NumVecs,
229                          unsigned *DOpcodes, unsigned *QOpcodes);
230
231  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
232  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
233  /// for loading D registers.  (Q registers are not supported.)
234  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
235                       unsigned *Opcodes);
236
237  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
238  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
239  /// generated to force the table registers to be consecutive.
240  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
241
242  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
244
245  /// SelectCMOVOp - Select CMOV instructions for ARM.
246  SDNode *SelectCMOVOp(SDNode *N);
247  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
248                              ARMCC::CondCodes CCVal, SDValue CCR,
249                              SDValue InFlag);
250  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
251                               ARMCC::CondCodes CCVal, SDValue CCR,
252                               SDValue InFlag);
253  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
254                              ARMCC::CondCodes CCVal, SDValue CCR,
255                              SDValue InFlag);
256  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
257                               ARMCC::CondCodes CCVal, SDValue CCR,
258                               SDValue InFlag);
259
260  // Select special operations if node forms integer ABS pattern
261  SDNode *SelectABSOp(SDNode *N);
262
263  SDNode *SelectConcatVector(SDNode *N);
264
265  SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
266
267  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
268  /// inline asm expressions.
269  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
270                                            char ConstraintCode,
271                                            std::vector<SDValue> &OutOps);
272
273  // Form pairs of consecutive S, D, or Q registers.
274  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
275  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
276  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
277
278  // Form sequences of 4 consecutive S, D, or Q registers.
279  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
280  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
282
283  // Get the alignment operand for a NEON VLD or VST instruction.
284  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
285};
286}
287
288/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
289/// operand. If so Imm will receive the 32-bit value.
290static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
291  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
292    Imm = cast<ConstantSDNode>(N)->getZExtValue();
293    return true;
294  }
295  return false;
296}
297
298// isInt32Immediate - This method tests to see if a constant operand.
299// If so Imm will receive the 32 bit value.
300static bool isInt32Immediate(SDValue N, unsigned &Imm) {
301  return isInt32Immediate(N.getNode(), Imm);
302}
303
304// isOpcWithIntImmediate - This method tests to see if the node is a specific
305// opcode and that it has a immediate integer right operand.
306// If so Imm will receive the 32 bit value.
307static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
308  return N->getOpcode() == Opc &&
309         isInt32Immediate(N->getOperand(1).getNode(), Imm);
310}
311
312/// \brief Check whether a particular node is a constant value representable as
313/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
314///
315/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
316static bool isScaledConstantInRange(SDValue Node, int Scale,
317                                    int RangeMin, int RangeMax,
318                                    int &ScaledConstant) {
319  assert(Scale > 0 && "Invalid scale!");
320
321  // Check that this is a constant.
322  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
323  if (!C)
324    return false;
325
326  ScaledConstant = (int) C->getZExtValue();
327  if ((ScaledConstant % Scale) != 0)
328    return false;
329
330  ScaledConstant /= Scale;
331  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
332}
333
334/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
335/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
336/// least on current ARM implementations) which should be avoidded.
337bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
338  if (OptLevel == CodeGenOpt::None)
339    return true;
340
341  if (!CheckVMLxHazard)
342    return true;
343
344  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
345    return true;
346
347  if (!N->hasOneUse())
348    return false;
349
350  SDNode *Use = *N->use_begin();
351  if (Use->getOpcode() == ISD::CopyToReg)
352    return true;
353  if (Use->isMachineOpcode()) {
354    const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
355    if (MCID.mayStore())
356      return true;
357    unsigned Opcode = MCID.getOpcode();
358    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
359      return true;
360    // vmlx feeding into another vmlx. We actually want to unfold
361    // the use later in the MLxExpansion pass. e.g.
362    // vmla
363    // vmla (stall 8 cycles)
364    //
365    // vmul (5 cycles)
366    // vadd (5 cycles)
367    // vmla
368    // This adds up to about 18 - 19 cycles.
369    //
370    // vmla
371    // vmul (stall 4 cycles)
372    // vadd adds up to about 14 cycles.
373    return TII->isFpMLxInstruction(Opcode);
374  }
375
376  return false;
377}
378
379bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
380                                            ARM_AM::ShiftOpc ShOpcVal,
381                                            unsigned ShAmt) {
382  if (!Subtarget->isCortexA9())
383    return true;
384  if (Shift.hasOneUse())
385    return true;
386  // R << 2 is free.
387  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
388}
389
390bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
391                                              SDValue &BaseReg,
392                                              SDValue &Opc,
393                                              bool CheckProfitability) {
394  if (DisableShifterOp)
395    return false;
396
397  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
398
399  // Don't match base register only case. That is matched to a separate
400  // lower complexity pattern with explicit register operand.
401  if (ShOpcVal == ARM_AM::no_shift) return false;
402
403  BaseReg = N.getOperand(0);
404  unsigned ShImmVal = 0;
405  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
406  if (!RHS) return false;
407  ShImmVal = RHS->getZExtValue() & 31;
408  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
409                                  MVT::i32);
410  return true;
411}
412
413bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
414                                              SDValue &BaseReg,
415                                              SDValue &ShReg,
416                                              SDValue &Opc,
417                                              bool CheckProfitability) {
418  if (DisableShifterOp)
419    return false;
420
421  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
422
423  // Don't match base register only case. That is matched to a separate
424  // lower complexity pattern with explicit register operand.
425  if (ShOpcVal == ARM_AM::no_shift) return false;
426
427  BaseReg = N.getOperand(0);
428  unsigned ShImmVal = 0;
429  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
430  if (RHS) return false;
431
432  ShReg = N.getOperand(1);
433  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
434    return false;
435  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
436                                  MVT::i32);
437  return true;
438}
439
440
441bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
442                                          SDValue &Base,
443                                          SDValue &OffImm) {
444  // Match simple R + imm12 operands.
445
446  // Base only.
447  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
448      !CurDAG->isBaseWithConstantOffset(N)) {
449    if (N.getOpcode() == ISD::FrameIndex) {
450      // Match frame index.
451      int FI = cast<FrameIndexSDNode>(N)->getIndex();
452      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
453      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
454      return true;
455    }
456
457    if (N.getOpcode() == ARMISD::Wrapper &&
458        !(Subtarget->useMovt() &&
459                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
460      Base = N.getOperand(0);
461    } else
462      Base = N;
463    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
464    return true;
465  }
466
467  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
468    int RHSC = (int)RHS->getZExtValue();
469    if (N.getOpcode() == ISD::SUB)
470      RHSC = -RHSC;
471
472    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
473      Base   = N.getOperand(0);
474      if (Base.getOpcode() == ISD::FrameIndex) {
475        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
476        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
477      }
478      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
479      return true;
480    }
481  }
482
483  // Base only.
484  Base = N;
485  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
486  return true;
487}
488
489
490
491bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
492                                      SDValue &Opc) {
493  if (N.getOpcode() == ISD::MUL &&
494      (!Subtarget->isCortexA9() || N.hasOneUse())) {
495    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
496      // X * [3,5,9] -> X + X * [2,4,8] etc.
497      int RHSC = (int)RHS->getZExtValue();
498      if (RHSC & 1) {
499        RHSC = RHSC & ~1;
500        ARM_AM::AddrOpc AddSub = ARM_AM::add;
501        if (RHSC < 0) {
502          AddSub = ARM_AM::sub;
503          RHSC = - RHSC;
504        }
505        if (isPowerOf2_32(RHSC)) {
506          unsigned ShAmt = Log2_32(RHSC);
507          Base = Offset = N.getOperand(0);
508          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
509                                                            ARM_AM::lsl),
510                                          MVT::i32);
511          return true;
512        }
513      }
514    }
515  }
516
517  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
518      // ISD::OR that is equivalent to an ISD::ADD.
519      !CurDAG->isBaseWithConstantOffset(N))
520    return false;
521
522  // Leave simple R +/- imm12 operands for LDRi12
523  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
524    int RHSC;
525    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
526                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
527      return false;
528  }
529
530  // Otherwise this is R +/- [possibly shifted] R.
531  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
532  ARM_AM::ShiftOpc ShOpcVal =
533    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
534  unsigned ShAmt = 0;
535
536  Base   = N.getOperand(0);
537  Offset = N.getOperand(1);
538
539  if (ShOpcVal != ARM_AM::no_shift) {
540    // Check to see if the RHS of the shift is a constant, if not, we can't fold
541    // it.
542    if (ConstantSDNode *Sh =
543           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
544      ShAmt = Sh->getZExtValue();
545      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
546        Offset = N.getOperand(1).getOperand(0);
547      else {
548        ShAmt = 0;
549        ShOpcVal = ARM_AM::no_shift;
550      }
551    } else {
552      ShOpcVal = ARM_AM::no_shift;
553    }
554  }
555
556  // Try matching (R shl C) + (R).
557  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
558      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
559    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
560    if (ShOpcVal != ARM_AM::no_shift) {
561      // Check to see if the RHS of the shift is a constant, if not, we can't
562      // fold it.
563      if (ConstantSDNode *Sh =
564          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
565        ShAmt = Sh->getZExtValue();
566        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
567          Offset = N.getOperand(0).getOperand(0);
568          Base = N.getOperand(1);
569        } else {
570          ShAmt = 0;
571          ShOpcVal = ARM_AM::no_shift;
572        }
573      } else {
574        ShOpcVal = ARM_AM::no_shift;
575      }
576    }
577  }
578
579  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
580                                  MVT::i32);
581  return true;
582}
583
584
585
586
587//-----
588
589AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
590                                                     SDValue &Base,
591                                                     SDValue &Offset,
592                                                     SDValue &Opc) {
593  if (N.getOpcode() == ISD::MUL &&
594      (!Subtarget->isCortexA9() || N.hasOneUse())) {
595    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
596      // X * [3,5,9] -> X + X * [2,4,8] etc.
597      int RHSC = (int)RHS->getZExtValue();
598      if (RHSC & 1) {
599        RHSC = RHSC & ~1;
600        ARM_AM::AddrOpc AddSub = ARM_AM::add;
601        if (RHSC < 0) {
602          AddSub = ARM_AM::sub;
603          RHSC = - RHSC;
604        }
605        if (isPowerOf2_32(RHSC)) {
606          unsigned ShAmt = Log2_32(RHSC);
607          Base = Offset = N.getOperand(0);
608          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
609                                                            ARM_AM::lsl),
610                                          MVT::i32);
611          return AM2_SHOP;
612        }
613      }
614    }
615  }
616
617  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
618      // ISD::OR that is equivalent to an ADD.
619      !CurDAG->isBaseWithConstantOffset(N)) {
620    Base = N;
621    if (N.getOpcode() == ISD::FrameIndex) {
622      int FI = cast<FrameIndexSDNode>(N)->getIndex();
623      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
624    } else if (N.getOpcode() == ARMISD::Wrapper &&
625               !(Subtarget->useMovt() &&
626                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
627      Base = N.getOperand(0);
628    }
629    Offset = CurDAG->getRegister(0, MVT::i32);
630    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
631                                                      ARM_AM::no_shift),
632                                    MVT::i32);
633    return AM2_BASE;
634  }
635
636  // Match simple R +/- imm12 operands.
637  if (N.getOpcode() != ISD::SUB) {
638    int RHSC;
639    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
640                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
641      Base = N.getOperand(0);
642      if (Base.getOpcode() == ISD::FrameIndex) {
643        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
644        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
645      }
646      Offset = CurDAG->getRegister(0, MVT::i32);
647
648      ARM_AM::AddrOpc AddSub = ARM_AM::add;
649      if (RHSC < 0) {
650        AddSub = ARM_AM::sub;
651        RHSC = - RHSC;
652      }
653      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
654                                                        ARM_AM::no_shift),
655                                      MVT::i32);
656      return AM2_BASE;
657    }
658  }
659
660  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
661    // Compute R +/- (R << N) and reuse it.
662    Base = N;
663    Offset = CurDAG->getRegister(0, MVT::i32);
664    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
665                                                      ARM_AM::no_shift),
666                                    MVT::i32);
667    return AM2_BASE;
668  }
669
670  // Otherwise this is R +/- [possibly shifted] R.
671  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
672  ARM_AM::ShiftOpc ShOpcVal =
673    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
674  unsigned ShAmt = 0;
675
676  Base   = N.getOperand(0);
677  Offset = N.getOperand(1);
678
679  if (ShOpcVal != ARM_AM::no_shift) {
680    // Check to see if the RHS of the shift is a constant, if not, we can't fold
681    // it.
682    if (ConstantSDNode *Sh =
683           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
684      ShAmt = Sh->getZExtValue();
685      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
686        Offset = N.getOperand(1).getOperand(0);
687      else {
688        ShAmt = 0;
689        ShOpcVal = ARM_AM::no_shift;
690      }
691    } else {
692      ShOpcVal = ARM_AM::no_shift;
693    }
694  }
695
696  // Try matching (R shl C) + (R).
697  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
698      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
699    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
700    if (ShOpcVal != ARM_AM::no_shift) {
701      // Check to see if the RHS of the shift is a constant, if not, we can't
702      // fold it.
703      if (ConstantSDNode *Sh =
704          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
705        ShAmt = Sh->getZExtValue();
706        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
707          Offset = N.getOperand(0).getOperand(0);
708          Base = N.getOperand(1);
709        } else {
710          ShAmt = 0;
711          ShOpcVal = ARM_AM::no_shift;
712        }
713      } else {
714        ShOpcVal = ARM_AM::no_shift;
715      }
716    }
717  }
718
719  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
720                                  MVT::i32);
721  return AM2_SHOP;
722}
723
724bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
725                                            SDValue &Offset, SDValue &Opc) {
726  unsigned Opcode = Op->getOpcode();
727  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
728    ? cast<LoadSDNode>(Op)->getAddressingMode()
729    : cast<StoreSDNode>(Op)->getAddressingMode();
730  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
731    ? ARM_AM::add : ARM_AM::sub;
732  int Val;
733  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
734    return false;
735
736  Offset = N;
737  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
738  unsigned ShAmt = 0;
739  if (ShOpcVal != ARM_AM::no_shift) {
740    // Check to see if the RHS of the shift is a constant, if not, we can't fold
741    // it.
742    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
743      ShAmt = Sh->getZExtValue();
744      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
745        Offset = N.getOperand(0);
746      else {
747        ShAmt = 0;
748        ShOpcVal = ARM_AM::no_shift;
749      }
750    } else {
751      ShOpcVal = ARM_AM::no_shift;
752    }
753  }
754
755  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
756                                  MVT::i32);
757  return true;
758}
759
760bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
761                                            SDValue &Offset, SDValue &Opc) {
762  unsigned Opcode = Op->getOpcode();
763  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
764    ? cast<LoadSDNode>(Op)->getAddressingMode()
765    : cast<StoreSDNode>(Op)->getAddressingMode();
766  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
767    ? ARM_AM::add : ARM_AM::sub;
768  int Val;
769  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
770    if (AddSub == ARM_AM::sub) Val *= -1;
771    Offset = CurDAG->getRegister(0, MVT::i32);
772    Opc = CurDAG->getTargetConstant(Val, MVT::i32);
773    return true;
774  }
775
776  return false;
777}
778
779
780bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
781                                            SDValue &Offset, SDValue &Opc) {
782  unsigned Opcode = Op->getOpcode();
783  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
784    ? cast<LoadSDNode>(Op)->getAddressingMode()
785    : cast<StoreSDNode>(Op)->getAddressingMode();
786  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
787    ? ARM_AM::add : ARM_AM::sub;
788  int Val;
789  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
790    Offset = CurDAG->getRegister(0, MVT::i32);
791    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
792                                                      ARM_AM::no_shift),
793                                    MVT::i32);
794    return true;
795  }
796
797  return false;
798}
799
800bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
801  Base = N;
802  return true;
803}
804
805bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
806                                      SDValue &Base, SDValue &Offset,
807                                      SDValue &Opc) {
808  if (N.getOpcode() == ISD::SUB) {
809    // X - C  is canonicalize to X + -C, no need to handle it here.
810    Base = N.getOperand(0);
811    Offset = N.getOperand(1);
812    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
813    return true;
814  }
815
816  if (!CurDAG->isBaseWithConstantOffset(N)) {
817    Base = N;
818    if (N.getOpcode() == ISD::FrameIndex) {
819      int FI = cast<FrameIndexSDNode>(N)->getIndex();
820      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
821    }
822    Offset = CurDAG->getRegister(0, MVT::i32);
823    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
824    return true;
825  }
826
827  // If the RHS is +/- imm8, fold into addr mode.
828  int RHSC;
829  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
830                              -256 + 1, 256, RHSC)) { // 8 bits.
831    Base = N.getOperand(0);
832    if (Base.getOpcode() == ISD::FrameIndex) {
833      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
834      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
835    }
836    Offset = CurDAG->getRegister(0, MVT::i32);
837
838    ARM_AM::AddrOpc AddSub = ARM_AM::add;
839    if (RHSC < 0) {
840      AddSub = ARM_AM::sub;
841      RHSC = -RHSC;
842    }
843    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
844    return true;
845  }
846
847  Base = N.getOperand(0);
848  Offset = N.getOperand(1);
849  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
850  return true;
851}
852
853bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
854                                            SDValue &Offset, SDValue &Opc) {
855  unsigned Opcode = Op->getOpcode();
856  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
857    ? cast<LoadSDNode>(Op)->getAddressingMode()
858    : cast<StoreSDNode>(Op)->getAddressingMode();
859  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
860    ? ARM_AM::add : ARM_AM::sub;
861  int Val;
862  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
863    Offset = CurDAG->getRegister(0, MVT::i32);
864    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
865    return true;
866  }
867
868  Offset = N;
869  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
870  return true;
871}
872
873bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
874                                      SDValue &Base, SDValue &Offset) {
875  if (!CurDAG->isBaseWithConstantOffset(N)) {
876    Base = N;
877    if (N.getOpcode() == ISD::FrameIndex) {
878      int FI = cast<FrameIndexSDNode>(N)->getIndex();
879      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
880    } else if (N.getOpcode() == ARMISD::Wrapper &&
881               !(Subtarget->useMovt() &&
882                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
883      Base = N.getOperand(0);
884    }
885    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
886                                       MVT::i32);
887    return true;
888  }
889
890  // If the RHS is +/- imm8, fold into addr mode.
891  int RHSC;
892  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
893                              -256 + 1, 256, RHSC)) {
894    Base = N.getOperand(0);
895    if (Base.getOpcode() == ISD::FrameIndex) {
896      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
897      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
898    }
899
900    ARM_AM::AddrOpc AddSub = ARM_AM::add;
901    if (RHSC < 0) {
902      AddSub = ARM_AM::sub;
903      RHSC = -RHSC;
904    }
905    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
906                                       MVT::i32);
907    return true;
908  }
909
910  Base = N;
911  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
912                                     MVT::i32);
913  return true;
914}
915
916bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
917                                      SDValue &Align) {
918  Addr = N;
919
920  unsigned Alignment = 0;
921  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
922    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
923    // The maximum alignment is equal to the memory size being referenced.
924    unsigned LSNAlign = LSN->getAlignment();
925    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
926    if (LSNAlign >= MemSize && MemSize > 1)
927      Alignment = MemSize;
928  } else {
929    // All other uses of addrmode6 are for intrinsics.  For now just record
930    // the raw alignment value; it will be refined later based on the legal
931    // alignment operands for the intrinsic.
932    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
933  }
934
935  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
936  return true;
937}
938
939bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
940                                            SDValue &Offset) {
941  LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
942  ISD::MemIndexedMode AM = LdSt->getAddressingMode();
943  if (AM != ISD::POST_INC)
944    return false;
945  Offset = N;
946  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
947    if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
948      Offset = CurDAG->getRegister(0, MVT::i32);
949  }
950  return true;
951}
952
953bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
954                                       SDValue &Offset, SDValue &Label) {
955  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
956    Offset = N.getOperand(0);
957    SDValue N1 = N.getOperand(1);
958    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
959                                      MVT::i32);
960    return true;
961  }
962
963  return false;
964}
965
966
967//===----------------------------------------------------------------------===//
968//                         Thumb Addressing Modes
969//===----------------------------------------------------------------------===//
970
971bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
972                                            SDValue &Base, SDValue &Offset){
973  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
974    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
975    if (!NC || !NC->isNullValue())
976      return false;
977
978    Base = Offset = N;
979    return true;
980  }
981
982  Base = N.getOperand(0);
983  Offset = N.getOperand(1);
984  return true;
985}
986
987bool
988ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
989                                       SDValue &Offset, unsigned Scale) {
990  if (Scale == 4) {
991    SDValue TmpBase, TmpOffImm;
992    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
993      return false;  // We want to select tLDRspi / tSTRspi instead.
994
995    if (N.getOpcode() == ARMISD::Wrapper &&
996        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
997      return false;  // We want to select tLDRpci instead.
998  }
999
1000  if (!CurDAG->isBaseWithConstantOffset(N))
1001    return false;
1002
1003  // Thumb does not have [sp, r] address mode.
1004  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1005  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1006  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1007      (RHSR && RHSR->getReg() == ARM::SP))
1008    return false;
1009
1010  // FIXME: Why do we explicitly check for a match here and then return false?
1011  // Presumably to allow something else to match, but shouldn't this be
1012  // documented?
1013  int RHSC;
1014  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1015    return false;
1016
1017  Base = N.getOperand(0);
1018  Offset = N.getOperand(1);
1019  return true;
1020}
1021
1022bool
1023ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1024                                          SDValue &Base,
1025                                          SDValue &Offset) {
1026  return SelectThumbAddrModeRI(N, Base, Offset, 1);
1027}
1028
1029bool
1030ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1031                                          SDValue &Base,
1032                                          SDValue &Offset) {
1033  return SelectThumbAddrModeRI(N, Base, Offset, 2);
1034}
1035
1036bool
1037ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1038                                          SDValue &Base,
1039                                          SDValue &Offset) {
1040  return SelectThumbAddrModeRI(N, Base, Offset, 4);
1041}
1042
1043bool
1044ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1045                                          SDValue &Base, SDValue &OffImm) {
1046  if (Scale == 4) {
1047    SDValue TmpBase, TmpOffImm;
1048    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1049      return false;  // We want to select tLDRspi / tSTRspi instead.
1050
1051    if (N.getOpcode() == ARMISD::Wrapper &&
1052        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1053      return false;  // We want to select tLDRpci instead.
1054  }
1055
1056  if (!CurDAG->isBaseWithConstantOffset(N)) {
1057    if (N.getOpcode() == ARMISD::Wrapper &&
1058        !(Subtarget->useMovt() &&
1059          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1060      Base = N.getOperand(0);
1061    } else {
1062      Base = N;
1063    }
1064
1065    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1066    return true;
1067  }
1068
1069  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1070  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1071  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1072      (RHSR && RHSR->getReg() == ARM::SP)) {
1073    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1074    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1075    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1076    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1077
1078    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1079    if (LHSC != 0 || RHSC != 0) return false;
1080
1081    Base = N;
1082    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1083    return true;
1084  }
1085
1086  // If the RHS is + imm5 * scale, fold into addr mode.
1087  int RHSC;
1088  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1089    Base = N.getOperand(0);
1090    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1091    return true;
1092  }
1093
1094  Base = N.getOperand(0);
1095  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1096  return true;
1097}
1098
1099bool
1100ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1101                                           SDValue &OffImm) {
1102  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1103}
1104
1105bool
1106ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1107                                           SDValue &OffImm) {
1108  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1109}
1110
1111bool
1112ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1113                                           SDValue &OffImm) {
1114  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1115}
1116
1117bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1118                                            SDValue &Base, SDValue &OffImm) {
1119  if (N.getOpcode() == ISD::FrameIndex) {
1120    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1121    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1122    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1123    return true;
1124  }
1125
1126  if (!CurDAG->isBaseWithConstantOffset(N))
1127    return false;
1128
1129  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1130  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1131      (LHSR && LHSR->getReg() == ARM::SP)) {
1132    // If the RHS is + imm8 * scale, fold into addr mode.
1133    int RHSC;
1134    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1135      Base = N.getOperand(0);
1136      if (Base.getOpcode() == ISD::FrameIndex) {
1137        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1138        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1139      }
1140      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1141      return true;
1142    }
1143  }
1144
1145  return false;
1146}
1147
1148
1149//===----------------------------------------------------------------------===//
1150//                        Thumb 2 Addressing Modes
1151//===----------------------------------------------------------------------===//
1152
1153
1154bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1155                                                SDValue &Opc) {
1156  if (DisableShifterOp)
1157    return false;
1158
1159  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1160
1161  // Don't match base register only case. That is matched to a separate
1162  // lower complexity pattern with explicit register operand.
1163  if (ShOpcVal == ARM_AM::no_shift) return false;
1164
1165  BaseReg = N.getOperand(0);
1166  unsigned ShImmVal = 0;
1167  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1168    ShImmVal = RHS->getZExtValue() & 31;
1169    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1170    return true;
1171  }
1172
1173  return false;
1174}
1175
1176bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1177                                            SDValue &Base, SDValue &OffImm) {
1178  // Match simple R + imm12 operands.
1179
1180  // Base only.
1181  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1182      !CurDAG->isBaseWithConstantOffset(N)) {
1183    if (N.getOpcode() == ISD::FrameIndex) {
1184      // Match frame index.
1185      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1186      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1187      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1188      return true;
1189    }
1190
1191    if (N.getOpcode() == ARMISD::Wrapper &&
1192               !(Subtarget->useMovt() &&
1193                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1194      Base = N.getOperand(0);
1195      if (Base.getOpcode() == ISD::TargetConstantPool)
1196        return false;  // We want to select t2LDRpci instead.
1197    } else
1198      Base = N;
1199    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1200    return true;
1201  }
1202
1203  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1204    if (SelectT2AddrModeImm8(N, Base, OffImm))
1205      // Let t2LDRi8 handle (R - imm8).
1206      return false;
1207
1208    int RHSC = (int)RHS->getZExtValue();
1209    if (N.getOpcode() == ISD::SUB)
1210      RHSC = -RHSC;
1211
1212    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1213      Base   = N.getOperand(0);
1214      if (Base.getOpcode() == ISD::FrameIndex) {
1215        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1216        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1217      }
1218      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1219      return true;
1220    }
1221  }
1222
1223  // Base only.
1224  Base = N;
1225  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1226  return true;
1227}
1228
1229bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1230                                           SDValue &Base, SDValue &OffImm) {
1231  // Match simple R - imm8 operands.
1232  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1233      !CurDAG->isBaseWithConstantOffset(N))
1234    return false;
1235
1236  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1237    int RHSC = (int)RHS->getSExtValue();
1238    if (N.getOpcode() == ISD::SUB)
1239      RHSC = -RHSC;
1240
1241    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1242      Base = N.getOperand(0);
1243      if (Base.getOpcode() == ISD::FrameIndex) {
1244        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1245        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1246      }
1247      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1248      return true;
1249    }
1250  }
1251
1252  return false;
1253}
1254
1255bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1256                                                 SDValue &OffImm){
1257  unsigned Opcode = Op->getOpcode();
1258  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1259    ? cast<LoadSDNode>(Op)->getAddressingMode()
1260    : cast<StoreSDNode>(Op)->getAddressingMode();
1261  int RHSC;
1262  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1263    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1264      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1265      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1266    return true;
1267  }
1268
1269  return false;
1270}
1271
1272bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1273                                            SDValue &Base,
1274                                            SDValue &OffReg, SDValue &ShImm) {
1275  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1276  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1277    return false;
1278
1279  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1280  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1281    int RHSC = (int)RHS->getZExtValue();
1282    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1283      return false;
1284    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1285      return false;
1286  }
1287
1288  // Look for (R + R) or (R + (R << [1,2,3])).
1289  unsigned ShAmt = 0;
1290  Base   = N.getOperand(0);
1291  OffReg = N.getOperand(1);
1292
1293  // Swap if it is ((R << c) + R).
1294  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1295  if (ShOpcVal != ARM_AM::lsl) {
1296    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1297    if (ShOpcVal == ARM_AM::lsl)
1298      std::swap(Base, OffReg);
1299  }
1300
1301  if (ShOpcVal == ARM_AM::lsl) {
1302    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1303    // it.
1304    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1305      ShAmt = Sh->getZExtValue();
1306      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1307        OffReg = OffReg.getOperand(0);
1308      else {
1309        ShAmt = 0;
1310        ShOpcVal = ARM_AM::no_shift;
1311      }
1312    } else {
1313      ShOpcVal = ARM_AM::no_shift;
1314    }
1315  }
1316
1317  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1318
1319  return true;
1320}
1321
1322//===--------------------------------------------------------------------===//
1323
1324/// getAL - Returns a ARMCC::AL immediate node.
1325static inline SDValue getAL(SelectionDAG *CurDAG) {
1326  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1327}
1328
1329SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1330  LoadSDNode *LD = cast<LoadSDNode>(N);
1331  ISD::MemIndexedMode AM = LD->getAddressingMode();
1332  if (AM == ISD::UNINDEXED)
1333    return NULL;
1334
1335  EVT LoadedVT = LD->getMemoryVT();
1336  SDValue Offset, AMOpc;
1337  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1338  unsigned Opcode = 0;
1339  bool Match = false;
1340  if (LoadedVT == MVT::i32 && isPre &&
1341      SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1342    Opcode = ARM::LDR_PRE_IMM;
1343    Match = true;
1344  } else if (LoadedVT == MVT::i32 && !isPre &&
1345      SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1346    Opcode = ARM::LDR_POST_IMM;
1347    Match = true;
1348  } else if (LoadedVT == MVT::i32 &&
1349      SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1350    Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1351    Match = true;
1352
1353  } else if (LoadedVT == MVT::i16 &&
1354             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1355    Match = true;
1356    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1357      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1358      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1359  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1360    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1361      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1362        Match = true;
1363        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1364      }
1365    } else {
1366      if (isPre &&
1367          SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1368        Match = true;
1369        Opcode = ARM::LDRB_PRE_IMM;
1370      } else if (!isPre &&
1371                  SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1372        Match = true;
1373        Opcode = ARM::LDRB_POST_IMM;
1374      } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1375        Match = true;
1376        Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1377      }
1378    }
1379  }
1380
1381  if (Match) {
1382    if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1383      SDValue Chain = LD->getChain();
1384      SDValue Base = LD->getBasePtr();
1385      SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1386                       CurDAG->getRegister(0, MVT::i32), Chain };
1387      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1388                                    MVT::i32, MVT::Other, Ops, 5);
1389    } else {
1390      SDValue Chain = LD->getChain();
1391      SDValue Base = LD->getBasePtr();
1392      SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1393                       CurDAG->getRegister(0, MVT::i32), Chain };
1394      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1395                                    MVT::i32, MVT::Other, Ops, 6);
1396    }
1397  }
1398
1399  return NULL;
1400}
1401
1402SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1403  LoadSDNode *LD = cast<LoadSDNode>(N);
1404  ISD::MemIndexedMode AM = LD->getAddressingMode();
1405  if (AM == ISD::UNINDEXED)
1406    return NULL;
1407
1408  EVT LoadedVT = LD->getMemoryVT();
1409  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1410  SDValue Offset;
1411  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1412  unsigned Opcode = 0;
1413  bool Match = false;
1414  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1415    switch (LoadedVT.getSimpleVT().SimpleTy) {
1416    case MVT::i32:
1417      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1418      break;
1419    case MVT::i16:
1420      if (isSExtLd)
1421        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1422      else
1423        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1424      break;
1425    case MVT::i8:
1426    case MVT::i1:
1427      if (isSExtLd)
1428        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1429      else
1430        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1431      break;
1432    default:
1433      return NULL;
1434    }
1435    Match = true;
1436  }
1437
1438  if (Match) {
1439    SDValue Chain = LD->getChain();
1440    SDValue Base = LD->getBasePtr();
1441    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1442                     CurDAG->getRegister(0, MVT::i32), Chain };
1443    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1444                                  MVT::Other, Ops, 5);
1445  }
1446
1447  return NULL;
1448}
1449
1450/// PairSRegs - Form a D register from a pair of S registers.
1451///
1452SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1453  DebugLoc dl = V0.getNode()->getDebugLoc();
1454  SDValue RegClass =
1455    CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1456  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1457  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1458  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1459  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1460}
1461
1462/// PairDRegs - Form a quad register from a pair of D registers.
1463///
1464SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1465  DebugLoc dl = V0.getNode()->getDebugLoc();
1466  SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1467  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1468  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1469  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1470  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1471}
1472
1473/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1474///
1475SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1476  DebugLoc dl = V0.getNode()->getDebugLoc();
1477  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1478  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1479  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1480  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1481  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1482}
1483
1484/// QuadSRegs - Form 4 consecutive S registers.
1485///
1486SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1487                                   SDValue V2, SDValue V3) {
1488  DebugLoc dl = V0.getNode()->getDebugLoc();
1489  SDValue RegClass =
1490    CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1491  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1492  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1493  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1494  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1495  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1496                                    V2, SubReg2, V3, SubReg3 };
1497  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1498}
1499
1500/// QuadDRegs - Form 4 consecutive D registers.
1501///
1502SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1503                                   SDValue V2, SDValue V3) {
1504  DebugLoc dl = V0.getNode()->getDebugLoc();
1505  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1506  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1507  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1508  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1509  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1510  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1511                                    V2, SubReg2, V3, SubReg3 };
1512  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1513}
1514
1515/// QuadQRegs - Form 4 consecutive Q registers.
1516///
1517SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1518                                   SDValue V2, SDValue V3) {
1519  DebugLoc dl = V0.getNode()->getDebugLoc();
1520  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1521  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1522  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1523  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1524  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1525  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1526                                    V2, SubReg2, V3, SubReg3 };
1527  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1528}
1529
1530/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1531/// of a NEON VLD or VST instruction.  The supported values depend on the
1532/// number of registers being loaded.
1533SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1534                                       bool is64BitVector) {
1535  unsigned NumRegs = NumVecs;
1536  if (!is64BitVector && NumVecs < 3)
1537    NumRegs *= 2;
1538
1539  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1540  if (Alignment >= 32 && NumRegs == 4)
1541    Alignment = 32;
1542  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1543    Alignment = 16;
1544  else if (Alignment >= 8)
1545    Alignment = 8;
1546  else
1547    Alignment = 0;
1548
1549  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1550}
1551
1552// Get the register stride update opcode of a VLD/VST instruction that
1553// is otherwise equivalent to the given fixed stride updating instruction.
1554static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1555  switch (Opc) {
1556  default: break;
1557  case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1558  case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1559  case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1560  case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1561  case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1562  case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1563  case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1564  case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1565  case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register;
1566  case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
1567  case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
1568  case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
1569
1570  case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1571  case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1572  case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1573  case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1574  case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1575  case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1576  case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1577  case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1578  case ARM::VST1q8PseudoWB_fixed: return ARM::VST1q8PseudoWB_register;
1579  case ARM::VST1q16PseudoWB_fixed: return ARM::VST1q16PseudoWB_register;
1580  case ARM::VST1q32PseudoWB_fixed: return ARM::VST1q32PseudoWB_register;
1581  case ARM::VST1q64PseudoWB_fixed: return ARM::VST1q64PseudoWB_register;
1582  case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1583  case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1584
1585  case ARM::VLD2d8PseudoWB_fixed: return ARM::VLD2d8PseudoWB_register;
1586  case ARM::VLD2d16PseudoWB_fixed: return ARM::VLD2d16PseudoWB_register;
1587  case ARM::VLD2d32PseudoWB_fixed: return ARM::VLD2d32PseudoWB_register;
1588  case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1589  case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1590  case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1591
1592  case ARM::VST2d8PseudoWB_fixed: return ARM::VST2d8PseudoWB_register;
1593  case ARM::VST2d16PseudoWB_fixed: return ARM::VST2d16PseudoWB_register;
1594  case ARM::VST2d32PseudoWB_fixed: return ARM::VST2d32PseudoWB_register;
1595  case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1596  case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1597  case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1598
1599  case ARM::VLD2DUPd8PseudoWB_fixed: return ARM::VLD2DUPd8PseudoWB_register;
1600  case ARM::VLD2DUPd16PseudoWB_fixed: return ARM::VLD2DUPd16PseudoWB_register;
1601  case ARM::VLD2DUPd32PseudoWB_fixed: return ARM::VLD2DUPd32PseudoWB_register;
1602  }
1603  return Opc; // If not one we handle, return it unchanged.
1604}
1605
1606SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1607                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1608                                   unsigned *QOpcodes1) {
1609  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1610  DebugLoc dl = N->getDebugLoc();
1611
1612  SDValue MemAddr, Align;
1613  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1614  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1615    return NULL;
1616
1617  SDValue Chain = N->getOperand(0);
1618  EVT VT = N->getValueType(0);
1619  bool is64BitVector = VT.is64BitVector();
1620  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1621
1622  unsigned OpcodeIndex;
1623  switch (VT.getSimpleVT().SimpleTy) {
1624  default: llvm_unreachable("unhandled vld type");
1625    // Double-register operations:
1626  case MVT::v8i8:  OpcodeIndex = 0; break;
1627  case MVT::v4i16: OpcodeIndex = 1; break;
1628  case MVT::v2f32:
1629  case MVT::v2i32: OpcodeIndex = 2; break;
1630  case MVT::v1i64: OpcodeIndex = 3; break;
1631    // Quad-register operations:
1632  case MVT::v16i8: OpcodeIndex = 0; break;
1633  case MVT::v8i16: OpcodeIndex = 1; break;
1634  case MVT::v4f32:
1635  case MVT::v4i32: OpcodeIndex = 2; break;
1636  case MVT::v2i64: OpcodeIndex = 3;
1637    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1638    break;
1639  }
1640
1641  EVT ResTy;
1642  if (NumVecs == 1)
1643    ResTy = VT;
1644  else {
1645    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1646    if (!is64BitVector)
1647      ResTyElts *= 2;
1648    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1649  }
1650  std::vector<EVT> ResTys;
1651  ResTys.push_back(ResTy);
1652  if (isUpdating)
1653    ResTys.push_back(MVT::i32);
1654  ResTys.push_back(MVT::Other);
1655
1656  SDValue Pred = getAL(CurDAG);
1657  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1658  SDNode *VLd;
1659  SmallVector<SDValue, 7> Ops;
1660
1661  // Double registers and VLD1/VLD2 quad registers are directly supported.
1662  if (is64BitVector || NumVecs <= 2) {
1663    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1664                    QOpcodes0[OpcodeIndex]);
1665    Ops.push_back(MemAddr);
1666    Ops.push_back(Align);
1667    if (isUpdating) {
1668      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1669      // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1670      // case entirely when the rest are updated to that form, too.
1671      if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1672        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1673      // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1674      // check for that explicitly too. Horribly hacky, but temporary.
1675      if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64PseudoWB_fixed) ||
1676          !isa<ConstantSDNode>(Inc.getNode()))
1677        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1678    }
1679    Ops.push_back(Pred);
1680    Ops.push_back(Reg0);
1681    Ops.push_back(Chain);
1682    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1683
1684  } else {
1685    // Otherwise, quad registers are loaded with two separate instructions,
1686    // where one loads the even registers and the other loads the odd registers.
1687    EVT AddrTy = MemAddr.getValueType();
1688
1689    // Load the even subregs.  This is always an updating load, so that it
1690    // provides the address to the second load for the odd subregs.
1691    SDValue ImplDef =
1692      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1693    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1694    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1695                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1696    Chain = SDValue(VLdA, 2);
1697
1698    // Load the odd subregs.
1699    Ops.push_back(SDValue(VLdA, 1));
1700    Ops.push_back(Align);
1701    if (isUpdating) {
1702      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1703      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1704             "only constant post-increment update allowed for VLD3/4");
1705      (void)Inc;
1706      Ops.push_back(Reg0);
1707    }
1708    Ops.push_back(SDValue(VLdA, 0));
1709    Ops.push_back(Pred);
1710    Ops.push_back(Reg0);
1711    Ops.push_back(Chain);
1712    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1713                                 Ops.data(), Ops.size());
1714  }
1715
1716  // Transfer memoperands.
1717  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1718  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1719  cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1720
1721  if (NumVecs == 1)
1722    return VLd;
1723
1724  // Extract out the subregisters.
1725  SDValue SuperReg = SDValue(VLd, 0);
1726  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1727         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1728  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1729  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1730    ReplaceUses(SDValue(N, Vec),
1731                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1732  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1733  if (isUpdating)
1734    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1735  return NULL;
1736}
1737
1738SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1739                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1740                                   unsigned *QOpcodes1) {
1741  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1742  DebugLoc dl = N->getDebugLoc();
1743
1744  SDValue MemAddr, Align;
1745  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1746  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1747  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1748    return NULL;
1749
1750  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1751  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1752
1753  SDValue Chain = N->getOperand(0);
1754  EVT VT = N->getOperand(Vec0Idx).getValueType();
1755  bool is64BitVector = VT.is64BitVector();
1756  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1757
1758  unsigned OpcodeIndex;
1759  switch (VT.getSimpleVT().SimpleTy) {
1760  default: llvm_unreachable("unhandled vst type");
1761    // Double-register operations:
1762  case MVT::v8i8:  OpcodeIndex = 0; break;
1763  case MVT::v4i16: OpcodeIndex = 1; break;
1764  case MVT::v2f32:
1765  case MVT::v2i32: OpcodeIndex = 2; break;
1766  case MVT::v1i64: OpcodeIndex = 3; break;
1767    // Quad-register operations:
1768  case MVT::v16i8: OpcodeIndex = 0; break;
1769  case MVT::v8i16: OpcodeIndex = 1; break;
1770  case MVT::v4f32:
1771  case MVT::v4i32: OpcodeIndex = 2; break;
1772  case MVT::v2i64: OpcodeIndex = 3;
1773    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1774    break;
1775  }
1776
1777  std::vector<EVT> ResTys;
1778  if (isUpdating)
1779    ResTys.push_back(MVT::i32);
1780  ResTys.push_back(MVT::Other);
1781
1782  SDValue Pred = getAL(CurDAG);
1783  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1784  SmallVector<SDValue, 7> Ops;
1785
1786  // Double registers and VST1/VST2 quad registers are directly supported.
1787  if (is64BitVector || NumVecs <= 2) {
1788    SDValue SrcReg;
1789    if (NumVecs == 1) {
1790      SrcReg = N->getOperand(Vec0Idx);
1791    } else if (is64BitVector) {
1792      // Form a REG_SEQUENCE to force register allocation.
1793      SDValue V0 = N->getOperand(Vec0Idx + 0);
1794      SDValue V1 = N->getOperand(Vec0Idx + 1);
1795      if (NumVecs == 2)
1796        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1797      else {
1798        SDValue V2 = N->getOperand(Vec0Idx + 2);
1799        // If it's a vst3, form a quad D-register and leave the last part as
1800        // an undef.
1801        SDValue V3 = (NumVecs == 3)
1802          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1803          : N->getOperand(Vec0Idx + 3);
1804        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1805      }
1806    } else {
1807      // Form a QQ register.
1808      SDValue Q0 = N->getOperand(Vec0Idx);
1809      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1810      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1811    }
1812
1813    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1814                    QOpcodes0[OpcodeIndex]);
1815    Ops.push_back(MemAddr);
1816    Ops.push_back(Align);
1817    if (isUpdating) {
1818      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1819      // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1820      // case entirely when the rest are updated to that form, too.
1821      if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1822        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1823      // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1824      // check for that explicitly too. Horribly hacky, but temporary.
1825      if ((NumVecs > 2 && Opc != ARM::VST1q64PseudoWB_fixed) ||
1826          !isa<ConstantSDNode>(Inc.getNode()))
1827        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1828    }
1829    Ops.push_back(SrcReg);
1830    Ops.push_back(Pred);
1831    Ops.push_back(Reg0);
1832    Ops.push_back(Chain);
1833    SDNode *VSt =
1834      CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1835
1836    // Transfer memoperands.
1837    cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1838
1839    return VSt;
1840  }
1841
1842  // Otherwise, quad registers are stored with two separate instructions,
1843  // where one stores the even registers and the other stores the odd registers.
1844
1845  // Form the QQQQ REG_SEQUENCE.
1846  SDValue V0 = N->getOperand(Vec0Idx + 0);
1847  SDValue V1 = N->getOperand(Vec0Idx + 1);
1848  SDValue V2 = N->getOperand(Vec0Idx + 2);
1849  SDValue V3 = (NumVecs == 3)
1850    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1851    : N->getOperand(Vec0Idx + 3);
1852  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1853
1854  // Store the even D registers.  This is always an updating store, so that it
1855  // provides the address to the second store for the odd subregs.
1856  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1857  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1858                                        MemAddr.getValueType(),
1859                                        MVT::Other, OpsA, 7);
1860  cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1861  Chain = SDValue(VStA, 1);
1862
1863  // Store the odd D registers.
1864  Ops.push_back(SDValue(VStA, 0));
1865  Ops.push_back(Align);
1866  if (isUpdating) {
1867    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1868    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1869           "only constant post-increment update allowed for VST3/4");
1870    (void)Inc;
1871    Ops.push_back(Reg0);
1872  }
1873  Ops.push_back(RegSeq);
1874  Ops.push_back(Pred);
1875  Ops.push_back(Reg0);
1876  Ops.push_back(Chain);
1877  SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1878                                        Ops.data(), Ops.size());
1879  cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1880  return VStB;
1881}
1882
1883SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1884                                         bool isUpdating, unsigned NumVecs,
1885                                         unsigned *DOpcodes,
1886                                         unsigned *QOpcodes) {
1887  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1888  DebugLoc dl = N->getDebugLoc();
1889
1890  SDValue MemAddr, Align;
1891  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1892  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1893  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1894    return NULL;
1895
1896  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1897  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1898
1899  SDValue Chain = N->getOperand(0);
1900  unsigned Lane =
1901    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1902  EVT VT = N->getOperand(Vec0Idx).getValueType();
1903  bool is64BitVector = VT.is64BitVector();
1904
1905  unsigned Alignment = 0;
1906  if (NumVecs != 3) {
1907    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1908    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1909    if (Alignment > NumBytes)
1910      Alignment = NumBytes;
1911    if (Alignment < 8 && Alignment < NumBytes)
1912      Alignment = 0;
1913    // Alignment must be a power of two; make sure of that.
1914    Alignment = (Alignment & -Alignment);
1915    if (Alignment == 1)
1916      Alignment = 0;
1917  }
1918  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1919
1920  unsigned OpcodeIndex;
1921  switch (VT.getSimpleVT().SimpleTy) {
1922  default: llvm_unreachable("unhandled vld/vst lane type");
1923    // Double-register operations:
1924  case MVT::v8i8:  OpcodeIndex = 0; break;
1925  case MVT::v4i16: OpcodeIndex = 1; break;
1926  case MVT::v2f32:
1927  case MVT::v2i32: OpcodeIndex = 2; break;
1928    // Quad-register operations:
1929  case MVT::v8i16: OpcodeIndex = 0; break;
1930  case MVT::v4f32:
1931  case MVT::v4i32: OpcodeIndex = 1; break;
1932  }
1933
1934  std::vector<EVT> ResTys;
1935  if (IsLoad) {
1936    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1937    if (!is64BitVector)
1938      ResTyElts *= 2;
1939    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1940                                      MVT::i64, ResTyElts));
1941  }
1942  if (isUpdating)
1943    ResTys.push_back(MVT::i32);
1944  ResTys.push_back(MVT::Other);
1945
1946  SDValue Pred = getAL(CurDAG);
1947  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1948
1949  SmallVector<SDValue, 8> Ops;
1950  Ops.push_back(MemAddr);
1951  Ops.push_back(Align);
1952  if (isUpdating) {
1953    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1954    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1955  }
1956
1957  SDValue SuperReg;
1958  SDValue V0 = N->getOperand(Vec0Idx + 0);
1959  SDValue V1 = N->getOperand(Vec0Idx + 1);
1960  if (NumVecs == 2) {
1961    if (is64BitVector)
1962      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1963    else
1964      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1965  } else {
1966    SDValue V2 = N->getOperand(Vec0Idx + 2);
1967    SDValue V3 = (NumVecs == 3)
1968      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1969      : N->getOperand(Vec0Idx + 3);
1970    if (is64BitVector)
1971      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1972    else
1973      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1974  }
1975  Ops.push_back(SuperReg);
1976  Ops.push_back(getI32Imm(Lane));
1977  Ops.push_back(Pred);
1978  Ops.push_back(Reg0);
1979  Ops.push_back(Chain);
1980
1981  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1982                                  QOpcodes[OpcodeIndex]);
1983  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1984                                         Ops.data(), Ops.size());
1985  cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1986  if (!IsLoad)
1987    return VLdLn;
1988
1989  // Extract the subregisters.
1990  SuperReg = SDValue(VLdLn, 0);
1991  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1992         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1993  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1994  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1995    ReplaceUses(SDValue(N, Vec),
1996                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1997  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1998  if (isUpdating)
1999    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2000  return NULL;
2001}
2002
2003SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2004                                      unsigned NumVecs, unsigned *Opcodes) {
2005  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2006  DebugLoc dl = N->getDebugLoc();
2007
2008  SDValue MemAddr, Align;
2009  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2010    return NULL;
2011
2012  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2013  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2014
2015  SDValue Chain = N->getOperand(0);
2016  EVT VT = N->getValueType(0);
2017
2018  unsigned Alignment = 0;
2019  if (NumVecs != 3) {
2020    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2021    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2022    if (Alignment > NumBytes)
2023      Alignment = NumBytes;
2024    if (Alignment < 8 && Alignment < NumBytes)
2025      Alignment = 0;
2026    // Alignment must be a power of two; make sure of that.
2027    Alignment = (Alignment & -Alignment);
2028    if (Alignment == 1)
2029      Alignment = 0;
2030  }
2031  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2032
2033  unsigned OpcodeIndex;
2034  switch (VT.getSimpleVT().SimpleTy) {
2035  default: llvm_unreachable("unhandled vld-dup type");
2036  case MVT::v8i8:  OpcodeIndex = 0; break;
2037  case MVT::v4i16: OpcodeIndex = 1; break;
2038  case MVT::v2f32:
2039  case MVT::v2i32: OpcodeIndex = 2; break;
2040  }
2041
2042  SDValue Pred = getAL(CurDAG);
2043  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2044  SDValue SuperReg;
2045  unsigned Opc = Opcodes[OpcodeIndex];
2046  SmallVector<SDValue, 6> Ops;
2047  Ops.push_back(MemAddr);
2048  Ops.push_back(Align);
2049  if (isUpdating) {
2050    // fixed-stride update instructions don't have an explicit writeback
2051    // operand. It's implicit in the opcode itself.
2052    SDValue Inc = N->getOperand(2);
2053    if (!isa<ConstantSDNode>(Inc.getNode()))
2054      Ops.push_back(Inc);
2055    // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2056    else if (NumVecs > 2)
2057      Ops.push_back(Reg0);
2058  }
2059  Ops.push_back(Pred);
2060  Ops.push_back(Reg0);
2061  Ops.push_back(Chain);
2062
2063  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2064  std::vector<EVT> ResTys;
2065  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2066  if (isUpdating)
2067    ResTys.push_back(MVT::i32);
2068  ResTys.push_back(MVT::Other);
2069  SDNode *VLdDup =
2070    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2071  cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2072  SuperReg = SDValue(VLdDup, 0);
2073
2074  // Extract the subregisters.
2075  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2076  unsigned SubIdx = ARM::dsub_0;
2077  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2078    ReplaceUses(SDValue(N, Vec),
2079                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2080  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2081  if (isUpdating)
2082    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2083  return NULL;
2084}
2085
2086SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2087                                    unsigned Opc) {
2088  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2089  DebugLoc dl = N->getDebugLoc();
2090  EVT VT = N->getValueType(0);
2091  unsigned FirstTblReg = IsExt ? 2 : 1;
2092
2093  // Form a REG_SEQUENCE to force register allocation.
2094  SDValue RegSeq;
2095  SDValue V0 = N->getOperand(FirstTblReg + 0);
2096  SDValue V1 = N->getOperand(FirstTblReg + 1);
2097  if (NumVecs == 2)
2098    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2099  else {
2100    SDValue V2 = N->getOperand(FirstTblReg + 2);
2101    // If it's a vtbl3, form a quad D-register and leave the last part as
2102    // an undef.
2103    SDValue V3 = (NumVecs == 3)
2104      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2105      : N->getOperand(FirstTblReg + 3);
2106    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2107  }
2108
2109  SmallVector<SDValue, 6> Ops;
2110  if (IsExt)
2111    Ops.push_back(N->getOperand(1));
2112  Ops.push_back(RegSeq);
2113  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2114  Ops.push_back(getAL(CurDAG)); // predicate
2115  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2116  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2117}
2118
2119SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2120                                                     bool isSigned) {
2121  if (!Subtarget->hasV6T2Ops())
2122    return NULL;
2123
2124  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2125    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2126
2127
2128  // For unsigned extracts, check for a shift right and mask
2129  unsigned And_imm = 0;
2130  if (N->getOpcode() == ISD::AND) {
2131    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2132
2133      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2134      if (And_imm & (And_imm + 1))
2135        return NULL;
2136
2137      unsigned Srl_imm = 0;
2138      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2139                                Srl_imm)) {
2140        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2141
2142        // Note: The width operand is encoded as width-1.
2143        unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2144        unsigned LSB = Srl_imm;
2145        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2146        SDValue Ops[] = { N->getOperand(0).getOperand(0),
2147                          CurDAG->getTargetConstant(LSB, MVT::i32),
2148                          CurDAG->getTargetConstant(Width, MVT::i32),
2149          getAL(CurDAG), Reg0 };
2150        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2151      }
2152    }
2153    return NULL;
2154  }
2155
2156  // Otherwise, we're looking for a shift of a shift
2157  unsigned Shl_imm = 0;
2158  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2159    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2160    unsigned Srl_imm = 0;
2161    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2162      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2163      // Note: The width operand is encoded as width-1.
2164      unsigned Width = 32 - Srl_imm - 1;
2165      int LSB = Srl_imm - Shl_imm;
2166      if (LSB < 0)
2167        return NULL;
2168      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2169      SDValue Ops[] = { N->getOperand(0).getOperand(0),
2170                        CurDAG->getTargetConstant(LSB, MVT::i32),
2171                        CurDAG->getTargetConstant(Width, MVT::i32),
2172                        getAL(CurDAG), Reg0 };
2173      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2174    }
2175  }
2176  return NULL;
2177}
2178
2179SDNode *ARMDAGToDAGISel::
2180SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2181                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2182  SDValue CPTmp0;
2183  SDValue CPTmp1;
2184  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2185    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2186    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2187    unsigned Opc = 0;
2188    switch (SOShOp) {
2189    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2190    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2191    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2192    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2193    default:
2194      llvm_unreachable("Unknown so_reg opcode!");
2195    }
2196    SDValue SOShImm =
2197      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2198    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2199    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2200    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2201  }
2202  return 0;
2203}
2204
2205SDNode *ARMDAGToDAGISel::
2206SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2207                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2208  SDValue CPTmp0;
2209  SDValue CPTmp1;
2210  SDValue CPTmp2;
2211  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2212    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2213    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2214    return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2215  }
2216
2217  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2218    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2219    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2220    return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2221  }
2222  return 0;
2223}
2224
2225SDNode *ARMDAGToDAGISel::
2226SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2227                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2228  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2229  if (!T)
2230    return 0;
2231
2232  unsigned Opc = 0;
2233  unsigned TrueImm = T->getZExtValue();
2234  if (is_t2_so_imm(TrueImm)) {
2235    Opc = ARM::t2MOVCCi;
2236  } else if (TrueImm <= 0xffff) {
2237    Opc = ARM::t2MOVCCi16;
2238  } else if (is_t2_so_imm_not(TrueImm)) {
2239    TrueImm = ~TrueImm;
2240    Opc = ARM::t2MVNCCi;
2241  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2242    // Large immediate.
2243    Opc = ARM::t2MOVCCi32imm;
2244  }
2245
2246  if (Opc) {
2247    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2248    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2249    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2250    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2251  }
2252
2253  return 0;
2254}
2255
2256SDNode *ARMDAGToDAGISel::
2257SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2258                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2259  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2260  if (!T)
2261    return 0;
2262
2263  unsigned Opc = 0;
2264  unsigned TrueImm = T->getZExtValue();
2265  bool isSoImm = is_so_imm(TrueImm);
2266  if (isSoImm) {
2267    Opc = ARM::MOVCCi;
2268  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2269    Opc = ARM::MOVCCi16;
2270  } else if (is_so_imm_not(TrueImm)) {
2271    TrueImm = ~TrueImm;
2272    Opc = ARM::MVNCCi;
2273  } else if (TrueVal.getNode()->hasOneUse() &&
2274             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2275    // Large immediate.
2276    Opc = ARM::MOVCCi32imm;
2277  }
2278
2279  if (Opc) {
2280    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2281    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2282    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2283    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2284  }
2285
2286  return 0;
2287}
2288
2289SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2290  EVT VT = N->getValueType(0);
2291  SDValue FalseVal = N->getOperand(0);
2292  SDValue TrueVal  = N->getOperand(1);
2293  SDValue CC = N->getOperand(2);
2294  SDValue CCR = N->getOperand(3);
2295  SDValue InFlag = N->getOperand(4);
2296  assert(CC.getOpcode() == ISD::Constant);
2297  assert(CCR.getOpcode() == ISD::Register);
2298  ARMCC::CondCodes CCVal =
2299    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2300
2301  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2302    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2303    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2304    // Pattern complexity = 18  cost = 1  size = 0
2305    SDValue CPTmp0;
2306    SDValue CPTmp1;
2307    SDValue CPTmp2;
2308    if (Subtarget->isThumb()) {
2309      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2310                                        CCVal, CCR, InFlag);
2311      if (!Res)
2312        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2313                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2314      if (Res)
2315        return Res;
2316    } else {
2317      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2318                                         CCVal, CCR, InFlag);
2319      if (!Res)
2320        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2321                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2322      if (Res)
2323        return Res;
2324    }
2325
2326    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2327    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2328    //             (imm:i32):$cc)
2329    // Emits: (MOVCCi:i32 GPR:i32:$false,
2330    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2331    // Pattern complexity = 10  cost = 1  size = 0
2332    if (Subtarget->isThumb()) {
2333      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2334                                        CCVal, CCR, InFlag);
2335      if (!Res)
2336        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2337                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2338      if (Res)
2339        return Res;
2340    } else {
2341      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2342                                         CCVal, CCR, InFlag);
2343      if (!Res)
2344        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2345                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2346      if (Res)
2347        return Res;
2348    }
2349  }
2350
2351  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2352  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2353  // Pattern complexity = 6  cost = 1  size = 0
2354  //
2355  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2356  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2357  // Pattern complexity = 6  cost = 11  size = 0
2358  //
2359  // Also VMOVScc and VMOVDcc.
2360  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2361  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2362  unsigned Opc = 0;
2363  switch (VT.getSimpleVT().SimpleTy) {
2364  default: assert(false && "Illegal conditional move type!");
2365    break;
2366  case MVT::i32:
2367    Opc = Subtarget->isThumb()
2368      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2369      : ARM::MOVCCr;
2370    break;
2371  case MVT::f32:
2372    Opc = ARM::VMOVScc;
2373    break;
2374  case MVT::f64:
2375    Opc = ARM::VMOVDcc;
2376    break;
2377  }
2378  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2379}
2380
2381/// Target-specific DAG combining for ISD::XOR.
2382/// Target-independent combining lowers SELECT_CC nodes of the form
2383/// select_cc setg[ge] X,  0,  X, -X
2384/// select_cc setgt    X, -1,  X, -X
2385/// select_cc setl[te] X,  0, -X,  X
2386/// select_cc setlt    X,  1, -X,  X
2387/// which represent Integer ABS into:
2388/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2389/// ARM instruction selection detects the latter and matches it to
2390/// ARM::ABS or ARM::t2ABS machine node.
2391SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2392  SDValue XORSrc0 = N->getOperand(0);
2393  SDValue XORSrc1 = N->getOperand(1);
2394  EVT VT = N->getValueType(0);
2395
2396  if (DisableARMIntABS)
2397    return NULL;
2398
2399  if (Subtarget->isThumb1Only())
2400    return NULL;
2401
2402  if (XORSrc0.getOpcode() != ISD::ADD ||
2403    XORSrc1.getOpcode() != ISD::SRA)
2404    return NULL;
2405
2406  SDValue ADDSrc0 = XORSrc0.getOperand(0);
2407  SDValue ADDSrc1 = XORSrc0.getOperand(1);
2408  SDValue SRASrc0 = XORSrc1.getOperand(0);
2409  SDValue SRASrc1 = XORSrc1.getOperand(1);
2410  ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
2411  EVT XType = SRASrc0.getValueType();
2412  unsigned Size = XType.getSizeInBits() - 1;
2413
2414  if (ADDSrc1 == XORSrc1  &&
2415      ADDSrc0 == SRASrc0 &&
2416      XType.isInteger() &&
2417      SRAConstant != NULL &&
2418      Size == SRAConstant->getZExtValue()) {
2419
2420    unsigned Opcode = ARM::ABS;
2421    if (Subtarget->isThumb2())
2422      Opcode = ARM::t2ABS;
2423
2424    return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2425  }
2426
2427  return NULL;
2428}
2429
2430SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2431  // The only time a CONCAT_VECTORS operation can have legal types is when
2432  // two 64-bit vectors are concatenated to a 128-bit vector.
2433  EVT VT = N->getValueType(0);
2434  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2435    llvm_unreachable("unexpected CONCAT_VECTORS");
2436  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2437}
2438
2439SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2440  SmallVector<SDValue, 6> Ops;
2441  Ops.push_back(Node->getOperand(1)); // Ptr
2442  Ops.push_back(Node->getOperand(2)); // Low part of Val1
2443  Ops.push_back(Node->getOperand(3)); // High part of Val1
2444  if (Opc == ARM::ATOMCMPXCHG6432) {
2445    Ops.push_back(Node->getOperand(4)); // Low part of Val2
2446    Ops.push_back(Node->getOperand(5)); // High part of Val2
2447  }
2448  Ops.push_back(Node->getOperand(0)); // Chain
2449  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2450  MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2451  SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2452                                           MVT::i32, MVT::i32, MVT::Other,
2453                                           Ops.data() ,Ops.size());
2454  cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2455  return ResNode;
2456}
2457
2458SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2459  DebugLoc dl = N->getDebugLoc();
2460
2461  if (N->isMachineOpcode())
2462    return NULL;   // Already selected.
2463
2464  switch (N->getOpcode()) {
2465  default: break;
2466  case ISD::XOR: {
2467    // Select special operations if XOR node forms integer ABS pattern
2468    SDNode *ResNode = SelectABSOp(N);
2469    if (ResNode)
2470      return ResNode;
2471    // Other cases are autogenerated.
2472    break;
2473  }
2474  case ISD::Constant: {
2475    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2476    bool UseCP = true;
2477    if (Subtarget->hasThumb2())
2478      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2479      // be done with MOV + MOVT, at worst.
2480      UseCP = 0;
2481    else {
2482      if (Subtarget->isThumb()) {
2483        UseCP = (Val > 255 &&                          // MOV
2484                 ~Val > 255 &&                         // MOV + MVN
2485                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2486      } else
2487        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2488                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2489                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2490    }
2491
2492    if (UseCP) {
2493      SDValue CPIdx =
2494        CurDAG->getTargetConstantPool(ConstantInt::get(
2495                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2496                                      TLI.getPointerTy());
2497
2498      SDNode *ResNode;
2499      if (Subtarget->isThumb1Only()) {
2500        SDValue Pred = getAL(CurDAG);
2501        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2502        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2503        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2504                                         Ops, 4);
2505      } else {
2506        SDValue Ops[] = {
2507          CPIdx,
2508          CurDAG->getTargetConstant(0, MVT::i32),
2509          getAL(CurDAG),
2510          CurDAG->getRegister(0, MVT::i32),
2511          CurDAG->getEntryNode()
2512        };
2513        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2514                                       Ops, 5);
2515      }
2516      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2517      return NULL;
2518    }
2519
2520    // Other cases are autogenerated.
2521    break;
2522  }
2523  case ISD::FrameIndex: {
2524    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2525    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2526    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2527    if (Subtarget->isThumb1Only()) {
2528      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2529                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2530      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2531    } else {
2532      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2533                      ARM::t2ADDri : ARM::ADDri);
2534      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2535                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2536                        CurDAG->getRegister(0, MVT::i32) };
2537      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2538    }
2539  }
2540  case ISD::SRL:
2541    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2542      return I;
2543    break;
2544  case ISD::SRA:
2545    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2546      return I;
2547    break;
2548  case ISD::MUL:
2549    if (Subtarget->isThumb1Only())
2550      break;
2551    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2552      unsigned RHSV = C->getZExtValue();
2553      if (!RHSV) break;
2554      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2555        unsigned ShImm = Log2_32(RHSV-1);
2556        if (ShImm >= 32)
2557          break;
2558        SDValue V = N->getOperand(0);
2559        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2560        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2561        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2562        if (Subtarget->isThumb()) {
2563          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2564          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2565        } else {
2566          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2567          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2568        }
2569      }
2570      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2571        unsigned ShImm = Log2_32(RHSV+1);
2572        if (ShImm >= 32)
2573          break;
2574        SDValue V = N->getOperand(0);
2575        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2576        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2577        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2578        if (Subtarget->isThumb()) {
2579          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2580          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2581        } else {
2582          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2583          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2584        }
2585      }
2586    }
2587    break;
2588  case ISD::AND: {
2589    // Check for unsigned bitfield extract
2590    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2591      return I;
2592
2593    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2594    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2595    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2596    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2597    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2598    EVT VT = N->getValueType(0);
2599    if (VT != MVT::i32)
2600      break;
2601    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2602      ? ARM::t2MOVTi16
2603      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2604    if (!Opc)
2605      break;
2606    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2607    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2608    if (!N1C)
2609      break;
2610    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2611      SDValue N2 = N0.getOperand(1);
2612      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2613      if (!N2C)
2614        break;
2615      unsigned N1CVal = N1C->getZExtValue();
2616      unsigned N2CVal = N2C->getZExtValue();
2617      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2618          (N1CVal & 0xffffU) == 0xffffU &&
2619          (N2CVal & 0xffffU) == 0x0U) {
2620        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2621                                                  MVT::i32);
2622        SDValue Ops[] = { N0.getOperand(0), Imm16,
2623                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2624        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2625      }
2626    }
2627    break;
2628  }
2629  case ARMISD::VMOVRRD:
2630    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2631                                  N->getOperand(0), getAL(CurDAG),
2632                                  CurDAG->getRegister(0, MVT::i32));
2633  case ISD::UMUL_LOHI: {
2634    if (Subtarget->isThumb1Only())
2635      break;
2636    if (Subtarget->isThumb()) {
2637      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2638                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2639                        CurDAG->getRegister(0, MVT::i32) };
2640      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2641    } else {
2642      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2643                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2644                        CurDAG->getRegister(0, MVT::i32) };
2645      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2646                                    ARM::UMULL : ARM::UMULLv5,
2647                                    dl, MVT::i32, MVT::i32, Ops, 5);
2648    }
2649  }
2650  case ISD::SMUL_LOHI: {
2651    if (Subtarget->isThumb1Only())
2652      break;
2653    if (Subtarget->isThumb()) {
2654      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2655                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2656      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2657    } else {
2658      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2659                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2660                        CurDAG->getRegister(0, MVT::i32) };
2661      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2662                                    ARM::SMULL : ARM::SMULLv5,
2663                                    dl, MVT::i32, MVT::i32, Ops, 5);
2664    }
2665  }
2666  case ISD::LOAD: {
2667    SDNode *ResNode = 0;
2668    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2669      ResNode = SelectT2IndexedLoad(N);
2670    else
2671      ResNode = SelectARMIndexedLoad(N);
2672    if (ResNode)
2673      return ResNode;
2674    // Other cases are autogenerated.
2675    break;
2676  }
2677  case ARMISD::BRCOND: {
2678    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2679    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2680    // Pattern complexity = 6  cost = 1  size = 0
2681
2682    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2683    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2684    // Pattern complexity = 6  cost = 1  size = 0
2685
2686    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2687    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2688    // Pattern complexity = 6  cost = 1  size = 0
2689
2690    unsigned Opc = Subtarget->isThumb() ?
2691      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2692    SDValue Chain = N->getOperand(0);
2693    SDValue N1 = N->getOperand(1);
2694    SDValue N2 = N->getOperand(2);
2695    SDValue N3 = N->getOperand(3);
2696    SDValue InFlag = N->getOperand(4);
2697    assert(N1.getOpcode() == ISD::BasicBlock);
2698    assert(N2.getOpcode() == ISD::Constant);
2699    assert(N3.getOpcode() == ISD::Register);
2700
2701    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2702                               cast<ConstantSDNode>(N2)->getZExtValue()),
2703                               MVT::i32);
2704    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2705    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2706                                             MVT::Glue, Ops, 5);
2707    Chain = SDValue(ResNode, 0);
2708    if (N->getNumValues() == 2) {
2709      InFlag = SDValue(ResNode, 1);
2710      ReplaceUses(SDValue(N, 1), InFlag);
2711    }
2712    ReplaceUses(SDValue(N, 0),
2713                SDValue(Chain.getNode(), Chain.getResNo()));
2714    return NULL;
2715  }
2716  case ARMISD::CMOV:
2717    return SelectCMOVOp(N);
2718  case ARMISD::VZIP: {
2719    unsigned Opc = 0;
2720    EVT VT = N->getValueType(0);
2721    switch (VT.getSimpleVT().SimpleTy) {
2722    default: return NULL;
2723    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2724    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2725    case MVT::v2f32:
2726    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2727    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2728    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2729    case MVT::v4f32:
2730    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2731    }
2732    SDValue Pred = getAL(CurDAG);
2733    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2734    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2735    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2736  }
2737  case ARMISD::VUZP: {
2738    unsigned Opc = 0;
2739    EVT VT = N->getValueType(0);
2740    switch (VT.getSimpleVT().SimpleTy) {
2741    default: return NULL;
2742    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2743    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2744    case MVT::v2f32:
2745    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2746    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2747    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2748    case MVT::v4f32:
2749    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2750    }
2751    SDValue Pred = getAL(CurDAG);
2752    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2753    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2754    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2755  }
2756  case ARMISD::VTRN: {
2757    unsigned Opc = 0;
2758    EVT VT = N->getValueType(0);
2759    switch (VT.getSimpleVT().SimpleTy) {
2760    default: return NULL;
2761    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2762    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2763    case MVT::v2f32:
2764    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2765    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2766    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2767    case MVT::v4f32:
2768    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2769    }
2770    SDValue Pred = getAL(CurDAG);
2771    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2772    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2773    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2774  }
2775  case ARMISD::BUILD_VECTOR: {
2776    EVT VecVT = N->getValueType(0);
2777    EVT EltVT = VecVT.getVectorElementType();
2778    unsigned NumElts = VecVT.getVectorNumElements();
2779    if (EltVT == MVT::f64) {
2780      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2781      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2782    }
2783    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2784    if (NumElts == 2)
2785      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2786    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2787    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2788                     N->getOperand(2), N->getOperand(3));
2789  }
2790
2791  case ARMISD::VLD2DUP: {
2792    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2793                           ARM::VLD2DUPd32Pseudo };
2794    return SelectVLDDup(N, false, 2, Opcodes);
2795  }
2796
2797  case ARMISD::VLD3DUP: {
2798    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2799                           ARM::VLD3DUPd32Pseudo };
2800    return SelectVLDDup(N, false, 3, Opcodes);
2801  }
2802
2803  case ARMISD::VLD4DUP: {
2804    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2805                           ARM::VLD4DUPd32Pseudo };
2806    return SelectVLDDup(N, false, 4, Opcodes);
2807  }
2808
2809  case ARMISD::VLD2DUP_UPD: {
2810    unsigned Opcodes[] = { ARM::VLD2DUPd8PseudoWB_fixed,
2811                           ARM::VLD2DUPd16PseudoWB_fixed,
2812                           ARM::VLD2DUPd32PseudoWB_fixed };
2813    return SelectVLDDup(N, true, 2, Opcodes);
2814  }
2815
2816  case ARMISD::VLD3DUP_UPD: {
2817    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2818                           ARM::VLD3DUPd32Pseudo_UPD };
2819    return SelectVLDDup(N, true, 3, Opcodes);
2820  }
2821
2822  case ARMISD::VLD4DUP_UPD: {
2823    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2824                           ARM::VLD4DUPd32Pseudo_UPD };
2825    return SelectVLDDup(N, true, 4, Opcodes);
2826  }
2827
2828  case ARMISD::VLD1_UPD: {
2829    unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
2830                            ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
2831    unsigned QOpcodes[] = { ARM::VLD1q8PseudoWB_fixed,
2832                            ARM::VLD1q16PseudoWB_fixed,
2833                            ARM::VLD1q32PseudoWB_fixed,
2834                            ARM::VLD1q64PseudoWB_fixed };
2835    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2836  }
2837
2838  case ARMISD::VLD2_UPD: {
2839    unsigned DOpcodes[] = { ARM::VLD2d8PseudoWB_fixed,
2840                            ARM::VLD2d16PseudoWB_fixed,
2841                            ARM::VLD2d32PseudoWB_fixed,
2842                            ARM::VLD1q64PseudoWB_fixed};
2843    unsigned QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2844                            ARM::VLD2q16PseudoWB_fixed,
2845                            ARM::VLD2q32PseudoWB_fixed };
2846    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2847  }
2848
2849  case ARMISD::VLD3_UPD: {
2850    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2851                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2852    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2853                             ARM::VLD3q16Pseudo_UPD,
2854                             ARM::VLD3q32Pseudo_UPD };
2855    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2856                             ARM::VLD3q16oddPseudo_UPD,
2857                             ARM::VLD3q32oddPseudo_UPD };
2858    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2859  }
2860
2861  case ARMISD::VLD4_UPD: {
2862    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2863                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2864    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2865                             ARM::VLD4q16Pseudo_UPD,
2866                             ARM::VLD4q32Pseudo_UPD };
2867    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2868                             ARM::VLD4q16oddPseudo_UPD,
2869                             ARM::VLD4q32oddPseudo_UPD };
2870    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2871  }
2872
2873  case ARMISD::VLD2LN_UPD: {
2874    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2875                            ARM::VLD2LNd32Pseudo_UPD };
2876    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2877                            ARM::VLD2LNq32Pseudo_UPD };
2878    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2879  }
2880
2881  case ARMISD::VLD3LN_UPD: {
2882    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2883                            ARM::VLD3LNd32Pseudo_UPD };
2884    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2885                            ARM::VLD3LNq32Pseudo_UPD };
2886    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2887  }
2888
2889  case ARMISD::VLD4LN_UPD: {
2890    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2891                            ARM::VLD4LNd32Pseudo_UPD };
2892    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2893                            ARM::VLD4LNq32Pseudo_UPD };
2894    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2895  }
2896
2897  case ARMISD::VST1_UPD: {
2898    unsigned DOpcodes[] = { ARM::VST1d8wb_fixed, ARM::VST1d16wb_fixed,
2899                            ARM::VST1d32wb_fixed, ARM::VST1d64wb_fixed };
2900    unsigned QOpcodes[] = { ARM::VST1q8PseudoWB_fixed,
2901                            ARM::VST1q16PseudoWB_fixed,
2902                            ARM::VST1q32PseudoWB_fixed,
2903                            ARM::VST1q64PseudoWB_fixed };
2904    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2905  }
2906
2907  case ARMISD::VST2_UPD: {
2908    unsigned DOpcodes[] = { ARM::VST2d8PseudoWB_fixed,
2909                            ARM::VST2d16PseudoWB_fixed,
2910                            ARM::VST2d32PseudoWB_fixed,
2911                            ARM::VST1q64PseudoWB_fixed};
2912    unsigned QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2913                            ARM::VST2q16PseudoWB_fixed,
2914                            ARM::VST2q32PseudoWB_fixed };
2915    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2916  }
2917
2918  case ARMISD::VST3_UPD: {
2919    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2920                            ARM::VST3d32Pseudo_UPD,ARM::VST1d64TPseudoWB_fixed};
2921    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2922                             ARM::VST3q16Pseudo_UPD,
2923                             ARM::VST3q32Pseudo_UPD };
2924    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2925                             ARM::VST3q16oddPseudo_UPD,
2926                             ARM::VST3q32oddPseudo_UPD };
2927    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2928  }
2929
2930  case ARMISD::VST4_UPD: {
2931    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2932                            ARM::VST4d32Pseudo_UPD,ARM::VST1d64QPseudoWB_fixed};
2933    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2934                             ARM::VST4q16Pseudo_UPD,
2935                             ARM::VST4q32Pseudo_UPD };
2936    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2937                             ARM::VST4q16oddPseudo_UPD,
2938                             ARM::VST4q32oddPseudo_UPD };
2939    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2940  }
2941
2942  case ARMISD::VST2LN_UPD: {
2943    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2944                            ARM::VST2LNd32Pseudo_UPD };
2945    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2946                            ARM::VST2LNq32Pseudo_UPD };
2947    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2948  }
2949
2950  case ARMISD::VST3LN_UPD: {
2951    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2952                            ARM::VST3LNd32Pseudo_UPD };
2953    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2954                            ARM::VST3LNq32Pseudo_UPD };
2955    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2956  }
2957
2958  case ARMISD::VST4LN_UPD: {
2959    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2960                            ARM::VST4LNd32Pseudo_UPD };
2961    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2962                            ARM::VST4LNq32Pseudo_UPD };
2963    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2964  }
2965
2966  case ISD::INTRINSIC_VOID:
2967  case ISD::INTRINSIC_W_CHAIN: {
2968    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2969    switch (IntNo) {
2970    default:
2971      break;
2972
2973    case Intrinsic::arm_ldrexd: {
2974      SDValue MemAddr = N->getOperand(2);
2975      DebugLoc dl = N->getDebugLoc();
2976      SDValue Chain = N->getOperand(0);
2977
2978      unsigned NewOpc = ARM::LDREXD;
2979      if (Subtarget->isThumb() && Subtarget->hasThumb2())
2980        NewOpc = ARM::t2LDREXD;
2981
2982      // arm_ldrexd returns a i64 value in {i32, i32}
2983      std::vector<EVT> ResTys;
2984      ResTys.push_back(MVT::i32);
2985      ResTys.push_back(MVT::i32);
2986      ResTys.push_back(MVT::Other);
2987
2988      // place arguments in the right order
2989      SmallVector<SDValue, 7> Ops;
2990      Ops.push_back(MemAddr);
2991      Ops.push_back(getAL(CurDAG));
2992      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2993      Ops.push_back(Chain);
2994      SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2995                                          Ops.size());
2996      // Transfer memoperands.
2997      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2998      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2999      cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3000
3001      // Until there's support for specifing explicit register constraints
3002      // like the use of even/odd register pair, hardcode ldrexd to always
3003      // use the pair [R0, R1] to hold the load result.
3004      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
3005                                   SDValue(Ld, 0), SDValue(0,0));
3006      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
3007                                   SDValue(Ld, 1), Chain.getValue(1));
3008
3009      // Remap uses.
3010      SDValue Glue = Chain.getValue(1);
3011      if (!SDValue(N, 0).use_empty()) {
3012        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3013                                                ARM::R0, MVT::i32, Glue);
3014        Glue = Result.getValue(2);
3015        ReplaceUses(SDValue(N, 0), Result);
3016      }
3017      if (!SDValue(N, 1).use_empty()) {
3018        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3019                                                ARM::R1, MVT::i32, Glue);
3020        Glue = Result.getValue(2);
3021        ReplaceUses(SDValue(N, 1), Result);
3022      }
3023
3024      ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
3025      return NULL;
3026    }
3027
3028    case Intrinsic::arm_strexd: {
3029      DebugLoc dl = N->getDebugLoc();
3030      SDValue Chain = N->getOperand(0);
3031      SDValue Val0 = N->getOperand(2);
3032      SDValue Val1 = N->getOperand(3);
3033      SDValue MemAddr = N->getOperand(4);
3034
3035      // Until there's support for specifing explicit register constraints
3036      // like the use of even/odd register pair, hardcode strexd to always
3037      // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
3038      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
3039                                   SDValue(0, 0));
3040      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
3041
3042      SDValue Glue = Chain.getValue(1);
3043      Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3044                                    ARM::R2, MVT::i32, Glue);
3045      Glue = Val0.getValue(1);
3046      Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3047                                    ARM::R3, MVT::i32, Glue);
3048
3049      // Store exclusive double return a i32 value which is the return status
3050      // of the issued store.
3051      std::vector<EVT> ResTys;
3052      ResTys.push_back(MVT::i32);
3053      ResTys.push_back(MVT::Other);
3054
3055      // place arguments in the right order
3056      SmallVector<SDValue, 7> Ops;
3057      Ops.push_back(Val0);
3058      Ops.push_back(Val1);
3059      Ops.push_back(MemAddr);
3060      Ops.push_back(getAL(CurDAG));
3061      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3062      Ops.push_back(Chain);
3063
3064      unsigned NewOpc = ARM::STREXD;
3065      if (Subtarget->isThumb() && Subtarget->hasThumb2())
3066        NewOpc = ARM::t2STREXD;
3067
3068      SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3069                                          Ops.size());
3070      // Transfer memoperands.
3071      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3072      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3073      cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3074
3075      return St;
3076    }
3077
3078    case Intrinsic::arm_neon_vld1: {
3079      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3080                              ARM::VLD1d32, ARM::VLD1d64 };
3081      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
3082                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
3083      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3084    }
3085
3086    case Intrinsic::arm_neon_vld2: {
3087      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
3088                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
3089      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3090                              ARM::VLD2q32Pseudo };
3091      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3092    }
3093
3094    case Intrinsic::arm_neon_vld3: {
3095      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
3096                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
3097      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3098                               ARM::VLD3q16Pseudo_UPD,
3099                               ARM::VLD3q32Pseudo_UPD };
3100      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3101                               ARM::VLD3q16oddPseudo,
3102                               ARM::VLD3q32oddPseudo };
3103      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3104    }
3105
3106    case Intrinsic::arm_neon_vld4: {
3107      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
3108                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
3109      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3110                               ARM::VLD4q16Pseudo_UPD,
3111                               ARM::VLD4q32Pseudo_UPD };
3112      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3113                               ARM::VLD4q16oddPseudo,
3114                               ARM::VLD4q32oddPseudo };
3115      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3116    }
3117
3118    case Intrinsic::arm_neon_vld2lane: {
3119      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
3120                              ARM::VLD2LNd32Pseudo };
3121      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
3122      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3123    }
3124
3125    case Intrinsic::arm_neon_vld3lane: {
3126      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
3127                              ARM::VLD3LNd32Pseudo };
3128      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
3129      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3130    }
3131
3132    case Intrinsic::arm_neon_vld4lane: {
3133      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
3134                              ARM::VLD4LNd32Pseudo };
3135      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
3136      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3137    }
3138
3139    case Intrinsic::arm_neon_vst1: {
3140      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3141                              ARM::VST1d32, ARM::VST1d64 };
3142      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
3143                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
3144      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3145    }
3146
3147    case Intrinsic::arm_neon_vst2: {
3148      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3149                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3150      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3151                              ARM::VST2q32Pseudo };
3152      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3153    }
3154
3155    case Intrinsic::arm_neon_vst3: {
3156      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3157                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3158      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3159                               ARM::VST3q16Pseudo_UPD,
3160                               ARM::VST3q32Pseudo_UPD };
3161      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3162                               ARM::VST3q16oddPseudo,
3163                               ARM::VST3q32oddPseudo };
3164      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3165    }
3166
3167    case Intrinsic::arm_neon_vst4: {
3168      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3169                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3170      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3171                               ARM::VST4q16Pseudo_UPD,
3172                               ARM::VST4q32Pseudo_UPD };
3173      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3174                               ARM::VST4q16oddPseudo,
3175                               ARM::VST4q32oddPseudo };
3176      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3177    }
3178
3179    case Intrinsic::arm_neon_vst2lane: {
3180      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3181                              ARM::VST2LNd32Pseudo };
3182      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3183      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3184    }
3185
3186    case Intrinsic::arm_neon_vst3lane: {
3187      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3188                              ARM::VST3LNd32Pseudo };
3189      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3190      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3191    }
3192
3193    case Intrinsic::arm_neon_vst4lane: {
3194      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3195                              ARM::VST4LNd32Pseudo };
3196      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3197      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3198    }
3199    }
3200    break;
3201  }
3202
3203  case ISD::INTRINSIC_WO_CHAIN: {
3204    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3205    switch (IntNo) {
3206    default:
3207      break;
3208
3209    case Intrinsic::arm_neon_vtbl2:
3210      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3211    case Intrinsic::arm_neon_vtbl3:
3212      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3213    case Intrinsic::arm_neon_vtbl4:
3214      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3215
3216    case Intrinsic::arm_neon_vtbx2:
3217      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3218    case Intrinsic::arm_neon_vtbx3:
3219      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3220    case Intrinsic::arm_neon_vtbx4:
3221      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3222    }
3223    break;
3224  }
3225
3226  case ARMISD::VTBL1: {
3227    DebugLoc dl = N->getDebugLoc();
3228    EVT VT = N->getValueType(0);
3229    SmallVector<SDValue, 6> Ops;
3230
3231    Ops.push_back(N->getOperand(0));
3232    Ops.push_back(N->getOperand(1));
3233    Ops.push_back(getAL(CurDAG));                    // Predicate
3234    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3235    return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3236  }
3237  case ARMISD::VTBL2: {
3238    DebugLoc dl = N->getDebugLoc();
3239    EVT VT = N->getValueType(0);
3240
3241    // Form a REG_SEQUENCE to force register allocation.
3242    SDValue V0 = N->getOperand(0);
3243    SDValue V1 = N->getOperand(1);
3244    SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3245
3246    SmallVector<SDValue, 6> Ops;
3247    Ops.push_back(RegSeq);
3248    Ops.push_back(N->getOperand(2));
3249    Ops.push_back(getAL(CurDAG));                    // Predicate
3250    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3251    return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3252                                  Ops.data(), Ops.size());
3253  }
3254
3255  case ISD::CONCAT_VECTORS:
3256    return SelectConcatVector(N);
3257
3258  case ARMISD::ATOMOR64_DAG:
3259    return SelectAtomic64(N, ARM::ATOMOR6432);
3260  case ARMISD::ATOMXOR64_DAG:
3261    return SelectAtomic64(N, ARM::ATOMXOR6432);
3262  case ARMISD::ATOMADD64_DAG:
3263    return SelectAtomic64(N, ARM::ATOMADD6432);
3264  case ARMISD::ATOMSUB64_DAG:
3265    return SelectAtomic64(N, ARM::ATOMSUB6432);
3266  case ARMISD::ATOMNAND64_DAG:
3267    return SelectAtomic64(N, ARM::ATOMNAND6432);
3268  case ARMISD::ATOMAND64_DAG:
3269    return SelectAtomic64(N, ARM::ATOMAND6432);
3270  case ARMISD::ATOMSWAP64_DAG:
3271    return SelectAtomic64(N, ARM::ATOMSWAP6432);
3272  case ARMISD::ATOMCMPXCHG64_DAG:
3273    return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3274  }
3275
3276  return SelectCode(N);
3277}
3278
3279bool ARMDAGToDAGISel::
3280SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3281                             std::vector<SDValue> &OutOps) {
3282  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3283  // Require the address to be in a register.  That is safe for all ARM
3284  // variants and it is hard to do anything much smarter without knowing
3285  // how the operand is used.
3286  OutOps.push_back(Op);
3287  return false;
3288}
3289
3290/// createARMISelDag - This pass converts a legalized DAG into a
3291/// ARM-specific DAG, ready for instruction scheduling.
3292///
3293FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3294                                     CodeGenOpt::Level OptLevel) {
3295  return new ARMDAGToDAGISel(TM, OptLevel);
3296}
3297