ARMISelDAGToDAG.cpp revision 5bafff36c798608a189c517d37527e4a38863071 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMConstantPoolValue.h"
17#include "ARMISelLowering.h"
18#include "ARMTargetMachine.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/CodeGen/SelectionDAGISel.h"
29#include "llvm/Target/TargetLowering.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Debug.h"
33using namespace llvm;
34
35static const unsigned arm_dsubreg_0 = 5;
36static const unsigned arm_dsubreg_1 = 6;
37
38//===--------------------------------------------------------------------===//
39/// ARMDAGToDAGISel - ARM specific code to select ARM machine
40/// instructions for SelectionDAG operations.
41///
42namespace {
43class ARMDAGToDAGISel : public SelectionDAGISel {
44  ARMTargetMachine &TM;
45
46  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47  /// make the right decision when generating code for different targets.
48  const ARMSubtarget *Subtarget;
49
50public:
51  explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
52    : SelectionDAGISel(tm), TM(tm),
53    Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
54  }
55
56  virtual const char *getPassName() const {
57    return "ARM Instruction Selection";
58  }
59
60 /// getI32Imm - Return a target constant with the specified value, of type i32.
61  inline SDValue getI32Imm(unsigned Imm) {
62    return CurDAG->getTargetConstant(Imm, MVT::i32);
63  }
64
65  SDNode *Select(SDValue Op);
66  virtual void InstructionSelect();
67  bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
68                       SDValue &Offset, SDValue &Opc);
69  bool SelectAddrMode2Offset(SDValue Op, SDValue N,
70                             SDValue &Offset, SDValue &Opc);
71  bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
72                       SDValue &Offset, SDValue &Opc);
73  bool SelectAddrMode3Offset(SDValue Op, SDValue N,
74                             SDValue &Offset, SDValue &Opc);
75  bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
76                       SDValue &Offset);
77
78  bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
79                         SDValue &Label);
80
81  bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
82                             SDValue &Offset);
83  bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
84                              SDValue &Base, SDValue &OffImm,
85                              SDValue &Offset);
86  bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
87                             SDValue &OffImm, SDValue &Offset);
88  bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
89                             SDValue &OffImm, SDValue &Offset);
90  bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
91                             SDValue &OffImm, SDValue &Offset);
92  bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
93                             SDValue &OffImm);
94
95  bool SelectShifterOperand(SDValue Op, SDValue N,
96                            SDValue &BaseReg, SDValue &Opc);
97
98  bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
99                               SDValue &B, SDValue &C);
100
101  // Include the pieces autogenerated from the target description.
102#include "ARMGenDAGISel.inc"
103
104private:
105    /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
106    /// inline asm expressions.
107    virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
108                                              char ConstraintCode,
109                                              std::vector<SDValue> &OutOps);
110};
111}
112
113void ARMDAGToDAGISel::InstructionSelect() {
114  DEBUG(BB->dump());
115
116  SelectRoot(*CurDAG);
117  CurDAG->RemoveDeadNodes();
118}
119
120bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
121                                      SDValue &Base, SDValue &Offset,
122                                      SDValue &Opc) {
123  if (N.getOpcode() == ISD::MUL) {
124    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
125      // X * [3,5,9] -> X + X * [2,4,8] etc.
126      int RHSC = (int)RHS->getZExtValue();
127      if (RHSC & 1) {
128        RHSC = RHSC & ~1;
129        ARM_AM::AddrOpc AddSub = ARM_AM::add;
130        if (RHSC < 0) {
131          AddSub = ARM_AM::sub;
132          RHSC = - RHSC;
133        }
134        if (isPowerOf2_32(RHSC)) {
135          unsigned ShAmt = Log2_32(RHSC);
136          Base = Offset = N.getOperand(0);
137          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
138                                                            ARM_AM::lsl),
139                                          MVT::i32);
140          return true;
141        }
142      }
143    }
144  }
145
146  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
147    Base = N;
148    if (N.getOpcode() == ISD::FrameIndex) {
149      int FI = cast<FrameIndexSDNode>(N)->getIndex();
150      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
151    } else if (N.getOpcode() == ARMISD::Wrapper) {
152      Base = N.getOperand(0);
153    }
154    Offset = CurDAG->getRegister(0, MVT::i32);
155    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
156                                                      ARM_AM::no_shift),
157                                    MVT::i32);
158    return true;
159  }
160
161  // Match simple R +/- imm12 operands.
162  if (N.getOpcode() == ISD::ADD)
163    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
164      int RHSC = (int)RHS->getZExtValue();
165      if ((RHSC >= 0 && RHSC < 0x1000) ||
166          (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
167        Base = N.getOperand(0);
168        if (Base.getOpcode() == ISD::FrameIndex) {
169          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
170          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
171        }
172        Offset = CurDAG->getRegister(0, MVT::i32);
173
174        ARM_AM::AddrOpc AddSub = ARM_AM::add;
175        if (RHSC < 0) {
176          AddSub = ARM_AM::sub;
177          RHSC = - RHSC;
178        }
179        Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
180                                                          ARM_AM::no_shift),
181                                        MVT::i32);
182        return true;
183      }
184    }
185
186  // Otherwise this is R +/- [possibly shifted] R
187  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
188  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
189  unsigned ShAmt = 0;
190
191  Base   = N.getOperand(0);
192  Offset = N.getOperand(1);
193
194  if (ShOpcVal != ARM_AM::no_shift) {
195    // Check to see if the RHS of the shift is a constant, if not, we can't fold
196    // it.
197    if (ConstantSDNode *Sh =
198           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
199      ShAmt = Sh->getZExtValue();
200      Offset = N.getOperand(1).getOperand(0);
201    } else {
202      ShOpcVal = ARM_AM::no_shift;
203    }
204  }
205
206  // Try matching (R shl C) + (R).
207  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
208    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
209    if (ShOpcVal != ARM_AM::no_shift) {
210      // Check to see if the RHS of the shift is a constant, if not, we can't
211      // fold it.
212      if (ConstantSDNode *Sh =
213          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
214        ShAmt = Sh->getZExtValue();
215        Offset = N.getOperand(0).getOperand(0);
216        Base = N.getOperand(1);
217      } else {
218        ShOpcVal = ARM_AM::no_shift;
219      }
220    }
221  }
222
223  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
224                                  MVT::i32);
225  return true;
226}
227
228bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
229                                            SDValue &Offset, SDValue &Opc) {
230  unsigned Opcode = Op.getOpcode();
231  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
232    ? cast<LoadSDNode>(Op)->getAddressingMode()
233    : cast<StoreSDNode>(Op)->getAddressingMode();
234  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
235    ? ARM_AM::add : ARM_AM::sub;
236  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
237    int Val = (int)C->getZExtValue();
238    if (Val >= 0 && Val < 0x1000) { // 12 bits.
239      Offset = CurDAG->getRegister(0, MVT::i32);
240      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
241                                                        ARM_AM::no_shift),
242                                      MVT::i32);
243      return true;
244    }
245  }
246
247  Offset = N;
248  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
249  unsigned ShAmt = 0;
250  if (ShOpcVal != ARM_AM::no_shift) {
251    // Check to see if the RHS of the shift is a constant, if not, we can't fold
252    // it.
253    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
254      ShAmt = Sh->getZExtValue();
255      Offset = N.getOperand(0);
256    } else {
257      ShOpcVal = ARM_AM::no_shift;
258    }
259  }
260
261  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
262                                  MVT::i32);
263  return true;
264}
265
266
267bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
268                                      SDValue &Base, SDValue &Offset,
269                                      SDValue &Opc) {
270  if (N.getOpcode() == ISD::SUB) {
271    // X - C  is canonicalize to X + -C, no need to handle it here.
272    Base = N.getOperand(0);
273    Offset = N.getOperand(1);
274    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
275    return true;
276  }
277
278  if (N.getOpcode() != ISD::ADD) {
279    Base = N;
280    if (N.getOpcode() == ISD::FrameIndex) {
281      int FI = cast<FrameIndexSDNode>(N)->getIndex();
282      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
283    }
284    Offset = CurDAG->getRegister(0, MVT::i32);
285    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
286    return true;
287  }
288
289  // If the RHS is +/- imm8, fold into addr mode.
290  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
291    int RHSC = (int)RHS->getZExtValue();
292    if ((RHSC >= 0 && RHSC < 256) ||
293        (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
294      Base = N.getOperand(0);
295      if (Base.getOpcode() == ISD::FrameIndex) {
296        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
297        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
298      }
299      Offset = CurDAG->getRegister(0, MVT::i32);
300
301      ARM_AM::AddrOpc AddSub = ARM_AM::add;
302      if (RHSC < 0) {
303        AddSub = ARM_AM::sub;
304        RHSC = - RHSC;
305      }
306      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
307      return true;
308    }
309  }
310
311  Base = N.getOperand(0);
312  Offset = N.getOperand(1);
313  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
314  return true;
315}
316
317bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
318                                            SDValue &Offset, SDValue &Opc) {
319  unsigned Opcode = Op.getOpcode();
320  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
321    ? cast<LoadSDNode>(Op)->getAddressingMode()
322    : cast<StoreSDNode>(Op)->getAddressingMode();
323  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
324    ? ARM_AM::add : ARM_AM::sub;
325  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
326    int Val = (int)C->getZExtValue();
327    if (Val >= 0 && Val < 256) {
328      Offset = CurDAG->getRegister(0, MVT::i32);
329      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
330      return true;
331    }
332  }
333
334  Offset = N;
335  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
336  return true;
337}
338
339
340bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
341                                      SDValue &Base, SDValue &Offset) {
342  if (N.getOpcode() != ISD::ADD) {
343    Base = N;
344    if (N.getOpcode() == ISD::FrameIndex) {
345      int FI = cast<FrameIndexSDNode>(N)->getIndex();
346      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
347    } else if (N.getOpcode() == ARMISD::Wrapper) {
348      Base = N.getOperand(0);
349    }
350    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
351                                       MVT::i32);
352    return true;
353  }
354
355  // If the RHS is +/- imm8, fold into addr mode.
356  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
357    int RHSC = (int)RHS->getZExtValue();
358    if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied by 4.
359      RHSC >>= 2;
360      if ((RHSC >= 0 && RHSC < 256) ||
361          (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
362        Base = N.getOperand(0);
363        if (Base.getOpcode() == ISD::FrameIndex) {
364          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
365          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
366        }
367
368        ARM_AM::AddrOpc AddSub = ARM_AM::add;
369        if (RHSC < 0) {
370          AddSub = ARM_AM::sub;
371          RHSC = - RHSC;
372        }
373        Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
374                                           MVT::i32);
375        return true;
376      }
377    }
378  }
379
380  Base = N;
381  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
382                                     MVT::i32);
383  return true;
384}
385
386bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
387                                        SDValue &Offset, SDValue &Label) {
388  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
389    Offset = N.getOperand(0);
390    SDValue N1 = N.getOperand(1);
391    Label  = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
392                                       MVT::i32);
393    return true;
394  }
395  return false;
396}
397
398bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
399                                            SDValue &Base, SDValue &Offset){
400  // FIXME dl should come from the parent load or store, not the address
401  DebugLoc dl = Op.getDebugLoc();
402  if (N.getOpcode() != ISD::ADD) {
403    Base = N;
404    // We must materialize a zero in a reg! Returning a constant here
405    // wouldn't work without additional code to position the node within
406    // ISel's topological ordering in a place where ISel will process it
407    // normally.  Instead, just explicitly issue a tMOVri8 node!
408    Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32,
409                                    CurDAG->getTargetConstant(0, MVT::i32)), 0);
410    return true;
411  }
412
413  Base = N.getOperand(0);
414  Offset = N.getOperand(1);
415  return true;
416}
417
418bool
419ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
420                                        unsigned Scale, SDValue &Base,
421                                        SDValue &OffImm, SDValue &Offset) {
422  if (Scale == 4) {
423    SDValue TmpBase, TmpOffImm;
424    if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
425      return false;  // We want to select tLDRspi / tSTRspi instead.
426    if (N.getOpcode() == ARMISD::Wrapper &&
427        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
428      return false;  // We want to select tLDRpci instead.
429  }
430
431  if (N.getOpcode() != ISD::ADD) {
432    Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
433    Offset = CurDAG->getRegister(0, MVT::i32);
434    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
435    return true;
436  }
437
438  // Thumb does not have [sp, r] address mode.
439  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
440  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
441  if ((LHSR && LHSR->getReg() == ARM::SP) ||
442      (RHSR && RHSR->getReg() == ARM::SP)) {
443    Base = N;
444    Offset = CurDAG->getRegister(0, MVT::i32);
445    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
446    return true;
447  }
448
449  // If the RHS is + imm5 * scale, fold into addr mode.
450  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
451    int RHSC = (int)RHS->getZExtValue();
452    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
453      RHSC /= Scale;
454      if (RHSC >= 0 && RHSC < 32) {
455        Base = N.getOperand(0);
456        Offset = CurDAG->getRegister(0, MVT::i32);
457        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
458        return true;
459      }
460    }
461  }
462
463  Base = N.getOperand(0);
464  Offset = N.getOperand(1);
465  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
466  return true;
467}
468
469bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
470                                            SDValue &Base, SDValue &OffImm,
471                                            SDValue &Offset) {
472  return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
473}
474
475bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
476                                            SDValue &Base, SDValue &OffImm,
477                                            SDValue &Offset) {
478  return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
479}
480
481bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
482                                            SDValue &Base, SDValue &OffImm,
483                                            SDValue &Offset) {
484  return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
485}
486
487bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
488                                           SDValue &Base, SDValue &OffImm) {
489  if (N.getOpcode() == ISD::FrameIndex) {
490    int FI = cast<FrameIndexSDNode>(N)->getIndex();
491    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
492    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
493    return true;
494  }
495
496  if (N.getOpcode() != ISD::ADD)
497    return false;
498
499  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
500  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
501      (LHSR && LHSR->getReg() == ARM::SP)) {
502    // If the RHS is + imm8 * scale, fold into addr mode.
503    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
504      int RHSC = (int)RHS->getZExtValue();
505      if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied.
506        RHSC >>= 2;
507        if (RHSC >= 0 && RHSC < 256) {
508          Base = N.getOperand(0);
509          if (Base.getOpcode() == ISD::FrameIndex) {
510            int FI = cast<FrameIndexSDNode>(Base)->getIndex();
511            Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
512          }
513          OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
514          return true;
515        }
516      }
517    }
518  }
519
520  return false;
521}
522
523bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op,
524                                           SDValue N,
525                                           SDValue &BaseReg,
526                                           SDValue &Opc) {
527  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
528
529  // Don't match base register only case. That is matched to a separate
530  // lower complexity pattern with explicit register operand.
531  if (ShOpcVal == ARM_AM::no_shift) return false;
532
533  BaseReg = N.getOperand(0);
534  unsigned ShImmVal = 0;
535  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1)))
536    ShImmVal = RHS->getZExtValue() & 31;
537  else
538    return false;
539
540  Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
541
542  return true;
543}
544
545bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
546                                              SDValue N,
547                                              SDValue &BaseReg,
548                                              SDValue &ShReg,
549                                              SDValue &Opc) {
550  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
551
552  // Don't match base register only case. That is matched to a separate
553  // lower complexity pattern with explicit register operand.
554  if (ShOpcVal == ARM_AM::no_shift) return false;
555
556  BaseReg = N.getOperand(0);
557  unsigned ShImmVal = 0;
558  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
559    ShReg = CurDAG->getRegister(0, MVT::i32);
560    ShImmVal = RHS->getZExtValue() & 31;
561  } else {
562    ShReg = N.getOperand(1);
563  }
564  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
565                                  MVT::i32);
566  return true;
567}
568
569/// getAL - Returns a ARMCC::AL immediate node.
570static inline SDValue getAL(SelectionDAG *CurDAG) {
571  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
572}
573
574
575SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
576  SDNode *N = Op.getNode();
577  DebugLoc dl = N->getDebugLoc();
578
579  if (N->isMachineOpcode())
580    return NULL;   // Already selected.
581
582  switch (N->getOpcode()) {
583  default: break;
584  case ISD::Constant: {
585    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
586    bool UseCP = true;
587    if (Subtarget->isThumb()) {
588      if (Subtarget->hasThumb2())
589        // Thumb2 has the MOVT instruction, so all immediates can
590        // be done with MOV + MOVT, at worst.
591        UseCP = 0;
592      else
593        UseCP = (Val > 255 &&                          // MOV
594                 ~Val > 255 &&                         // MOV + MVN
595                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
596    } else
597      UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
598               ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
599               !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
600    if (UseCP) {
601      SDValue CPIdx =
602        CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
603                                      TLI.getPointerTy());
604
605      SDNode *ResNode;
606      if (Subtarget->isThumb())
607        ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
608                                        CPIdx, CurDAG->getEntryNode());
609      else {
610        SDValue Ops[] = {
611          CPIdx,
612          CurDAG->getRegister(0, MVT::i32),
613          CurDAG->getTargetConstant(0, MVT::i32),
614          getAL(CurDAG),
615          CurDAG->getRegister(0, MVT::i32),
616          CurDAG->getEntryNode()
617        };
618        ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
619                                      Ops, 6);
620      }
621      ReplaceUses(Op, SDValue(ResNode, 0));
622      return NULL;
623    }
624
625    // Other cases are autogenerated.
626    break;
627  }
628  case ISD::FrameIndex: {
629    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
630    int FI = cast<FrameIndexSDNode>(N)->getIndex();
631    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
632    if (Subtarget->isThumb()) {
633      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
634                                  CurDAG->getTargetConstant(0, MVT::i32));
635    } else {
636      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
637                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
638                          CurDAG->getRegister(0, MVT::i32) };
639      return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
640    }
641  }
642  case ISD::ADD: {
643    if (!Subtarget->isThumb())
644      break;
645    // Select add sp, c to tADDhirr.
646    SDValue N0 = Op.getOperand(0);
647    SDValue N1 = Op.getOperand(1);
648    RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
649    RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
650    if (LHSR && LHSR->getReg() == ARM::SP) {
651      std::swap(N0, N1);
652      std::swap(LHSR, RHSR);
653    }
654    if (RHSR && RHSR->getReg() == ARM::SP) {
655      SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
656                                  Op.getValueType(), N0, N0), 0);
657      return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
658    }
659    break;
660  }
661  case ISD::MUL:
662    if (Subtarget->isThumb())
663      break;
664    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
665      unsigned RHSV = C->getZExtValue();
666      if (!RHSV) break;
667      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
668        SDValue V = Op.getOperand(0);
669        unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
670        SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
671                            CurDAG->getTargetConstant(ShImm, MVT::i32),
672                            getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
673                            CurDAG->getRegister(0, MVT::i32) };
674        return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
675      }
676      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
677        SDValue V = Op.getOperand(0);
678        unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
679        SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
680                            CurDAG->getTargetConstant(ShImm, MVT::i32),
681                            getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
682                            CurDAG->getRegister(0, MVT::i32) };
683        return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
684      }
685    }
686    break;
687  case ARMISD::FMRRD:
688    return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
689                                 Op.getOperand(0), getAL(CurDAG),
690                                 CurDAG->getRegister(0, MVT::i32));
691  case ISD::UMUL_LOHI: {
692    SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
693                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
694                        CurDAG->getRegister(0, MVT::i32) };
695    return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
696  }
697  case ISD::SMUL_LOHI: {
698    SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
699                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
700                        CurDAG->getRegister(0, MVT::i32) };
701    return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
702  }
703  case ISD::LOAD: {
704    LoadSDNode *LD = cast<LoadSDNode>(Op);
705    ISD::MemIndexedMode AM = LD->getAddressingMode();
706    MVT LoadedVT = LD->getMemoryVT();
707    if (AM != ISD::UNINDEXED) {
708      SDValue Offset, AMOpc;
709      bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
710      unsigned Opcode = 0;
711      bool Match = false;
712      if (LoadedVT == MVT::i32 &&
713          SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
714        Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
715        Match = true;
716      } else if (LoadedVT == MVT::i16 &&
717                 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
718        Match = true;
719        Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
720          ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
721          : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
722      } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
723        if (LD->getExtensionType() == ISD::SEXTLOAD) {
724          if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
725            Match = true;
726            Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
727          }
728        } else {
729          if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
730            Match = true;
731            Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
732          }
733        }
734      }
735
736      if (Match) {
737        SDValue Chain = LD->getChain();
738        SDValue Base = LD->getBasePtr();
739        SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
740                           CurDAG->getRegister(0, MVT::i32), Chain };
741        return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32,
742                                     MVT::Other, Ops, 6);
743      }
744    }
745    // Other cases are autogenerated.
746    break;
747  }
748  case ARMISD::BRCOND: {
749    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
750    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
751    // Pattern complexity = 6  cost = 1  size = 0
752
753    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
754    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
755    // Pattern complexity = 6  cost = 1  size = 0
756
757    unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
758    SDValue Chain = Op.getOperand(0);
759    SDValue N1 = Op.getOperand(1);
760    SDValue N2 = Op.getOperand(2);
761    SDValue N3 = Op.getOperand(3);
762    SDValue InFlag = Op.getOperand(4);
763    assert(N1.getOpcode() == ISD::BasicBlock);
764    assert(N2.getOpcode() == ISD::Constant);
765    assert(N3.getOpcode() == ISD::Register);
766
767    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
768                               cast<ConstantSDNode>(N2)->getZExtValue()),
769                               MVT::i32);
770    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
771    SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
772                                            MVT::Flag, Ops, 5);
773    Chain = SDValue(ResNode, 0);
774    if (Op.getNode()->getNumValues() == 2) {
775      InFlag = SDValue(ResNode, 1);
776      ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
777    }
778    ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
779    return NULL;
780  }
781  case ARMISD::CMOV: {
782    bool isThumb = Subtarget->isThumb();
783    MVT VT = Op.getValueType();
784    SDValue N0 = Op.getOperand(0);
785    SDValue N1 = Op.getOperand(1);
786    SDValue N2 = Op.getOperand(2);
787    SDValue N3 = Op.getOperand(3);
788    SDValue InFlag = Op.getOperand(4);
789    assert(N2.getOpcode() == ISD::Constant);
790    assert(N3.getOpcode() == ISD::Register);
791
792    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
793    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
794    // Pattern complexity = 18  cost = 1  size = 0
795    SDValue CPTmp0;
796    SDValue CPTmp1;
797    SDValue CPTmp2;
798    if (!isThumb && VT == MVT::i32 &&
799        SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
800      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
801                               cast<ConstantSDNode>(N2)->getZExtValue()),
802                               MVT::i32);
803      SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
804      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
805    }
806
807    // Pattern: (ARMcmov:i32 GPR:i32:$false,
808    //             (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
809    //             (imm:i32):$cc)
810    // Emits: (MOVCCi:i32 GPR:i32:$false,
811    //           (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
812    // Pattern complexity = 10  cost = 1  size = 0
813    if (VT == MVT::i32 &&
814        N3.getOpcode() == ISD::Constant &&
815        Predicate_so_imm(N3.getNode())) {
816      SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
817                               cast<ConstantSDNode>(N1)->getZExtValue()),
818                               MVT::i32);
819      Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
820      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
821                               cast<ConstantSDNode>(N2)->getZExtValue()),
822                               MVT::i32);
823      SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
824      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
825    }
826
827    // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
828    // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
829    // Pattern complexity = 6  cost = 1  size = 0
830    //
831    // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
832    // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
833    // Pattern complexity = 6  cost = 11  size = 0
834    //
835    // Also FCPYScc and FCPYDcc.
836    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
837                               cast<ConstantSDNode>(N2)->getZExtValue()),
838                               MVT::i32);
839    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
840    unsigned Opc = 0;
841    switch (VT.getSimpleVT()) {
842    default: assert(false && "Illegal conditional move type!");
843      break;
844    case MVT::i32:
845      Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
846      break;
847    case MVT::f32:
848      Opc = ARM::FCPYScc;
849      break;
850    case MVT::f64:
851      Opc = ARM::FCPYDcc;
852      break;
853    }
854    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
855  }
856  case ARMISD::CNEG: {
857    MVT VT = Op.getValueType();
858    SDValue N0 = Op.getOperand(0);
859    SDValue N1 = Op.getOperand(1);
860    SDValue N2 = Op.getOperand(2);
861    SDValue N3 = Op.getOperand(3);
862    SDValue InFlag = Op.getOperand(4);
863    assert(N2.getOpcode() == ISD::Constant);
864    assert(N3.getOpcode() == ISD::Register);
865
866    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
867                               cast<ConstantSDNode>(N2)->getZExtValue()),
868                               MVT::i32);
869    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
870    unsigned Opc = 0;
871    switch (VT.getSimpleVT()) {
872    default: assert(false && "Illegal conditional move type!");
873      break;
874    case MVT::f32:
875      Opc = ARM::FNEGScc;
876      break;
877    case MVT::f64:
878      Opc = ARM::FNEGDcc;
879      break;
880    }
881    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
882  }
883
884  case ISD::DECLARE: {
885    SDValue Chain = Op.getOperand(0);
886    SDValue N1 = Op.getOperand(1);
887    SDValue N2 = Op.getOperand(2);
888    FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
889    // FIXME: handle VLAs.
890    if (!FINode) {
891      ReplaceUses(Op.getValue(0), Chain);
892      return NULL;
893    }
894    if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
895      N2 = N2.getOperand(0);
896    LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
897    if (!Ld) {
898      ReplaceUses(Op.getValue(0), Chain);
899      return NULL;
900    }
901    SDValue BasePtr = Ld->getBasePtr();
902    assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
903           isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
904           "llvm.dbg.variable should be a constantpool node");
905    ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
906    GlobalValue *GV = 0;
907    if (CP->isMachineConstantPoolEntry()) {
908      ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
909      GV = ACPV->getGV();
910    } else
911      GV = dyn_cast<GlobalValue>(CP->getConstVal());
912    if (!GV) {
913      ReplaceUses(Op.getValue(0), Chain);
914      return NULL;
915    }
916
917    SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
918                                               TLI.getPointerTy());
919    SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
920    SDValue Ops[] = { Tmp1, Tmp2, Chain };
921    return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
922                                 MVT::Other, Ops, 3);
923  }
924
925  case ISD::CONCAT_VECTORS: {
926    MVT VT = Op.getValueType();
927    assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
928           "unexpected CONCAT_VECTORS");
929    SDValue N0 = Op.getOperand(0);
930    SDValue N1 = Op.getOperand(1);
931    SDNode *Result =
932      CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
933    if (N0.getOpcode() != ISD::UNDEF)
934      Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
935                                     SDValue(Result, 0), N0,
936                                     CurDAG->getTargetConstant(arm_dsubreg_0,
937                                                               MVT::i32));
938    if (N1.getOpcode() != ISD::UNDEF)
939      Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
940                                     SDValue(Result, 0), N1,
941                                     CurDAG->getTargetConstant(arm_dsubreg_1,
942                                                               MVT::i32));
943    return Result;
944  }
945
946  case ISD::VECTOR_SHUFFLE: {
947    MVT VT = Op.getValueType();
948
949    // Match 128-bit splat to VDUPLANEQ.  (This could be done with a Pat in
950    // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
951    // transformed first into a lane number and then to both a subregister
952    // index and an adjusted lane number.)  If the source operand is a
953    // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
954    ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
955    if (VT.is128BitVector() && SVOp->isSplat() &&
956        Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
957        Op.getOperand(1).getOpcode() == ISD::UNDEF) {
958      unsigned LaneVal = SVOp->getSplatIndex();
959
960      MVT HalfVT;
961      unsigned Opc = 0;
962      switch (VT.getVectorElementType().getSimpleVT()) {
963      default: assert(false && "unhandled VDUP splat type");
964      case MVT::i8:  Opc = ARM::VDUPLN8q;  HalfVT = MVT::v8i8; break;
965      case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
966      case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
967      case MVT::f32: Opc = ARM::VDUPLNfq;  HalfVT = MVT::v2f32; break;
968      }
969
970      // The source operand needs to be changed to a subreg of the original
971      // 128-bit operand, and the lane number needs to be adjusted accordingly.
972      unsigned NumElts = VT.getVectorNumElements() / 2;
973      unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
974      SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
975      SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
976      SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
977                                             dl, HalfVT, N->getOperand(0), SR);
978      return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
979    }
980
981    break;
982  }
983  }
984
985  return SelectCode(Op);
986}
987
988bool ARMDAGToDAGISel::
989SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
990                             std::vector<SDValue> &OutOps) {
991  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
992
993  SDValue Base, Offset, Opc;
994  if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
995    return true;
996
997  OutOps.push_back(Base);
998  OutOps.push_back(Offset);
999  OutOps.push_back(Opc);
1000  return false;
1001}
1002
1003/// createARMISelDag - This pass converts a legalized DAG into a
1004/// ARM-specific DAG, ready for instruction scheduling.
1005///
1006FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
1007  return new ARMDAGToDAGISel(TM);
1008}
1009