ARMISelDAGToDAG.cpp revision 5e47a9a6e46bd271eba058fb831da1a1edf8707c 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMConstantPoolValue.h"
17#include "ARMISelLowering.h"
18#include "ARMTargetMachine.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/CodeGen/SelectionDAGISel.h"
29#include "llvm/Target/TargetLowering.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Debug.h"
33using namespace llvm;
34
35static const unsigned arm_dsubreg_0 = 5;
36static const unsigned arm_dsubreg_1 = 6;
37
38//===--------------------------------------------------------------------===//
39/// ARMDAGToDAGISel - ARM specific code to select ARM machine
40/// instructions for SelectionDAG operations.
41///
42namespace {
43class ARMDAGToDAGISel : public SelectionDAGISel {
44  ARMBaseTargetMachine &TM;
45
46  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47  /// make the right decision when generating code for different targets.
48  const ARMSubtarget *Subtarget;
49
50public:
51  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
52    : SelectionDAGISel(tm), TM(tm),
53    Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
54  }
55
56  virtual const char *getPassName() const {
57    return "ARM Instruction Selection";
58  }
59
60 /// getI32Imm - Return a target constant with the specified value, of type i32.
61  inline SDValue getI32Imm(unsigned Imm) {
62    return CurDAG->getTargetConstant(Imm, MVT::i32);
63  }
64
65  SDNode *Select(SDValue Op);
66  virtual void InstructionSelect();
67  bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
68                               SDValue &B, SDValue &C);
69  bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
70                       SDValue &Offset, SDValue &Opc);
71  bool SelectAddrMode2Offset(SDValue Op, SDValue N,
72                             SDValue &Offset, SDValue &Opc);
73  bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
74                       SDValue &Offset, SDValue &Opc);
75  bool SelectAddrMode3Offset(SDValue Op, SDValue N,
76                             SDValue &Offset, SDValue &Opc);
77  bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
78                       SDValue &Offset);
79
80  bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
81                         SDValue &Label);
82
83  bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
84                             SDValue &Offset);
85  bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
86                              SDValue &Base, SDValue &OffImm,
87                              SDValue &Offset);
88  bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
89                             SDValue &OffImm, SDValue &Offset);
90  bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
91                             SDValue &OffImm, SDValue &Offset);
92  bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
93                             SDValue &OffImm, SDValue &Offset);
94  bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
95                             SDValue &OffImm);
96
97  bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
98                                 SDValue &BaseReg, SDValue &Opc);
99  bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
100                             SDValue &OffImm);
101  bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
102                            SDValue &OffImm);
103  bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
104                             SDValue &OffReg, SDValue &ShImm);
105
106
107  // Include the pieces autogenerated from the target description.
108#include "ARMGenDAGISel.inc"
109
110private:
111    /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
112    /// inline asm expressions.
113    virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
114                                              char ConstraintCode,
115                                              std::vector<SDValue> &OutOps);
116};
117}
118
119void ARMDAGToDAGISel::InstructionSelect() {
120  DEBUG(BB->dump());
121
122  SelectRoot(*CurDAG);
123  CurDAG->RemoveDeadNodes();
124}
125
126bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
127                                              SDValue N,
128                                              SDValue &BaseReg,
129                                              SDValue &ShReg,
130                                              SDValue &Opc) {
131  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
132
133  // Don't match base register only case. That is matched to a separate
134  // lower complexity pattern with explicit register operand.
135  if (ShOpcVal == ARM_AM::no_shift) return false;
136
137  BaseReg = N.getOperand(0);
138  unsigned ShImmVal = 0;
139  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
140    ShReg = CurDAG->getRegister(0, MVT::i32);
141    ShImmVal = RHS->getZExtValue() & 31;
142  } else {
143    ShReg = N.getOperand(1);
144  }
145  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
146                                  MVT::i32);
147  return true;
148}
149
150bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
151                                      SDValue &Base, SDValue &Offset,
152                                      SDValue &Opc) {
153  if (N.getOpcode() == ISD::MUL) {
154    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
155      // X * [3,5,9] -> X + X * [2,4,8] etc.
156      int RHSC = (int)RHS->getZExtValue();
157      if (RHSC & 1) {
158        RHSC = RHSC & ~1;
159        ARM_AM::AddrOpc AddSub = ARM_AM::add;
160        if (RHSC < 0) {
161          AddSub = ARM_AM::sub;
162          RHSC = - RHSC;
163        }
164        if (isPowerOf2_32(RHSC)) {
165          unsigned ShAmt = Log2_32(RHSC);
166          Base = Offset = N.getOperand(0);
167          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
168                                                            ARM_AM::lsl),
169                                          MVT::i32);
170          return true;
171        }
172      }
173    }
174  }
175
176  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
177    Base = N;
178    if (N.getOpcode() == ISD::FrameIndex) {
179      int FI = cast<FrameIndexSDNode>(N)->getIndex();
180      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
181    } else if (N.getOpcode() == ARMISD::Wrapper) {
182      Base = N.getOperand(0);
183    }
184    Offset = CurDAG->getRegister(0, MVT::i32);
185    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
186                                                      ARM_AM::no_shift),
187                                    MVT::i32);
188    return true;
189  }
190
191  // Match simple R +/- imm12 operands.
192  if (N.getOpcode() == ISD::ADD)
193    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
194      int RHSC = (int)RHS->getZExtValue();
195      if ((RHSC >= 0 && RHSC < 0x1000) ||
196          (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
197        Base = N.getOperand(0);
198        if (Base.getOpcode() == ISD::FrameIndex) {
199          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
200          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
201        }
202        Offset = CurDAG->getRegister(0, MVT::i32);
203
204        ARM_AM::AddrOpc AddSub = ARM_AM::add;
205        if (RHSC < 0) {
206          AddSub = ARM_AM::sub;
207          RHSC = - RHSC;
208        }
209        Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
210                                                          ARM_AM::no_shift),
211                                        MVT::i32);
212        return true;
213      }
214    }
215
216  // Otherwise this is R +/- [possibly shifted] R
217  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
218  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
219  unsigned ShAmt = 0;
220
221  Base   = N.getOperand(0);
222  Offset = N.getOperand(1);
223
224  if (ShOpcVal != ARM_AM::no_shift) {
225    // Check to see if the RHS of the shift is a constant, if not, we can't fold
226    // it.
227    if (ConstantSDNode *Sh =
228           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
229      ShAmt = Sh->getZExtValue();
230      Offset = N.getOperand(1).getOperand(0);
231    } else {
232      ShOpcVal = ARM_AM::no_shift;
233    }
234  }
235
236  // Try matching (R shl C) + (R).
237  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
238    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
239    if (ShOpcVal != ARM_AM::no_shift) {
240      // Check to see if the RHS of the shift is a constant, if not, we can't
241      // fold it.
242      if (ConstantSDNode *Sh =
243          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
244        ShAmt = Sh->getZExtValue();
245        Offset = N.getOperand(0).getOperand(0);
246        Base = N.getOperand(1);
247      } else {
248        ShOpcVal = ARM_AM::no_shift;
249      }
250    }
251  }
252
253  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
254                                  MVT::i32);
255  return true;
256}
257
258bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
259                                            SDValue &Offset, SDValue &Opc) {
260  unsigned Opcode = Op.getOpcode();
261  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
262    ? cast<LoadSDNode>(Op)->getAddressingMode()
263    : cast<StoreSDNode>(Op)->getAddressingMode();
264  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
265    ? ARM_AM::add : ARM_AM::sub;
266  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
267    int Val = (int)C->getZExtValue();
268    if (Val >= 0 && Val < 0x1000) { // 12 bits.
269      Offset = CurDAG->getRegister(0, MVT::i32);
270      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
271                                                        ARM_AM::no_shift),
272                                      MVT::i32);
273      return true;
274    }
275  }
276
277  Offset = N;
278  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
279  unsigned ShAmt = 0;
280  if (ShOpcVal != ARM_AM::no_shift) {
281    // Check to see if the RHS of the shift is a constant, if not, we can't fold
282    // it.
283    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
284      ShAmt = Sh->getZExtValue();
285      Offset = N.getOperand(0);
286    } else {
287      ShOpcVal = ARM_AM::no_shift;
288    }
289  }
290
291  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
292                                  MVT::i32);
293  return true;
294}
295
296
297bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
298                                      SDValue &Base, SDValue &Offset,
299                                      SDValue &Opc) {
300  if (N.getOpcode() == ISD::SUB) {
301    // X - C  is canonicalize to X + -C, no need to handle it here.
302    Base = N.getOperand(0);
303    Offset = N.getOperand(1);
304    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
305    return true;
306  }
307
308  if (N.getOpcode() != ISD::ADD) {
309    Base = N;
310    if (N.getOpcode() == ISD::FrameIndex) {
311      int FI = cast<FrameIndexSDNode>(N)->getIndex();
312      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
313    }
314    Offset = CurDAG->getRegister(0, MVT::i32);
315    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
316    return true;
317  }
318
319  // If the RHS is +/- imm8, fold into addr mode.
320  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
321    int RHSC = (int)RHS->getZExtValue();
322    if ((RHSC >= 0 && RHSC < 256) ||
323        (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
324      Base = N.getOperand(0);
325      if (Base.getOpcode() == ISD::FrameIndex) {
326        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
327        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
328      }
329      Offset = CurDAG->getRegister(0, MVT::i32);
330
331      ARM_AM::AddrOpc AddSub = ARM_AM::add;
332      if (RHSC < 0) {
333        AddSub = ARM_AM::sub;
334        RHSC = - RHSC;
335      }
336      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
337      return true;
338    }
339  }
340
341  Base = N.getOperand(0);
342  Offset = N.getOperand(1);
343  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
344  return true;
345}
346
347bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
348                                            SDValue &Offset, SDValue &Opc) {
349  unsigned Opcode = Op.getOpcode();
350  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
351    ? cast<LoadSDNode>(Op)->getAddressingMode()
352    : cast<StoreSDNode>(Op)->getAddressingMode();
353  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
354    ? ARM_AM::add : ARM_AM::sub;
355  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
356    int Val = (int)C->getZExtValue();
357    if (Val >= 0 && Val < 256) {
358      Offset = CurDAG->getRegister(0, MVT::i32);
359      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
360      return true;
361    }
362  }
363
364  Offset = N;
365  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
366  return true;
367}
368
369
370bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
371                                      SDValue &Base, SDValue &Offset) {
372  if (N.getOpcode() != ISD::ADD) {
373    Base = N;
374    if (N.getOpcode() == ISD::FrameIndex) {
375      int FI = cast<FrameIndexSDNode>(N)->getIndex();
376      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
377    } else if (N.getOpcode() == ARMISD::Wrapper) {
378      Base = N.getOperand(0);
379    }
380    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
381                                       MVT::i32);
382    return true;
383  }
384
385  // If the RHS is +/- imm8, fold into addr mode.
386  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
387    int RHSC = (int)RHS->getZExtValue();
388    if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied by 4.
389      RHSC >>= 2;
390      if ((RHSC >= 0 && RHSC < 256) ||
391          (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
392        Base = N.getOperand(0);
393        if (Base.getOpcode() == ISD::FrameIndex) {
394          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
395          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
396        }
397
398        ARM_AM::AddrOpc AddSub = ARM_AM::add;
399        if (RHSC < 0) {
400          AddSub = ARM_AM::sub;
401          RHSC = - RHSC;
402        }
403        Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
404                                           MVT::i32);
405        return true;
406      }
407    }
408  }
409
410  Base = N;
411  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
412                                     MVT::i32);
413  return true;
414}
415
416bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
417                                        SDValue &Offset, SDValue &Label) {
418  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
419    Offset = N.getOperand(0);
420    SDValue N1 = N.getOperand(1);
421    Label  = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
422                                       MVT::i32);
423    return true;
424  }
425  return false;
426}
427
428bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
429                                            SDValue &Base, SDValue &Offset){
430  // FIXME dl should come from the parent load or store, not the address
431  DebugLoc dl = Op.getDebugLoc();
432  if (N.getOpcode() != ISD::ADD) {
433    Base = N;
434    // We must materialize a zero in a reg! Returning a constant here
435    // wouldn't work without additional code to position the node within
436    // ISel's topological ordering in a place where ISel will process it
437    // normally.  Instead, just explicitly issue a tMOVri8 node!
438    Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32,
439                                    CurDAG->getTargetConstant(0, MVT::i32)), 0);
440    return true;
441  }
442
443  Base = N.getOperand(0);
444  Offset = N.getOperand(1);
445  return true;
446}
447
448bool
449ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
450                                        unsigned Scale, SDValue &Base,
451                                        SDValue &OffImm, SDValue &Offset) {
452  if (Scale == 4) {
453    SDValue TmpBase, TmpOffImm;
454    if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
455      return false;  // We want to select tLDRspi / tSTRspi instead.
456    if (N.getOpcode() == ARMISD::Wrapper &&
457        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
458      return false;  // We want to select tLDRpci instead.
459  }
460
461  if (N.getOpcode() != ISD::ADD) {
462    Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
463    Offset = CurDAG->getRegister(0, MVT::i32);
464    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
465    return true;
466  }
467
468  // Thumb does not have [sp, r] address mode.
469  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
470  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
471  if ((LHSR && LHSR->getReg() == ARM::SP) ||
472      (RHSR && RHSR->getReg() == ARM::SP)) {
473    Base = N;
474    Offset = CurDAG->getRegister(0, MVT::i32);
475    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
476    return true;
477  }
478
479  // If the RHS is + imm5 * scale, fold into addr mode.
480  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
481    int RHSC = (int)RHS->getZExtValue();
482    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
483      RHSC /= Scale;
484      if (RHSC >= 0 && RHSC < 32) {
485        Base = N.getOperand(0);
486        Offset = CurDAG->getRegister(0, MVT::i32);
487        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
488        return true;
489      }
490    }
491  }
492
493  Base = N.getOperand(0);
494  Offset = N.getOperand(1);
495  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
496  return true;
497}
498
499bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
500                                            SDValue &Base, SDValue &OffImm,
501                                            SDValue &Offset) {
502  return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
503}
504
505bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
506                                            SDValue &Base, SDValue &OffImm,
507                                            SDValue &Offset) {
508  return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
509}
510
511bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
512                                            SDValue &Base, SDValue &OffImm,
513                                            SDValue &Offset) {
514  return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
515}
516
517bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
518                                           SDValue &Base, SDValue &OffImm) {
519  if (N.getOpcode() == ISD::FrameIndex) {
520    int FI = cast<FrameIndexSDNode>(N)->getIndex();
521    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
522    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
523    return true;
524  }
525
526  if (N.getOpcode() != ISD::ADD)
527    return false;
528
529  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
530  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
531      (LHSR && LHSR->getReg() == ARM::SP)) {
532    // If the RHS is + imm8 * scale, fold into addr mode.
533    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
534      int RHSC = (int)RHS->getZExtValue();
535      if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied.
536        RHSC >>= 2;
537        if (RHSC >= 0 && RHSC < 256) {
538          Base = N.getOperand(0);
539          if (Base.getOpcode() == ISD::FrameIndex) {
540            int FI = cast<FrameIndexSDNode>(Base)->getIndex();
541            Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
542          }
543          OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
544          return true;
545        }
546      }
547    }
548  }
549
550  return false;
551}
552
553bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
554                                                SDValue &BaseReg,
555                                                SDValue &Opc) {
556  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
557
558  // Don't match base register only case. That is matched to a separate
559  // lower complexity pattern with explicit register operand.
560  if (ShOpcVal == ARM_AM::no_shift) return false;
561
562  BaseReg = N.getOperand(0);
563  unsigned ShImmVal = 0;
564  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
565    ShImmVal = RHS->getZExtValue() & 31;
566    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
567    return true;
568  }
569
570  return false;
571}
572
573bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
574                                            SDValue &Base, SDValue &OffImm) {
575  // Match simple R + imm12 operands.
576  if (N.getOpcode() != ISD::ADD)
577    return false;
578
579  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
580    int RHSC = (int)RHS->getZExtValue();
581    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
582      Base   = N.getOperand(0);
583      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
584      return true;
585    }
586  }
587
588  return false;
589}
590
591bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
592                                           SDValue &Base, SDValue &OffImm) {
593  if (N.getOpcode() == ISD::ADD) {
594    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
595      int RHSC = (int)RHS->getZExtValue();
596      if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
597        Base   = N.getOperand(0);
598        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
599        return true;
600      }
601    }
602  } else if (N.getOpcode() == ISD::SUB) {
603    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
604      int RHSC = (int)RHS->getZExtValue();
605      if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
606        Base   = N.getOperand(0);
607        OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
608        return true;
609      }
610    }
611  }
612
613  return false;
614}
615
616bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
617                                            SDValue &Base,
618                                            SDValue &OffReg, SDValue &ShImm) {
619  // Base only.
620  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
621    Base = N;
622    if (N.getOpcode() == ISD::FrameIndex) {
623      int FI = cast<FrameIndexSDNode>(N)->getIndex();
624      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
625    } else if (N.getOpcode() == ARMISD::Wrapper) {
626      Base = N.getOperand(0);
627      if (Base.getOpcode() == ISD::TargetConstantPool)
628        return false;  // We want to select t2LDRpci instead.
629    }
630    OffReg = CurDAG->getRegister(0, MVT::i32);
631    ShImm  = CurDAG->getTargetConstant(0, MVT::i32);
632    return true;
633  }
634
635  // Look for (R + R) or (R + (R << [1,2,3])).
636  unsigned ShAmt = 0;
637  Base   = N.getOperand(0);
638  OffReg = N.getOperand(1);
639
640  // Swap if it is ((R << c) + R).
641  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
642  if (ShOpcVal != ARM_AM::lsl) {
643    ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
644    if (ShOpcVal == ARM_AM::lsl)
645      std::swap(Base, OffReg);
646  }
647
648  if (ShOpcVal == ARM_AM::lsl) {
649    // Check to see if the RHS of the shift is a constant, if not, we can't fold
650    // it.
651    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
652      ShAmt = Sh->getZExtValue();
653      if (ShAmt >= 4) {
654        ShAmt = 0;
655        ShOpcVal = ARM_AM::no_shift;
656      } else
657        OffReg = OffReg.getOperand(0);
658    } else {
659      ShOpcVal = ARM_AM::no_shift;
660    }
661  } else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
662             SelectT2AddrModeImm8 (Op, N, Base, ShImm))
663    // Don't match if it's possible to match to one of the r +/- imm cases.
664    return false;
665
666  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
667
668  return true;
669}
670
671//===--------------------------------------------------------------------===//
672
673/// getAL - Returns a ARMCC::AL immediate node.
674static inline SDValue getAL(SelectionDAG *CurDAG) {
675  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
676}
677
678
679SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
680  SDNode *N = Op.getNode();
681  DebugLoc dl = N->getDebugLoc();
682
683  if (N->isMachineOpcode())
684    return NULL;   // Already selected.
685
686  switch (N->getOpcode()) {
687  default: break;
688  case ISD::Constant: {
689    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
690    bool UseCP = true;
691    if (Subtarget->isThumb()) {
692      if (Subtarget->hasThumb2())
693        // Thumb2 has the MOVT instruction, so all immediates can
694        // be done with MOV + MOVT, at worst.
695        UseCP = 0;
696      else
697        UseCP = (Val > 255 &&                          // MOV
698                 ~Val > 255 &&                         // MOV + MVN
699                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
700    } else
701      UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
702               ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
703               !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
704    if (UseCP) {
705      SDValue CPIdx =
706        CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
707                                      TLI.getPointerTy());
708
709      SDNode *ResNode;
710      if (Subtarget->isThumb())
711        ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
712                                        CPIdx, CurDAG->getEntryNode());
713      else {
714        SDValue Ops[] = {
715          CPIdx,
716          CurDAG->getRegister(0, MVT::i32),
717          CurDAG->getTargetConstant(0, MVT::i32),
718          getAL(CurDAG),
719          CurDAG->getRegister(0, MVT::i32),
720          CurDAG->getEntryNode()
721        };
722        ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
723                                      Ops, 6);
724      }
725      ReplaceUses(Op, SDValue(ResNode, 0));
726      return NULL;
727    }
728
729    // Other cases are autogenerated.
730    break;
731  }
732  case ISD::FrameIndex: {
733    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
734    int FI = cast<FrameIndexSDNode>(N)->getIndex();
735    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
736    if (Subtarget->isThumb()) {
737      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
738                                  CurDAG->getTargetConstant(0, MVT::i32));
739    } else {
740      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
741                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
742                          CurDAG->getRegister(0, MVT::i32) };
743      return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
744    }
745  }
746  case ISD::ADD: {
747    if (!Subtarget->isThumb())
748      break;
749    // Select add sp, c to tADDhirr.
750    SDValue N0 = Op.getOperand(0);
751    SDValue N1 = Op.getOperand(1);
752    RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
753    RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
754    if (LHSR && LHSR->getReg() == ARM::SP) {
755      std::swap(N0, N1);
756      std::swap(LHSR, RHSR);
757    }
758    if (RHSR && RHSR->getReg() == ARM::SP) {
759      SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
760                                  Op.getValueType(), N0, N0), 0);
761      return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
762    }
763    break;
764  }
765  case ISD::MUL:
766    if (Subtarget->isThumb())
767      break;
768    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
769      unsigned RHSV = C->getZExtValue();
770      if (!RHSV) break;
771      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
772        SDValue V = Op.getOperand(0);
773        unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
774        SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
775                            CurDAG->getTargetConstant(ShImm, MVT::i32),
776                            getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
777                            CurDAG->getRegister(0, MVT::i32) };
778        return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
779      }
780      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
781        SDValue V = Op.getOperand(0);
782        unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
783        SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
784                            CurDAG->getTargetConstant(ShImm, MVT::i32),
785                            getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
786                            CurDAG->getRegister(0, MVT::i32) };
787        return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
788      }
789    }
790    break;
791  case ARMISD::FMRRD:
792    return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
793                                 Op.getOperand(0), getAL(CurDAG),
794                                 CurDAG->getRegister(0, MVT::i32));
795  case ISD::UMUL_LOHI: {
796    SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
797                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
798                        CurDAG->getRegister(0, MVT::i32) };
799    return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
800  }
801  case ISD::SMUL_LOHI: {
802    SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
803                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
804                        CurDAG->getRegister(0, MVT::i32) };
805    return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
806  }
807  case ISD::LOAD: {
808    LoadSDNode *LD = cast<LoadSDNode>(Op);
809    ISD::MemIndexedMode AM = LD->getAddressingMode();
810    MVT LoadedVT = LD->getMemoryVT();
811    if (AM != ISD::UNINDEXED) {
812      SDValue Offset, AMOpc;
813      bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
814      unsigned Opcode = 0;
815      bool Match = false;
816      if (LoadedVT == MVT::i32 &&
817          SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
818        Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
819        Match = true;
820      } else if (LoadedVT == MVT::i16 &&
821                 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
822        Match = true;
823        Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
824          ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
825          : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
826      } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
827        if (LD->getExtensionType() == ISD::SEXTLOAD) {
828          if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
829            Match = true;
830            Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
831          }
832        } else {
833          if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
834            Match = true;
835            Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
836          }
837        }
838      }
839
840      if (Match) {
841        SDValue Chain = LD->getChain();
842        SDValue Base = LD->getBasePtr();
843        SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
844                           CurDAG->getRegister(0, MVT::i32), Chain };
845        return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32,
846                                     MVT::Other, Ops, 6);
847      }
848    }
849    // Other cases are autogenerated.
850    break;
851  }
852  case ARMISD::BRCOND: {
853    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
854    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
855    // Pattern complexity = 6  cost = 1  size = 0
856
857    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
858    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
859    // Pattern complexity = 6  cost = 1  size = 0
860
861    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
862    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
863    // Pattern complexity = 6  cost = 1  size = 0
864
865    unsigned Opc = Subtarget->isThumb() ?
866      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
867    SDValue Chain = Op.getOperand(0);
868    SDValue N1 = Op.getOperand(1);
869    SDValue N2 = Op.getOperand(2);
870    SDValue N3 = Op.getOperand(3);
871    SDValue InFlag = Op.getOperand(4);
872    assert(N1.getOpcode() == ISD::BasicBlock);
873    assert(N2.getOpcode() == ISD::Constant);
874    assert(N3.getOpcode() == ISD::Register);
875
876    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
877                               cast<ConstantSDNode>(N2)->getZExtValue()),
878                               MVT::i32);
879    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
880    SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
881                                            MVT::Flag, Ops, 5);
882    Chain = SDValue(ResNode, 0);
883    if (Op.getNode()->getNumValues() == 2) {
884      InFlag = SDValue(ResNode, 1);
885      ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
886    }
887    ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
888    return NULL;
889  }
890  case ARMISD::CMOV: {
891    bool isThumb = Subtarget->isThumb();
892    MVT VT = Op.getValueType();
893    SDValue N0 = Op.getOperand(0);
894    SDValue N1 = Op.getOperand(1);
895    SDValue N2 = Op.getOperand(2);
896    SDValue N3 = Op.getOperand(3);
897    SDValue InFlag = Op.getOperand(4);
898    assert(N2.getOpcode() == ISD::Constant);
899    assert(N3.getOpcode() == ISD::Register);
900
901    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
902    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
903    // Pattern complexity = 18  cost = 1  size = 0
904    SDValue CPTmp0;
905    SDValue CPTmp1;
906    SDValue CPTmp2;
907    if (!isThumb && VT == MVT::i32 &&
908        SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
909      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
910                               cast<ConstantSDNode>(N2)->getZExtValue()),
911                               MVT::i32);
912      SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
913      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
914    }
915
916    // Pattern: (ARMcmov:i32 GPR:i32:$false,
917    //             (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
918    //             (imm:i32):$cc)
919    // Emits: (MOVCCi:i32 GPR:i32:$false,
920    //           (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
921    // Pattern complexity = 10  cost = 1  size = 0
922    if (VT == MVT::i32 &&
923        N3.getOpcode() == ISD::Constant &&
924        Predicate_so_imm(N3.getNode())) {
925      SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
926                               cast<ConstantSDNode>(N1)->getZExtValue()),
927                               MVT::i32);
928      Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
929      SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
930                               cast<ConstantSDNode>(N2)->getZExtValue()),
931                               MVT::i32);
932      SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
933      return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
934    }
935
936    // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
937    // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
938    // Pattern complexity = 6  cost = 1  size = 0
939    //
940    // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
941    // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
942    // Pattern complexity = 6  cost = 11  size = 0
943    //
944    // Also FCPYScc and FCPYDcc.
945    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
946                               cast<ConstantSDNode>(N2)->getZExtValue()),
947                               MVT::i32);
948    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
949    unsigned Opc = 0;
950    switch (VT.getSimpleVT()) {
951    default: assert(false && "Illegal conditional move type!");
952      break;
953    case MVT::i32:
954      Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
955      break;
956    case MVT::f32:
957      Opc = ARM::FCPYScc;
958      break;
959    case MVT::f64:
960      Opc = ARM::FCPYDcc;
961      break;
962    }
963    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
964  }
965  case ARMISD::CNEG: {
966    MVT VT = Op.getValueType();
967    SDValue N0 = Op.getOperand(0);
968    SDValue N1 = Op.getOperand(1);
969    SDValue N2 = Op.getOperand(2);
970    SDValue N3 = Op.getOperand(3);
971    SDValue InFlag = Op.getOperand(4);
972    assert(N2.getOpcode() == ISD::Constant);
973    assert(N3.getOpcode() == ISD::Register);
974
975    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
976                               cast<ConstantSDNode>(N2)->getZExtValue()),
977                               MVT::i32);
978    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
979    unsigned Opc = 0;
980    switch (VT.getSimpleVT()) {
981    default: assert(false && "Illegal conditional move type!");
982      break;
983    case MVT::f32:
984      Opc = ARM::FNEGScc;
985      break;
986    case MVT::f64:
987      Opc = ARM::FNEGDcc;
988      break;
989    }
990    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
991  }
992
993  case ISD::DECLARE: {
994    SDValue Chain = Op.getOperand(0);
995    SDValue N1 = Op.getOperand(1);
996    SDValue N2 = Op.getOperand(2);
997    FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
998    // FIXME: handle VLAs.
999    if (!FINode) {
1000      ReplaceUses(Op.getValue(0), Chain);
1001      return NULL;
1002    }
1003    if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
1004      N2 = N2.getOperand(0);
1005    LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
1006    if (!Ld) {
1007      ReplaceUses(Op.getValue(0), Chain);
1008      return NULL;
1009    }
1010    SDValue BasePtr = Ld->getBasePtr();
1011    assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
1012           isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
1013           "llvm.dbg.variable should be a constantpool node");
1014    ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
1015    GlobalValue *GV = 0;
1016    if (CP->isMachineConstantPoolEntry()) {
1017      ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
1018      GV = ACPV->getGV();
1019    } else
1020      GV = dyn_cast<GlobalValue>(CP->getConstVal());
1021    if (!GV) {
1022      ReplaceUses(Op.getValue(0), Chain);
1023      return NULL;
1024    }
1025
1026    SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1027                                               TLI.getPointerTy());
1028    SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1029    SDValue Ops[] = { Tmp1, Tmp2, Chain };
1030    return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1031                                 MVT::Other, Ops, 3);
1032  }
1033
1034  case ISD::CONCAT_VECTORS: {
1035    MVT VT = Op.getValueType();
1036    assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
1037           "unexpected CONCAT_VECTORS");
1038    SDValue N0 = Op.getOperand(0);
1039    SDValue N1 = Op.getOperand(1);
1040    SDNode *Result =
1041      CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
1042    if (N0.getOpcode() != ISD::UNDEF)
1043      Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1044                                     SDValue(Result, 0), N0,
1045                                     CurDAG->getTargetConstant(arm_dsubreg_0,
1046                                                               MVT::i32));
1047    if (N1.getOpcode() != ISD::UNDEF)
1048      Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1049                                     SDValue(Result, 0), N1,
1050                                     CurDAG->getTargetConstant(arm_dsubreg_1,
1051                                                               MVT::i32));
1052    return Result;
1053  }
1054
1055  case ISD::VECTOR_SHUFFLE: {
1056    MVT VT = Op.getValueType();
1057
1058    // Match 128-bit splat to VDUPLANEQ.  (This could be done with a Pat in
1059    // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
1060    // transformed first into a lane number and then to both a subregister
1061    // index and an adjusted lane number.)  If the source operand is a
1062    // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
1063    ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1064    if (VT.is128BitVector() && SVOp->isSplat() &&
1065        Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
1066        Op.getOperand(1).getOpcode() == ISD::UNDEF) {
1067      unsigned LaneVal = SVOp->getSplatIndex();
1068
1069      MVT HalfVT;
1070      unsigned Opc = 0;
1071      switch (VT.getVectorElementType().getSimpleVT()) {
1072      default: assert(false && "unhandled VDUP splat type");
1073      case MVT::i8:  Opc = ARM::VDUPLN8q;  HalfVT = MVT::v8i8; break;
1074      case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
1075      case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
1076      case MVT::f32: Opc = ARM::VDUPLNfq;  HalfVT = MVT::v2f32; break;
1077      }
1078
1079      // The source operand needs to be changed to a subreg of the original
1080      // 128-bit operand, and the lane number needs to be adjusted accordingly.
1081      unsigned NumElts = VT.getVectorNumElements() / 2;
1082      unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
1083      SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
1084      SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
1085      SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
1086                                             dl, HalfVT, N->getOperand(0), SR);
1087      return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
1088    }
1089
1090    break;
1091  }
1092  }
1093
1094  return SelectCode(Op);
1095}
1096
1097bool ARMDAGToDAGISel::
1098SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1099                             std::vector<SDValue> &OutOps) {
1100  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1101
1102  SDValue Base, Offset, Opc;
1103  if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1104    return true;
1105
1106  OutOps.push_back(Base);
1107  OutOps.push_back(Offset);
1108  OutOps.push_back(Opc);
1109  return false;
1110}
1111
1112/// createARMISelDag - This pass converts a legalized DAG into a
1113/// ARM-specific DAG, ready for instruction scheduling.
1114///
1115FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1116  return new ARMDAGToDAGISel(TM);
1117}
1118