ARMISelDAGToDAG.cpp revision 63f3544a7f6ca09e7515d6b0e1bf9e8e884131e2 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMTargetMachine.h"
18#include "llvm/CallingConv.h"
19#include "llvm/Constants.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/LLVMContext.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/CodeGen/SelectionDAGISel.h"
29#include "llvm/Target/TargetLowering.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36
37using namespace llvm;
38
39static cl::opt<bool>
40DisableShifterOp("disable-shifter-op", cl::Hidden,
41  cl::desc("Disable isel of shifter-op"),
42  cl::init(false));
43
44//===--------------------------------------------------------------------===//
45/// ARMDAGToDAGISel - ARM specific code to select ARM machine
46/// instructions for SelectionDAG operations.
47///
48namespace {
49
50enum AddrMode2Type {
51  AM2_BASE, // Simple AM2 (+-imm12)
52  AM2_SHOP  // Shifter-op AM2
53};
54
55class ARMDAGToDAGISel : public SelectionDAGISel {
56  ARMBaseTargetMachine &TM;
57
58  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
59  /// make the right decision when generating code for different targets.
60  const ARMSubtarget *Subtarget;
61
62public:
63  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
64                           CodeGenOpt::Level OptLevel)
65    : SelectionDAGISel(tm, OptLevel), TM(tm),
66    Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
67  }
68
69  virtual const char *getPassName() const {
70    return "ARM Instruction Selection";
71  }
72
73  /// getI32Imm - Return a target constant of type i32 with the specified
74  /// value.
75  inline SDValue getI32Imm(unsigned Imm) {
76    return CurDAG->getTargetConstant(Imm, MVT::i32);
77  }
78
79  SDNode *Select(SDNode *N);
80
81  bool isShifterOpProfitable(const SDValue &Shift,
82                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
83  bool SelectShifterOperandReg(SDValue N, SDValue &A,
84                               SDValue &B, SDValue &C);
85  bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
86                                    SDValue &B, SDValue &C);
87  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
88  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
89
90  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
91                                      SDValue &Offset, SDValue &Opc);
92  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
93                           SDValue &Opc) {
94    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
95  }
96
97  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
98                           SDValue &Opc) {
99    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
100  }
101
102  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
103                       SDValue &Opc) {
104    SelectAddrMode2Worker(N, Base, Offset, Opc);
105//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
106    // This always matches one way or another.
107    return true;
108  }
109
110  bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
111                             SDValue &Offset, SDValue &Opc);
112  bool SelectAddrMode3(SDValue N, SDValue &Base,
113                       SDValue &Offset, SDValue &Opc);
114  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
115                             SDValue &Offset, SDValue &Opc);
116  bool SelectAddrMode5(SDValue N, SDValue &Base,
117                       SDValue &Offset);
118  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
119
120  bool SelectAddrModePC(SDValue N, SDValue &Offset,
121                        SDValue &Label);
122
123  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
124  bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
125                              SDValue &Base, SDValue &OffImm,
126                              SDValue &Offset);
127  bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
128                             SDValue &OffImm, SDValue &Offset);
129  bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
130                             SDValue &OffImm, SDValue &Offset);
131  bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
132                             SDValue &OffImm, SDValue &Offset);
133  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
134
135  bool SelectT2ShifterOperandReg(SDValue N,
136                                 SDValue &BaseReg, SDValue &Opc);
137  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
138  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
139                            SDValue &OffImm);
140  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
141                                 SDValue &OffImm);
142  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
143                             SDValue &OffReg, SDValue &ShImm);
144
145  inline bool is_so_imm(unsigned Imm) const {
146    return ARM_AM::getSOImmVal(Imm) != -1;
147  }
148
149  inline bool is_so_imm_not(unsigned Imm) const {
150    return ARM_AM::getSOImmVal(~Imm) != -1;
151  }
152
153  inline bool is_t2_so_imm(unsigned Imm) const {
154    return ARM_AM::getT2SOImmVal(Imm) != -1;
155  }
156
157  inline bool is_t2_so_imm_not(unsigned Imm) const {
158    return ARM_AM::getT2SOImmVal(~Imm) != -1;
159  }
160
161  inline bool Pred_so_imm(SDNode *inN) const {
162    ConstantSDNode *N = cast<ConstantSDNode>(inN);
163    return is_so_imm(N->getZExtValue());
164  }
165
166  inline bool Pred_t2_so_imm(SDNode *inN) const {
167    ConstantSDNode *N = cast<ConstantSDNode>(inN);
168    return is_t2_so_imm(N->getZExtValue());
169  }
170
171  // Include the pieces autogenerated from the target description.
172#include "ARMGenDAGISel.inc"
173
174private:
175  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
176  /// ARM.
177  SDNode *SelectARMIndexedLoad(SDNode *N);
178  SDNode *SelectT2IndexedLoad(SDNode *N);
179
180  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
181  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
182  /// loads of D registers and even subregs and odd subregs of Q registers.
183  /// For NumVecs <= 2, QOpcodes1 is not used.
184  SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
185                    unsigned *QOpcodes0, unsigned *QOpcodes1);
186
187  /// SelectVST - Select NEON store intrinsics.  NumVecs should
188  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
189  /// stores of D registers and even subregs and odd subregs of Q registers.
190  /// For NumVecs <= 2, QOpcodes1 is not used.
191  SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
192                    unsigned *QOpcodes0, unsigned *QOpcodes1);
193
194  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
195  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
196  /// load/store of D registers and Q registers.
197  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
198                          unsigned *DOpcodes, unsigned *QOpcodes);
199
200  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
201  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
202  /// generated to force the table registers to be consecutive.
203  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
204
205  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
206  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
207
208  /// SelectCMOVOp - Select CMOV instructions for ARM.
209  SDNode *SelectCMOVOp(SDNode *N);
210  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
211                              ARMCC::CondCodes CCVal, SDValue CCR,
212                              SDValue InFlag);
213  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
214                               ARMCC::CondCodes CCVal, SDValue CCR,
215                               SDValue InFlag);
216  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
217                              ARMCC::CondCodes CCVal, SDValue CCR,
218                              SDValue InFlag);
219  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
220                               ARMCC::CondCodes CCVal, SDValue CCR,
221                               SDValue InFlag);
222
223  SDNode *SelectConcatVector(SDNode *N);
224
225  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
226  /// inline asm expressions.
227  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
228                                            char ConstraintCode,
229                                            std::vector<SDValue> &OutOps);
230
231  // Form pairs of consecutive S, D, or Q registers.
232  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
233  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
234  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
235
236  // Form sequences of 4 consecutive S, D, or Q registers.
237  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
238  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
239  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
240
241  // Get the alignment operand for a NEON VLD or VST instruction.
242  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
243};
244}
245
246/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
247/// operand. If so Imm will receive the 32-bit value.
248static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
249  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
250    Imm = cast<ConstantSDNode>(N)->getZExtValue();
251    return true;
252  }
253  return false;
254}
255
256// isInt32Immediate - This method tests to see if a constant operand.
257// If so Imm will receive the 32 bit value.
258static bool isInt32Immediate(SDValue N, unsigned &Imm) {
259  return isInt32Immediate(N.getNode(), Imm);
260}
261
262// isOpcWithIntImmediate - This method tests to see if the node is a specific
263// opcode and that it has a immediate integer right operand.
264// If so Imm will receive the 32 bit value.
265static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
266  return N->getOpcode() == Opc &&
267         isInt32Immediate(N->getOperand(1).getNode(), Imm);
268}
269
270
271bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
272                                            ARM_AM::ShiftOpc ShOpcVal,
273                                            unsigned ShAmt) {
274  if (!Subtarget->isCortexA9())
275    return true;
276  if (Shift.hasOneUse())
277    return true;
278  // R << 2 is free.
279  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
280}
281
282bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
283                                              SDValue &BaseReg,
284                                              SDValue &ShReg,
285                                              SDValue &Opc) {
286  if (DisableShifterOp)
287    return false;
288
289  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
290
291  // Don't match base register only case. That is matched to a separate
292  // lower complexity pattern with explicit register operand.
293  if (ShOpcVal == ARM_AM::no_shift) return false;
294
295  BaseReg = N.getOperand(0);
296  unsigned ShImmVal = 0;
297  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
298    ShReg = CurDAG->getRegister(0, MVT::i32);
299    ShImmVal = RHS->getZExtValue() & 31;
300  } else {
301    ShReg = N.getOperand(1);
302    if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
303      return false;
304  }
305  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
306                                  MVT::i32);
307  return true;
308}
309
310bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
311                                                   SDValue &BaseReg,
312                                                   SDValue &ShReg,
313                                                   SDValue &Opc) {
314  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
315
316  // Don't match base register only case. That is matched to a separate
317  // lower complexity pattern with explicit register operand.
318  if (ShOpcVal == ARM_AM::no_shift) return false;
319
320  BaseReg = N.getOperand(0);
321  unsigned ShImmVal = 0;
322  // Do not check isShifterOpProfitable. This must return true.
323  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
324    ShReg = CurDAG->getRegister(0, MVT::i32);
325    ShImmVal = RHS->getZExtValue() & 31;
326  } else {
327    ShReg = N.getOperand(1);
328  }
329  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
330                                  MVT::i32);
331  return true;
332}
333
334bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
335                                          SDValue &Base,
336                                          SDValue &OffImm) {
337  // Match simple R + imm12 operands.
338
339  // Base only.
340  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
341    if (N.getOpcode() == ISD::FrameIndex) {
342      // Match frame index...
343      int FI = cast<FrameIndexSDNode>(N)->getIndex();
344      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
345      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
346      return true;
347    } else if (N.getOpcode() == ARMISD::Wrapper &&
348               !(Subtarget->useMovt() &&
349                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
350      Base = N.getOperand(0);
351    } else
352      Base = N;
353    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
354    return true;
355  }
356
357  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
358    int RHSC = (int)RHS->getZExtValue();
359    if (N.getOpcode() == ISD::SUB)
360      RHSC = -RHSC;
361
362    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
363      Base   = N.getOperand(0);
364      if (Base.getOpcode() == ISD::FrameIndex) {
365        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
366        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
367      }
368      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
369      return true;
370    }
371  }
372
373  // Base only.
374  Base = N;
375  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
376  return true;
377}
378
379
380
381bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
382                                      SDValue &Opc) {
383  if (N.getOpcode() == ISD::MUL &&
384      (!Subtarget->isCortexA9() || N.hasOneUse())) {
385    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
386      // X * [3,5,9] -> X + X * [2,4,8] etc.
387      int RHSC = (int)RHS->getZExtValue();
388      if (RHSC & 1) {
389        RHSC = RHSC & ~1;
390        ARM_AM::AddrOpc AddSub = ARM_AM::add;
391        if (RHSC < 0) {
392          AddSub = ARM_AM::sub;
393          RHSC = - RHSC;
394        }
395        if (isPowerOf2_32(RHSC)) {
396          unsigned ShAmt = Log2_32(RHSC);
397          Base = Offset = N.getOperand(0);
398          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
399                                                            ARM_AM::lsl),
400                                          MVT::i32);
401          return true;
402        }
403      }
404    }
405  }
406
407  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
408    return false;
409
410  // Leave simple R +/- imm12 operands for LDRi12
411  if (N.getOpcode() == ISD::ADD) {
412    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
413      int RHSC = (int)RHS->getZExtValue();
414      if ((RHSC >= 0 && RHSC < 0x1000) ||
415          (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
416        return false;
417    }
418  }
419
420  if (Subtarget->isCortexA9() && !N.hasOneUse())
421    // Compute R +/- (R << N) and reuse it.
422    return false;
423
424  // Otherwise this is R +/- [possibly shifted] R.
425  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
426  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
427  unsigned ShAmt = 0;
428
429  Base   = N.getOperand(0);
430  Offset = N.getOperand(1);
431
432  if (ShOpcVal != ARM_AM::no_shift) {
433    // Check to see if the RHS of the shift is a constant, if not, we can't fold
434    // it.
435    if (ConstantSDNode *Sh =
436           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
437      ShAmt = Sh->getZExtValue();
438      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
439        Offset = N.getOperand(1).getOperand(0);
440      else {
441        ShAmt = 0;
442        ShOpcVal = ARM_AM::no_shift;
443      }
444    } else {
445      ShOpcVal = ARM_AM::no_shift;
446    }
447  }
448
449  // Try matching (R shl C) + (R).
450  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
451      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
452    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
453    if (ShOpcVal != ARM_AM::no_shift) {
454      // Check to see if the RHS of the shift is a constant, if not, we can't
455      // fold it.
456      if (ConstantSDNode *Sh =
457          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
458        ShAmt = Sh->getZExtValue();
459        if (!Subtarget->isCortexA9() ||
460            (N.hasOneUse() &&
461             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
462          Offset = N.getOperand(0).getOperand(0);
463          Base = N.getOperand(1);
464        } else {
465          ShAmt = 0;
466          ShOpcVal = ARM_AM::no_shift;
467        }
468      } else {
469        ShOpcVal = ARM_AM::no_shift;
470      }
471    }
472  }
473
474  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
475                                  MVT::i32);
476  return true;
477}
478
479
480
481
482//-----
483
484AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
485                                                     SDValue &Base,
486                                                     SDValue &Offset,
487                                                     SDValue &Opc) {
488  if (N.getOpcode() == ISD::MUL &&
489      (!Subtarget->isCortexA9() || N.hasOneUse())) {
490    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
491      // X * [3,5,9] -> X + X * [2,4,8] etc.
492      int RHSC = (int)RHS->getZExtValue();
493      if (RHSC & 1) {
494        RHSC = RHSC & ~1;
495        ARM_AM::AddrOpc AddSub = ARM_AM::add;
496        if (RHSC < 0) {
497          AddSub = ARM_AM::sub;
498          RHSC = - RHSC;
499        }
500        if (isPowerOf2_32(RHSC)) {
501          unsigned ShAmt = Log2_32(RHSC);
502          Base = Offset = N.getOperand(0);
503          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
504                                                            ARM_AM::lsl),
505                                          MVT::i32);
506          return AM2_SHOP;
507        }
508      }
509    }
510  }
511
512  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
513    Base = N;
514    if (N.getOpcode() == ISD::FrameIndex) {
515      int FI = cast<FrameIndexSDNode>(N)->getIndex();
516      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
517    } else if (N.getOpcode() == ARMISD::Wrapper &&
518               !(Subtarget->useMovt() &&
519                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
520      Base = N.getOperand(0);
521    }
522    Offset = CurDAG->getRegister(0, MVT::i32);
523    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
524                                                      ARM_AM::no_shift),
525                                    MVT::i32);
526    return AM2_BASE;
527  }
528
529  // Match simple R +/- imm12 operands.
530  if (N.getOpcode() == ISD::ADD) {
531    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
532      int RHSC = (int)RHS->getZExtValue();
533      if ((RHSC >= 0 && RHSC < 0x1000) ||
534          (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
535        Base = N.getOperand(0);
536        if (Base.getOpcode() == ISD::FrameIndex) {
537          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
538          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
539        }
540        Offset = CurDAG->getRegister(0, MVT::i32);
541
542        ARM_AM::AddrOpc AddSub = ARM_AM::add;
543        if (RHSC < 0) {
544          AddSub = ARM_AM::sub;
545          RHSC = - RHSC;
546        }
547        Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
548                                                          ARM_AM::no_shift),
549                                        MVT::i32);
550        return AM2_BASE;
551      }
552    }
553  }
554
555  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
556    // Compute R +/- (R << N) and reuse it.
557    Base = N;
558    Offset = CurDAG->getRegister(0, MVT::i32);
559    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
560                                                      ARM_AM::no_shift),
561                                    MVT::i32);
562    return AM2_BASE;
563  }
564
565  // Otherwise this is R +/- [possibly shifted] R.
566  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
567  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
568  unsigned ShAmt = 0;
569
570  Base   = N.getOperand(0);
571  Offset = N.getOperand(1);
572
573  if (ShOpcVal != ARM_AM::no_shift) {
574    // Check to see if the RHS of the shift is a constant, if not, we can't fold
575    // it.
576    if (ConstantSDNode *Sh =
577           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
578      ShAmt = Sh->getZExtValue();
579      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
580        Offset = N.getOperand(1).getOperand(0);
581      else {
582        ShAmt = 0;
583        ShOpcVal = ARM_AM::no_shift;
584      }
585    } else {
586      ShOpcVal = ARM_AM::no_shift;
587    }
588  }
589
590  // Try matching (R shl C) + (R).
591  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
592      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
593    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
594    if (ShOpcVal != ARM_AM::no_shift) {
595      // Check to see if the RHS of the shift is a constant, if not, we can't
596      // fold it.
597      if (ConstantSDNode *Sh =
598          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
599        ShAmt = Sh->getZExtValue();
600        if (!Subtarget->isCortexA9() ||
601            (N.hasOneUse() &&
602             isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
603          Offset = N.getOperand(0).getOperand(0);
604          Base = N.getOperand(1);
605        } else {
606          ShAmt = 0;
607          ShOpcVal = ARM_AM::no_shift;
608        }
609      } else {
610        ShOpcVal = ARM_AM::no_shift;
611      }
612    }
613  }
614
615  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
616                                  MVT::i32);
617  return AM2_SHOP;
618}
619
620bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
621                                            SDValue &Offset, SDValue &Opc) {
622  unsigned Opcode = Op->getOpcode();
623  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
624    ? cast<LoadSDNode>(Op)->getAddressingMode()
625    : cast<StoreSDNode>(Op)->getAddressingMode();
626  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
627    ? ARM_AM::add : ARM_AM::sub;
628  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
629    int Val = (int)C->getZExtValue();
630    if (Val >= 0 && Val < 0x1000) { // 12 bits.
631      Offset = CurDAG->getRegister(0, MVT::i32);
632      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
633                                                        ARM_AM::no_shift),
634                                      MVT::i32);
635      return true;
636    }
637  }
638
639  Offset = N;
640  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
641  unsigned ShAmt = 0;
642  if (ShOpcVal != ARM_AM::no_shift) {
643    // Check to see if the RHS of the shift is a constant, if not, we can't fold
644    // it.
645    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
646      ShAmt = Sh->getZExtValue();
647      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
648        Offset = N.getOperand(0);
649      else {
650        ShAmt = 0;
651        ShOpcVal = ARM_AM::no_shift;
652      }
653    } else {
654      ShOpcVal = ARM_AM::no_shift;
655    }
656  }
657
658  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
659                                  MVT::i32);
660  return true;
661}
662
663
664bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
665                                      SDValue &Base, SDValue &Offset,
666                                      SDValue &Opc) {
667  if (N.getOpcode() == ISD::SUB) {
668    // X - C  is canonicalize to X + -C, no need to handle it here.
669    Base = N.getOperand(0);
670    Offset = N.getOperand(1);
671    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
672    return true;
673  }
674
675  if (N.getOpcode() != ISD::ADD) {
676    Base = N;
677    if (N.getOpcode() == ISD::FrameIndex) {
678      int FI = cast<FrameIndexSDNode>(N)->getIndex();
679      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
680    }
681    Offset = CurDAG->getRegister(0, MVT::i32);
682    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
683    return true;
684  }
685
686  // If the RHS is +/- imm8, fold into addr mode.
687  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
688    int RHSC = (int)RHS->getZExtValue();
689    if ((RHSC >= 0 && RHSC < 256) ||
690        (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
691      Base = N.getOperand(0);
692      if (Base.getOpcode() == ISD::FrameIndex) {
693        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
694        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
695      }
696      Offset = CurDAG->getRegister(0, MVT::i32);
697
698      ARM_AM::AddrOpc AddSub = ARM_AM::add;
699      if (RHSC < 0) {
700        AddSub = ARM_AM::sub;
701        RHSC = - RHSC;
702      }
703      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
704      return true;
705    }
706  }
707
708  Base = N.getOperand(0);
709  Offset = N.getOperand(1);
710  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
711  return true;
712}
713
714bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
715                                            SDValue &Offset, SDValue &Opc) {
716  unsigned Opcode = Op->getOpcode();
717  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
718    ? cast<LoadSDNode>(Op)->getAddressingMode()
719    : cast<StoreSDNode>(Op)->getAddressingMode();
720  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
721    ? ARM_AM::add : ARM_AM::sub;
722  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
723    int Val = (int)C->getZExtValue();
724    if (Val >= 0 && Val < 256) {
725      Offset = CurDAG->getRegister(0, MVT::i32);
726      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
727      return true;
728    }
729  }
730
731  Offset = N;
732  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
733  return true;
734}
735
736bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
737                                      SDValue &Base, SDValue &Offset) {
738  if (N.getOpcode() != ISD::ADD) {
739    Base = N;
740    if (N.getOpcode() == ISD::FrameIndex) {
741      int FI = cast<FrameIndexSDNode>(N)->getIndex();
742      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
743    } else if (N.getOpcode() == ARMISD::Wrapper &&
744               !(Subtarget->useMovt() &&
745                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
746      Base = N.getOperand(0);
747    }
748    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
749                                       MVT::i32);
750    return true;
751  }
752
753  // If the RHS is +/- imm8, fold into addr mode.
754  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
755    int RHSC = (int)RHS->getZExtValue();
756    if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied by 4.
757      RHSC >>= 2;
758      if ((RHSC >= 0 && RHSC < 256) ||
759          (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
760        Base = N.getOperand(0);
761        if (Base.getOpcode() == ISD::FrameIndex) {
762          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
763          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
764        }
765
766        ARM_AM::AddrOpc AddSub = ARM_AM::add;
767        if (RHSC < 0) {
768          AddSub = ARM_AM::sub;
769          RHSC = - RHSC;
770        }
771        Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
772                                           MVT::i32);
773        return true;
774      }
775    }
776  }
777
778  Base = N;
779  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
780                                     MVT::i32);
781  return true;
782}
783
784bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
785                                      SDValue &Align) {
786  Addr = N;
787
788  unsigned Alignment = 0;
789  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
790    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
791    // The maximum alignment is equal to the memory size being referenced.
792    unsigned LSNAlign = LSN->getAlignment();
793    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
794    if (LSNAlign > MemSize && MemSize > 1)
795      Alignment = MemSize;
796  } else {
797    // All other uses of addrmode6 are for intrinsics.  For now just record
798    // the raw alignment value; it will be refined later based on the legal
799    // alignment operands for the intrinsic.
800    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
801  }
802
803  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
804  return true;
805}
806
807bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
808                                       SDValue &Offset, SDValue &Label) {
809  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
810    Offset = N.getOperand(0);
811    SDValue N1 = N.getOperand(1);
812    Label  = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
813                                       MVT::i32);
814    return true;
815  }
816  return false;
817}
818
819bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
820                                            SDValue &Base, SDValue &Offset){
821  // FIXME dl should come from the parent load or store, not the address
822  if (N.getOpcode() != ISD::ADD) {
823    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
824    if (!NC || !NC->isNullValue())
825      return false;
826
827    Base = Offset = N;
828    return true;
829  }
830
831  Base = N.getOperand(0);
832  Offset = N.getOperand(1);
833  return true;
834}
835
836bool
837ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
838                                        unsigned Scale, SDValue &Base,
839                                        SDValue &OffImm, SDValue &Offset) {
840  if (Scale == 4) {
841    SDValue TmpBase, TmpOffImm;
842    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
843      return false;  // We want to select tLDRspi / tSTRspi instead.
844    if (N.getOpcode() == ARMISD::Wrapper &&
845        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
846      return false;  // We want to select tLDRpci instead.
847  }
848
849  if (N.getOpcode() != ISD::ADD) {
850    if (N.getOpcode() == ARMISD::Wrapper &&
851        !(Subtarget->useMovt() &&
852          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
853      Base = N.getOperand(0);
854    } else
855      Base = N;
856
857    Offset = CurDAG->getRegister(0, MVT::i32);
858    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
859    return true;
860  }
861
862  // Thumb does not have [sp, r] address mode.
863  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
864  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
865  if ((LHSR && LHSR->getReg() == ARM::SP) ||
866      (RHSR && RHSR->getReg() == ARM::SP)) {
867    Base = N;
868    Offset = CurDAG->getRegister(0, MVT::i32);
869    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
870    return true;
871  }
872
873  // If the RHS is + imm5 * scale, fold into addr mode.
874  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
875    int RHSC = (int)RHS->getZExtValue();
876    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
877      RHSC /= Scale;
878      if (RHSC >= 0 && RHSC < 32) {
879        Base = N.getOperand(0);
880        Offset = CurDAG->getRegister(0, MVT::i32);
881        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
882        return true;
883      }
884    }
885  }
886
887  Base = N.getOperand(0);
888  Offset = N.getOperand(1);
889  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
890  return true;
891}
892
893bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
894                                            SDValue &Base, SDValue &OffImm,
895                                            SDValue &Offset) {
896  return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
897}
898
899bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
900                                            SDValue &Base, SDValue &OffImm,
901                                            SDValue &Offset) {
902  return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
903}
904
905bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
906                                            SDValue &Base, SDValue &OffImm,
907                                            SDValue &Offset) {
908  return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
909}
910
911bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
912                                            SDValue &Base, SDValue &OffImm) {
913  if (N.getOpcode() == ISD::FrameIndex) {
914    int FI = cast<FrameIndexSDNode>(N)->getIndex();
915    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
916    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
917    return true;
918  }
919
920  if (N.getOpcode() != ISD::ADD)
921    return false;
922
923  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
924  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
925      (LHSR && LHSR->getReg() == ARM::SP)) {
926    // If the RHS is + imm8 * scale, fold into addr mode.
927    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
928      int RHSC = (int)RHS->getZExtValue();
929      if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied.
930        RHSC >>= 2;
931        if (RHSC >= 0 && RHSC < 256) {
932          Base = N.getOperand(0);
933          if (Base.getOpcode() == ISD::FrameIndex) {
934            int FI = cast<FrameIndexSDNode>(Base)->getIndex();
935            Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
936          }
937          OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
938          return true;
939        }
940      }
941    }
942  }
943
944  return false;
945}
946
947bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
948                                                SDValue &Opc) {
949  if (DisableShifterOp)
950    return false;
951
952  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
953
954  // Don't match base register only case. That is matched to a separate
955  // lower complexity pattern with explicit register operand.
956  if (ShOpcVal == ARM_AM::no_shift) return false;
957
958  BaseReg = N.getOperand(0);
959  unsigned ShImmVal = 0;
960  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
961    ShImmVal = RHS->getZExtValue() & 31;
962    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
963    return true;
964  }
965
966  return false;
967}
968
969bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
970                                            SDValue &Base, SDValue &OffImm) {
971  // Match simple R + imm12 operands.
972
973  // Base only.
974  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
975    if (N.getOpcode() == ISD::FrameIndex) {
976      // Match frame index...
977      int FI = cast<FrameIndexSDNode>(N)->getIndex();
978      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
979      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
980      return true;
981    } else if (N.getOpcode() == ARMISD::Wrapper &&
982               !(Subtarget->useMovt() &&
983                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
984      Base = N.getOperand(0);
985      if (Base.getOpcode() == ISD::TargetConstantPool)
986        return false;  // We want to select t2LDRpci instead.
987    } else
988      Base = N;
989    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
990    return true;
991  }
992
993  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
994    if (SelectT2AddrModeImm8(N, Base, OffImm))
995      // Let t2LDRi8 handle (R - imm8).
996      return false;
997
998    int RHSC = (int)RHS->getZExtValue();
999    if (N.getOpcode() == ISD::SUB)
1000      RHSC = -RHSC;
1001
1002    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1003      Base   = N.getOperand(0);
1004      if (Base.getOpcode() == ISD::FrameIndex) {
1005        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1006        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1007      }
1008      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1009      return true;
1010    }
1011  }
1012
1013  // Base only.
1014  Base = N;
1015  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1016  return true;
1017}
1018
1019bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1020                                           SDValue &Base, SDValue &OffImm) {
1021  // Match simple R - imm8 operands.
1022  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
1023    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1024      int RHSC = (int)RHS->getSExtValue();
1025      if (N.getOpcode() == ISD::SUB)
1026        RHSC = -RHSC;
1027
1028      if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1029        Base = N.getOperand(0);
1030        if (Base.getOpcode() == ISD::FrameIndex) {
1031          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1032          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1033        }
1034        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1035        return true;
1036      }
1037    }
1038  }
1039
1040  return false;
1041}
1042
1043bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1044                                                 SDValue &OffImm){
1045  unsigned Opcode = Op->getOpcode();
1046  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1047    ? cast<LoadSDNode>(Op)->getAddressingMode()
1048    : cast<StoreSDNode>(Op)->getAddressingMode();
1049  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
1050    int RHSC = (int)RHS->getZExtValue();
1051    if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
1052      OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1053        ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1054        : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1055      return true;
1056    }
1057  }
1058
1059  return false;
1060}
1061
1062bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1063                                            SDValue &Base,
1064                                            SDValue &OffReg, SDValue &ShImm) {
1065  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1066  if (N.getOpcode() != ISD::ADD)
1067    return false;
1068
1069  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1070  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1071    int RHSC = (int)RHS->getZExtValue();
1072    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1073      return false;
1074    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1075      return false;
1076  }
1077
1078  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1079    // Compute R + (R << [1,2,3]) and reuse it.
1080    Base = N;
1081    return false;
1082  }
1083
1084  // Look for (R + R) or (R + (R << [1,2,3])).
1085  unsigned ShAmt = 0;
1086  Base   = N.getOperand(0);
1087  OffReg = N.getOperand(1);
1088
1089  // Swap if it is ((R << c) + R).
1090  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1091  if (ShOpcVal != ARM_AM::lsl) {
1092    ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1093    if (ShOpcVal == ARM_AM::lsl)
1094      std::swap(Base, OffReg);
1095  }
1096
1097  if (ShOpcVal == ARM_AM::lsl) {
1098    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1099    // it.
1100    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1101      ShAmt = Sh->getZExtValue();
1102      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1103        OffReg = OffReg.getOperand(0);
1104      else {
1105        ShAmt = 0;
1106        ShOpcVal = ARM_AM::no_shift;
1107      }
1108    } else {
1109      ShOpcVal = ARM_AM::no_shift;
1110    }
1111  }
1112
1113  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1114
1115  return true;
1116}
1117
1118//===--------------------------------------------------------------------===//
1119
1120/// getAL - Returns a ARMCC::AL immediate node.
1121static inline SDValue getAL(SelectionDAG *CurDAG) {
1122  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1123}
1124
1125SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1126  LoadSDNode *LD = cast<LoadSDNode>(N);
1127  ISD::MemIndexedMode AM = LD->getAddressingMode();
1128  if (AM == ISD::UNINDEXED)
1129    return NULL;
1130
1131  EVT LoadedVT = LD->getMemoryVT();
1132  SDValue Offset, AMOpc;
1133  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1134  unsigned Opcode = 0;
1135  bool Match = false;
1136  if (LoadedVT == MVT::i32 &&
1137      SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1138    Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1139    Match = true;
1140  } else if (LoadedVT == MVT::i16 &&
1141             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1142    Match = true;
1143    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1144      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1145      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1146  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1147    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1148      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1149        Match = true;
1150        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1151      }
1152    } else {
1153      if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1154        Match = true;
1155        Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1156      }
1157    }
1158  }
1159
1160  if (Match) {
1161    SDValue Chain = LD->getChain();
1162    SDValue Base = LD->getBasePtr();
1163    SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1164                     CurDAG->getRegister(0, MVT::i32), Chain };
1165    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1166                                  MVT::Other, Ops, 6);
1167  }
1168
1169  return NULL;
1170}
1171
1172SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1173  LoadSDNode *LD = cast<LoadSDNode>(N);
1174  ISD::MemIndexedMode AM = LD->getAddressingMode();
1175  if (AM == ISD::UNINDEXED)
1176    return NULL;
1177
1178  EVT LoadedVT = LD->getMemoryVT();
1179  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1180  SDValue Offset;
1181  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1182  unsigned Opcode = 0;
1183  bool Match = false;
1184  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1185    switch (LoadedVT.getSimpleVT().SimpleTy) {
1186    case MVT::i32:
1187      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1188      break;
1189    case MVT::i16:
1190      if (isSExtLd)
1191        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1192      else
1193        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1194      break;
1195    case MVT::i8:
1196    case MVT::i1:
1197      if (isSExtLd)
1198        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1199      else
1200        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1201      break;
1202    default:
1203      return NULL;
1204    }
1205    Match = true;
1206  }
1207
1208  if (Match) {
1209    SDValue Chain = LD->getChain();
1210    SDValue Base = LD->getBasePtr();
1211    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1212                     CurDAG->getRegister(0, MVT::i32), Chain };
1213    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1214                                  MVT::Other, Ops, 5);
1215  }
1216
1217  return NULL;
1218}
1219
1220/// PairSRegs - Form a D register from a pair of S registers.
1221///
1222SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1223  DebugLoc dl = V0.getNode()->getDebugLoc();
1224  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1225  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1226  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1227  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1228}
1229
1230/// PairDRegs - Form a quad register from a pair of D registers.
1231///
1232SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1233  DebugLoc dl = V0.getNode()->getDebugLoc();
1234  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1235  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1236  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1237  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1238}
1239
1240/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1241///
1242SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1243  DebugLoc dl = V0.getNode()->getDebugLoc();
1244  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1245  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1246  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1247  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1248}
1249
1250/// QuadSRegs - Form 4 consecutive S registers.
1251///
1252SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1253                                   SDValue V2, SDValue V3) {
1254  DebugLoc dl = V0.getNode()->getDebugLoc();
1255  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1256  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1257  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1258  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1259  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1260  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1261}
1262
1263/// QuadDRegs - Form 4 consecutive D registers.
1264///
1265SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1266                                   SDValue V2, SDValue V3) {
1267  DebugLoc dl = V0.getNode()->getDebugLoc();
1268  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1269  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1270  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1271  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1272  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1273  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1274}
1275
1276/// QuadQRegs - Form 4 consecutive Q registers.
1277///
1278SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1279                                   SDValue V2, SDValue V3) {
1280  DebugLoc dl = V0.getNode()->getDebugLoc();
1281  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1282  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1283  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1284  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1285  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1286  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1287}
1288
1289/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1290/// of a NEON VLD or VST instruction.  The supported values depend on the
1291/// number of registers being loaded.
1292SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1293                                       bool is64BitVector) {
1294  unsigned NumRegs = NumVecs;
1295  if (!is64BitVector && NumVecs < 3)
1296    NumRegs *= 2;
1297
1298  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1299  if (Alignment >= 32 && NumRegs == 4)
1300    Alignment = 32;
1301  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1302    Alignment = 16;
1303  else if (Alignment >= 8)
1304    Alignment = 8;
1305  else
1306    Alignment = 0;
1307
1308  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1309}
1310
1311SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1312                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1313                                   unsigned *QOpcodes1) {
1314  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1315  DebugLoc dl = N->getDebugLoc();
1316
1317  SDValue MemAddr, Align;
1318  if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1319    return NULL;
1320
1321  SDValue Chain = N->getOperand(0);
1322  EVT VT = N->getValueType(0);
1323  bool is64BitVector = VT.is64BitVector();
1324  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1325
1326  unsigned OpcodeIndex;
1327  switch (VT.getSimpleVT().SimpleTy) {
1328  default: llvm_unreachable("unhandled vld type");
1329    // Double-register operations:
1330  case MVT::v8i8:  OpcodeIndex = 0; break;
1331  case MVT::v4i16: OpcodeIndex = 1; break;
1332  case MVT::v2f32:
1333  case MVT::v2i32: OpcodeIndex = 2; break;
1334  case MVT::v1i64: OpcodeIndex = 3; break;
1335    // Quad-register operations:
1336  case MVT::v16i8: OpcodeIndex = 0; break;
1337  case MVT::v8i16: OpcodeIndex = 1; break;
1338  case MVT::v4f32:
1339  case MVT::v4i32: OpcodeIndex = 2; break;
1340  case MVT::v2i64: OpcodeIndex = 3;
1341    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1342    break;
1343  }
1344
1345  EVT ResTy;
1346  if (NumVecs == 1)
1347    ResTy = VT;
1348  else {
1349    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1350    if (!is64BitVector)
1351      ResTyElts *= 2;
1352    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1353  }
1354
1355  SDValue Pred = getAL(CurDAG);
1356  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1357  SDValue SuperReg;
1358  if (is64BitVector) {
1359    unsigned Opc = DOpcodes[OpcodeIndex];
1360    const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1361    SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1362    if (NumVecs == 1)
1363      return VLd;
1364
1365    SuperReg = SDValue(VLd, 0);
1366    assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1367    for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1368      SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1369                                                 dl, VT, SuperReg);
1370      ReplaceUses(SDValue(N, Vec), D);
1371    }
1372    ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1373    return NULL;
1374  }
1375
1376  if (NumVecs <= 2) {
1377    // Quad registers are directly supported for VLD1 and VLD2,
1378    // loading pairs of D regs.
1379    unsigned Opc = QOpcodes0[OpcodeIndex];
1380    const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1381    SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1382    if (NumVecs == 1)
1383      return VLd;
1384
1385    SuperReg = SDValue(VLd, 0);
1386    Chain = SDValue(VLd, 1);
1387
1388  } else {
1389    // Otherwise, quad registers are loaded with two separate instructions,
1390    // where one loads the even registers and the other loads the odd registers.
1391    EVT AddrTy = MemAddr.getValueType();
1392
1393    // Load the even subregs.
1394    unsigned Opc = QOpcodes0[OpcodeIndex];
1395    SDValue ImplDef =
1396      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1397    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1398    SDNode *VLdA =
1399      CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1400    Chain = SDValue(VLdA, 2);
1401
1402    // Load the odd subregs.
1403    Opc = QOpcodes1[OpcodeIndex];
1404    const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1405                             Pred, Reg0, Chain };
1406    SDNode *VLdB =
1407      CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1408    SuperReg = SDValue(VLdB, 0);
1409    Chain = SDValue(VLdB, 2);
1410  }
1411
1412  // Extract out the Q registers.
1413  assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1414  for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1415    SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1416                                               dl, VT, SuperReg);
1417    ReplaceUses(SDValue(N, Vec), Q);
1418  }
1419  ReplaceUses(SDValue(N, NumVecs), Chain);
1420  return NULL;
1421}
1422
1423SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1424                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1425                                   unsigned *QOpcodes1) {
1426  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1427  DebugLoc dl = N->getDebugLoc();
1428
1429  SDValue MemAddr, Align;
1430  if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1431    return NULL;
1432
1433  SDValue Chain = N->getOperand(0);
1434  EVT VT = N->getOperand(3).getValueType();
1435  bool is64BitVector = VT.is64BitVector();
1436  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1437
1438  unsigned OpcodeIndex;
1439  switch (VT.getSimpleVT().SimpleTy) {
1440  default: llvm_unreachable("unhandled vst type");
1441    // Double-register operations:
1442  case MVT::v8i8:  OpcodeIndex = 0; break;
1443  case MVT::v4i16: OpcodeIndex = 1; break;
1444  case MVT::v2f32:
1445  case MVT::v2i32: OpcodeIndex = 2; break;
1446  case MVT::v1i64: OpcodeIndex = 3; break;
1447    // Quad-register operations:
1448  case MVT::v16i8: OpcodeIndex = 0; break;
1449  case MVT::v8i16: OpcodeIndex = 1; break;
1450  case MVT::v4f32:
1451  case MVT::v4i32: OpcodeIndex = 2; break;
1452  case MVT::v2i64: OpcodeIndex = 3;
1453    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1454    break;
1455  }
1456
1457  SDValue Pred = getAL(CurDAG);
1458  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1459
1460  SmallVector<SDValue, 7> Ops;
1461  Ops.push_back(MemAddr);
1462  Ops.push_back(Align);
1463
1464  if (is64BitVector) {
1465    if (NumVecs == 1) {
1466      Ops.push_back(N->getOperand(3));
1467    } else {
1468      SDValue RegSeq;
1469      SDValue V0 = N->getOperand(0+3);
1470      SDValue V1 = N->getOperand(1+3);
1471
1472      // Form a REG_SEQUENCE to force register allocation.
1473      if (NumVecs == 2)
1474        RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1475      else {
1476        SDValue V2 = N->getOperand(2+3);
1477        // If it's a vld3, form a quad D-register and leave the last part as
1478        // an undef.
1479        SDValue V3 = (NumVecs == 3)
1480          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1481          : N->getOperand(3+3);
1482        RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1483      }
1484      Ops.push_back(RegSeq);
1485    }
1486    Ops.push_back(Pred);
1487    Ops.push_back(Reg0); // predicate register
1488    Ops.push_back(Chain);
1489    unsigned Opc = DOpcodes[OpcodeIndex];
1490    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1491  }
1492
1493  if (NumVecs <= 2) {
1494    // Quad registers are directly supported for VST1 and VST2.
1495    unsigned Opc = QOpcodes0[OpcodeIndex];
1496    if (NumVecs == 1) {
1497      Ops.push_back(N->getOperand(3));
1498    } else {
1499      // Form a QQ register.
1500      SDValue Q0 = N->getOperand(3);
1501      SDValue Q1 = N->getOperand(4);
1502      Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1503    }
1504    Ops.push_back(Pred);
1505    Ops.push_back(Reg0); // predicate register
1506    Ops.push_back(Chain);
1507    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1508  }
1509
1510  // Otherwise, quad registers are stored with two separate instructions,
1511  // where one stores the even registers and the other stores the odd registers.
1512
1513  // Form the QQQQ REG_SEQUENCE.
1514  SDValue V0 = N->getOperand(0+3);
1515  SDValue V1 = N->getOperand(1+3);
1516  SDValue V2 = N->getOperand(2+3);
1517  SDValue V3 = (NumVecs == 3)
1518    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1519    : N->getOperand(3+3);
1520  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1521
1522  // Store the even D registers.
1523  Ops.push_back(Reg0); // post-access address offset
1524  Ops.push_back(RegSeq);
1525  Ops.push_back(Pred);
1526  Ops.push_back(Reg0); // predicate register
1527  Ops.push_back(Chain);
1528  unsigned Opc = QOpcodes0[OpcodeIndex];
1529  SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1530                                        MVT::Other, Ops.data(), 7);
1531  Chain = SDValue(VStA, 1);
1532
1533  // Store the odd D registers.
1534  Ops[0] = SDValue(VStA, 0); // MemAddr
1535  Ops[6] = Chain;
1536  Opc = QOpcodes1[OpcodeIndex];
1537  SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1538                                        MVT::Other, Ops.data(), 7);
1539  Chain = SDValue(VStB, 1);
1540  ReplaceUses(SDValue(N, 0), Chain);
1541  return NULL;
1542}
1543
1544SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1545                                         unsigned NumVecs, unsigned *DOpcodes,
1546                                         unsigned *QOpcodes) {
1547  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1548  DebugLoc dl = N->getDebugLoc();
1549
1550  SDValue MemAddr, Align;
1551  if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1552    return NULL;
1553
1554  SDValue Chain = N->getOperand(0);
1555  unsigned Lane =
1556    cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1557  EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1558  bool is64BitVector = VT.is64BitVector();
1559
1560  unsigned Alignment = 0;
1561  if (NumVecs != 3) {
1562    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1563    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1564    if (Alignment > NumBytes)
1565      Alignment = NumBytes;
1566    // Alignment must be a power of two; make sure of that.
1567    Alignment = (Alignment & -Alignment);
1568    if (Alignment == 1)
1569      Alignment = 0;
1570  }
1571  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1572
1573  unsigned OpcodeIndex;
1574  switch (VT.getSimpleVT().SimpleTy) {
1575  default: llvm_unreachable("unhandled vld/vst lane type");
1576    // Double-register operations:
1577  case MVT::v8i8:  OpcodeIndex = 0; break;
1578  case MVT::v4i16: OpcodeIndex = 1; break;
1579  case MVT::v2f32:
1580  case MVT::v2i32: OpcodeIndex = 2; break;
1581    // Quad-register operations:
1582  case MVT::v8i16: OpcodeIndex = 0; break;
1583  case MVT::v4f32:
1584  case MVT::v4i32: OpcodeIndex = 1; break;
1585  }
1586
1587  SDValue Pred = getAL(CurDAG);
1588  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1589
1590  SmallVector<SDValue, 7> Ops;
1591  Ops.push_back(MemAddr);
1592  Ops.push_back(Align);
1593
1594  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1595                                  QOpcodes[OpcodeIndex]);
1596
1597  SDValue SuperReg;
1598  SDValue V0 = N->getOperand(0+3);
1599  SDValue V1 = N->getOperand(1+3);
1600  if (NumVecs == 2) {
1601    if (is64BitVector)
1602      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1603    else
1604      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1605  } else {
1606    SDValue V2 = N->getOperand(2+3);
1607    SDValue V3 = (NumVecs == 3)
1608      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1609      : N->getOperand(3+3);
1610    if (is64BitVector)
1611      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1612    else
1613      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1614  }
1615  Ops.push_back(SuperReg);
1616  Ops.push_back(getI32Imm(Lane));
1617  Ops.push_back(Pred);
1618  Ops.push_back(Reg0);
1619  Ops.push_back(Chain);
1620
1621  if (!IsLoad)
1622    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7);
1623
1624  EVT ResTy;
1625  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1626  if (!is64BitVector)
1627    ResTyElts *= 2;
1628  ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1629
1630  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other,
1631                                         Ops.data(), 7);
1632  SuperReg = SDValue(VLdLn, 0);
1633  Chain = SDValue(VLdLn, 1);
1634
1635  // Extract the subregisters.
1636  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1637  assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1638  unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1639  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1640    ReplaceUses(SDValue(N, Vec),
1641                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1642  ReplaceUses(SDValue(N, NumVecs), Chain);
1643  return NULL;
1644}
1645
1646SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1647                                    unsigned Opc) {
1648  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1649  DebugLoc dl = N->getDebugLoc();
1650  EVT VT = N->getValueType(0);
1651  unsigned FirstTblReg = IsExt ? 2 : 1;
1652
1653  // Form a REG_SEQUENCE to force register allocation.
1654  SDValue RegSeq;
1655  SDValue V0 = N->getOperand(FirstTblReg + 0);
1656  SDValue V1 = N->getOperand(FirstTblReg + 1);
1657  if (NumVecs == 2)
1658    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1659  else {
1660    SDValue V2 = N->getOperand(FirstTblReg + 2);
1661    // If it's a vtbl3, form a quad D-register and leave the last part as
1662    // an undef.
1663    SDValue V3 = (NumVecs == 3)
1664      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1665      : N->getOperand(FirstTblReg + 3);
1666    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1667  }
1668
1669  SmallVector<SDValue, 6> Ops;
1670  if (IsExt)
1671    Ops.push_back(N->getOperand(1));
1672  Ops.push_back(RegSeq);
1673  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1674  Ops.push_back(getAL(CurDAG)); // predicate
1675  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1676  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1677}
1678
1679SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1680                                                     bool isSigned) {
1681  if (!Subtarget->hasV6T2Ops())
1682    return NULL;
1683
1684  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1685    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1686
1687
1688  // For unsigned extracts, check for a shift right and mask
1689  unsigned And_imm = 0;
1690  if (N->getOpcode() == ISD::AND) {
1691    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1692
1693      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1694      if (And_imm & (And_imm + 1))
1695        return NULL;
1696
1697      unsigned Srl_imm = 0;
1698      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1699                                Srl_imm)) {
1700        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1701
1702        unsigned Width = CountTrailingOnes_32(And_imm);
1703        unsigned LSB = Srl_imm;
1704        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1705        SDValue Ops[] = { N->getOperand(0).getOperand(0),
1706                          CurDAG->getTargetConstant(LSB, MVT::i32),
1707                          CurDAG->getTargetConstant(Width, MVT::i32),
1708          getAL(CurDAG), Reg0 };
1709        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1710      }
1711    }
1712    return NULL;
1713  }
1714
1715  // Otherwise, we're looking for a shift of a shift
1716  unsigned Shl_imm = 0;
1717  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1718    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1719    unsigned Srl_imm = 0;
1720    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1721      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1722      unsigned Width = 32 - Srl_imm;
1723      int LSB = Srl_imm - Shl_imm;
1724      if (LSB < 0)
1725        return NULL;
1726      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1727      SDValue Ops[] = { N->getOperand(0).getOperand(0),
1728                        CurDAG->getTargetConstant(LSB, MVT::i32),
1729                        CurDAG->getTargetConstant(Width, MVT::i32),
1730                        getAL(CurDAG), Reg0 };
1731      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1732    }
1733  }
1734  return NULL;
1735}
1736
1737SDNode *ARMDAGToDAGISel::
1738SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1739                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1740  SDValue CPTmp0;
1741  SDValue CPTmp1;
1742  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1743    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1744    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1745    unsigned Opc = 0;
1746    switch (SOShOp) {
1747    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1748    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1749    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1750    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1751    default:
1752      llvm_unreachable("Unknown so_reg opcode!");
1753      break;
1754    }
1755    SDValue SOShImm =
1756      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1757    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1758    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1759    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1760  }
1761  return 0;
1762}
1763
1764SDNode *ARMDAGToDAGISel::
1765SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1766                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1767  SDValue CPTmp0;
1768  SDValue CPTmp1;
1769  SDValue CPTmp2;
1770  if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1771    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1772    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1773    return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1774  }
1775  return 0;
1776}
1777
1778SDNode *ARMDAGToDAGISel::
1779SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1780                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1781  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1782  if (!T)
1783    return 0;
1784
1785  unsigned Opc = 0;
1786  unsigned TrueImm = T->getZExtValue();
1787  bool isSoImm = is_t2_so_imm(TrueImm);
1788  if (isSoImm || TrueImm <= 0xffff) {
1789    Opc = isSoImm ? ARM::t2MOVCCi : ARM::t2MOVCCi16;
1790  } else if (is_t2_so_imm_not(TrueImm)) {
1791    TrueImm = ~TrueImm;
1792    Opc = ARM::t2MVNCCi;
1793  } else if (Subtarget->hasV6T2Ops()) {
1794    // Large immediate.
1795    Opc = ARM::t2MOVCCi32imm;
1796  }
1797
1798  if (Opc) {
1799    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1800    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1801    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1802    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1803  }
1804
1805  return 0;
1806}
1807
1808SDNode *ARMDAGToDAGISel::
1809SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1810                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1811  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1812  if (!T)
1813    return 0;
1814
1815  unsigned Opc = 0;
1816  unsigned TrueImm = T->getZExtValue();
1817  bool isSoImm = is_so_imm(TrueImm);
1818  if (isSoImm || (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff)) {
1819    Opc = isSoImm ? ARM::MOVCCi : ARM::MOVCCi16;
1820  } else if (is_so_imm_not(TrueImm)) {
1821    TrueImm = ~TrueImm;
1822    Opc = ARM::MVNCCi;
1823  } else if (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm)) {
1824    // Large immediate.
1825    Opc = ARM::MOVCCi32imm;
1826  }
1827
1828  if (Opc) {
1829    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1830    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1831    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1832    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1833  }
1834
1835  return 0;
1836}
1837
1838SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1839  EVT VT = N->getValueType(0);
1840  SDValue FalseVal = N->getOperand(0);
1841  SDValue TrueVal  = N->getOperand(1);
1842  SDValue CC = N->getOperand(2);
1843  SDValue CCR = N->getOperand(3);
1844  SDValue InFlag = N->getOperand(4);
1845  assert(CC.getOpcode() == ISD::Constant);
1846  assert(CCR.getOpcode() == ISD::Register);
1847  ARMCC::CondCodes CCVal =
1848    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1849
1850  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1851    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1852    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1853    // Pattern complexity = 18  cost = 1  size = 0
1854    SDValue CPTmp0;
1855    SDValue CPTmp1;
1856    SDValue CPTmp2;
1857    if (Subtarget->isThumb()) {
1858      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1859                                        CCVal, CCR, InFlag);
1860      if (!Res)
1861        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1862                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1863      if (Res)
1864        return Res;
1865    } else {
1866      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1867                                         CCVal, CCR, InFlag);
1868      if (!Res)
1869        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1870                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1871      if (Res)
1872        return Res;
1873    }
1874
1875    // Pattern: (ARMcmov:i32 GPR:i32:$false,
1876    //             (imm:i32)<<P:Pred_so_imm>>:$true,
1877    //             (imm:i32):$cc)
1878    // Emits: (MOVCCi:i32 GPR:i32:$false,
1879    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1880    // Pattern complexity = 10  cost = 1  size = 0
1881    if (Subtarget->isThumb()) {
1882      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
1883                                        CCVal, CCR, InFlag);
1884      if (!Res)
1885        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
1886                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1887      if (Res)
1888        return Res;
1889    } else {
1890      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
1891                                         CCVal, CCR, InFlag);
1892      if (!Res)
1893        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
1894                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1895      if (Res)
1896        return Res;
1897    }
1898  }
1899
1900  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1901  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1902  // Pattern complexity = 6  cost = 1  size = 0
1903  //
1904  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1905  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1906  // Pattern complexity = 6  cost = 11  size = 0
1907  //
1908  // Also FCPYScc and FCPYDcc.
1909  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1910  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1911  unsigned Opc = 0;
1912  switch (VT.getSimpleVT().SimpleTy) {
1913  default: assert(false && "Illegal conditional move type!");
1914    break;
1915  case MVT::i32:
1916    Opc = Subtarget->isThumb()
1917      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1918      : ARM::MOVCCr;
1919    break;
1920  case MVT::f32:
1921    Opc = ARM::VMOVScc;
1922    break;
1923  case MVT::f64:
1924    Opc = ARM::VMOVDcc;
1925    break;
1926  }
1927  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1928}
1929
1930SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1931  // The only time a CONCAT_VECTORS operation can have legal types is when
1932  // two 64-bit vectors are concatenated to a 128-bit vector.
1933  EVT VT = N->getValueType(0);
1934  if (!VT.is128BitVector() || N->getNumOperands() != 2)
1935    llvm_unreachable("unexpected CONCAT_VECTORS");
1936  DebugLoc dl = N->getDebugLoc();
1937  SDValue V0 = N->getOperand(0);
1938  SDValue V1 = N->getOperand(1);
1939  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1940  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1941  const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1942  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1943}
1944
1945SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1946  DebugLoc dl = N->getDebugLoc();
1947
1948  if (N->isMachineOpcode())
1949    return NULL;   // Already selected.
1950
1951  switch (N->getOpcode()) {
1952  default: break;
1953  case ISD::Constant: {
1954    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1955    bool UseCP = true;
1956    if (Subtarget->hasThumb2())
1957      // Thumb2-aware targets have the MOVT instruction, so all immediates can
1958      // be done with MOV + MOVT, at worst.
1959      UseCP = 0;
1960    else {
1961      if (Subtarget->isThumb()) {
1962        UseCP = (Val > 255 &&                          // MOV
1963                 ~Val > 255 &&                         // MOV + MVN
1964                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
1965      } else
1966        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
1967                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
1968                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
1969    }
1970
1971    if (UseCP) {
1972      SDValue CPIdx =
1973        CurDAG->getTargetConstantPool(ConstantInt::get(
1974                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
1975                                      TLI.getPointerTy());
1976
1977      SDNode *ResNode;
1978      if (Subtarget->isThumb1Only()) {
1979        SDValue Pred = getAL(CurDAG);
1980        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1981        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1982        ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1983                                         Ops, 4);
1984      } else {
1985        SDValue Ops[] = {
1986          CPIdx,
1987          CurDAG->getTargetConstant(0, MVT::i32),
1988          getAL(CurDAG),
1989          CurDAG->getRegister(0, MVT::i32),
1990          CurDAG->getEntryNode()
1991        };
1992        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1993                                       Ops, 5);
1994      }
1995      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1996      return NULL;
1997    }
1998
1999    // Other cases are autogenerated.
2000    break;
2001  }
2002  case ISD::FrameIndex: {
2003    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2004    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2005    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2006    if (Subtarget->isThumb1Only()) {
2007      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2008                                  CurDAG->getTargetConstant(0, MVT::i32));
2009    } else {
2010      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2011                      ARM::t2ADDri : ARM::ADDri);
2012      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2013                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2014                        CurDAG->getRegister(0, MVT::i32) };
2015      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2016    }
2017  }
2018  case ISD::SRL:
2019    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2020      return I;
2021    break;
2022  case ISD::SRA:
2023    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2024      return I;
2025    break;
2026  case ISD::MUL:
2027    if (Subtarget->isThumb1Only())
2028      break;
2029    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2030      unsigned RHSV = C->getZExtValue();
2031      if (!RHSV) break;
2032      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2033        unsigned ShImm = Log2_32(RHSV-1);
2034        if (ShImm >= 32)
2035          break;
2036        SDValue V = N->getOperand(0);
2037        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2038        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2039        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2040        if (Subtarget->isThumb()) {
2041          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2042          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2043        } else {
2044          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2045          return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2046        }
2047      }
2048      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2049        unsigned ShImm = Log2_32(RHSV+1);
2050        if (ShImm >= 32)
2051          break;
2052        SDValue V = N->getOperand(0);
2053        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2054        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2055        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2056        if (Subtarget->isThumb()) {
2057          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2058          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2059        } else {
2060          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2061          return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2062        }
2063      }
2064    }
2065    break;
2066  case ISD::AND: {
2067    // Check for unsigned bitfield extract
2068    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2069      return I;
2070
2071    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2072    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2073    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2074    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2075    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2076    EVT VT = N->getValueType(0);
2077    if (VT != MVT::i32)
2078      break;
2079    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2080      ? ARM::t2MOVTi16
2081      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2082    if (!Opc)
2083      break;
2084    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2085    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2086    if (!N1C)
2087      break;
2088    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2089      SDValue N2 = N0.getOperand(1);
2090      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2091      if (!N2C)
2092        break;
2093      unsigned N1CVal = N1C->getZExtValue();
2094      unsigned N2CVal = N2C->getZExtValue();
2095      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2096          (N1CVal & 0xffffU) == 0xffffU &&
2097          (N2CVal & 0xffffU) == 0x0U) {
2098        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2099                                                  MVT::i32);
2100        SDValue Ops[] = { N0.getOperand(0), Imm16,
2101                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2102        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2103      }
2104    }
2105    break;
2106  }
2107  case ARMISD::VMOVRRD:
2108    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2109                                  N->getOperand(0), getAL(CurDAG),
2110                                  CurDAG->getRegister(0, MVT::i32));
2111  case ISD::UMUL_LOHI: {
2112    if (Subtarget->isThumb1Only())
2113      break;
2114    if (Subtarget->isThumb()) {
2115      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2116                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2117                        CurDAG->getRegister(0, MVT::i32) };
2118      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2119    } else {
2120      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2121                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2122                        CurDAG->getRegister(0, MVT::i32) };
2123      return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2124    }
2125  }
2126  case ISD::SMUL_LOHI: {
2127    if (Subtarget->isThumb1Only())
2128      break;
2129    if (Subtarget->isThumb()) {
2130      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2131                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2132      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2133    } else {
2134      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2135                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2136                        CurDAG->getRegister(0, MVT::i32) };
2137      return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2138    }
2139  }
2140  case ISD::LOAD: {
2141    SDNode *ResNode = 0;
2142    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2143      ResNode = SelectT2IndexedLoad(N);
2144    else
2145      ResNode = SelectARMIndexedLoad(N);
2146    if (ResNode)
2147      return ResNode;
2148    // Other cases are autogenerated.
2149    break;
2150  }
2151  case ARMISD::BRCOND: {
2152    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2153    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2154    // Pattern complexity = 6  cost = 1  size = 0
2155
2156    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2157    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2158    // Pattern complexity = 6  cost = 1  size = 0
2159
2160    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2161    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2162    // Pattern complexity = 6  cost = 1  size = 0
2163
2164    unsigned Opc = Subtarget->isThumb() ?
2165      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2166    SDValue Chain = N->getOperand(0);
2167    SDValue N1 = N->getOperand(1);
2168    SDValue N2 = N->getOperand(2);
2169    SDValue N3 = N->getOperand(3);
2170    SDValue InFlag = N->getOperand(4);
2171    assert(N1.getOpcode() == ISD::BasicBlock);
2172    assert(N2.getOpcode() == ISD::Constant);
2173    assert(N3.getOpcode() == ISD::Register);
2174
2175    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2176                               cast<ConstantSDNode>(N2)->getZExtValue()),
2177                               MVT::i32);
2178    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2179    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2180                                             MVT::Flag, Ops, 5);
2181    Chain = SDValue(ResNode, 0);
2182    if (N->getNumValues() == 2) {
2183      InFlag = SDValue(ResNode, 1);
2184      ReplaceUses(SDValue(N, 1), InFlag);
2185    }
2186    ReplaceUses(SDValue(N, 0),
2187                SDValue(Chain.getNode(), Chain.getResNo()));
2188    return NULL;
2189  }
2190  case ARMISD::CMOV:
2191    return SelectCMOVOp(N);
2192  case ARMISD::CNEG: {
2193    EVT VT = N->getValueType(0);
2194    SDValue N0 = N->getOperand(0);
2195    SDValue N1 = N->getOperand(1);
2196    SDValue N2 = N->getOperand(2);
2197    SDValue N3 = N->getOperand(3);
2198    SDValue InFlag = N->getOperand(4);
2199    assert(N2.getOpcode() == ISD::Constant);
2200    assert(N3.getOpcode() == ISD::Register);
2201
2202    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2203                               cast<ConstantSDNode>(N2)->getZExtValue()),
2204                               MVT::i32);
2205    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2206    unsigned Opc = 0;
2207    switch (VT.getSimpleVT().SimpleTy) {
2208    default: assert(false && "Illegal conditional move type!");
2209      break;
2210    case MVT::f32:
2211      Opc = ARM::VNEGScc;
2212      break;
2213    case MVT::f64:
2214      Opc = ARM::VNEGDcc;
2215      break;
2216    }
2217    return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2218  }
2219
2220  case ARMISD::VZIP: {
2221    unsigned Opc = 0;
2222    EVT VT = N->getValueType(0);
2223    switch (VT.getSimpleVT().SimpleTy) {
2224    default: return NULL;
2225    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2226    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2227    case MVT::v2f32:
2228    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2229    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2230    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2231    case MVT::v4f32:
2232    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2233    }
2234    SDValue Pred = getAL(CurDAG);
2235    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2236    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2237    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2238  }
2239  case ARMISD::VUZP: {
2240    unsigned Opc = 0;
2241    EVT VT = N->getValueType(0);
2242    switch (VT.getSimpleVT().SimpleTy) {
2243    default: return NULL;
2244    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2245    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2246    case MVT::v2f32:
2247    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2248    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2249    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2250    case MVT::v4f32:
2251    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2252    }
2253    SDValue Pred = getAL(CurDAG);
2254    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2255    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2256    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2257  }
2258  case ARMISD::VTRN: {
2259    unsigned Opc = 0;
2260    EVT VT = N->getValueType(0);
2261    switch (VT.getSimpleVT().SimpleTy) {
2262    default: return NULL;
2263    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2264    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2265    case MVT::v2f32:
2266    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2267    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2268    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2269    case MVT::v4f32:
2270    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2271    }
2272    SDValue Pred = getAL(CurDAG);
2273    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2274    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2275    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2276  }
2277  case ARMISD::BUILD_VECTOR: {
2278    EVT VecVT = N->getValueType(0);
2279    EVT EltVT = VecVT.getVectorElementType();
2280    unsigned NumElts = VecVT.getVectorNumElements();
2281    if (EltVT == MVT::f64) {
2282      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2283      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2284    }
2285    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2286    if (NumElts == 2)
2287      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2288    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2289    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2290                     N->getOperand(2), N->getOperand(3));
2291  }
2292
2293  case ISD::INTRINSIC_VOID:
2294  case ISD::INTRINSIC_W_CHAIN: {
2295    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2296    switch (IntNo) {
2297    default:
2298      break;
2299
2300    case Intrinsic::arm_neon_vld1: {
2301      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2302                              ARM::VLD1d32, ARM::VLD1d64 };
2303      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2304                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2305      return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2306    }
2307
2308    case Intrinsic::arm_neon_vld2: {
2309      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2310                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2311      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2312                              ARM::VLD2q32Pseudo };
2313      return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2314    }
2315
2316    case Intrinsic::arm_neon_vld3: {
2317      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2318                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2319      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2320                               ARM::VLD3q16Pseudo_UPD,
2321                               ARM::VLD3q32Pseudo_UPD };
2322      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2323                               ARM::VLD3q16oddPseudo_UPD,
2324                               ARM::VLD3q32oddPseudo_UPD };
2325      return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2326    }
2327
2328    case Intrinsic::arm_neon_vld4: {
2329      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2330                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2331      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2332                               ARM::VLD4q16Pseudo_UPD,
2333                               ARM::VLD4q32Pseudo_UPD };
2334      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2335                               ARM::VLD4q16oddPseudo_UPD,
2336                               ARM::VLD4q32oddPseudo_UPD };
2337      return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2338    }
2339
2340    case Intrinsic::arm_neon_vld2lane: {
2341      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2342                              ARM::VLD2LNd32Pseudo };
2343      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2344      return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes);
2345    }
2346
2347    case Intrinsic::arm_neon_vld3lane: {
2348      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2349                              ARM::VLD3LNd32Pseudo };
2350      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2351      return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes);
2352    }
2353
2354    case Intrinsic::arm_neon_vld4lane: {
2355      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2356                              ARM::VLD4LNd32Pseudo };
2357      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2358      return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes);
2359    }
2360
2361    case Intrinsic::arm_neon_vst1: {
2362      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2363                              ARM::VST1d32, ARM::VST1d64 };
2364      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2365                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2366      return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2367    }
2368
2369    case Intrinsic::arm_neon_vst2: {
2370      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2371                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2372      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2373                              ARM::VST2q32Pseudo };
2374      return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2375    }
2376
2377    case Intrinsic::arm_neon_vst3: {
2378      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2379                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2380      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2381                               ARM::VST3q16Pseudo_UPD,
2382                               ARM::VST3q32Pseudo_UPD };
2383      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2384                               ARM::VST3q16oddPseudo_UPD,
2385                               ARM::VST3q32oddPseudo_UPD };
2386      return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2387    }
2388
2389    case Intrinsic::arm_neon_vst4: {
2390      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2391                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2392      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2393                               ARM::VST4q16Pseudo_UPD,
2394                               ARM::VST4q32Pseudo_UPD };
2395      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2396                               ARM::VST4q16oddPseudo_UPD,
2397                               ARM::VST4q32oddPseudo_UPD };
2398      return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2399    }
2400
2401    case Intrinsic::arm_neon_vst2lane: {
2402      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2403                              ARM::VST2LNd32Pseudo };
2404      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2405      return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes);
2406    }
2407
2408    case Intrinsic::arm_neon_vst3lane: {
2409      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2410                              ARM::VST3LNd32Pseudo };
2411      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2412      return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes);
2413    }
2414
2415    case Intrinsic::arm_neon_vst4lane: {
2416      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2417                              ARM::VST4LNd32Pseudo };
2418      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2419      return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes);
2420    }
2421    }
2422    break;
2423  }
2424
2425  case ISD::INTRINSIC_WO_CHAIN: {
2426    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2427    switch (IntNo) {
2428    default:
2429      break;
2430
2431    case Intrinsic::arm_neon_vtbl2:
2432      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2433    case Intrinsic::arm_neon_vtbl3:
2434      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2435    case Intrinsic::arm_neon_vtbl4:
2436      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2437
2438    case Intrinsic::arm_neon_vtbx2:
2439      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2440    case Intrinsic::arm_neon_vtbx3:
2441      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2442    case Intrinsic::arm_neon_vtbx4:
2443      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2444    }
2445    break;
2446  }
2447
2448  case ISD::CONCAT_VECTORS:
2449    return SelectConcatVector(N);
2450  }
2451
2452  return SelectCode(N);
2453}
2454
2455bool ARMDAGToDAGISel::
2456SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2457                             std::vector<SDValue> &OutOps) {
2458  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2459  // Require the address to be in a register.  That is safe for all ARM
2460  // variants and it is hard to do anything much smarter without knowing
2461  // how the operand is used.
2462  OutOps.push_back(Op);
2463  return false;
2464}
2465
2466/// createARMISelDag - This pass converts a legalized DAG into a
2467/// ARM-specific DAG, ready for instruction scheduling.
2468///
2469FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2470                                     CodeGenOpt::Level OptLevel) {
2471  return new ARMDAGToDAGISel(TM, OptLevel);
2472}
2473