ARMISelDAGToDAG.cpp revision 8742867f958221d4a8cbbba7eef309bfe037653c 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMTargetMachine.h"
16#include "llvm/CallingConv.h"
17#include "llvm/DerivedTypes.h"
18#include "llvm/Function.h"
19#include "llvm/Intrinsics.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/CodeGen/SelectionDAGISel.h"
25#include "llvm/CodeGen/SSARegMap.h"
26#include "llvm/Target/TargetLowering.h"
27#include "llvm/Support/Debug.h"
28#include <iostream>
29#include <queue>
30#include <set>
31using namespace llvm;
32
33namespace {
34  class ARMTargetLowering : public TargetLowering {
35  public:
36    ARMTargetLowering(TargetMachine &TM);
37    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
38    virtual const char *getTargetNodeName(unsigned Opcode) const;
39  };
40
41}
42
43ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
44  : TargetLowering(TM) {
45  setOperationAction(ISD::RET,           MVT::Other, Custom);
46  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
47  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
48
49  setSchedulingPreference(SchedulingForRegPressure);
50}
51
52namespace llvm {
53  namespace ARMISD {
54    enum NodeType {
55      // Start the numbering where the builting ops and target ops leave off.
56      FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
57      /// CALL - A direct function call.
58      CALL,
59
60      /// Return with a flag operand.
61      RET_FLAG
62    };
63  }
64}
65
66const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
67  switch (Opcode) {
68  default: return 0;
69  case ARMISD::CALL:          return "ARMISD::CALL";
70  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
71  }
72}
73
74// This transforms a ISD::CALL node into a
75// callseq_star <- ARMISD:CALL <- callseq_end
76// chain
77static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
78  SDOperand Chain    = Op.getOperand(0);
79  unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
80  assert(CallConv == CallingConv::C && "unknown calling convention");
81  bool isVarArg      = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
82  bool isTailCall    = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
83  assert(isTailCall == false && "tail call not supported");
84  SDOperand Callee   = Op.getOperand(4);
85  unsigned NumOps    = (Op.getNumOperands() - 5) / 2;
86
87  // Count how many bytes are to be pushed on the stack. Initially
88  // only the link register.
89  unsigned NumBytes = 4;
90
91  // Add up all the space actually used.
92  for (unsigned i = 4; i < NumOps; ++i)
93    NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
94
95  // Adjust the stack pointer for the new arguments...
96  // These operations are automatically eliminated by the prolog/epilog pass
97  Chain = DAG.getCALLSEQ_START(Chain,
98                               DAG.getConstant(NumBytes, MVT::i32));
99
100  SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32);
101
102  static const unsigned int num_regs = 4;
103  static const unsigned regs[num_regs] = {
104    ARM::R0, ARM::R1, ARM::R2, ARM::R3
105  };
106
107  std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
108  std::vector<SDOperand> MemOpChains;
109
110  for (unsigned i = 0; i != NumOps; ++i) {
111    SDOperand Arg = Op.getOperand(5+2*i);
112    assert(Arg.getValueType() == MVT::i32);
113    if (i < num_regs)
114      RegsToPass.push_back(std::make_pair(regs[i], Arg));
115    else {
116      unsigned ArgOffset = (i - num_regs) * 4;
117      SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
118      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
119      MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
120                                          Arg, PtrOff, DAG.getSrcValue(NULL)));
121    }
122  }
123  if (!MemOpChains.empty())
124    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
125
126  // Build a sequence of copy-to-reg nodes chained together with token chain
127  // and flag operands which copy the outgoing args into the appropriate regs.
128  SDOperand InFlag;
129  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
130    Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
131                             InFlag);
132    InFlag = Chain.getValue(1);
133  }
134
135  std::vector<MVT::ValueType> NodeTys;
136  NodeTys.push_back(MVT::Other);   // Returns a chain
137  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
138
139  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
140  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
141  // node so that legalize doesn't hack it.
142  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
143    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
144
145  // If this is a direct call, pass the chain and the callee.
146  assert (Callee.Val);
147  std::vector<SDOperand> Ops;
148  Ops.push_back(Chain);
149  Ops.push_back(Callee);
150
151  // Add argument registers to the end of the list so that they are known live
152  // into the call.
153  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
154    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
155                                  RegsToPass[i].second.getValueType()));
156
157  unsigned CallOpc = ARMISD::CALL;
158  if (InFlag.Val)
159    Ops.push_back(InFlag);
160  Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
161  InFlag = Chain.getValue(1);
162
163  std::vector<SDOperand> ResultVals;
164  NodeTys.clear();
165
166  // If the call has results, copy the values out of the ret val registers.
167  switch (Op.Val->getValueType(0)) {
168  default: assert(0 && "Unexpected ret value!");
169  case MVT::Other:
170    break;
171  case MVT::i32:
172    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
173    ResultVals.push_back(Chain.getValue(0));
174    NodeTys.push_back(MVT::i32);
175  }
176
177  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
178                      DAG.getConstant(NumBytes, MVT::i32));
179  NodeTys.push_back(MVT::Other);
180
181  if (ResultVals.empty())
182    return Chain;
183
184  ResultVals.push_back(Chain);
185  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
186                              ResultVals.size());
187  return Res.getValue(Op.ResNo);
188}
189
190static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
191  SDOperand Copy;
192  SDOperand Chain = Op.getOperand(0);
193  switch(Op.getNumOperands()) {
194  default:
195    assert(0 && "Do not know how to return this many arguments!");
196    abort();
197  case 1: {
198    SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
199    return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
200  }
201  case 3:
202    Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
203    if (DAG.getMachineFunction().liveout_empty())
204      DAG.getMachineFunction().addLiveOut(ARM::R0);
205    break;
206  }
207
208  //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
209  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
210}
211
212static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
213				      unsigned ArgNo) {
214  MachineFunction &MF = DAG.getMachineFunction();
215  MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
216  assert (ObjectVT == MVT::i32);
217  SDOperand Root = Op.getOperand(0);
218  SSARegMap *RegMap = MF.getSSARegMap();
219
220  unsigned num_regs = 4;
221  static const unsigned REGS[] = {
222    ARM::R0, ARM::R1, ARM::R2, ARM::R3
223  };
224
225  if(ArgNo < num_regs) {
226    unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
227    MF.addLiveIn(REGS[ArgNo], VReg);
228    return DAG.getCopyFromReg(Root, VReg, MVT::i32);
229  } else {
230    // If the argument is actually used, emit a load from the right stack
231      // slot.
232    if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
233      unsigned ArgOffset = (ArgNo - num_regs) * 4;
234
235      MachineFrameInfo *MFI = MF.getFrameInfo();
236      unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
237      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
238      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
239      return DAG.getLoad(ObjectVT, Root, FIN,
240			 DAG.getSrcValue(NULL));
241    } else {
242      // Don't emit a dead load.
243      return DAG.getNode(ISD::UNDEF, ObjectVT);
244    }
245  }
246}
247
248static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
249  MVT::ValueType PtrVT = Op.getValueType();
250  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
251  Constant *C = CP->get();
252  SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
253
254  return CPI;
255}
256
257static SDOperand LowerGlobalAddress(SDOperand Op,
258				    SelectionDAG &DAG) {
259  GlobalValue  *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
260  SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, 2);
261  return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr,
262		     DAG.getSrcValue(NULL));
263}
264
265static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
266  std::vector<SDOperand> ArgValues;
267  SDOperand Root = Op.getOperand(0);
268
269  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
270    SDOperand ArgVal = LowerFORMAL_ARGUMENT(Op, DAG, ArgNo);
271
272    ArgValues.push_back(ArgVal);
273  }
274
275  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
276  assert(!isVarArg);
277
278  ArgValues.push_back(Root);
279
280  // Return the new list of results.
281  std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
282                                    Op.Val->value_end());
283  return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
284}
285
286SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
287  switch (Op.getOpcode()) {
288  default:
289    assert(0 && "Should not custom lower this!");
290    abort();
291  case ISD::ConstantPool:
292    return LowerConstantPool(Op, DAG);
293  case ISD::GlobalAddress:
294    return LowerGlobalAddress(Op, DAG);
295  case ISD::FORMAL_ARGUMENTS:
296    return LowerFORMAL_ARGUMENTS(Op, DAG);
297  case ISD::CALL:
298    return LowerCALL(Op, DAG);
299  case ISD::RET:
300    return LowerRET(Op, DAG);
301  }
302}
303
304//===----------------------------------------------------------------------===//
305// Instruction Selector Implementation
306//===----------------------------------------------------------------------===//
307
308//===--------------------------------------------------------------------===//
309/// ARMDAGToDAGISel - ARM specific code to select ARM machine
310/// instructions for SelectionDAG operations.
311///
312namespace {
313class ARMDAGToDAGISel : public SelectionDAGISel {
314  ARMTargetLowering Lowering;
315
316public:
317  ARMDAGToDAGISel(TargetMachine &TM)
318    : SelectionDAGISel(Lowering), Lowering(TM) {
319  }
320
321  SDNode *Select(SDOperand &Result, SDOperand Op);
322  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
323  bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
324
325  // Include the pieces autogenerated from the target description.
326#include "ARMGenDAGISel.inc"
327};
328
329void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
330  DEBUG(BB->dump());
331
332  DAG.setRoot(SelectRoot(DAG.getRoot()));
333  DAG.RemoveDeadNodes();
334
335  ScheduleAndEmitDAG(DAG);
336}
337
338//register plus/minus 12 bit offset
339bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
340				    SDOperand &Base) {
341  Offset = CurDAG->getTargetConstant(0, MVT::i32);
342  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
343    Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
344  }
345  else
346    Base = N;
347  return true;      //any address fits in a register
348}
349
350SDNode *ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
351  SDNode *N = Op.Val;
352
353  switch (N->getOpcode()) {
354  default:
355    return SelectCode(Result, Op);
356    break;
357  }
358  return NULL;
359}
360
361}  // end anonymous namespace
362
363/// createARMISelDag - This pass converts a legalized DAG into a
364/// ARM-specific DAG, ready for instruction scheduling.
365///
366FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
367  return new ARMDAGToDAGISel(TM);
368}
369