ARMISelDAGToDAG.cpp revision b0117eed84b7899c677a1da5e074fe3a2b7046dd 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(true));
49
50static cl::opt<bool>
51DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
52  cl::desc("Enable / disable ARM integer abs transform"),
53  cl::init(false));
54
55//===--------------------------------------------------------------------===//
56/// ARMDAGToDAGISel - ARM specific code to select ARM machine
57/// instructions for SelectionDAG operations.
58///
59namespace {
60
61enum AddrMode2Type {
62  AM2_BASE, // Simple AM2 (+-imm12)
63  AM2_SHOP  // Shifter-op AM2
64};
65
66class ARMDAGToDAGISel : public SelectionDAGISel {
67  ARMBaseTargetMachine &TM;
68  const ARMBaseInstrInfo *TII;
69
70  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
71  /// make the right decision when generating code for different targets.
72  const ARMSubtarget *Subtarget;
73
74public:
75  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
76                           CodeGenOpt::Level OptLevel)
77    : SelectionDAGISel(tm, OptLevel), TM(tm),
78      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
79      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
80  }
81
82  virtual const char *getPassName() const {
83    return "ARM Instruction Selection";
84  }
85
86  /// getI32Imm - Return a target constant of type i32 with the specified
87  /// value.
88  inline SDValue getI32Imm(unsigned Imm) {
89    return CurDAG->getTargetConstant(Imm, MVT::i32);
90  }
91
92  SDNode *Select(SDNode *N);
93
94
95  bool hasNoVMLxHazardUse(SDNode *N) const;
96  bool isShifterOpProfitable(const SDValue &Shift,
97                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
98  bool SelectRegShifterOperand(SDValue N, SDValue &A,
99                               SDValue &B, SDValue &C,
100                               bool CheckProfitability = true);
101  bool SelectImmShifterOperand(SDValue N, SDValue &A,
102                               SDValue &B, bool CheckProfitability = true);
103  bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
104                                    SDValue &B, SDValue &C) {
105    // Don't apply the profitability check
106    return SelectRegShifterOperand(N, A, B, C, false);
107  }
108  bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
109                                    SDValue &B) {
110    // Don't apply the profitability check
111    return SelectImmShifterOperand(N, A, B, false);
112  }
113
114  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116
117  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
118                                      SDValue &Offset, SDValue &Opc);
119  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
120                           SDValue &Opc) {
121    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
122  }
123
124  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
125                           SDValue &Opc) {
126    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
127  }
128
129  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
130                       SDValue &Opc) {
131    SelectAddrMode2Worker(N, Base, Offset, Opc);
132//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
133    // This always matches one way or another.
134    return true;
135  }
136
137  bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
138                             SDValue &Offset, SDValue &Opc);
139  bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
140                             SDValue &Offset, SDValue &Opc);
141  bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142                             SDValue &Offset, SDValue &Opc);
143  bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
144  bool SelectAddrMode3(SDValue N, SDValue &Base,
145                       SDValue &Offset, SDValue &Opc);
146  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
147                             SDValue &Offset, SDValue &Opc);
148  bool SelectAddrMode5(SDValue N, SDValue &Base,
149                       SDValue &Offset);
150  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151  bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
152
153  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
154
155  // Thumb Addressing Modes:
156  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
157  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
158                             unsigned Scale);
159  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
160  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
161  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
162  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
163                                SDValue &OffImm);
164  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
165                                 SDValue &OffImm);
166  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
167                                 SDValue &OffImm);
168  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
169                                 SDValue &OffImm);
170  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
171
172  // Thumb 2 Addressing Modes:
173  bool SelectT2ShifterOperandReg(SDValue N,
174                                 SDValue &BaseReg, SDValue &Opc);
175  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
176  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
177                            SDValue &OffImm);
178  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
179                                 SDValue &OffImm);
180  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
181                             SDValue &OffReg, SDValue &ShImm);
182
183  inline bool is_so_imm(unsigned Imm) const {
184    return ARM_AM::getSOImmVal(Imm) != -1;
185  }
186
187  inline bool is_so_imm_not(unsigned Imm) const {
188    return ARM_AM::getSOImmVal(~Imm) != -1;
189  }
190
191  inline bool is_t2_so_imm(unsigned Imm) const {
192    return ARM_AM::getT2SOImmVal(Imm) != -1;
193  }
194
195  inline bool is_t2_so_imm_not(unsigned Imm) const {
196    return ARM_AM::getT2SOImmVal(~Imm) != -1;
197  }
198
199  // Include the pieces autogenerated from the target description.
200#include "ARMGenDAGISel.inc"
201
202private:
203  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
204  /// ARM.
205  SDNode *SelectARMIndexedLoad(SDNode *N);
206  SDNode *SelectT2IndexedLoad(SDNode *N);
207
208  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
209  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
210  /// loads of D registers and even subregs and odd subregs of Q registers.
211  /// For NumVecs <= 2, QOpcodes1 is not used.
212  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
213                    unsigned *DOpcodes,
214                    unsigned *QOpcodes0, unsigned *QOpcodes1);
215
216  /// SelectVST - Select NEON store intrinsics.  NumVecs should
217  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
218  /// stores of D registers and even subregs and odd subregs of Q registers.
219  /// For NumVecs <= 2, QOpcodes1 is not used.
220  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
221                    unsigned *DOpcodes,
222                    unsigned *QOpcodes0, unsigned *QOpcodes1);
223
224  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
225  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
226  /// load/store of D registers and Q registers.
227  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
228                          bool isUpdating, unsigned NumVecs,
229                          unsigned *DOpcodes, unsigned *QOpcodes);
230
231  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
232  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
233  /// for loading D registers.  (Q registers are not supported.)
234  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
235                       unsigned *Opcodes);
236
237  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
238  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
239  /// generated to force the table registers to be consecutive.
240  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
241
242  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
244
245  /// SelectCMOVOp - Select CMOV instructions for ARM.
246  SDNode *SelectCMOVOp(SDNode *N);
247  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
248                              ARMCC::CondCodes CCVal, SDValue CCR,
249                              SDValue InFlag);
250  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
251                               ARMCC::CondCodes CCVal, SDValue CCR,
252                               SDValue InFlag);
253  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
254                              ARMCC::CondCodes CCVal, SDValue CCR,
255                              SDValue InFlag);
256  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
257                               ARMCC::CondCodes CCVal, SDValue CCR,
258                               SDValue InFlag);
259
260  // Select special operations if node forms integer ABS pattern
261  SDNode *SelectABSOp(SDNode *N);
262
263  SDNode *SelectConcatVector(SDNode *N);
264
265  SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
266
267  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
268  /// inline asm expressions.
269  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
270                                            char ConstraintCode,
271                                            std::vector<SDValue> &OutOps);
272
273  // Form pairs of consecutive S, D, or Q registers.
274  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
275  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
276  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
277
278  // Form sequences of 4 consecutive S, D, or Q registers.
279  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
280  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
282
283  // Get the alignment operand for a NEON VLD or VST instruction.
284  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
285};
286}
287
288/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
289/// operand. If so Imm will receive the 32-bit value.
290static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
291  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
292    Imm = cast<ConstantSDNode>(N)->getZExtValue();
293    return true;
294  }
295  return false;
296}
297
298// isInt32Immediate - This method tests to see if a constant operand.
299// If so Imm will receive the 32 bit value.
300static bool isInt32Immediate(SDValue N, unsigned &Imm) {
301  return isInt32Immediate(N.getNode(), Imm);
302}
303
304// isOpcWithIntImmediate - This method tests to see if the node is a specific
305// opcode and that it has a immediate integer right operand.
306// If so Imm will receive the 32 bit value.
307static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
308  return N->getOpcode() == Opc &&
309         isInt32Immediate(N->getOperand(1).getNode(), Imm);
310}
311
312/// \brief Check whether a particular node is a constant value representable as
313/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
314///
315/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
316static bool isScaledConstantInRange(SDValue Node, int Scale,
317                                    int RangeMin, int RangeMax,
318                                    int &ScaledConstant) {
319  assert(Scale > 0 && "Invalid scale!");
320
321  // Check that this is a constant.
322  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
323  if (!C)
324    return false;
325
326  ScaledConstant = (int) C->getZExtValue();
327  if ((ScaledConstant % Scale) != 0)
328    return false;
329
330  ScaledConstant /= Scale;
331  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
332}
333
334/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
335/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
336/// least on current ARM implementations) which should be avoidded.
337bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
338  if (OptLevel == CodeGenOpt::None)
339    return true;
340
341  if (!CheckVMLxHazard)
342    return true;
343
344  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
345    return true;
346
347  if (!N->hasOneUse())
348    return false;
349
350  SDNode *Use = *N->use_begin();
351  if (Use->getOpcode() == ISD::CopyToReg)
352    return true;
353  if (Use->isMachineOpcode()) {
354    const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
355    if (MCID.mayStore())
356      return true;
357    unsigned Opcode = MCID.getOpcode();
358    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
359      return true;
360    // vmlx feeding into another vmlx. We actually want to unfold
361    // the use later in the MLxExpansion pass. e.g.
362    // vmla
363    // vmla (stall 8 cycles)
364    //
365    // vmul (5 cycles)
366    // vadd (5 cycles)
367    // vmla
368    // This adds up to about 18 - 19 cycles.
369    //
370    // vmla
371    // vmul (stall 4 cycles)
372    // vadd adds up to about 14 cycles.
373    return TII->isFpMLxInstruction(Opcode);
374  }
375
376  return false;
377}
378
379bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
380                                            ARM_AM::ShiftOpc ShOpcVal,
381                                            unsigned ShAmt) {
382  if (!Subtarget->isCortexA9())
383    return true;
384  if (Shift.hasOneUse())
385    return true;
386  // R << 2 is free.
387  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
388}
389
390bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
391                                              SDValue &BaseReg,
392                                              SDValue &Opc,
393                                              bool CheckProfitability) {
394  if (DisableShifterOp)
395    return false;
396
397  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
398
399  // Don't match base register only case. That is matched to a separate
400  // lower complexity pattern with explicit register operand.
401  if (ShOpcVal == ARM_AM::no_shift) return false;
402
403  BaseReg = N.getOperand(0);
404  unsigned ShImmVal = 0;
405  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
406  if (!RHS) return false;
407  ShImmVal = RHS->getZExtValue() & 31;
408  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
409                                  MVT::i32);
410  return true;
411}
412
413bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
414                                              SDValue &BaseReg,
415                                              SDValue &ShReg,
416                                              SDValue &Opc,
417                                              bool CheckProfitability) {
418  if (DisableShifterOp)
419    return false;
420
421  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
422
423  // Don't match base register only case. That is matched to a separate
424  // lower complexity pattern with explicit register operand.
425  if (ShOpcVal == ARM_AM::no_shift) return false;
426
427  BaseReg = N.getOperand(0);
428  unsigned ShImmVal = 0;
429  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
430  if (RHS) return false;
431
432  ShReg = N.getOperand(1);
433  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
434    return false;
435  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
436                                  MVT::i32);
437  return true;
438}
439
440
441bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
442                                          SDValue &Base,
443                                          SDValue &OffImm) {
444  // Match simple R + imm12 operands.
445
446  // Base only.
447  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
448      !CurDAG->isBaseWithConstantOffset(N)) {
449    if (N.getOpcode() == ISD::FrameIndex) {
450      // Match frame index.
451      int FI = cast<FrameIndexSDNode>(N)->getIndex();
452      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
453      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
454      return true;
455    }
456
457    if (N.getOpcode() == ARMISD::Wrapper &&
458        !(Subtarget->useMovt() &&
459                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
460      Base = N.getOperand(0);
461    } else
462      Base = N;
463    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
464    return true;
465  }
466
467  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
468    int RHSC = (int)RHS->getZExtValue();
469    if (N.getOpcode() == ISD::SUB)
470      RHSC = -RHSC;
471
472    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
473      Base   = N.getOperand(0);
474      if (Base.getOpcode() == ISD::FrameIndex) {
475        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
476        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
477      }
478      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
479      return true;
480    }
481  }
482
483  // Base only.
484  Base = N;
485  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
486  return true;
487}
488
489
490
491bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
492                                      SDValue &Opc) {
493  if (N.getOpcode() == ISD::MUL &&
494      (!Subtarget->isCortexA9() || N.hasOneUse())) {
495    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
496      // X * [3,5,9] -> X + X * [2,4,8] etc.
497      int RHSC = (int)RHS->getZExtValue();
498      if (RHSC & 1) {
499        RHSC = RHSC & ~1;
500        ARM_AM::AddrOpc AddSub = ARM_AM::add;
501        if (RHSC < 0) {
502          AddSub = ARM_AM::sub;
503          RHSC = - RHSC;
504        }
505        if (isPowerOf2_32(RHSC)) {
506          unsigned ShAmt = Log2_32(RHSC);
507          Base = Offset = N.getOperand(0);
508          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
509                                                            ARM_AM::lsl),
510                                          MVT::i32);
511          return true;
512        }
513      }
514    }
515  }
516
517  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
518      // ISD::OR that is equivalent to an ISD::ADD.
519      !CurDAG->isBaseWithConstantOffset(N))
520    return false;
521
522  // Leave simple R +/- imm12 operands for LDRi12
523  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
524    int RHSC;
525    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
526                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
527      return false;
528  }
529
530  // Otherwise this is R +/- [possibly shifted] R.
531  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
532  ARM_AM::ShiftOpc ShOpcVal =
533    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
534  unsigned ShAmt = 0;
535
536  Base   = N.getOperand(0);
537  Offset = N.getOperand(1);
538
539  if (ShOpcVal != ARM_AM::no_shift) {
540    // Check to see if the RHS of the shift is a constant, if not, we can't fold
541    // it.
542    if (ConstantSDNode *Sh =
543           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
544      ShAmt = Sh->getZExtValue();
545      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
546        Offset = N.getOperand(1).getOperand(0);
547      else {
548        ShAmt = 0;
549        ShOpcVal = ARM_AM::no_shift;
550      }
551    } else {
552      ShOpcVal = ARM_AM::no_shift;
553    }
554  }
555
556  // Try matching (R shl C) + (R).
557  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
558      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
559    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
560    if (ShOpcVal != ARM_AM::no_shift) {
561      // Check to see if the RHS of the shift is a constant, if not, we can't
562      // fold it.
563      if (ConstantSDNode *Sh =
564          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
565        ShAmt = Sh->getZExtValue();
566        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
567          Offset = N.getOperand(0).getOperand(0);
568          Base = N.getOperand(1);
569        } else {
570          ShAmt = 0;
571          ShOpcVal = ARM_AM::no_shift;
572        }
573      } else {
574        ShOpcVal = ARM_AM::no_shift;
575      }
576    }
577  }
578
579  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
580                                  MVT::i32);
581  return true;
582}
583
584
585
586
587//-----
588
589AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
590                                                     SDValue &Base,
591                                                     SDValue &Offset,
592                                                     SDValue &Opc) {
593  if (N.getOpcode() == ISD::MUL &&
594      (!Subtarget->isCortexA9() || N.hasOneUse())) {
595    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
596      // X * [3,5,9] -> X + X * [2,4,8] etc.
597      int RHSC = (int)RHS->getZExtValue();
598      if (RHSC & 1) {
599        RHSC = RHSC & ~1;
600        ARM_AM::AddrOpc AddSub = ARM_AM::add;
601        if (RHSC < 0) {
602          AddSub = ARM_AM::sub;
603          RHSC = - RHSC;
604        }
605        if (isPowerOf2_32(RHSC)) {
606          unsigned ShAmt = Log2_32(RHSC);
607          Base = Offset = N.getOperand(0);
608          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
609                                                            ARM_AM::lsl),
610                                          MVT::i32);
611          return AM2_SHOP;
612        }
613      }
614    }
615  }
616
617  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
618      // ISD::OR that is equivalent to an ADD.
619      !CurDAG->isBaseWithConstantOffset(N)) {
620    Base = N;
621    if (N.getOpcode() == ISD::FrameIndex) {
622      int FI = cast<FrameIndexSDNode>(N)->getIndex();
623      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
624    } else if (N.getOpcode() == ARMISD::Wrapper &&
625               !(Subtarget->useMovt() &&
626                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
627      Base = N.getOperand(0);
628    }
629    Offset = CurDAG->getRegister(0, MVT::i32);
630    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
631                                                      ARM_AM::no_shift),
632                                    MVT::i32);
633    return AM2_BASE;
634  }
635
636  // Match simple R +/- imm12 operands.
637  if (N.getOpcode() != ISD::SUB) {
638    int RHSC;
639    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
640                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
641      Base = N.getOperand(0);
642      if (Base.getOpcode() == ISD::FrameIndex) {
643        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
644        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
645      }
646      Offset = CurDAG->getRegister(0, MVT::i32);
647
648      ARM_AM::AddrOpc AddSub = ARM_AM::add;
649      if (RHSC < 0) {
650        AddSub = ARM_AM::sub;
651        RHSC = - RHSC;
652      }
653      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
654                                                        ARM_AM::no_shift),
655                                      MVT::i32);
656      return AM2_BASE;
657    }
658  }
659
660  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
661    // Compute R +/- (R << N) and reuse it.
662    Base = N;
663    Offset = CurDAG->getRegister(0, MVT::i32);
664    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
665                                                      ARM_AM::no_shift),
666                                    MVT::i32);
667    return AM2_BASE;
668  }
669
670  // Otherwise this is R +/- [possibly shifted] R.
671  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
672  ARM_AM::ShiftOpc ShOpcVal =
673    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
674  unsigned ShAmt = 0;
675
676  Base   = N.getOperand(0);
677  Offset = N.getOperand(1);
678
679  if (ShOpcVal != ARM_AM::no_shift) {
680    // Check to see if the RHS of the shift is a constant, if not, we can't fold
681    // it.
682    if (ConstantSDNode *Sh =
683           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
684      ShAmt = Sh->getZExtValue();
685      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
686        Offset = N.getOperand(1).getOperand(0);
687      else {
688        ShAmt = 0;
689        ShOpcVal = ARM_AM::no_shift;
690      }
691    } else {
692      ShOpcVal = ARM_AM::no_shift;
693    }
694  }
695
696  // Try matching (R shl C) + (R).
697  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
698      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
699    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
700    if (ShOpcVal != ARM_AM::no_shift) {
701      // Check to see if the RHS of the shift is a constant, if not, we can't
702      // fold it.
703      if (ConstantSDNode *Sh =
704          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
705        ShAmt = Sh->getZExtValue();
706        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
707          Offset = N.getOperand(0).getOperand(0);
708          Base = N.getOperand(1);
709        } else {
710          ShAmt = 0;
711          ShOpcVal = ARM_AM::no_shift;
712        }
713      } else {
714        ShOpcVal = ARM_AM::no_shift;
715      }
716    }
717  }
718
719  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
720                                  MVT::i32);
721  return AM2_SHOP;
722}
723
724bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
725                                            SDValue &Offset, SDValue &Opc) {
726  unsigned Opcode = Op->getOpcode();
727  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
728    ? cast<LoadSDNode>(Op)->getAddressingMode()
729    : cast<StoreSDNode>(Op)->getAddressingMode();
730  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
731    ? ARM_AM::add : ARM_AM::sub;
732  int Val;
733  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
734    return false;
735
736  Offset = N;
737  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
738  unsigned ShAmt = 0;
739  if (ShOpcVal != ARM_AM::no_shift) {
740    // Check to see if the RHS of the shift is a constant, if not, we can't fold
741    // it.
742    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
743      ShAmt = Sh->getZExtValue();
744      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
745        Offset = N.getOperand(0);
746      else {
747        ShAmt = 0;
748        ShOpcVal = ARM_AM::no_shift;
749      }
750    } else {
751      ShOpcVal = ARM_AM::no_shift;
752    }
753  }
754
755  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
756                                  MVT::i32);
757  return true;
758}
759
760bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
761                                            SDValue &Offset, SDValue &Opc) {
762  unsigned Opcode = Op->getOpcode();
763  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
764    ? cast<LoadSDNode>(Op)->getAddressingMode()
765    : cast<StoreSDNode>(Op)->getAddressingMode();
766  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
767    ? ARM_AM::add : ARM_AM::sub;
768  int Val;
769  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
770    if (AddSub == ARM_AM::sub) Val *= -1;
771    Offset = CurDAG->getRegister(0, MVT::i32);
772    Opc = CurDAG->getTargetConstant(Val, MVT::i32);
773    return true;
774  }
775
776  return false;
777}
778
779
780bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
781                                            SDValue &Offset, SDValue &Opc) {
782  unsigned Opcode = Op->getOpcode();
783  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
784    ? cast<LoadSDNode>(Op)->getAddressingMode()
785    : cast<StoreSDNode>(Op)->getAddressingMode();
786  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
787    ? ARM_AM::add : ARM_AM::sub;
788  int Val;
789  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
790    Offset = CurDAG->getRegister(0, MVT::i32);
791    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
792                                                      ARM_AM::no_shift),
793                                    MVT::i32);
794    return true;
795  }
796
797  return false;
798}
799
800bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
801  Base = N;
802  return true;
803}
804
805bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
806                                      SDValue &Base, SDValue &Offset,
807                                      SDValue &Opc) {
808  if (N.getOpcode() == ISD::SUB) {
809    // X - C  is canonicalize to X + -C, no need to handle it here.
810    Base = N.getOperand(0);
811    Offset = N.getOperand(1);
812    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
813    return true;
814  }
815
816  if (!CurDAG->isBaseWithConstantOffset(N)) {
817    Base = N;
818    if (N.getOpcode() == ISD::FrameIndex) {
819      int FI = cast<FrameIndexSDNode>(N)->getIndex();
820      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
821    }
822    Offset = CurDAG->getRegister(0, MVT::i32);
823    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
824    return true;
825  }
826
827  // If the RHS is +/- imm8, fold into addr mode.
828  int RHSC;
829  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
830                              -256 + 1, 256, RHSC)) { // 8 bits.
831    Base = N.getOperand(0);
832    if (Base.getOpcode() == ISD::FrameIndex) {
833      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
834      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
835    }
836    Offset = CurDAG->getRegister(0, MVT::i32);
837
838    ARM_AM::AddrOpc AddSub = ARM_AM::add;
839    if (RHSC < 0) {
840      AddSub = ARM_AM::sub;
841      RHSC = -RHSC;
842    }
843    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
844    return true;
845  }
846
847  Base = N.getOperand(0);
848  Offset = N.getOperand(1);
849  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
850  return true;
851}
852
853bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
854                                            SDValue &Offset, SDValue &Opc) {
855  unsigned Opcode = Op->getOpcode();
856  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
857    ? cast<LoadSDNode>(Op)->getAddressingMode()
858    : cast<StoreSDNode>(Op)->getAddressingMode();
859  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
860    ? ARM_AM::add : ARM_AM::sub;
861  int Val;
862  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
863    Offset = CurDAG->getRegister(0, MVT::i32);
864    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
865    return true;
866  }
867
868  Offset = N;
869  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
870  return true;
871}
872
873bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
874                                      SDValue &Base, SDValue &Offset) {
875  if (!CurDAG->isBaseWithConstantOffset(N)) {
876    Base = N;
877    if (N.getOpcode() == ISD::FrameIndex) {
878      int FI = cast<FrameIndexSDNode>(N)->getIndex();
879      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
880    } else if (N.getOpcode() == ARMISD::Wrapper &&
881               !(Subtarget->useMovt() &&
882                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
883      Base = N.getOperand(0);
884    }
885    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
886                                       MVT::i32);
887    return true;
888  }
889
890  // If the RHS is +/- imm8, fold into addr mode.
891  int RHSC;
892  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
893                              -256 + 1, 256, RHSC)) {
894    Base = N.getOperand(0);
895    if (Base.getOpcode() == ISD::FrameIndex) {
896      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
897      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
898    }
899
900    ARM_AM::AddrOpc AddSub = ARM_AM::add;
901    if (RHSC < 0) {
902      AddSub = ARM_AM::sub;
903      RHSC = -RHSC;
904    }
905    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
906                                       MVT::i32);
907    return true;
908  }
909
910  Base = N;
911  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
912                                     MVT::i32);
913  return true;
914}
915
916bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
917                                      SDValue &Align) {
918  Addr = N;
919
920  unsigned Alignment = 0;
921  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
922    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
923    // The maximum alignment is equal to the memory size being referenced.
924    unsigned LSNAlign = LSN->getAlignment();
925    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
926    if (LSNAlign >= MemSize && MemSize > 1)
927      Alignment = MemSize;
928  } else {
929    // All other uses of addrmode6 are for intrinsics.  For now just record
930    // the raw alignment value; it will be refined later based on the legal
931    // alignment operands for the intrinsic.
932    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
933  }
934
935  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
936  return true;
937}
938
939bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
940                                            SDValue &Offset) {
941  LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
942  ISD::MemIndexedMode AM = LdSt->getAddressingMode();
943  if (AM != ISD::POST_INC)
944    return false;
945  Offset = N;
946  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
947    if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
948      Offset = CurDAG->getRegister(0, MVT::i32);
949  }
950  return true;
951}
952
953bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
954                                       SDValue &Offset, SDValue &Label) {
955  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
956    Offset = N.getOperand(0);
957    SDValue N1 = N.getOperand(1);
958    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
959                                      MVT::i32);
960    return true;
961  }
962
963  return false;
964}
965
966
967//===----------------------------------------------------------------------===//
968//                         Thumb Addressing Modes
969//===----------------------------------------------------------------------===//
970
971bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
972                                            SDValue &Base, SDValue &Offset){
973  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
974    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
975    if (!NC || !NC->isNullValue())
976      return false;
977
978    Base = Offset = N;
979    return true;
980  }
981
982  Base = N.getOperand(0);
983  Offset = N.getOperand(1);
984  return true;
985}
986
987bool
988ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
989                                       SDValue &Offset, unsigned Scale) {
990  if (Scale == 4) {
991    SDValue TmpBase, TmpOffImm;
992    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
993      return false;  // We want to select tLDRspi / tSTRspi instead.
994
995    if (N.getOpcode() == ARMISD::Wrapper &&
996        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
997      return false;  // We want to select tLDRpci instead.
998  }
999
1000  if (!CurDAG->isBaseWithConstantOffset(N))
1001    return false;
1002
1003  // Thumb does not have [sp, r] address mode.
1004  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1005  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1006  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1007      (RHSR && RHSR->getReg() == ARM::SP))
1008    return false;
1009
1010  // FIXME: Why do we explicitly check for a match here and then return false?
1011  // Presumably to allow something else to match, but shouldn't this be
1012  // documented?
1013  int RHSC;
1014  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1015    return false;
1016
1017  Base = N.getOperand(0);
1018  Offset = N.getOperand(1);
1019  return true;
1020}
1021
1022bool
1023ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1024                                          SDValue &Base,
1025                                          SDValue &Offset) {
1026  return SelectThumbAddrModeRI(N, Base, Offset, 1);
1027}
1028
1029bool
1030ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1031                                          SDValue &Base,
1032                                          SDValue &Offset) {
1033  return SelectThumbAddrModeRI(N, Base, Offset, 2);
1034}
1035
1036bool
1037ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1038                                          SDValue &Base,
1039                                          SDValue &Offset) {
1040  return SelectThumbAddrModeRI(N, Base, Offset, 4);
1041}
1042
1043bool
1044ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1045                                          SDValue &Base, SDValue &OffImm) {
1046  if (Scale == 4) {
1047    SDValue TmpBase, TmpOffImm;
1048    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1049      return false;  // We want to select tLDRspi / tSTRspi instead.
1050
1051    if (N.getOpcode() == ARMISD::Wrapper &&
1052        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1053      return false;  // We want to select tLDRpci instead.
1054  }
1055
1056  if (!CurDAG->isBaseWithConstantOffset(N)) {
1057    if (N.getOpcode() == ARMISD::Wrapper &&
1058        !(Subtarget->useMovt() &&
1059          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1060      Base = N.getOperand(0);
1061    } else {
1062      Base = N;
1063    }
1064
1065    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1066    return true;
1067  }
1068
1069  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1070  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1071  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1072      (RHSR && RHSR->getReg() == ARM::SP)) {
1073    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1074    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1075    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1076    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1077
1078    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1079    if (LHSC != 0 || RHSC != 0) return false;
1080
1081    Base = N;
1082    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1083    return true;
1084  }
1085
1086  // If the RHS is + imm5 * scale, fold into addr mode.
1087  int RHSC;
1088  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1089    Base = N.getOperand(0);
1090    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1091    return true;
1092  }
1093
1094  Base = N.getOperand(0);
1095  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1096  return true;
1097}
1098
1099bool
1100ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1101                                           SDValue &OffImm) {
1102  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1103}
1104
1105bool
1106ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1107                                           SDValue &OffImm) {
1108  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1109}
1110
1111bool
1112ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1113                                           SDValue &OffImm) {
1114  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1115}
1116
1117bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1118                                            SDValue &Base, SDValue &OffImm) {
1119  if (N.getOpcode() == ISD::FrameIndex) {
1120    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1121    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1122    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1123    return true;
1124  }
1125
1126  if (!CurDAG->isBaseWithConstantOffset(N))
1127    return false;
1128
1129  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1130  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1131      (LHSR && LHSR->getReg() == ARM::SP)) {
1132    // If the RHS is + imm8 * scale, fold into addr mode.
1133    int RHSC;
1134    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1135      Base = N.getOperand(0);
1136      if (Base.getOpcode() == ISD::FrameIndex) {
1137        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1138        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1139      }
1140      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1141      return true;
1142    }
1143  }
1144
1145  return false;
1146}
1147
1148
1149//===----------------------------------------------------------------------===//
1150//                        Thumb 2 Addressing Modes
1151//===----------------------------------------------------------------------===//
1152
1153
1154bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1155                                                SDValue &Opc) {
1156  if (DisableShifterOp)
1157    return false;
1158
1159  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1160
1161  // Don't match base register only case. That is matched to a separate
1162  // lower complexity pattern with explicit register operand.
1163  if (ShOpcVal == ARM_AM::no_shift) return false;
1164
1165  BaseReg = N.getOperand(0);
1166  unsigned ShImmVal = 0;
1167  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1168    ShImmVal = RHS->getZExtValue() & 31;
1169    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1170    return true;
1171  }
1172
1173  return false;
1174}
1175
1176bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1177                                            SDValue &Base, SDValue &OffImm) {
1178  // Match simple R + imm12 operands.
1179
1180  // Base only.
1181  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1182      !CurDAG->isBaseWithConstantOffset(N)) {
1183    if (N.getOpcode() == ISD::FrameIndex) {
1184      // Match frame index.
1185      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1186      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1187      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1188      return true;
1189    }
1190
1191    if (N.getOpcode() == ARMISD::Wrapper &&
1192               !(Subtarget->useMovt() &&
1193                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1194      Base = N.getOperand(0);
1195      if (Base.getOpcode() == ISD::TargetConstantPool)
1196        return false;  // We want to select t2LDRpci instead.
1197    } else
1198      Base = N;
1199    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1200    return true;
1201  }
1202
1203  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1204    if (SelectT2AddrModeImm8(N, Base, OffImm))
1205      // Let t2LDRi8 handle (R - imm8).
1206      return false;
1207
1208    int RHSC = (int)RHS->getZExtValue();
1209    if (N.getOpcode() == ISD::SUB)
1210      RHSC = -RHSC;
1211
1212    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1213      Base   = N.getOperand(0);
1214      if (Base.getOpcode() == ISD::FrameIndex) {
1215        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1216        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1217      }
1218      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1219      return true;
1220    }
1221  }
1222
1223  // Base only.
1224  Base = N;
1225  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1226  return true;
1227}
1228
1229bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1230                                           SDValue &Base, SDValue &OffImm) {
1231  // Match simple R - imm8 operands.
1232  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1233      !CurDAG->isBaseWithConstantOffset(N))
1234    return false;
1235
1236  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1237    int RHSC = (int)RHS->getSExtValue();
1238    if (N.getOpcode() == ISD::SUB)
1239      RHSC = -RHSC;
1240
1241    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1242      Base = N.getOperand(0);
1243      if (Base.getOpcode() == ISD::FrameIndex) {
1244        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1245        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1246      }
1247      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1248      return true;
1249    }
1250  }
1251
1252  return false;
1253}
1254
1255bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1256                                                 SDValue &OffImm){
1257  unsigned Opcode = Op->getOpcode();
1258  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1259    ? cast<LoadSDNode>(Op)->getAddressingMode()
1260    : cast<StoreSDNode>(Op)->getAddressingMode();
1261  int RHSC;
1262  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1263    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1264      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1265      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1266    return true;
1267  }
1268
1269  return false;
1270}
1271
1272bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1273                                            SDValue &Base,
1274                                            SDValue &OffReg, SDValue &ShImm) {
1275  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1276  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1277    return false;
1278
1279  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1280  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1281    int RHSC = (int)RHS->getZExtValue();
1282    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1283      return false;
1284    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1285      return false;
1286  }
1287
1288  // Look for (R + R) or (R + (R << [1,2,3])).
1289  unsigned ShAmt = 0;
1290  Base   = N.getOperand(0);
1291  OffReg = N.getOperand(1);
1292
1293  // Swap if it is ((R << c) + R).
1294  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1295  if (ShOpcVal != ARM_AM::lsl) {
1296    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1297    if (ShOpcVal == ARM_AM::lsl)
1298      std::swap(Base, OffReg);
1299  }
1300
1301  if (ShOpcVal == ARM_AM::lsl) {
1302    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1303    // it.
1304    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1305      ShAmt = Sh->getZExtValue();
1306      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1307        OffReg = OffReg.getOperand(0);
1308      else {
1309        ShAmt = 0;
1310        ShOpcVal = ARM_AM::no_shift;
1311      }
1312    } else {
1313      ShOpcVal = ARM_AM::no_shift;
1314    }
1315  }
1316
1317  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1318
1319  return true;
1320}
1321
1322//===--------------------------------------------------------------------===//
1323
1324/// getAL - Returns a ARMCC::AL immediate node.
1325static inline SDValue getAL(SelectionDAG *CurDAG) {
1326  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1327}
1328
1329SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1330  LoadSDNode *LD = cast<LoadSDNode>(N);
1331  ISD::MemIndexedMode AM = LD->getAddressingMode();
1332  if (AM == ISD::UNINDEXED)
1333    return NULL;
1334
1335  EVT LoadedVT = LD->getMemoryVT();
1336  SDValue Offset, AMOpc;
1337  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1338  unsigned Opcode = 0;
1339  bool Match = false;
1340  if (LoadedVT == MVT::i32 && isPre &&
1341      SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1342    Opcode = ARM::LDR_PRE_IMM;
1343    Match = true;
1344  } else if (LoadedVT == MVT::i32 && !isPre &&
1345      SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1346    Opcode = ARM::LDR_POST_IMM;
1347    Match = true;
1348  } else if (LoadedVT == MVT::i32 &&
1349      SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1350    Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1351    Match = true;
1352
1353  } else if (LoadedVT == MVT::i16 &&
1354             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1355    Match = true;
1356    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1357      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1358      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1359  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1360    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1361      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1362        Match = true;
1363        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1364      }
1365    } else {
1366      if (isPre &&
1367          SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1368        Match = true;
1369        Opcode = ARM::LDRB_PRE_IMM;
1370      } else if (!isPre &&
1371                  SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1372        Match = true;
1373        Opcode = ARM::LDRB_POST_IMM;
1374      } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1375        Match = true;
1376        Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1377      }
1378    }
1379  }
1380
1381  if (Match) {
1382    if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1383      SDValue Chain = LD->getChain();
1384      SDValue Base = LD->getBasePtr();
1385      SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1386                       CurDAG->getRegister(0, MVT::i32), Chain };
1387      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1388                                    MVT::i32, MVT::Other, Ops, 5);
1389    } else {
1390      SDValue Chain = LD->getChain();
1391      SDValue Base = LD->getBasePtr();
1392      SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1393                       CurDAG->getRegister(0, MVT::i32), Chain };
1394      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1395                                    MVT::i32, MVT::Other, Ops, 6);
1396    }
1397  }
1398
1399  return NULL;
1400}
1401
1402SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1403  LoadSDNode *LD = cast<LoadSDNode>(N);
1404  ISD::MemIndexedMode AM = LD->getAddressingMode();
1405  if (AM == ISD::UNINDEXED)
1406    return NULL;
1407
1408  EVT LoadedVT = LD->getMemoryVT();
1409  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1410  SDValue Offset;
1411  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1412  unsigned Opcode = 0;
1413  bool Match = false;
1414  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1415    switch (LoadedVT.getSimpleVT().SimpleTy) {
1416    case MVT::i32:
1417      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1418      break;
1419    case MVT::i16:
1420      if (isSExtLd)
1421        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1422      else
1423        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1424      break;
1425    case MVT::i8:
1426    case MVT::i1:
1427      if (isSExtLd)
1428        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1429      else
1430        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1431      break;
1432    default:
1433      return NULL;
1434    }
1435    Match = true;
1436  }
1437
1438  if (Match) {
1439    SDValue Chain = LD->getChain();
1440    SDValue Base = LD->getBasePtr();
1441    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1442                     CurDAG->getRegister(0, MVT::i32), Chain };
1443    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1444                                  MVT::Other, Ops, 5);
1445  }
1446
1447  return NULL;
1448}
1449
1450/// PairSRegs - Form a D register from a pair of S registers.
1451///
1452SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1453  DebugLoc dl = V0.getNode()->getDebugLoc();
1454  SDValue RegClass =
1455    CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1456  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1457  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1458  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1459  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1460}
1461
1462/// PairDRegs - Form a quad register from a pair of D registers.
1463///
1464SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1465  DebugLoc dl = V0.getNode()->getDebugLoc();
1466  SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1467  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1468  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1469  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1470  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1471}
1472
1473/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1474///
1475SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1476  DebugLoc dl = V0.getNode()->getDebugLoc();
1477  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1478  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1479  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1480  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1481  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1482}
1483
1484/// QuadSRegs - Form 4 consecutive S registers.
1485///
1486SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1487                                   SDValue V2, SDValue V3) {
1488  DebugLoc dl = V0.getNode()->getDebugLoc();
1489  SDValue RegClass =
1490    CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1491  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1492  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1493  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1494  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1495  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1496                                    V2, SubReg2, V3, SubReg3 };
1497  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1498}
1499
1500/// QuadDRegs - Form 4 consecutive D registers.
1501///
1502SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1503                                   SDValue V2, SDValue V3) {
1504  DebugLoc dl = V0.getNode()->getDebugLoc();
1505  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1506  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1507  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1508  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1509  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1510  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1511                                    V2, SubReg2, V3, SubReg3 };
1512  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1513}
1514
1515/// QuadQRegs - Form 4 consecutive Q registers.
1516///
1517SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1518                                   SDValue V2, SDValue V3) {
1519  DebugLoc dl = V0.getNode()->getDebugLoc();
1520  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1521  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1522  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1523  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1524  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1525  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1526                                    V2, SubReg2, V3, SubReg3 };
1527  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1528}
1529
1530/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1531/// of a NEON VLD or VST instruction.  The supported values depend on the
1532/// number of registers being loaded.
1533SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1534                                       bool is64BitVector) {
1535  unsigned NumRegs = NumVecs;
1536  if (!is64BitVector && NumVecs < 3)
1537    NumRegs *= 2;
1538
1539  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1540  if (Alignment >= 32 && NumRegs == 4)
1541    Alignment = 32;
1542  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1543    Alignment = 16;
1544  else if (Alignment >= 8)
1545    Alignment = 8;
1546  else
1547    Alignment = 0;
1548
1549  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1550}
1551
1552// Get the register stride update opcode of a VLD/VST instruction that
1553// is otherwise equivalent to the given fixed stride updating instruction.
1554static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1555  switch (Opc) {
1556  default: break;
1557  case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1558  case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1559  case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1560  case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1561  case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1562  case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1563  case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1564  case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1565  case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register;
1566  case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
1567  case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
1568  case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
1569  }
1570  return Opc; // If not one we handle, return it unchanged.
1571}
1572
1573SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1574                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1575                                   unsigned *QOpcodes1) {
1576  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1577  DebugLoc dl = N->getDebugLoc();
1578
1579  SDValue MemAddr, Align;
1580  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1581  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1582    return NULL;
1583
1584  SDValue Chain = N->getOperand(0);
1585  EVT VT = N->getValueType(0);
1586  bool is64BitVector = VT.is64BitVector();
1587  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1588
1589  unsigned OpcodeIndex;
1590  switch (VT.getSimpleVT().SimpleTy) {
1591  default: llvm_unreachable("unhandled vld type");
1592    // Double-register operations:
1593  case MVT::v8i8:  OpcodeIndex = 0; break;
1594  case MVT::v4i16: OpcodeIndex = 1; break;
1595  case MVT::v2f32:
1596  case MVT::v2i32: OpcodeIndex = 2; break;
1597  case MVT::v1i64: OpcodeIndex = 3; break;
1598    // Quad-register operations:
1599  case MVT::v16i8: OpcodeIndex = 0; break;
1600  case MVT::v8i16: OpcodeIndex = 1; break;
1601  case MVT::v4f32:
1602  case MVT::v4i32: OpcodeIndex = 2; break;
1603  case MVT::v2i64: OpcodeIndex = 3;
1604    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1605    break;
1606  }
1607
1608  EVT ResTy;
1609  if (NumVecs == 1)
1610    ResTy = VT;
1611  else {
1612    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1613    if (!is64BitVector)
1614      ResTyElts *= 2;
1615    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1616  }
1617  std::vector<EVT> ResTys;
1618  ResTys.push_back(ResTy);
1619  if (isUpdating)
1620    ResTys.push_back(MVT::i32);
1621  ResTys.push_back(MVT::Other);
1622
1623  SDValue Pred = getAL(CurDAG);
1624  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1625  SDNode *VLd;
1626  SmallVector<SDValue, 7> Ops;
1627
1628  // Double registers and VLD1/VLD2 quad registers are directly supported.
1629  if (is64BitVector || NumVecs <= 2) {
1630    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1631                    QOpcodes0[OpcodeIndex]);
1632    Ops.push_back(MemAddr);
1633    Ops.push_back(Align);
1634    if (isUpdating) {
1635      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1636      // FIXME: VLD1 fixed increment doesn't need Reg0. Remove the reg0
1637      // case entirely when the rest are updated to that form, too.
1638      // Do that before committing this change. Likewise, the opcode
1639      // update call will become unconditional.
1640      if (NumVecs == 1 && !isa<ConstantSDNode>(Inc.getNode()))
1641        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1642      if (NumVecs != 1 || !isa<ConstantSDNode>(Inc.getNode()))
1643        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1644    }
1645    Ops.push_back(Pred);
1646    Ops.push_back(Reg0);
1647    Ops.push_back(Chain);
1648    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1649
1650  } else {
1651    // Otherwise, quad registers are loaded with two separate instructions,
1652    // where one loads the even registers and the other loads the odd registers.
1653    EVT AddrTy = MemAddr.getValueType();
1654
1655    // Load the even subregs.  This is always an updating load, so that it
1656    // provides the address to the second load for the odd subregs.
1657    SDValue ImplDef =
1658      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1659    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1660    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1661                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1662    Chain = SDValue(VLdA, 2);
1663
1664    // Load the odd subregs.
1665    Ops.push_back(SDValue(VLdA, 1));
1666    Ops.push_back(Align);
1667    if (isUpdating) {
1668      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1669      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1670             "only constant post-increment update allowed for VLD3/4");
1671      (void)Inc;
1672      Ops.push_back(Reg0);
1673    }
1674    Ops.push_back(SDValue(VLdA, 0));
1675    Ops.push_back(Pred);
1676    Ops.push_back(Reg0);
1677    Ops.push_back(Chain);
1678    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1679                                 Ops.data(), Ops.size());
1680  }
1681
1682  // Transfer memoperands.
1683  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1684  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1685  cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1686
1687  if (NumVecs == 1)
1688    return VLd;
1689
1690  // Extract out the subregisters.
1691  SDValue SuperReg = SDValue(VLd, 0);
1692  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1693         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1694  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1695  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1696    ReplaceUses(SDValue(N, Vec),
1697                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1698  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1699  if (isUpdating)
1700    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1701  return NULL;
1702}
1703
1704SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1705                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1706                                   unsigned *QOpcodes1) {
1707  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1708  DebugLoc dl = N->getDebugLoc();
1709
1710  SDValue MemAddr, Align;
1711  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1712  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1713  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1714    return NULL;
1715
1716  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1717  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1718
1719  SDValue Chain = N->getOperand(0);
1720  EVT VT = N->getOperand(Vec0Idx).getValueType();
1721  bool is64BitVector = VT.is64BitVector();
1722  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1723
1724  unsigned OpcodeIndex;
1725  switch (VT.getSimpleVT().SimpleTy) {
1726  default: llvm_unreachable("unhandled vst type");
1727    // Double-register operations:
1728  case MVT::v8i8:  OpcodeIndex = 0; break;
1729  case MVT::v4i16: OpcodeIndex = 1; break;
1730  case MVT::v2f32:
1731  case MVT::v2i32: OpcodeIndex = 2; break;
1732  case MVT::v1i64: OpcodeIndex = 3; break;
1733    // Quad-register operations:
1734  case MVT::v16i8: OpcodeIndex = 0; break;
1735  case MVT::v8i16: OpcodeIndex = 1; break;
1736  case MVT::v4f32:
1737  case MVT::v4i32: OpcodeIndex = 2; break;
1738  case MVT::v2i64: OpcodeIndex = 3;
1739    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1740    break;
1741  }
1742
1743  std::vector<EVT> ResTys;
1744  if (isUpdating)
1745    ResTys.push_back(MVT::i32);
1746  ResTys.push_back(MVT::Other);
1747
1748  SDValue Pred = getAL(CurDAG);
1749  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1750  SmallVector<SDValue, 7> Ops;
1751
1752  // Double registers and VST1/VST2 quad registers are directly supported.
1753  if (is64BitVector || NumVecs <= 2) {
1754    SDValue SrcReg;
1755    if (NumVecs == 1) {
1756      SrcReg = N->getOperand(Vec0Idx);
1757    } else if (is64BitVector) {
1758      // Form a REG_SEQUENCE to force register allocation.
1759      SDValue V0 = N->getOperand(Vec0Idx + 0);
1760      SDValue V1 = N->getOperand(Vec0Idx + 1);
1761      if (NumVecs == 2)
1762        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1763      else {
1764        SDValue V2 = N->getOperand(Vec0Idx + 2);
1765        // If it's a vst3, form a quad D-register and leave the last part as
1766        // an undef.
1767        SDValue V3 = (NumVecs == 3)
1768          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1769          : N->getOperand(Vec0Idx + 3);
1770        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1771      }
1772    } else {
1773      // Form a QQ register.
1774      SDValue Q0 = N->getOperand(Vec0Idx);
1775      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1776      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1777    }
1778
1779    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1780                    QOpcodes0[OpcodeIndex]);
1781    Ops.push_back(MemAddr);
1782    Ops.push_back(Align);
1783    if (isUpdating) {
1784      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1785      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1786    }
1787    Ops.push_back(SrcReg);
1788    Ops.push_back(Pred);
1789    Ops.push_back(Reg0);
1790    Ops.push_back(Chain);
1791    SDNode *VSt =
1792      CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1793
1794    // Transfer memoperands.
1795    cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1796
1797    return VSt;
1798  }
1799
1800  // Otherwise, quad registers are stored with two separate instructions,
1801  // where one stores the even registers and the other stores the odd registers.
1802
1803  // Form the QQQQ REG_SEQUENCE.
1804  SDValue V0 = N->getOperand(Vec0Idx + 0);
1805  SDValue V1 = N->getOperand(Vec0Idx + 1);
1806  SDValue V2 = N->getOperand(Vec0Idx + 2);
1807  SDValue V3 = (NumVecs == 3)
1808    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1809    : N->getOperand(Vec0Idx + 3);
1810  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1811
1812  // Store the even D registers.  This is always an updating store, so that it
1813  // provides the address to the second store for the odd subregs.
1814  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1815  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1816                                        MemAddr.getValueType(),
1817                                        MVT::Other, OpsA, 7);
1818  cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1819  Chain = SDValue(VStA, 1);
1820
1821  // Store the odd D registers.
1822  Ops.push_back(SDValue(VStA, 0));
1823  Ops.push_back(Align);
1824  if (isUpdating) {
1825    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1826    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1827           "only constant post-increment update allowed for VST3/4");
1828    (void)Inc;
1829    Ops.push_back(Reg0);
1830  }
1831  Ops.push_back(RegSeq);
1832  Ops.push_back(Pred);
1833  Ops.push_back(Reg0);
1834  Ops.push_back(Chain);
1835  SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1836                                        Ops.data(), Ops.size());
1837  cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1838  return VStB;
1839}
1840
1841SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1842                                         bool isUpdating, unsigned NumVecs,
1843                                         unsigned *DOpcodes,
1844                                         unsigned *QOpcodes) {
1845  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1846  DebugLoc dl = N->getDebugLoc();
1847
1848  SDValue MemAddr, Align;
1849  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1850  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1851  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1852    return NULL;
1853
1854  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1855  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1856
1857  SDValue Chain = N->getOperand(0);
1858  unsigned Lane =
1859    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1860  EVT VT = N->getOperand(Vec0Idx).getValueType();
1861  bool is64BitVector = VT.is64BitVector();
1862
1863  unsigned Alignment = 0;
1864  if (NumVecs != 3) {
1865    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1866    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1867    if (Alignment > NumBytes)
1868      Alignment = NumBytes;
1869    if (Alignment < 8 && Alignment < NumBytes)
1870      Alignment = 0;
1871    // Alignment must be a power of two; make sure of that.
1872    Alignment = (Alignment & -Alignment);
1873    if (Alignment == 1)
1874      Alignment = 0;
1875  }
1876  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1877
1878  unsigned OpcodeIndex;
1879  switch (VT.getSimpleVT().SimpleTy) {
1880  default: llvm_unreachable("unhandled vld/vst lane type");
1881    // Double-register operations:
1882  case MVT::v8i8:  OpcodeIndex = 0; break;
1883  case MVT::v4i16: OpcodeIndex = 1; break;
1884  case MVT::v2f32:
1885  case MVT::v2i32: OpcodeIndex = 2; break;
1886    // Quad-register operations:
1887  case MVT::v8i16: OpcodeIndex = 0; break;
1888  case MVT::v4f32:
1889  case MVT::v4i32: OpcodeIndex = 1; break;
1890  }
1891
1892  std::vector<EVT> ResTys;
1893  if (IsLoad) {
1894    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1895    if (!is64BitVector)
1896      ResTyElts *= 2;
1897    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1898                                      MVT::i64, ResTyElts));
1899  }
1900  if (isUpdating)
1901    ResTys.push_back(MVT::i32);
1902  ResTys.push_back(MVT::Other);
1903
1904  SDValue Pred = getAL(CurDAG);
1905  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1906
1907  SmallVector<SDValue, 8> Ops;
1908  Ops.push_back(MemAddr);
1909  Ops.push_back(Align);
1910  if (isUpdating) {
1911    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1912    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1913  }
1914
1915  SDValue SuperReg;
1916  SDValue V0 = N->getOperand(Vec0Idx + 0);
1917  SDValue V1 = N->getOperand(Vec0Idx + 1);
1918  if (NumVecs == 2) {
1919    if (is64BitVector)
1920      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1921    else
1922      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1923  } else {
1924    SDValue V2 = N->getOperand(Vec0Idx + 2);
1925    SDValue V3 = (NumVecs == 3)
1926      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1927      : N->getOperand(Vec0Idx + 3);
1928    if (is64BitVector)
1929      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1930    else
1931      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1932  }
1933  Ops.push_back(SuperReg);
1934  Ops.push_back(getI32Imm(Lane));
1935  Ops.push_back(Pred);
1936  Ops.push_back(Reg0);
1937  Ops.push_back(Chain);
1938
1939  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1940                                  QOpcodes[OpcodeIndex]);
1941  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1942                                         Ops.data(), Ops.size());
1943  cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1944  if (!IsLoad)
1945    return VLdLn;
1946
1947  // Extract the subregisters.
1948  SuperReg = SDValue(VLdLn, 0);
1949  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1950         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1951  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1952  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1953    ReplaceUses(SDValue(N, Vec),
1954                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1955  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1956  if (isUpdating)
1957    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1958  return NULL;
1959}
1960
1961SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1962                                      unsigned NumVecs, unsigned *Opcodes) {
1963  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1964  DebugLoc dl = N->getDebugLoc();
1965
1966  SDValue MemAddr, Align;
1967  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1968    return NULL;
1969
1970  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1971  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1972
1973  SDValue Chain = N->getOperand(0);
1974  EVT VT = N->getValueType(0);
1975
1976  unsigned Alignment = 0;
1977  if (NumVecs != 3) {
1978    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1979    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1980    if (Alignment > NumBytes)
1981      Alignment = NumBytes;
1982    if (Alignment < 8 && Alignment < NumBytes)
1983      Alignment = 0;
1984    // Alignment must be a power of two; make sure of that.
1985    Alignment = (Alignment & -Alignment);
1986    if (Alignment == 1)
1987      Alignment = 0;
1988  }
1989  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1990
1991  unsigned OpcodeIndex;
1992  switch (VT.getSimpleVT().SimpleTy) {
1993  default: llvm_unreachable("unhandled vld-dup type");
1994  case MVT::v8i8:  OpcodeIndex = 0; break;
1995  case MVT::v4i16: OpcodeIndex = 1; break;
1996  case MVT::v2f32:
1997  case MVT::v2i32: OpcodeIndex = 2; break;
1998  }
1999
2000  SDValue Pred = getAL(CurDAG);
2001  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2002  SDValue SuperReg;
2003  unsigned Opc = Opcodes[OpcodeIndex];
2004  SmallVector<SDValue, 6> Ops;
2005  Ops.push_back(MemAddr);
2006  Ops.push_back(Align);
2007  if (isUpdating) {
2008    SDValue Inc = N->getOperand(2);
2009    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2010  }
2011  Ops.push_back(Pred);
2012  Ops.push_back(Reg0);
2013  Ops.push_back(Chain);
2014
2015  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2016  std::vector<EVT> ResTys;
2017  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2018  if (isUpdating)
2019    ResTys.push_back(MVT::i32);
2020  ResTys.push_back(MVT::Other);
2021  SDNode *VLdDup =
2022    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2023  cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2024  SuperReg = SDValue(VLdDup, 0);
2025
2026  // Extract the subregisters.
2027  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2028  unsigned SubIdx = ARM::dsub_0;
2029  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2030    ReplaceUses(SDValue(N, Vec),
2031                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2032  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2033  if (isUpdating)
2034    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2035  return NULL;
2036}
2037
2038SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2039                                    unsigned Opc) {
2040  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2041  DebugLoc dl = N->getDebugLoc();
2042  EVT VT = N->getValueType(0);
2043  unsigned FirstTblReg = IsExt ? 2 : 1;
2044
2045  // Form a REG_SEQUENCE to force register allocation.
2046  SDValue RegSeq;
2047  SDValue V0 = N->getOperand(FirstTblReg + 0);
2048  SDValue V1 = N->getOperand(FirstTblReg + 1);
2049  if (NumVecs == 2)
2050    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2051  else {
2052    SDValue V2 = N->getOperand(FirstTblReg + 2);
2053    // If it's a vtbl3, form a quad D-register and leave the last part as
2054    // an undef.
2055    SDValue V3 = (NumVecs == 3)
2056      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2057      : N->getOperand(FirstTblReg + 3);
2058    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2059  }
2060
2061  SmallVector<SDValue, 6> Ops;
2062  if (IsExt)
2063    Ops.push_back(N->getOperand(1));
2064  Ops.push_back(RegSeq);
2065  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2066  Ops.push_back(getAL(CurDAG)); // predicate
2067  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2068  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2069}
2070
2071SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2072                                                     bool isSigned) {
2073  if (!Subtarget->hasV6T2Ops())
2074    return NULL;
2075
2076  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2077    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2078
2079
2080  // For unsigned extracts, check for a shift right and mask
2081  unsigned And_imm = 0;
2082  if (N->getOpcode() == ISD::AND) {
2083    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2084
2085      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2086      if (And_imm & (And_imm + 1))
2087        return NULL;
2088
2089      unsigned Srl_imm = 0;
2090      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2091                                Srl_imm)) {
2092        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2093
2094        // Note: The width operand is encoded as width-1.
2095        unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2096        unsigned LSB = Srl_imm;
2097        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2098        SDValue Ops[] = { N->getOperand(0).getOperand(0),
2099                          CurDAG->getTargetConstant(LSB, MVT::i32),
2100                          CurDAG->getTargetConstant(Width, MVT::i32),
2101          getAL(CurDAG), Reg0 };
2102        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2103      }
2104    }
2105    return NULL;
2106  }
2107
2108  // Otherwise, we're looking for a shift of a shift
2109  unsigned Shl_imm = 0;
2110  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2111    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2112    unsigned Srl_imm = 0;
2113    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2114      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2115      // Note: The width operand is encoded as width-1.
2116      unsigned Width = 32 - Srl_imm - 1;
2117      int LSB = Srl_imm - Shl_imm;
2118      if (LSB < 0)
2119        return NULL;
2120      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2121      SDValue Ops[] = { N->getOperand(0).getOperand(0),
2122                        CurDAG->getTargetConstant(LSB, MVT::i32),
2123                        CurDAG->getTargetConstant(Width, MVT::i32),
2124                        getAL(CurDAG), Reg0 };
2125      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2126    }
2127  }
2128  return NULL;
2129}
2130
2131SDNode *ARMDAGToDAGISel::
2132SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2133                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2134  SDValue CPTmp0;
2135  SDValue CPTmp1;
2136  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2137    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2138    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2139    unsigned Opc = 0;
2140    switch (SOShOp) {
2141    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2142    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2143    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2144    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2145    default:
2146      llvm_unreachable("Unknown so_reg opcode!");
2147      break;
2148    }
2149    SDValue SOShImm =
2150      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2151    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2152    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2153    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2154  }
2155  return 0;
2156}
2157
2158SDNode *ARMDAGToDAGISel::
2159SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2160                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2161  SDValue CPTmp0;
2162  SDValue CPTmp1;
2163  SDValue CPTmp2;
2164  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2165    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2166    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2167    return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2168  }
2169
2170  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2171    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2172    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2173    return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2174  }
2175  return 0;
2176}
2177
2178SDNode *ARMDAGToDAGISel::
2179SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2180                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2181  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2182  if (!T)
2183    return 0;
2184
2185  unsigned Opc = 0;
2186  unsigned TrueImm = T->getZExtValue();
2187  if (is_t2_so_imm(TrueImm)) {
2188    Opc = ARM::t2MOVCCi;
2189  } else if (TrueImm <= 0xffff) {
2190    Opc = ARM::t2MOVCCi16;
2191  } else if (is_t2_so_imm_not(TrueImm)) {
2192    TrueImm = ~TrueImm;
2193    Opc = ARM::t2MVNCCi;
2194  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2195    // Large immediate.
2196    Opc = ARM::t2MOVCCi32imm;
2197  }
2198
2199  if (Opc) {
2200    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2201    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2202    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2203    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2204  }
2205
2206  return 0;
2207}
2208
2209SDNode *ARMDAGToDAGISel::
2210SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2211                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2212  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2213  if (!T)
2214    return 0;
2215
2216  unsigned Opc = 0;
2217  unsigned TrueImm = T->getZExtValue();
2218  bool isSoImm = is_so_imm(TrueImm);
2219  if (isSoImm) {
2220    Opc = ARM::MOVCCi;
2221  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2222    Opc = ARM::MOVCCi16;
2223  } else if (is_so_imm_not(TrueImm)) {
2224    TrueImm = ~TrueImm;
2225    Opc = ARM::MVNCCi;
2226  } else if (TrueVal.getNode()->hasOneUse() &&
2227             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2228    // Large immediate.
2229    Opc = ARM::MOVCCi32imm;
2230  }
2231
2232  if (Opc) {
2233    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2234    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2235    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2236    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2237  }
2238
2239  return 0;
2240}
2241
2242SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2243  EVT VT = N->getValueType(0);
2244  SDValue FalseVal = N->getOperand(0);
2245  SDValue TrueVal  = N->getOperand(1);
2246  SDValue CC = N->getOperand(2);
2247  SDValue CCR = N->getOperand(3);
2248  SDValue InFlag = N->getOperand(4);
2249  assert(CC.getOpcode() == ISD::Constant);
2250  assert(CCR.getOpcode() == ISD::Register);
2251  ARMCC::CondCodes CCVal =
2252    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2253
2254  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2255    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2256    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2257    // Pattern complexity = 18  cost = 1  size = 0
2258    SDValue CPTmp0;
2259    SDValue CPTmp1;
2260    SDValue CPTmp2;
2261    if (Subtarget->isThumb()) {
2262      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2263                                        CCVal, CCR, InFlag);
2264      if (!Res)
2265        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2266                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2267      if (Res)
2268        return Res;
2269    } else {
2270      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2271                                         CCVal, CCR, InFlag);
2272      if (!Res)
2273        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2274                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2275      if (Res)
2276        return Res;
2277    }
2278
2279    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2280    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2281    //             (imm:i32):$cc)
2282    // Emits: (MOVCCi:i32 GPR:i32:$false,
2283    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2284    // Pattern complexity = 10  cost = 1  size = 0
2285    if (Subtarget->isThumb()) {
2286      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2287                                        CCVal, CCR, InFlag);
2288      if (!Res)
2289        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2290                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2291      if (Res)
2292        return Res;
2293    } else {
2294      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2295                                         CCVal, CCR, InFlag);
2296      if (!Res)
2297        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2298                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2299      if (Res)
2300        return Res;
2301    }
2302  }
2303
2304  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2305  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2306  // Pattern complexity = 6  cost = 1  size = 0
2307  //
2308  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2309  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2310  // Pattern complexity = 6  cost = 11  size = 0
2311  //
2312  // Also VMOVScc and VMOVDcc.
2313  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2314  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2315  unsigned Opc = 0;
2316  switch (VT.getSimpleVT().SimpleTy) {
2317  default: assert(false && "Illegal conditional move type!");
2318    break;
2319  case MVT::i32:
2320    Opc = Subtarget->isThumb()
2321      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2322      : ARM::MOVCCr;
2323    break;
2324  case MVT::f32:
2325    Opc = ARM::VMOVScc;
2326    break;
2327  case MVT::f64:
2328    Opc = ARM::VMOVDcc;
2329    break;
2330  }
2331  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2332}
2333
2334/// Target-specific DAG combining for ISD::XOR.
2335/// Target-independent combining lowers SELECT_CC nodes of the form
2336/// select_cc setg[ge] X,  0,  X, -X
2337/// select_cc setgt    X, -1,  X, -X
2338/// select_cc setl[te] X,  0, -X,  X
2339/// select_cc setlt    X,  1, -X,  X
2340/// which represent Integer ABS into:
2341/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2342/// ARM instruction selection detects the latter and matches it to
2343/// ARM::ABS or ARM::t2ABS machine node.
2344SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2345  SDValue XORSrc0 = N->getOperand(0);
2346  SDValue XORSrc1 = N->getOperand(1);
2347  EVT VT = N->getValueType(0);
2348
2349  if (DisableARMIntABS)
2350    return NULL;
2351
2352  if (Subtarget->isThumb1Only())
2353    return NULL;
2354
2355  if (XORSrc0.getOpcode() != ISD::ADD ||
2356    XORSrc1.getOpcode() != ISD::SRA)
2357    return NULL;
2358
2359  SDValue ADDSrc0 = XORSrc0.getOperand(0);
2360  SDValue ADDSrc1 = XORSrc0.getOperand(1);
2361  SDValue SRASrc0 = XORSrc1.getOperand(0);
2362  SDValue SRASrc1 = XORSrc1.getOperand(1);
2363  ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
2364  EVT XType = SRASrc0.getValueType();
2365  unsigned Size = XType.getSizeInBits() - 1;
2366
2367  if (ADDSrc1 == XORSrc1  &&
2368      ADDSrc0 == SRASrc0 &&
2369      XType.isInteger() &&
2370      SRAConstant != NULL &&
2371      Size == SRAConstant->getZExtValue()) {
2372
2373    unsigned Opcode = ARM::ABS;
2374    if (Subtarget->isThumb2())
2375      Opcode = ARM::t2ABS;
2376
2377    return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2378  }
2379
2380  return NULL;
2381}
2382
2383SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2384  // The only time a CONCAT_VECTORS operation can have legal types is when
2385  // two 64-bit vectors are concatenated to a 128-bit vector.
2386  EVT VT = N->getValueType(0);
2387  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2388    llvm_unreachable("unexpected CONCAT_VECTORS");
2389  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2390}
2391
2392SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2393  SmallVector<SDValue, 6> Ops;
2394  Ops.push_back(Node->getOperand(1)); // Ptr
2395  Ops.push_back(Node->getOperand(2)); // Low part of Val1
2396  Ops.push_back(Node->getOperand(3)); // High part of Val1
2397  if (Opc == ARM::ATOMCMPXCHG6432) {
2398    Ops.push_back(Node->getOperand(4)); // Low part of Val2
2399    Ops.push_back(Node->getOperand(5)); // High part of Val2
2400  }
2401  Ops.push_back(Node->getOperand(0)); // Chain
2402  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2403  MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2404  SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2405                                           MVT::i32, MVT::i32, MVT::Other,
2406                                           Ops.data() ,Ops.size());
2407  cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2408  return ResNode;
2409}
2410
2411SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2412  DebugLoc dl = N->getDebugLoc();
2413
2414  if (N->isMachineOpcode())
2415    return NULL;   // Already selected.
2416
2417  switch (N->getOpcode()) {
2418  default: break;
2419  case ISD::XOR: {
2420    // Select special operations if XOR node forms integer ABS pattern
2421    SDNode *ResNode = SelectABSOp(N);
2422    if (ResNode)
2423      return ResNode;
2424    // Other cases are autogenerated.
2425    break;
2426  }
2427  case ISD::Constant: {
2428    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2429    bool UseCP = true;
2430    if (Subtarget->hasThumb2())
2431      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2432      // be done with MOV + MOVT, at worst.
2433      UseCP = 0;
2434    else {
2435      if (Subtarget->isThumb()) {
2436        UseCP = (Val > 255 &&                          // MOV
2437                 ~Val > 255 &&                         // MOV + MVN
2438                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2439      } else
2440        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2441                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2442                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2443    }
2444
2445    if (UseCP) {
2446      SDValue CPIdx =
2447        CurDAG->getTargetConstantPool(ConstantInt::get(
2448                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2449                                      TLI.getPointerTy());
2450
2451      SDNode *ResNode;
2452      if (Subtarget->isThumb1Only()) {
2453        SDValue Pred = getAL(CurDAG);
2454        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2455        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2456        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2457                                         Ops, 4);
2458      } else {
2459        SDValue Ops[] = {
2460          CPIdx,
2461          CurDAG->getTargetConstant(0, MVT::i32),
2462          getAL(CurDAG),
2463          CurDAG->getRegister(0, MVT::i32),
2464          CurDAG->getEntryNode()
2465        };
2466        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2467                                       Ops, 5);
2468      }
2469      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2470      return NULL;
2471    }
2472
2473    // Other cases are autogenerated.
2474    break;
2475  }
2476  case ISD::FrameIndex: {
2477    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2478    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2479    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2480    if (Subtarget->isThumb1Only()) {
2481      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2482                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2483      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2484    } else {
2485      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2486                      ARM::t2ADDri : ARM::ADDri);
2487      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2488                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2489                        CurDAG->getRegister(0, MVT::i32) };
2490      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2491    }
2492  }
2493  case ISD::SRL:
2494    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2495      return I;
2496    break;
2497  case ISD::SRA:
2498    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2499      return I;
2500    break;
2501  case ISD::MUL:
2502    if (Subtarget->isThumb1Only())
2503      break;
2504    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2505      unsigned RHSV = C->getZExtValue();
2506      if (!RHSV) break;
2507      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2508        unsigned ShImm = Log2_32(RHSV-1);
2509        if (ShImm >= 32)
2510          break;
2511        SDValue V = N->getOperand(0);
2512        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2513        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2514        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2515        if (Subtarget->isThumb()) {
2516          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2517          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2518        } else {
2519          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2520          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2521        }
2522      }
2523      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2524        unsigned ShImm = Log2_32(RHSV+1);
2525        if (ShImm >= 32)
2526          break;
2527        SDValue V = N->getOperand(0);
2528        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2529        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2530        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2531        if (Subtarget->isThumb()) {
2532          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2533          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2534        } else {
2535          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2536          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2537        }
2538      }
2539    }
2540    break;
2541  case ISD::AND: {
2542    // Check for unsigned bitfield extract
2543    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2544      return I;
2545
2546    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2547    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2548    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2549    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2550    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2551    EVT VT = N->getValueType(0);
2552    if (VT != MVT::i32)
2553      break;
2554    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2555      ? ARM::t2MOVTi16
2556      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2557    if (!Opc)
2558      break;
2559    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2560    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2561    if (!N1C)
2562      break;
2563    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2564      SDValue N2 = N0.getOperand(1);
2565      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2566      if (!N2C)
2567        break;
2568      unsigned N1CVal = N1C->getZExtValue();
2569      unsigned N2CVal = N2C->getZExtValue();
2570      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2571          (N1CVal & 0xffffU) == 0xffffU &&
2572          (N2CVal & 0xffffU) == 0x0U) {
2573        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2574                                                  MVT::i32);
2575        SDValue Ops[] = { N0.getOperand(0), Imm16,
2576                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2577        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2578      }
2579    }
2580    break;
2581  }
2582  case ARMISD::VMOVRRD:
2583    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2584                                  N->getOperand(0), getAL(CurDAG),
2585                                  CurDAG->getRegister(0, MVT::i32));
2586  case ISD::UMUL_LOHI: {
2587    if (Subtarget->isThumb1Only())
2588      break;
2589    if (Subtarget->isThumb()) {
2590      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2591                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2592                        CurDAG->getRegister(0, MVT::i32) };
2593      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2594    } else {
2595      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2596                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2597                        CurDAG->getRegister(0, MVT::i32) };
2598      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2599                                    ARM::UMULL : ARM::UMULLv5,
2600                                    dl, MVT::i32, MVT::i32, Ops, 5);
2601    }
2602  }
2603  case ISD::SMUL_LOHI: {
2604    if (Subtarget->isThumb1Only())
2605      break;
2606    if (Subtarget->isThumb()) {
2607      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2608                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2609      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2610    } else {
2611      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2612                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2613                        CurDAG->getRegister(0, MVT::i32) };
2614      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2615                                    ARM::SMULL : ARM::SMULLv5,
2616                                    dl, MVT::i32, MVT::i32, Ops, 5);
2617    }
2618  }
2619  case ISD::LOAD: {
2620    SDNode *ResNode = 0;
2621    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2622      ResNode = SelectT2IndexedLoad(N);
2623    else
2624      ResNode = SelectARMIndexedLoad(N);
2625    if (ResNode)
2626      return ResNode;
2627    // Other cases are autogenerated.
2628    break;
2629  }
2630  case ARMISD::BRCOND: {
2631    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2632    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2633    // Pattern complexity = 6  cost = 1  size = 0
2634
2635    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2636    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2637    // Pattern complexity = 6  cost = 1  size = 0
2638
2639    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2640    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2641    // Pattern complexity = 6  cost = 1  size = 0
2642
2643    unsigned Opc = Subtarget->isThumb() ?
2644      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2645    SDValue Chain = N->getOperand(0);
2646    SDValue N1 = N->getOperand(1);
2647    SDValue N2 = N->getOperand(2);
2648    SDValue N3 = N->getOperand(3);
2649    SDValue InFlag = N->getOperand(4);
2650    assert(N1.getOpcode() == ISD::BasicBlock);
2651    assert(N2.getOpcode() == ISD::Constant);
2652    assert(N3.getOpcode() == ISD::Register);
2653
2654    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2655                               cast<ConstantSDNode>(N2)->getZExtValue()),
2656                               MVT::i32);
2657    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2658    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2659                                             MVT::Glue, Ops, 5);
2660    Chain = SDValue(ResNode, 0);
2661    if (N->getNumValues() == 2) {
2662      InFlag = SDValue(ResNode, 1);
2663      ReplaceUses(SDValue(N, 1), InFlag);
2664    }
2665    ReplaceUses(SDValue(N, 0),
2666                SDValue(Chain.getNode(), Chain.getResNo()));
2667    return NULL;
2668  }
2669  case ARMISD::CMOV:
2670    return SelectCMOVOp(N);
2671  case ARMISD::VZIP: {
2672    unsigned Opc = 0;
2673    EVT VT = N->getValueType(0);
2674    switch (VT.getSimpleVT().SimpleTy) {
2675    default: return NULL;
2676    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2677    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2678    case MVT::v2f32:
2679    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2680    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2681    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2682    case MVT::v4f32:
2683    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2684    }
2685    SDValue Pred = getAL(CurDAG);
2686    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2687    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2688    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2689  }
2690  case ARMISD::VUZP: {
2691    unsigned Opc = 0;
2692    EVT VT = N->getValueType(0);
2693    switch (VT.getSimpleVT().SimpleTy) {
2694    default: return NULL;
2695    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2696    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2697    case MVT::v2f32:
2698    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2699    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2700    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2701    case MVT::v4f32:
2702    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2703    }
2704    SDValue Pred = getAL(CurDAG);
2705    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2706    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2707    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2708  }
2709  case ARMISD::VTRN: {
2710    unsigned Opc = 0;
2711    EVT VT = N->getValueType(0);
2712    switch (VT.getSimpleVT().SimpleTy) {
2713    default: return NULL;
2714    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2715    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2716    case MVT::v2f32:
2717    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2718    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2719    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2720    case MVT::v4f32:
2721    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2722    }
2723    SDValue Pred = getAL(CurDAG);
2724    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2725    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2726    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2727  }
2728  case ARMISD::BUILD_VECTOR: {
2729    EVT VecVT = N->getValueType(0);
2730    EVT EltVT = VecVT.getVectorElementType();
2731    unsigned NumElts = VecVT.getVectorNumElements();
2732    if (EltVT == MVT::f64) {
2733      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2734      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2735    }
2736    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2737    if (NumElts == 2)
2738      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2739    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2740    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2741                     N->getOperand(2), N->getOperand(3));
2742  }
2743
2744  case ARMISD::VLD2DUP: {
2745    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2746                           ARM::VLD2DUPd32Pseudo };
2747    return SelectVLDDup(N, false, 2, Opcodes);
2748  }
2749
2750  case ARMISD::VLD3DUP: {
2751    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2752                           ARM::VLD3DUPd32Pseudo };
2753    return SelectVLDDup(N, false, 3, Opcodes);
2754  }
2755
2756  case ARMISD::VLD4DUP: {
2757    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2758                           ARM::VLD4DUPd32Pseudo };
2759    return SelectVLDDup(N, false, 4, Opcodes);
2760  }
2761
2762  case ARMISD::VLD2DUP_UPD: {
2763    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2764                           ARM::VLD2DUPd32Pseudo_UPD };
2765    return SelectVLDDup(N, true, 2, Opcodes);
2766  }
2767
2768  case ARMISD::VLD3DUP_UPD: {
2769    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2770                           ARM::VLD3DUPd32Pseudo_UPD };
2771    return SelectVLDDup(N, true, 3, Opcodes);
2772  }
2773
2774  case ARMISD::VLD4DUP_UPD: {
2775    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2776                           ARM::VLD4DUPd32Pseudo_UPD };
2777    return SelectVLDDup(N, true, 4, Opcodes);
2778  }
2779
2780  case ARMISD::VLD1_UPD: {
2781    unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
2782                            ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
2783    unsigned QOpcodes[] = { ARM::VLD1q8PseudoWB_fixed,
2784                            ARM::VLD1q16PseudoWB_fixed,
2785                            ARM::VLD1q32PseudoWB_fixed,
2786                            ARM::VLD1q64PseudoWB_fixed };
2787    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2788  }
2789
2790  case ARMISD::VLD2_UPD: {
2791    unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2792                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2793    unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2794                            ARM::VLD2q32Pseudo_UPD };
2795    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2796  }
2797
2798  case ARMISD::VLD3_UPD: {
2799    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2800                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2801    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2802                             ARM::VLD3q16Pseudo_UPD,
2803                             ARM::VLD3q32Pseudo_UPD };
2804    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2805                             ARM::VLD3q16oddPseudo_UPD,
2806                             ARM::VLD3q32oddPseudo_UPD };
2807    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2808  }
2809
2810  case ARMISD::VLD4_UPD: {
2811    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2812                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2813    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2814                             ARM::VLD4q16Pseudo_UPD,
2815                             ARM::VLD4q32Pseudo_UPD };
2816    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2817                             ARM::VLD4q16oddPseudo_UPD,
2818                             ARM::VLD4q32oddPseudo_UPD };
2819    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2820  }
2821
2822  case ARMISD::VLD2LN_UPD: {
2823    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2824                            ARM::VLD2LNd32Pseudo_UPD };
2825    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2826                            ARM::VLD2LNq32Pseudo_UPD };
2827    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2828  }
2829
2830  case ARMISD::VLD3LN_UPD: {
2831    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2832                            ARM::VLD3LNd32Pseudo_UPD };
2833    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2834                            ARM::VLD3LNq32Pseudo_UPD };
2835    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2836  }
2837
2838  case ARMISD::VLD4LN_UPD: {
2839    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2840                            ARM::VLD4LNd32Pseudo_UPD };
2841    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2842                            ARM::VLD4LNq32Pseudo_UPD };
2843    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2844  }
2845
2846  case ARMISD::VST1_UPD: {
2847    unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2848                            ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2849    unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2850                            ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2851    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2852  }
2853
2854  case ARMISD::VST2_UPD: {
2855    unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2856                            ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2857    unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2858                            ARM::VST2q32Pseudo_UPD };
2859    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2860  }
2861
2862  case ARMISD::VST3_UPD: {
2863    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2864                            ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2865    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2866                             ARM::VST3q16Pseudo_UPD,
2867                             ARM::VST3q32Pseudo_UPD };
2868    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2869                             ARM::VST3q16oddPseudo_UPD,
2870                             ARM::VST3q32oddPseudo_UPD };
2871    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2872  }
2873
2874  case ARMISD::VST4_UPD: {
2875    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2876                            ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2877    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2878                             ARM::VST4q16Pseudo_UPD,
2879                             ARM::VST4q32Pseudo_UPD };
2880    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2881                             ARM::VST4q16oddPseudo_UPD,
2882                             ARM::VST4q32oddPseudo_UPD };
2883    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2884  }
2885
2886  case ARMISD::VST2LN_UPD: {
2887    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2888                            ARM::VST2LNd32Pseudo_UPD };
2889    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2890                            ARM::VST2LNq32Pseudo_UPD };
2891    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2892  }
2893
2894  case ARMISD::VST3LN_UPD: {
2895    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2896                            ARM::VST3LNd32Pseudo_UPD };
2897    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2898                            ARM::VST3LNq32Pseudo_UPD };
2899    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2900  }
2901
2902  case ARMISD::VST4LN_UPD: {
2903    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2904                            ARM::VST4LNd32Pseudo_UPD };
2905    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2906                            ARM::VST4LNq32Pseudo_UPD };
2907    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2908  }
2909
2910  case ISD::INTRINSIC_VOID:
2911  case ISD::INTRINSIC_W_CHAIN: {
2912    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2913    switch (IntNo) {
2914    default:
2915      break;
2916
2917    case Intrinsic::arm_ldrexd: {
2918      SDValue MemAddr = N->getOperand(2);
2919      DebugLoc dl = N->getDebugLoc();
2920      SDValue Chain = N->getOperand(0);
2921
2922      unsigned NewOpc = ARM::LDREXD;
2923      if (Subtarget->isThumb() && Subtarget->hasThumb2())
2924        NewOpc = ARM::t2LDREXD;
2925
2926      // arm_ldrexd returns a i64 value in {i32, i32}
2927      std::vector<EVT> ResTys;
2928      ResTys.push_back(MVT::i32);
2929      ResTys.push_back(MVT::i32);
2930      ResTys.push_back(MVT::Other);
2931
2932      // place arguments in the right order
2933      SmallVector<SDValue, 7> Ops;
2934      Ops.push_back(MemAddr);
2935      Ops.push_back(getAL(CurDAG));
2936      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2937      Ops.push_back(Chain);
2938      SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2939                                          Ops.size());
2940      // Transfer memoperands.
2941      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2942      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2943      cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2944
2945      // Until there's support for specifing explicit register constraints
2946      // like the use of even/odd register pair, hardcode ldrexd to always
2947      // use the pair [R0, R1] to hold the load result.
2948      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
2949                                   SDValue(Ld, 0), SDValue(0,0));
2950      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
2951                                   SDValue(Ld, 1), Chain.getValue(1));
2952
2953      // Remap uses.
2954      SDValue Glue = Chain.getValue(1);
2955      if (!SDValue(N, 0).use_empty()) {
2956        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2957                                                ARM::R0, MVT::i32, Glue);
2958        Glue = Result.getValue(2);
2959        ReplaceUses(SDValue(N, 0), Result);
2960      }
2961      if (!SDValue(N, 1).use_empty()) {
2962        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2963                                                ARM::R1, MVT::i32, Glue);
2964        Glue = Result.getValue(2);
2965        ReplaceUses(SDValue(N, 1), Result);
2966      }
2967
2968      ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
2969      return NULL;
2970    }
2971
2972    case Intrinsic::arm_strexd: {
2973      DebugLoc dl = N->getDebugLoc();
2974      SDValue Chain = N->getOperand(0);
2975      SDValue Val0 = N->getOperand(2);
2976      SDValue Val1 = N->getOperand(3);
2977      SDValue MemAddr = N->getOperand(4);
2978
2979      // Until there's support for specifing explicit register constraints
2980      // like the use of even/odd register pair, hardcode strexd to always
2981      // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
2982      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
2983                                   SDValue(0, 0));
2984      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
2985
2986      SDValue Glue = Chain.getValue(1);
2987      Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2988                                    ARM::R2, MVT::i32, Glue);
2989      Glue = Val0.getValue(1);
2990      Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2991                                    ARM::R3, MVT::i32, Glue);
2992
2993      // Store exclusive double return a i32 value which is the return status
2994      // of the issued store.
2995      std::vector<EVT> ResTys;
2996      ResTys.push_back(MVT::i32);
2997      ResTys.push_back(MVT::Other);
2998
2999      // place arguments in the right order
3000      SmallVector<SDValue, 7> Ops;
3001      Ops.push_back(Val0);
3002      Ops.push_back(Val1);
3003      Ops.push_back(MemAddr);
3004      Ops.push_back(getAL(CurDAG));
3005      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3006      Ops.push_back(Chain);
3007
3008      unsigned NewOpc = ARM::STREXD;
3009      if (Subtarget->isThumb() && Subtarget->hasThumb2())
3010        NewOpc = ARM::t2STREXD;
3011
3012      SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3013                                          Ops.size());
3014      // Transfer memoperands.
3015      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3016      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3017      cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3018
3019      return St;
3020    }
3021
3022    case Intrinsic::arm_neon_vld1: {
3023      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3024                              ARM::VLD1d32, ARM::VLD1d64 };
3025      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
3026                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
3027      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3028    }
3029
3030    case Intrinsic::arm_neon_vld2: {
3031      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
3032                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
3033      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3034                              ARM::VLD2q32Pseudo };
3035      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3036    }
3037
3038    case Intrinsic::arm_neon_vld3: {
3039      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
3040                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
3041      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3042                               ARM::VLD3q16Pseudo_UPD,
3043                               ARM::VLD3q32Pseudo_UPD };
3044      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3045                               ARM::VLD3q16oddPseudo,
3046                               ARM::VLD3q32oddPseudo };
3047      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3048    }
3049
3050    case Intrinsic::arm_neon_vld4: {
3051      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
3052                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
3053      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3054                               ARM::VLD4q16Pseudo_UPD,
3055                               ARM::VLD4q32Pseudo_UPD };
3056      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3057                               ARM::VLD4q16oddPseudo,
3058                               ARM::VLD4q32oddPseudo };
3059      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3060    }
3061
3062    case Intrinsic::arm_neon_vld2lane: {
3063      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
3064                              ARM::VLD2LNd32Pseudo };
3065      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
3066      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3067    }
3068
3069    case Intrinsic::arm_neon_vld3lane: {
3070      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
3071                              ARM::VLD3LNd32Pseudo };
3072      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
3073      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3074    }
3075
3076    case Intrinsic::arm_neon_vld4lane: {
3077      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
3078                              ARM::VLD4LNd32Pseudo };
3079      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
3080      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3081    }
3082
3083    case Intrinsic::arm_neon_vst1: {
3084      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3085                              ARM::VST1d32, ARM::VST1d64 };
3086      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
3087                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
3088      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3089    }
3090
3091    case Intrinsic::arm_neon_vst2: {
3092      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3093                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3094      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3095                              ARM::VST2q32Pseudo };
3096      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3097    }
3098
3099    case Intrinsic::arm_neon_vst3: {
3100      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3101                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3102      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3103                               ARM::VST3q16Pseudo_UPD,
3104                               ARM::VST3q32Pseudo_UPD };
3105      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3106                               ARM::VST3q16oddPseudo,
3107                               ARM::VST3q32oddPseudo };
3108      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3109    }
3110
3111    case Intrinsic::arm_neon_vst4: {
3112      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3113                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3114      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3115                               ARM::VST4q16Pseudo_UPD,
3116                               ARM::VST4q32Pseudo_UPD };
3117      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3118                               ARM::VST4q16oddPseudo,
3119                               ARM::VST4q32oddPseudo };
3120      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3121    }
3122
3123    case Intrinsic::arm_neon_vst2lane: {
3124      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3125                              ARM::VST2LNd32Pseudo };
3126      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3127      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3128    }
3129
3130    case Intrinsic::arm_neon_vst3lane: {
3131      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3132                              ARM::VST3LNd32Pseudo };
3133      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3134      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3135    }
3136
3137    case Intrinsic::arm_neon_vst4lane: {
3138      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3139                              ARM::VST4LNd32Pseudo };
3140      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3141      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3142    }
3143    }
3144    break;
3145  }
3146
3147  case ISD::INTRINSIC_WO_CHAIN: {
3148    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3149    switch (IntNo) {
3150    default:
3151      break;
3152
3153    case Intrinsic::arm_neon_vtbl2:
3154      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3155    case Intrinsic::arm_neon_vtbl3:
3156      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3157    case Intrinsic::arm_neon_vtbl4:
3158      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3159
3160    case Intrinsic::arm_neon_vtbx2:
3161      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3162    case Intrinsic::arm_neon_vtbx3:
3163      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3164    case Intrinsic::arm_neon_vtbx4:
3165      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3166    }
3167    break;
3168  }
3169
3170  case ARMISD::VTBL1: {
3171    DebugLoc dl = N->getDebugLoc();
3172    EVT VT = N->getValueType(0);
3173    SmallVector<SDValue, 6> Ops;
3174
3175    Ops.push_back(N->getOperand(0));
3176    Ops.push_back(N->getOperand(1));
3177    Ops.push_back(getAL(CurDAG));                    // Predicate
3178    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3179    return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3180  }
3181  case ARMISD::VTBL2: {
3182    DebugLoc dl = N->getDebugLoc();
3183    EVT VT = N->getValueType(0);
3184
3185    // Form a REG_SEQUENCE to force register allocation.
3186    SDValue V0 = N->getOperand(0);
3187    SDValue V1 = N->getOperand(1);
3188    SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3189
3190    SmallVector<SDValue, 6> Ops;
3191    Ops.push_back(RegSeq);
3192    Ops.push_back(N->getOperand(2));
3193    Ops.push_back(getAL(CurDAG));                    // Predicate
3194    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3195    return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3196                                  Ops.data(), Ops.size());
3197  }
3198
3199  case ISD::CONCAT_VECTORS:
3200    return SelectConcatVector(N);
3201
3202  case ARMISD::ATOMOR64_DAG:
3203    return SelectAtomic64(N, ARM::ATOMOR6432);
3204  case ARMISD::ATOMXOR64_DAG:
3205    return SelectAtomic64(N, ARM::ATOMXOR6432);
3206  case ARMISD::ATOMADD64_DAG:
3207    return SelectAtomic64(N, ARM::ATOMADD6432);
3208  case ARMISD::ATOMSUB64_DAG:
3209    return SelectAtomic64(N, ARM::ATOMSUB6432);
3210  case ARMISD::ATOMNAND64_DAG:
3211    return SelectAtomic64(N, ARM::ATOMNAND6432);
3212  case ARMISD::ATOMAND64_DAG:
3213    return SelectAtomic64(N, ARM::ATOMAND6432);
3214  case ARMISD::ATOMSWAP64_DAG:
3215    return SelectAtomic64(N, ARM::ATOMSWAP6432);
3216  case ARMISD::ATOMCMPXCHG64_DAG:
3217    return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3218  }
3219
3220  return SelectCode(N);
3221}
3222
3223bool ARMDAGToDAGISel::
3224SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3225                             std::vector<SDValue> &OutOps) {
3226  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3227  // Require the address to be in a register.  That is safe for all ARM
3228  // variants and it is hard to do anything much smarter without knowing
3229  // how the operand is used.
3230  OutOps.push_back(Op);
3231  return false;
3232}
3233
3234/// createARMISelDag - This pass converts a legalized DAG into a
3235/// ARM-specific DAG, ready for instruction scheduling.
3236///
3237FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3238                                     CodeGenOpt::Level OptLevel) {
3239  return new ARMDAGToDAGISel(TM, OptLevel);
3240}
3241