ARMISelDAGToDAG.cpp revision dada95b5b3acbce56440124c242673f30f596f92
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the ARM target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMConstantPoolValue.h" 17#include "ARMISelLowering.h" 18#include "ARMTargetMachine.h" 19#include "llvm/CallingConv.h" 20#include "llvm/Constants.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/Intrinsics.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Support/Compiler.h" 32#include "llvm/Support/Debug.h" 33using namespace llvm; 34 35//===--------------------------------------------------------------------===// 36/// ARMDAGToDAGISel - ARM specific code to select ARM machine 37/// instructions for SelectionDAG operations. 38/// 39namespace { 40class ARMDAGToDAGISel : public SelectionDAGISel { 41 ARMTargetMachine &TM; 42 43 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 44 /// make the right decision when generating code for different targets. 45 const ARMSubtarget *Subtarget; 46 47public: 48 explicit ARMDAGToDAGISel(ARMTargetMachine &tm) 49 : SelectionDAGISel(tm), TM(tm), 50 Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 51 } 52 53 virtual const char *getPassName() const { 54 return "ARM Instruction Selection"; 55 } 56 57 SDNode *Select(SDValue Op); 58 virtual void InstructionSelect(); 59 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base, 60 SDValue &Offset, SDValue &Opc); 61 bool SelectAddrMode2Offset(SDValue Op, SDValue N, 62 SDValue &Offset, SDValue &Opc); 63 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base, 64 SDValue &Offset, SDValue &Opc); 65 bool SelectAddrMode3Offset(SDValue Op, SDValue N, 66 SDValue &Offset, SDValue &Opc); 67 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base, 68 SDValue &Offset); 69 70 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset, 71 SDValue &Label); 72 73 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base, 74 SDValue &Offset); 75 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale, 76 SDValue &Base, SDValue &OffImm, 77 SDValue &Offset); 78 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base, 79 SDValue &OffImm, SDValue &Offset); 80 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base, 81 SDValue &OffImm, SDValue &Offset); 82 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base, 83 SDValue &OffImm, SDValue &Offset); 84 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base, 85 SDValue &OffImm); 86 87 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A, 88 SDValue &B, SDValue &C); 89 90 // Include the pieces autogenerated from the target description. 91#include "ARMGenDAGISel.inc" 92 93private: 94 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 95 /// inline asm expressions. 96 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 97 char ConstraintCode, 98 std::vector<SDValue> &OutOps); 99}; 100} 101 102void ARMDAGToDAGISel::InstructionSelect() { 103 DEBUG(BB->dump()); 104 105 SelectRoot(*CurDAG); 106 CurDAG->RemoveDeadNodes(); 107} 108 109bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N, 110 SDValue &Base, SDValue &Offset, 111 SDValue &Opc) { 112 if (N.getOpcode() == ISD::MUL) { 113 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 114 // X * [3,5,9] -> X + X * [2,4,8] etc. 115 int RHSC = (int)RHS->getZExtValue(); 116 if (RHSC & 1) { 117 RHSC = RHSC & ~1; 118 ARM_AM::AddrOpc AddSub = ARM_AM::add; 119 if (RHSC < 0) { 120 AddSub = ARM_AM::sub; 121 RHSC = - RHSC; 122 } 123 if (isPowerOf2_32(RHSC)) { 124 unsigned ShAmt = Log2_32(RHSC); 125 Base = Offset = N.getOperand(0); 126 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, 127 ARM_AM::lsl), 128 MVT::i32); 129 return true; 130 } 131 } 132 } 133 } 134 135 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) { 136 Base = N; 137 if (N.getOpcode() == ISD::FrameIndex) { 138 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 139 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 140 } else if (N.getOpcode() == ARMISD::Wrapper) { 141 Base = N.getOperand(0); 142 } 143 Offset = CurDAG->getRegister(0, MVT::i32); 144 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, 145 ARM_AM::no_shift), 146 MVT::i32); 147 return true; 148 } 149 150 // Match simple R +/- imm12 operands. 151 if (N.getOpcode() == ISD::ADD) 152 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 153 int RHSC = (int)RHS->getZExtValue(); 154 if ((RHSC >= 0 && RHSC < 0x1000) || 155 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits. 156 Base = N.getOperand(0); 157 if (Base.getOpcode() == ISD::FrameIndex) { 158 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 159 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 160 } 161 Offset = CurDAG->getRegister(0, MVT::i32); 162 163 ARM_AM::AddrOpc AddSub = ARM_AM::add; 164 if (RHSC < 0) { 165 AddSub = ARM_AM::sub; 166 RHSC = - RHSC; 167 } 168 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, 169 ARM_AM::no_shift), 170 MVT::i32); 171 return true; 172 } 173 } 174 175 // Otherwise this is R +/- [possibly shifted] R 176 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub; 177 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1)); 178 unsigned ShAmt = 0; 179 180 Base = N.getOperand(0); 181 Offset = N.getOperand(1); 182 183 if (ShOpcVal != ARM_AM::no_shift) { 184 // Check to see if the RHS of the shift is a constant, if not, we can't fold 185 // it. 186 if (ConstantSDNode *Sh = 187 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) { 188 ShAmt = Sh->getZExtValue(); 189 Offset = N.getOperand(1).getOperand(0); 190 } else { 191 ShOpcVal = ARM_AM::no_shift; 192 } 193 } 194 195 // Try matching (R shl C) + (R). 196 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) { 197 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0)); 198 if (ShOpcVal != ARM_AM::no_shift) { 199 // Check to see if the RHS of the shift is a constant, if not, we can't 200 // fold it. 201 if (ConstantSDNode *Sh = 202 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) { 203 ShAmt = Sh->getZExtValue(); 204 Offset = N.getOperand(0).getOperand(0); 205 Base = N.getOperand(1); 206 } else { 207 ShOpcVal = ARM_AM::no_shift; 208 } 209 } 210 } 211 212 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 213 MVT::i32); 214 return true; 215} 216 217bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N, 218 SDValue &Offset, SDValue &Opc) { 219 unsigned Opcode = Op.getOpcode(); 220 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 221 ? cast<LoadSDNode>(Op)->getAddressingMode() 222 : cast<StoreSDNode>(Op)->getAddressingMode(); 223 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 224 ? ARM_AM::add : ARM_AM::sub; 225 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 226 int Val = (int)C->getZExtValue(); 227 if (Val >= 0 && Val < 0x1000) { // 12 bits. 228 Offset = CurDAG->getRegister(0, MVT::i32); 229 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, 230 ARM_AM::no_shift), 231 MVT::i32); 232 return true; 233 } 234 } 235 236 Offset = N; 237 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 238 unsigned ShAmt = 0; 239 if (ShOpcVal != ARM_AM::no_shift) { 240 // Check to see if the RHS of the shift is a constant, if not, we can't fold 241 // it. 242 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 243 ShAmt = Sh->getZExtValue(); 244 Offset = N.getOperand(0); 245 } else { 246 ShOpcVal = ARM_AM::no_shift; 247 } 248 } 249 250 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 251 MVT::i32); 252 return true; 253} 254 255 256bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N, 257 SDValue &Base, SDValue &Offset, 258 SDValue &Opc) { 259 if (N.getOpcode() == ISD::SUB) { 260 // X - C is canonicalize to X + -C, no need to handle it here. 261 Base = N.getOperand(0); 262 Offset = N.getOperand(1); 263 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32); 264 return true; 265 } 266 267 if (N.getOpcode() != ISD::ADD) { 268 Base = N; 269 if (N.getOpcode() == ISD::FrameIndex) { 270 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 271 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 272 } 273 Offset = CurDAG->getRegister(0, MVT::i32); 274 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32); 275 return true; 276 } 277 278 // If the RHS is +/- imm8, fold into addr mode. 279 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 280 int RHSC = (int)RHS->getZExtValue(); 281 if ((RHSC >= 0 && RHSC < 256) || 282 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 283 Base = N.getOperand(0); 284 if (Base.getOpcode() == ISD::FrameIndex) { 285 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 286 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 287 } 288 Offset = CurDAG->getRegister(0, MVT::i32); 289 290 ARM_AM::AddrOpc AddSub = ARM_AM::add; 291 if (RHSC < 0) { 292 AddSub = ARM_AM::sub; 293 RHSC = - RHSC; 294 } 295 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32); 296 return true; 297 } 298 } 299 300 Base = N.getOperand(0); 301 Offset = N.getOperand(1); 302 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32); 303 return true; 304} 305 306bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N, 307 SDValue &Offset, SDValue &Opc) { 308 unsigned Opcode = Op.getOpcode(); 309 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 310 ? cast<LoadSDNode>(Op)->getAddressingMode() 311 : cast<StoreSDNode>(Op)->getAddressingMode(); 312 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 313 ? ARM_AM::add : ARM_AM::sub; 314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 315 int Val = (int)C->getZExtValue(); 316 if (Val >= 0 && Val < 256) { 317 Offset = CurDAG->getRegister(0, MVT::i32); 318 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32); 319 return true; 320 } 321 } 322 323 Offset = N; 324 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32); 325 return true; 326} 327 328 329bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N, 330 SDValue &Base, SDValue &Offset) { 331 if (N.getOpcode() != ISD::ADD) { 332 Base = N; 333 if (N.getOpcode() == ISD::FrameIndex) { 334 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 335 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 336 } else if (N.getOpcode() == ARMISD::Wrapper) { 337 Base = N.getOperand(0); 338 } 339 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 340 MVT::i32); 341 return true; 342 } 343 344 // If the RHS is +/- imm8, fold into addr mode. 345 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 346 int RHSC = (int)RHS->getZExtValue(); 347 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4. 348 RHSC >>= 2; 349 if ((RHSC >= 0 && RHSC < 256) || 350 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 351 Base = N.getOperand(0); 352 if (Base.getOpcode() == ISD::FrameIndex) { 353 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 354 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 355 } 356 357 ARM_AM::AddrOpc AddSub = ARM_AM::add; 358 if (RHSC < 0) { 359 AddSub = ARM_AM::sub; 360 RHSC = - RHSC; 361 } 362 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC), 363 MVT::i32); 364 return true; 365 } 366 } 367 } 368 369 Base = N; 370 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 371 MVT::i32); 372 return true; 373} 374 375bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N, 376 SDValue &Offset, SDValue &Label) { 377 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) { 378 Offset = N.getOperand(0); 379 SDValue N1 = N.getOperand(1); 380 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(), 381 MVT::i32); 382 return true; 383 } 384 return false; 385} 386 387bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N, 388 SDValue &Base, SDValue &Offset){ 389 // FIXME dl should come from the parent load or store, not the address 390 DebugLoc dl = Op.getDebugLoc(); 391 if (N.getOpcode() != ISD::ADD) { 392 Base = N; 393 // We must materialize a zero in a reg! Returning a constant here 394 // wouldn't work without additional code to position the node within 395 // ISel's topological ordering in a place where ISel will process it 396 // normally. Instead, just explicitly issue a tMOVri8 node! 397 Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32, 398 CurDAG->getTargetConstant(0, MVT::i32)), 0); 399 return true; 400 } 401 402 Base = N.getOperand(0); 403 Offset = N.getOperand(1); 404 return true; 405} 406 407bool 408ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N, 409 unsigned Scale, SDValue &Base, 410 SDValue &OffImm, SDValue &Offset) { 411 if (Scale == 4) { 412 SDValue TmpBase, TmpOffImm; 413 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm)) 414 return false; // We want to select tLDRspi / tSTRspi instead. 415 if (N.getOpcode() == ARMISD::Wrapper && 416 N.getOperand(0).getOpcode() == ISD::TargetConstantPool) 417 return false; // We want to select tLDRpci instead. 418 } 419 420 if (N.getOpcode() != ISD::ADD) { 421 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N; 422 Offset = CurDAG->getRegister(0, MVT::i32); 423 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 424 return true; 425 } 426 427 // Thumb does not have [sp, r] address mode. 428 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 429 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); 430 if ((LHSR && LHSR->getReg() == ARM::SP) || 431 (RHSR && RHSR->getReg() == ARM::SP)) { 432 Base = N; 433 Offset = CurDAG->getRegister(0, MVT::i32); 434 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 435 return true; 436 } 437 438 // If the RHS is + imm5 * scale, fold into addr mode. 439 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 440 int RHSC = (int)RHS->getZExtValue(); 441 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied. 442 RHSC /= Scale; 443 if (RHSC >= 0 && RHSC < 32) { 444 Base = N.getOperand(0); 445 Offset = CurDAG->getRegister(0, MVT::i32); 446 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 447 return true; 448 } 449 } 450 } 451 452 Base = N.getOperand(0); 453 Offset = N.getOperand(1); 454 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 455 return true; 456} 457 458bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N, 459 SDValue &Base, SDValue &OffImm, 460 SDValue &Offset) { 461 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset); 462} 463 464bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N, 465 SDValue &Base, SDValue &OffImm, 466 SDValue &Offset) { 467 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset); 468} 469 470bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N, 471 SDValue &Base, SDValue &OffImm, 472 SDValue &Offset) { 473 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset); 474} 475 476bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N, 477 SDValue &Base, SDValue &OffImm) { 478 if (N.getOpcode() == ISD::FrameIndex) { 479 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 480 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 481 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 482 return true; 483 } 484 485 if (N.getOpcode() != ISD::ADD) 486 return false; 487 488 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 489 if (N.getOperand(0).getOpcode() == ISD::FrameIndex || 490 (LHSR && LHSR->getReg() == ARM::SP)) { 491 // If the RHS is + imm8 * scale, fold into addr mode. 492 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 493 int RHSC = (int)RHS->getZExtValue(); 494 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied. 495 RHSC >>= 2; 496 if (RHSC >= 0 && RHSC < 256) { 497 Base = N.getOperand(0); 498 if (Base.getOpcode() == ISD::FrameIndex) { 499 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 500 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 501 } 502 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 503 return true; 504 } 505 } 506 } 507 } 508 509 return false; 510} 511 512bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op, 513 SDValue N, 514 SDValue &BaseReg, 515 SDValue &ShReg, 516 SDValue &Opc) { 517 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 518 519 // Don't match base register only case. That is matched to a separate 520 // lower complexity pattern with explicit register operand. 521 if (ShOpcVal == ARM_AM::no_shift) return false; 522 523 BaseReg = N.getOperand(0); 524 unsigned ShImmVal = 0; 525 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 526 ShReg = CurDAG->getRegister(0, MVT::i32); 527 ShImmVal = RHS->getZExtValue() & 31; 528 } else { 529 ShReg = N.getOperand(1); 530 } 531 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), 532 MVT::i32); 533 return true; 534} 535 536/// getAL - Returns a ARMCC::AL immediate node. 537static inline SDValue getAL(SelectionDAG *CurDAG) { 538 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); 539} 540 541 542SDNode *ARMDAGToDAGISel::Select(SDValue Op) { 543 SDNode *N = Op.getNode(); 544 DebugLoc dl = N->getDebugLoc(); 545 546 if (N->isMachineOpcode()) 547 return NULL; // Already selected. 548 549 switch (N->getOpcode()) { 550 default: break; 551 case ISD::Constant: { 552 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue(); 553 bool UseCP = true; 554 if (Subtarget->isThumb()) 555 UseCP = (Val > 255 && // MOV 556 ~Val > 255 && // MOV + MVN 557 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL 558 else 559 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV 560 ARM_AM::getSOImmVal(~Val) == -1 && // MVN 561 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. 562 if (UseCP) { 563 SDValue CPIdx = 564 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val), 565 TLI.getPointerTy()); 566 567 SDNode *ResNode; 568 if (Subtarget->isThumb()) 569 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, 570 CPIdx, CurDAG->getEntryNode()); 571 else { 572 SDValue Ops[] = { 573 CPIdx, 574 CurDAG->getRegister(0, MVT::i32), 575 CurDAG->getTargetConstant(0, MVT::i32), 576 getAL(CurDAG), 577 CurDAG->getRegister(0, MVT::i32), 578 CurDAG->getEntryNode() 579 }; 580 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, 581 Ops, 6); 582 } 583 ReplaceUses(Op, SDValue(ResNode, 0)); 584 return NULL; 585 } 586 587 // Other cases are autogenerated. 588 break; 589 } 590 case ISD::FrameIndex: { 591 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm. 592 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 593 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 594 if (Subtarget->isThumb()) { 595 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, 596 CurDAG->getTargetConstant(0, MVT::i32)); 597 } else { 598 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), 599 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 600 CurDAG->getRegister(0, MVT::i32) }; 601 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5); 602 } 603 } 604 case ISD::ADD: { 605 if (!Subtarget->isThumb()) 606 break; 607 // Select add sp, c to tADDhirr. 608 SDValue N0 = Op.getOperand(0); 609 SDValue N1 = Op.getOperand(1); 610 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0)); 611 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1)); 612 if (LHSR && LHSR->getReg() == ARM::SP) { 613 std::swap(N0, N1); 614 std::swap(LHSR, RHSR); 615 } 616 if (RHSR && RHSR->getReg() == ARM::SP) { 617 SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl, 618 Op.getValueType(), N0, N0), 0); 619 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1); 620 } 621 break; 622 } 623 case ISD::MUL: 624 if (Subtarget->isThumb()) 625 break; 626 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 627 unsigned RHSV = C->getZExtValue(); 628 if (!RHSV) break; 629 if (isPowerOf2_32(RHSV-1)) { // 2^n+1? 630 SDValue V = Op.getOperand(0); 631 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1)); 632 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32), 633 CurDAG->getTargetConstant(ShImm, MVT::i32), 634 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 635 CurDAG->getRegister(0, MVT::i32) }; 636 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7); 637 } 638 if (isPowerOf2_32(RHSV+1)) { // 2^n-1? 639 SDValue V = Op.getOperand(0); 640 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1)); 641 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32), 642 CurDAG->getTargetConstant(ShImm, MVT::i32), 643 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 644 CurDAG->getRegister(0, MVT::i32) }; 645 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7); 646 } 647 } 648 break; 649 case ARMISD::FMRRD: 650 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32, 651 Op.getOperand(0), getAL(CurDAG), 652 CurDAG->getRegister(0, MVT::i32)); 653 case ISD::UMUL_LOHI: { 654 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), 655 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 656 CurDAG->getRegister(0, MVT::i32) }; 657 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); 658 } 659 case ISD::SMUL_LOHI: { 660 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), 661 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 662 CurDAG->getRegister(0, MVT::i32) }; 663 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); 664 } 665 case ISD::LOAD: { 666 LoadSDNode *LD = cast<LoadSDNode>(Op); 667 ISD::MemIndexedMode AM = LD->getAddressingMode(); 668 MVT LoadedVT = LD->getMemoryVT(); 669 if (AM != ISD::UNINDEXED) { 670 SDValue Offset, AMOpc; 671 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 672 unsigned Opcode = 0; 673 bool Match = false; 674 if (LoadedVT == MVT::i32 && 675 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) { 676 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST; 677 Match = true; 678 } else if (LoadedVT == MVT::i16 && 679 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) { 680 Match = true; 681 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) 682 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) 683 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); 684 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { 685 if (LD->getExtensionType() == ISD::SEXTLOAD) { 686 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) { 687 Match = true; 688 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; 689 } 690 } else { 691 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) { 692 Match = true; 693 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST; 694 } 695 } 696 } 697 698 if (Match) { 699 SDValue Chain = LD->getChain(); 700 SDValue Base = LD->getBasePtr(); 701 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), 702 CurDAG->getRegister(0, MVT::i32), Chain }; 703 return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32, 704 MVT::Other, Ops, 6); 705 } 706 } 707 // Other cases are autogenerated. 708 break; 709 } 710 case ARMISD::BRCOND: { 711 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 712 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc) 713 // Pattern complexity = 6 cost = 1 size = 0 714 715 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 716 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc) 717 // Pattern complexity = 6 cost = 1 size = 0 718 719 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc; 720 SDValue Chain = Op.getOperand(0); 721 SDValue N1 = Op.getOperand(1); 722 SDValue N2 = Op.getOperand(2); 723 SDValue N3 = Op.getOperand(3); 724 SDValue InFlag = Op.getOperand(4); 725 assert(N1.getOpcode() == ISD::BasicBlock); 726 assert(N2.getOpcode() == ISD::Constant); 727 assert(N3.getOpcode() == ISD::Register); 728 729 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 730 cast<ConstantSDNode>(N2)->getZExtValue()), 731 MVT::i32); 732 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; 733 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other, 734 MVT::Flag, Ops, 5); 735 Chain = SDValue(ResNode, 0); 736 if (Op.getNode()->getNumValues() == 2) { 737 InFlag = SDValue(ResNode, 1); 738 ReplaceUses(SDValue(Op.getNode(), 1), InFlag); 739 } 740 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo())); 741 return NULL; 742 } 743 case ARMISD::CMOV: { 744 bool isThumb = Subtarget->isThumb(); 745 MVT VT = Op.getValueType(); 746 SDValue N0 = Op.getOperand(0); 747 SDValue N1 = Op.getOperand(1); 748 SDValue N2 = Op.getOperand(2); 749 SDValue N3 = Op.getOperand(3); 750 SDValue InFlag = Op.getOperand(4); 751 assert(N2.getOpcode() == ISD::Constant); 752 assert(N3.getOpcode() == ISD::Register); 753 754 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 755 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 756 // Pattern complexity = 18 cost = 1 size = 0 757 SDValue CPTmp0; 758 SDValue CPTmp1; 759 SDValue CPTmp2; 760 if (!isThumb && VT == MVT::i32 && 761 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) { 762 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 763 cast<ConstantSDNode>(N2)->getZExtValue()), 764 MVT::i32); 765 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag }; 766 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7); 767 } 768 769 // Pattern: (ARMcmov:i32 GPR:i32:$false, 770 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true, 771 // (imm:i32):$cc) 772 // Emits: (MOVCCi:i32 GPR:i32:$false, 773 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc) 774 // Pattern complexity = 10 cost = 1 size = 0 775 if (VT == MVT::i32 && 776 N3.getOpcode() == ISD::Constant && 777 Predicate_so_imm(N3.getNode())) { 778 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) 779 cast<ConstantSDNode>(N1)->getZExtValue()), 780 MVT::i32); 781 Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode()); 782 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 783 cast<ConstantSDNode>(N2)->getZExtValue()), 784 MVT::i32); 785 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; 786 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5); 787 } 788 789 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 790 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 791 // Pattern complexity = 6 cost = 1 size = 0 792 // 793 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 794 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 795 // Pattern complexity = 6 cost = 11 size = 0 796 // 797 // Also FCPYScc and FCPYDcc. 798 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 799 cast<ConstantSDNode>(N2)->getZExtValue()), 800 MVT::i32); 801 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; 802 unsigned Opc = 0; 803 switch (VT.getSimpleVT()) { 804 default: assert(false && "Illegal conditional move type!"); 805 break; 806 case MVT::i32: 807 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr; 808 break; 809 case MVT::f32: 810 Opc = ARM::FCPYScc; 811 break; 812 case MVT::f64: 813 Opc = ARM::FCPYDcc; 814 break; 815 } 816 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5); 817 } 818 case ARMISD::CNEG: { 819 MVT VT = Op.getValueType(); 820 SDValue N0 = Op.getOperand(0); 821 SDValue N1 = Op.getOperand(1); 822 SDValue N2 = Op.getOperand(2); 823 SDValue N3 = Op.getOperand(3); 824 SDValue InFlag = Op.getOperand(4); 825 assert(N2.getOpcode() == ISD::Constant); 826 assert(N3.getOpcode() == ISD::Register); 827 828 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 829 cast<ConstantSDNode>(N2)->getZExtValue()), 830 MVT::i32); 831 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; 832 unsigned Opc = 0; 833 switch (VT.getSimpleVT()) { 834 default: assert(false && "Illegal conditional move type!"); 835 break; 836 case MVT::f32: 837 Opc = ARM::FNEGScc; 838 break; 839 case MVT::f64: 840 Opc = ARM::FNEGDcc; 841 break; 842 } 843 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5); 844 } 845 846 case ISD::DECLARE: { 847 SDValue Chain = Op.getOperand(0); 848 SDValue N1 = Op.getOperand(1); 849 SDValue N2 = Op.getOperand(2); 850 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1); 851 // FIXME: handle VLAs. 852 if (!FINode) { 853 ReplaceUses(Op.getValue(0), Chain); 854 return NULL; 855 } 856 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0))) 857 N2 = N2.getOperand(0); 858 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2); 859 if (!Ld) { 860 ReplaceUses(Op.getValue(0), Chain); 861 return NULL; 862 } 863 SDValue BasePtr = Ld->getBasePtr(); 864 assert(BasePtr.getOpcode() == ARMISD::Wrapper && 865 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) && 866 "llvm.dbg.variable should be a constantpool node"); 867 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0)); 868 GlobalValue *GV = 0; 869 if (CP->isMachineConstantPoolEntry()) { 870 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal(); 871 GV = ACPV->getGV(); 872 } else 873 GV = dyn_cast<GlobalValue>(CP->getConstVal()); 874 if (!GV) { 875 ReplaceUses(Op.getValue(0), Chain); 876 return NULL; 877 } 878 879 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(), 880 TLI.getPointerTy()); 881 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); 882 SDValue Ops[] = { Tmp1, Tmp2, Chain }; 883 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, 884 MVT::Other, Ops, 3); 885 } 886 } 887 888 return SelectCode(Op); 889} 890 891bool ARMDAGToDAGISel:: 892SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 893 std::vector<SDValue> &OutOps) { 894 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 895 896 SDValue Base, Offset, Opc; 897 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc)) 898 return true; 899 900 OutOps.push_back(Base); 901 OutOps.push_back(Offset); 902 OutOps.push_back(Opc); 903 return false; 904} 905 906/// createARMISelDag - This pass converts a legalized DAG into a 907/// ARM-specific DAG, ready for instruction scheduling. 908/// 909FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) { 910 return new ARMDAGToDAGISel(TM); 911} 912