ARMISelDAGToDAG.cpp revision e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMISelLowering.h"
17#include "ARMTargetMachine.h"
18#include "llvm/CallingConv.h"
19#include "llvm/Constants.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/LLVMContext.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/CodeGen/SelectionDAGISel.h"
29#include "llvm/Target/TargetLowering.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35
36using namespace llvm;
37
38//===--------------------------------------------------------------------===//
39/// ARMDAGToDAGISel - ARM specific code to select ARM machine
40/// instructions for SelectionDAG operations.
41///
42namespace {
43class ARMDAGToDAGISel : public SelectionDAGISel {
44  ARMBaseTargetMachine &TM;
45
46  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47  /// make the right decision when generating code for different targets.
48  const ARMSubtarget *Subtarget;
49
50public:
51  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
52                           CodeGenOpt::Level OptLevel)
53    : SelectionDAGISel(tm, OptLevel), TM(tm),
54    Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
55  }
56
57  virtual const char *getPassName() const {
58    return "ARM Instruction Selection";
59  }
60
61  /// getI32Imm - Return a target constant of type i32 with the specified
62  /// value.
63  inline SDValue getI32Imm(unsigned Imm) {
64    return CurDAG->getTargetConstant(Imm, MVT::i32);
65  }
66
67  SDNode *Select(SDValue Op);
68  virtual void InstructionSelect();
69  bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
70                               SDValue &B, SDValue &C);
71  bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
72                       SDValue &Offset, SDValue &Opc);
73  bool SelectAddrMode2Offset(SDValue Op, SDValue N,
74                             SDValue &Offset, SDValue &Opc);
75  bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
76                       SDValue &Offset, SDValue &Opc);
77  bool SelectAddrMode3Offset(SDValue Op, SDValue N,
78                             SDValue &Offset, SDValue &Opc);
79  bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
80                       SDValue &Mode);
81  bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
82                       SDValue &Offset);
83  bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
84                       SDValue &Opc, SDValue &Align);
85
86  bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
87                        SDValue &Label);
88
89  bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
90                             SDValue &Offset);
91  bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92                              SDValue &Base, SDValue &OffImm,
93                              SDValue &Offset);
94  bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95                             SDValue &OffImm, SDValue &Offset);
96  bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97                             SDValue &OffImm, SDValue &Offset);
98  bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99                             SDValue &OffImm, SDValue &Offset);
100  bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
101                             SDValue &OffImm);
102
103  bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104                                 SDValue &BaseReg, SDValue &Opc);
105  bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
106                             SDValue &OffImm);
107  bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
108                            SDValue &OffImm);
109  bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
110                                 SDValue &OffImm);
111  bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
112                              SDValue &OffImm);
113  bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114                             SDValue &OffReg, SDValue &ShImm);
115
116  // Include the pieces autogenerated from the target description.
117#include "ARMGenDAGISel.inc"
118
119private:
120  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
121  /// ARM.
122  SDNode *SelectARMIndexedLoad(SDValue Op);
123  SDNode *SelectT2IndexedLoad(SDValue Op);
124
125  /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126  SDNode *SelectDYN_ALLOC(SDValue Op);
127
128  /// SelectVLD - Select NEON load intrinsics.  NumVecs should
129  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
130  /// loads of D registers and even subregs and odd subregs of Q registers.
131  /// For NumVecs == 2, QOpcodes1 is not used.
132  SDNode *SelectVLD(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
133                    unsigned *QOpcodes0, unsigned *QOpcodes1);
134
135  /// SelectVST - Select NEON store intrinsics.  NumVecs should
136  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
137  /// stores of D registers and even subregs and odd subregs of Q registers.
138  /// For NumVecs == 2, QOpcodes1 is not used.
139  SDNode *SelectVST(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
140                    unsigned *QOpcodes0, unsigned *QOpcodes1);
141
142  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
143  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
144  /// load/store of D registers and even subregs and odd subregs of Q registers.
145  SDNode *SelectVLDSTLane(SDValue Op, bool IsLoad, unsigned NumVecs,
146                          unsigned *DOpcodes, unsigned *QOpcodes0,
147                          unsigned *QOpcodes1);
148
149  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
150  SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
151
152  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
153  /// inline asm expressions.
154  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
155                                            char ConstraintCode,
156                                            std::vector<SDValue> &OutOps);
157
158  /// PairDRegs - Insert a pair of double registers into an implicit def to
159  /// form a quad register.
160  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
161};
162}
163
164/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
165/// operand. If so Imm will receive the 32-bit value.
166static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
167  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
168    Imm = cast<ConstantSDNode>(N)->getZExtValue();
169    return true;
170  }
171  return false;
172}
173
174// isInt32Immediate - This method tests to see if a constant operand.
175// If so Imm will receive the 32 bit value.
176static bool isInt32Immediate(SDValue N, unsigned &Imm) {
177  return isInt32Immediate(N.getNode(), Imm);
178}
179
180// isOpcWithIntImmediate - This method tests to see if the node is a specific
181// opcode and that it has a immediate integer right operand.
182// If so Imm will receive the 32 bit value.
183static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
184  return N->getOpcode() == Opc &&
185         isInt32Immediate(N->getOperand(1).getNode(), Imm);
186}
187
188
189void ARMDAGToDAGISel::InstructionSelect() {
190  SelectRoot(*CurDAG);
191  CurDAG->RemoveDeadNodes();
192}
193
194bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
195                                              SDValue N,
196                                              SDValue &BaseReg,
197                                              SDValue &ShReg,
198                                              SDValue &Opc) {
199  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
200
201  // Don't match base register only case. That is matched to a separate
202  // lower complexity pattern with explicit register operand.
203  if (ShOpcVal == ARM_AM::no_shift) return false;
204
205  BaseReg = N.getOperand(0);
206  unsigned ShImmVal = 0;
207  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
208    ShReg = CurDAG->getRegister(0, MVT::i32);
209    ShImmVal = RHS->getZExtValue() & 31;
210  } else {
211    ShReg = N.getOperand(1);
212  }
213  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
214                                  MVT::i32);
215  return true;
216}
217
218bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
219                                      SDValue &Base, SDValue &Offset,
220                                      SDValue &Opc) {
221  if (N.getOpcode() == ISD::MUL) {
222    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
223      // X * [3,5,9] -> X + X * [2,4,8] etc.
224      int RHSC = (int)RHS->getZExtValue();
225      if (RHSC & 1) {
226        RHSC = RHSC & ~1;
227        ARM_AM::AddrOpc AddSub = ARM_AM::add;
228        if (RHSC < 0) {
229          AddSub = ARM_AM::sub;
230          RHSC = - RHSC;
231        }
232        if (isPowerOf2_32(RHSC)) {
233          unsigned ShAmt = Log2_32(RHSC);
234          Base = Offset = N.getOperand(0);
235          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
236                                                            ARM_AM::lsl),
237                                          MVT::i32);
238          return true;
239        }
240      }
241    }
242  }
243
244  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
245    Base = N;
246    if (N.getOpcode() == ISD::FrameIndex) {
247      int FI = cast<FrameIndexSDNode>(N)->getIndex();
248      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
249    } else if (N.getOpcode() == ARMISD::Wrapper) {
250      Base = N.getOperand(0);
251    }
252    Offset = CurDAG->getRegister(0, MVT::i32);
253    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
254                                                      ARM_AM::no_shift),
255                                    MVT::i32);
256    return true;
257  }
258
259  // Match simple R +/- imm12 operands.
260  if (N.getOpcode() == ISD::ADD)
261    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
262      int RHSC = (int)RHS->getZExtValue();
263      if ((RHSC >= 0 && RHSC < 0x1000) ||
264          (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
265        Base = N.getOperand(0);
266        if (Base.getOpcode() == ISD::FrameIndex) {
267          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
268          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
269        }
270        Offset = CurDAG->getRegister(0, MVT::i32);
271
272        ARM_AM::AddrOpc AddSub = ARM_AM::add;
273        if (RHSC < 0) {
274          AddSub = ARM_AM::sub;
275          RHSC = - RHSC;
276        }
277        Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
278                                                          ARM_AM::no_shift),
279                                        MVT::i32);
280        return true;
281      }
282    }
283
284  // Otherwise this is R +/- [possibly shifted] R.
285  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
286  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
287  unsigned ShAmt = 0;
288
289  Base   = N.getOperand(0);
290  Offset = N.getOperand(1);
291
292  if (ShOpcVal != ARM_AM::no_shift) {
293    // Check to see if the RHS of the shift is a constant, if not, we can't fold
294    // it.
295    if (ConstantSDNode *Sh =
296           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
297      ShAmt = Sh->getZExtValue();
298      Offset = N.getOperand(1).getOperand(0);
299    } else {
300      ShOpcVal = ARM_AM::no_shift;
301    }
302  }
303
304  // Try matching (R shl C) + (R).
305  if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
306    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
307    if (ShOpcVal != ARM_AM::no_shift) {
308      // Check to see if the RHS of the shift is a constant, if not, we can't
309      // fold it.
310      if (ConstantSDNode *Sh =
311          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
312        ShAmt = Sh->getZExtValue();
313        Offset = N.getOperand(0).getOperand(0);
314        Base = N.getOperand(1);
315      } else {
316        ShOpcVal = ARM_AM::no_shift;
317      }
318    }
319  }
320
321  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
322                                  MVT::i32);
323  return true;
324}
325
326bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
327                                            SDValue &Offset, SDValue &Opc) {
328  unsigned Opcode = Op.getOpcode();
329  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
330    ? cast<LoadSDNode>(Op)->getAddressingMode()
331    : cast<StoreSDNode>(Op)->getAddressingMode();
332  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
333    ? ARM_AM::add : ARM_AM::sub;
334  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
335    int Val = (int)C->getZExtValue();
336    if (Val >= 0 && Val < 0x1000) { // 12 bits.
337      Offset = CurDAG->getRegister(0, MVT::i32);
338      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
339                                                        ARM_AM::no_shift),
340                                      MVT::i32);
341      return true;
342    }
343  }
344
345  Offset = N;
346  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
347  unsigned ShAmt = 0;
348  if (ShOpcVal != ARM_AM::no_shift) {
349    // Check to see if the RHS of the shift is a constant, if not, we can't fold
350    // it.
351    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
352      ShAmt = Sh->getZExtValue();
353      Offset = N.getOperand(0);
354    } else {
355      ShOpcVal = ARM_AM::no_shift;
356    }
357  }
358
359  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
360                                  MVT::i32);
361  return true;
362}
363
364
365bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
366                                      SDValue &Base, SDValue &Offset,
367                                      SDValue &Opc) {
368  if (N.getOpcode() == ISD::SUB) {
369    // X - C  is canonicalize to X + -C, no need to handle it here.
370    Base = N.getOperand(0);
371    Offset = N.getOperand(1);
372    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
373    return true;
374  }
375
376  if (N.getOpcode() != ISD::ADD) {
377    Base = N;
378    if (N.getOpcode() == ISD::FrameIndex) {
379      int FI = cast<FrameIndexSDNode>(N)->getIndex();
380      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
381    }
382    Offset = CurDAG->getRegister(0, MVT::i32);
383    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
384    return true;
385  }
386
387  // If the RHS is +/- imm8, fold into addr mode.
388  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
389    int RHSC = (int)RHS->getZExtValue();
390    if ((RHSC >= 0 && RHSC < 256) ||
391        (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
392      Base = N.getOperand(0);
393      if (Base.getOpcode() == ISD::FrameIndex) {
394        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
395        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
396      }
397      Offset = CurDAG->getRegister(0, MVT::i32);
398
399      ARM_AM::AddrOpc AddSub = ARM_AM::add;
400      if (RHSC < 0) {
401        AddSub = ARM_AM::sub;
402        RHSC = - RHSC;
403      }
404      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
405      return true;
406    }
407  }
408
409  Base = N.getOperand(0);
410  Offset = N.getOperand(1);
411  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
412  return true;
413}
414
415bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
416                                            SDValue &Offset, SDValue &Opc) {
417  unsigned Opcode = Op.getOpcode();
418  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
419    ? cast<LoadSDNode>(Op)->getAddressingMode()
420    : cast<StoreSDNode>(Op)->getAddressingMode();
421  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
422    ? ARM_AM::add : ARM_AM::sub;
423  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
424    int Val = (int)C->getZExtValue();
425    if (Val >= 0 && Val < 256) {
426      Offset = CurDAG->getRegister(0, MVT::i32);
427      Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
428      return true;
429    }
430  }
431
432  Offset = N;
433  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
434  return true;
435}
436
437bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
438                                      SDValue &Addr, SDValue &Mode) {
439  Addr = N;
440  Mode = CurDAG->getTargetConstant(0, MVT::i32);
441  return true;
442}
443
444bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
445                                      SDValue &Base, SDValue &Offset) {
446  if (N.getOpcode() != ISD::ADD) {
447    Base = N;
448    if (N.getOpcode() == ISD::FrameIndex) {
449      int FI = cast<FrameIndexSDNode>(N)->getIndex();
450      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
451    } else if (N.getOpcode() == ARMISD::Wrapper) {
452      Base = N.getOperand(0);
453    }
454    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
455                                       MVT::i32);
456    return true;
457  }
458
459  // If the RHS is +/- imm8, fold into addr mode.
460  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
461    int RHSC = (int)RHS->getZExtValue();
462    if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied by 4.
463      RHSC >>= 2;
464      if ((RHSC >= 0 && RHSC < 256) ||
465          (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
466        Base = N.getOperand(0);
467        if (Base.getOpcode() == ISD::FrameIndex) {
468          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
469          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
470        }
471
472        ARM_AM::AddrOpc AddSub = ARM_AM::add;
473        if (RHSC < 0) {
474          AddSub = ARM_AM::sub;
475          RHSC = - RHSC;
476        }
477        Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
478                                           MVT::i32);
479        return true;
480      }
481    }
482  }
483
484  Base = N;
485  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
486                                     MVT::i32);
487  return true;
488}
489
490bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
491                                      SDValue &Addr, SDValue &Update,
492                                      SDValue &Opc, SDValue &Align) {
493  Addr = N;
494  // Default to no writeback.
495  Update = CurDAG->getRegister(0, MVT::i32);
496  Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
497  // Default to no alignment.
498  Align = CurDAG->getTargetConstant(0, MVT::i32);
499  return true;
500}
501
502bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
503                                       SDValue &Offset, SDValue &Label) {
504  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
505    Offset = N.getOperand(0);
506    SDValue N1 = N.getOperand(1);
507    Label  = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
508                                       MVT::i32);
509    return true;
510  }
511  return false;
512}
513
514bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
515                                            SDValue &Base, SDValue &Offset){
516  // FIXME dl should come from the parent load or store, not the address
517  DebugLoc dl = Op.getDebugLoc();
518  if (N.getOpcode() != ISD::ADD) {
519    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
520    if (!NC || NC->getZExtValue() != 0)
521      return false;
522
523    Base = Offset = N;
524    return true;
525  }
526
527  Base = N.getOperand(0);
528  Offset = N.getOperand(1);
529  return true;
530}
531
532bool
533ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
534                                        unsigned Scale, SDValue &Base,
535                                        SDValue &OffImm, SDValue &Offset) {
536  if (Scale == 4) {
537    SDValue TmpBase, TmpOffImm;
538    if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
539      return false;  // We want to select tLDRspi / tSTRspi instead.
540    if (N.getOpcode() == ARMISD::Wrapper &&
541        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
542      return false;  // We want to select tLDRpci instead.
543  }
544
545  if (N.getOpcode() != ISD::ADD) {
546    Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
547    Offset = CurDAG->getRegister(0, MVT::i32);
548    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
549    return true;
550  }
551
552  // Thumb does not have [sp, r] address mode.
553  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
554  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
555  if ((LHSR && LHSR->getReg() == ARM::SP) ||
556      (RHSR && RHSR->getReg() == ARM::SP)) {
557    Base = N;
558    Offset = CurDAG->getRegister(0, MVT::i32);
559    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
560    return true;
561  }
562
563  // If the RHS is + imm5 * scale, fold into addr mode.
564  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
565    int RHSC = (int)RHS->getZExtValue();
566    if ((RHSC & (Scale-1)) == 0) {  // The constant is implicitly multiplied.
567      RHSC /= Scale;
568      if (RHSC >= 0 && RHSC < 32) {
569        Base = N.getOperand(0);
570        Offset = CurDAG->getRegister(0, MVT::i32);
571        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
572        return true;
573      }
574    }
575  }
576
577  Base = N.getOperand(0);
578  Offset = N.getOperand(1);
579  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
580  return true;
581}
582
583bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
584                                            SDValue &Base, SDValue &OffImm,
585                                            SDValue &Offset) {
586  return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
587}
588
589bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
590                                            SDValue &Base, SDValue &OffImm,
591                                            SDValue &Offset) {
592  return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
593}
594
595bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
596                                            SDValue &Base, SDValue &OffImm,
597                                            SDValue &Offset) {
598  return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
599}
600
601bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
602                                           SDValue &Base, SDValue &OffImm) {
603  if (N.getOpcode() == ISD::FrameIndex) {
604    int FI = cast<FrameIndexSDNode>(N)->getIndex();
605    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
606    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
607    return true;
608  }
609
610  if (N.getOpcode() != ISD::ADD)
611    return false;
612
613  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
614  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
615      (LHSR && LHSR->getReg() == ARM::SP)) {
616    // If the RHS is + imm8 * scale, fold into addr mode.
617    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
618      int RHSC = (int)RHS->getZExtValue();
619      if ((RHSC & 3) == 0) {  // The constant is implicitly multiplied.
620        RHSC >>= 2;
621        if (RHSC >= 0 && RHSC < 256) {
622          Base = N.getOperand(0);
623          if (Base.getOpcode() == ISD::FrameIndex) {
624            int FI = cast<FrameIndexSDNode>(Base)->getIndex();
625            Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
626          }
627          OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
628          return true;
629        }
630      }
631    }
632  }
633
634  return false;
635}
636
637bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
638                                                SDValue &BaseReg,
639                                                SDValue &Opc) {
640  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
641
642  // Don't match base register only case. That is matched to a separate
643  // lower complexity pattern with explicit register operand.
644  if (ShOpcVal == ARM_AM::no_shift) return false;
645
646  BaseReg = N.getOperand(0);
647  unsigned ShImmVal = 0;
648  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
649    ShImmVal = RHS->getZExtValue() & 31;
650    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
651    return true;
652  }
653
654  return false;
655}
656
657bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
658                                            SDValue &Base, SDValue &OffImm) {
659  // Match simple R + imm12 operands.
660
661  // Base only.
662  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
663    if (N.getOpcode() == ISD::FrameIndex) {
664      // Match frame index...
665      int FI = cast<FrameIndexSDNode>(N)->getIndex();
666      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
667      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
668      return true;
669    } else if (N.getOpcode() == ARMISD::Wrapper) {
670      Base = N.getOperand(0);
671      if (Base.getOpcode() == ISD::TargetConstantPool)
672        return false;  // We want to select t2LDRpci instead.
673    } else
674      Base = N;
675    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
676    return true;
677  }
678
679  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
680    if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
681      // Let t2LDRi8 handle (R - imm8).
682      return false;
683
684    int RHSC = (int)RHS->getZExtValue();
685    if (N.getOpcode() == ISD::SUB)
686      RHSC = -RHSC;
687
688    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
689      Base   = N.getOperand(0);
690      if (Base.getOpcode() == ISD::FrameIndex) {
691        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
692        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
693      }
694      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
695      return true;
696    }
697  }
698
699  // Base only.
700  Base = N;
701  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
702  return true;
703}
704
705bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
706                                           SDValue &Base, SDValue &OffImm) {
707  // Match simple R - imm8 operands.
708  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
709    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
710      int RHSC = (int)RHS->getSExtValue();
711      if (N.getOpcode() == ISD::SUB)
712        RHSC = -RHSC;
713
714      if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
715        Base = N.getOperand(0);
716        if (Base.getOpcode() == ISD::FrameIndex) {
717          int FI = cast<FrameIndexSDNode>(Base)->getIndex();
718          Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
719        }
720        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
721        return true;
722      }
723    }
724  }
725
726  return false;
727}
728
729bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
730                                                 SDValue &OffImm){
731  unsigned Opcode = Op.getOpcode();
732  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
733    ? cast<LoadSDNode>(Op)->getAddressingMode()
734    : cast<StoreSDNode>(Op)->getAddressingMode();
735  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
736    int RHSC = (int)RHS->getZExtValue();
737    if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
738      OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
739        ? CurDAG->getTargetConstant(RHSC, MVT::i32)
740        : CurDAG->getTargetConstant(-RHSC, MVT::i32);
741      return true;
742    }
743  }
744
745  return false;
746}
747
748bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
749                                             SDValue &Base, SDValue &OffImm) {
750  if (N.getOpcode() == ISD::ADD) {
751    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
752      int RHSC = (int)RHS->getZExtValue();
753      if (((RHSC & 0x3) == 0) &&
754          ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
755        Base   = N.getOperand(0);
756        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
757        return true;
758      }
759    }
760  } else if (N.getOpcode() == ISD::SUB) {
761    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
762      int RHSC = (int)RHS->getZExtValue();
763      if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
764        Base   = N.getOperand(0);
765        OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
766        return true;
767      }
768    }
769  }
770
771  return false;
772}
773
774bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
775                                            SDValue &Base,
776                                            SDValue &OffReg, SDValue &ShImm) {
777  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
778  if (N.getOpcode() != ISD::ADD)
779    return false;
780
781  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
782  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
783    int RHSC = (int)RHS->getZExtValue();
784    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
785      return false;
786    else if (RHSC < 0 && RHSC >= -255) // 8 bits
787      return false;
788  }
789
790  // Look for (R + R) or (R + (R << [1,2,3])).
791  unsigned ShAmt = 0;
792  Base   = N.getOperand(0);
793  OffReg = N.getOperand(1);
794
795  // Swap if it is ((R << c) + R).
796  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
797  if (ShOpcVal != ARM_AM::lsl) {
798    ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
799    if (ShOpcVal == ARM_AM::lsl)
800      std::swap(Base, OffReg);
801  }
802
803  if (ShOpcVal == ARM_AM::lsl) {
804    // Check to see if the RHS of the shift is a constant, if not, we can't fold
805    // it.
806    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
807      ShAmt = Sh->getZExtValue();
808      if (ShAmt >= 4) {
809        ShAmt = 0;
810        ShOpcVal = ARM_AM::no_shift;
811      } else
812        OffReg = OffReg.getOperand(0);
813    } else {
814      ShOpcVal = ARM_AM::no_shift;
815    }
816  }
817
818  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
819
820  return true;
821}
822
823//===--------------------------------------------------------------------===//
824
825/// getAL - Returns a ARMCC::AL immediate node.
826static inline SDValue getAL(SelectionDAG *CurDAG) {
827  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
828}
829
830SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
831  LoadSDNode *LD = cast<LoadSDNode>(Op);
832  ISD::MemIndexedMode AM = LD->getAddressingMode();
833  if (AM == ISD::UNINDEXED)
834    return NULL;
835
836  EVT LoadedVT = LD->getMemoryVT();
837  SDValue Offset, AMOpc;
838  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
839  unsigned Opcode = 0;
840  bool Match = false;
841  if (LoadedVT == MVT::i32 &&
842      SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
843    Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
844    Match = true;
845  } else if (LoadedVT == MVT::i16 &&
846             SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
847    Match = true;
848    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
849      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
850      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
851  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
852    if (LD->getExtensionType() == ISD::SEXTLOAD) {
853      if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
854        Match = true;
855        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
856      }
857    } else {
858      if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
859        Match = true;
860        Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
861      }
862    }
863  }
864
865  if (Match) {
866    SDValue Chain = LD->getChain();
867    SDValue Base = LD->getBasePtr();
868    SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
869                     CurDAG->getRegister(0, MVT::i32), Chain };
870    return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
871                                  MVT::Other, Ops, 6);
872  }
873
874  return NULL;
875}
876
877SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
878  LoadSDNode *LD = cast<LoadSDNode>(Op);
879  ISD::MemIndexedMode AM = LD->getAddressingMode();
880  if (AM == ISD::UNINDEXED)
881    return NULL;
882
883  EVT LoadedVT = LD->getMemoryVT();
884  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
885  SDValue Offset;
886  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
887  unsigned Opcode = 0;
888  bool Match = false;
889  if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
890    switch (LoadedVT.getSimpleVT().SimpleTy) {
891    case MVT::i32:
892      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
893      break;
894    case MVT::i16:
895      if (isSExtLd)
896        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
897      else
898        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
899      break;
900    case MVT::i8:
901    case MVT::i1:
902      if (isSExtLd)
903        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
904      else
905        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
906      break;
907    default:
908      return NULL;
909    }
910    Match = true;
911  }
912
913  if (Match) {
914    SDValue Chain = LD->getChain();
915    SDValue Base = LD->getBasePtr();
916    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
917                     CurDAG->getRegister(0, MVT::i32), Chain };
918    return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
919                                  MVT::Other, Ops, 5);
920  }
921
922  return NULL;
923}
924
925SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
926  SDNode *N = Op.getNode();
927  DebugLoc dl = N->getDebugLoc();
928  EVT VT = Op.getValueType();
929  SDValue Chain = Op.getOperand(0);
930  SDValue Size = Op.getOperand(1);
931  SDValue Align = Op.getOperand(2);
932  SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
933  int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
934  if (AlignVal < 0)
935    // We need to align the stack. Use Thumb1 tAND which is the only thumb
936    // instruction that can read and write SP. This matches to a pseudo
937    // instruction that has a chain to ensure the result is written back to
938    // the stack pointer.
939    SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
940
941  bool isC = isa<ConstantSDNode>(Size);
942  uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
943  // Handle the most common case for both Thumb1 and Thumb2:
944  // tSUBspi - immediate is between 0 ... 508 inclusive.
945  if (C <= 508 && ((C & 3) == 0))
946    // FIXME: tSUBspi encode scale 4 implicitly.
947    return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
948                                CurDAG->getTargetConstant(C/4, MVT::i32),
949                                Chain);
950
951  if (Subtarget->isThumb1Only()) {
952    // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
953    // should have negated the size operand already. FIXME: We can't insert
954    // new target independent node at this stage so we are forced to negate
955    // it earlier. Is there a better solution?
956    return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
957                                Chain);
958  } else if (Subtarget->isThumb2()) {
959    if (isC && Predicate_t2_so_imm(Size.getNode())) {
960      // t2SUBrSPi
961      SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
962      return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
963    } else if (isC && Predicate_imm0_4095(Size.getNode())) {
964      // t2SUBrSPi12
965      SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
966      return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
967    } else {
968      // t2SUBrSPs
969      SDValue Ops[] = { SP, Size,
970                        getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
971      return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
972    }
973  }
974
975  // FIXME: Add ADD / SUB sp instructions for ARM.
976  return 0;
977}
978
979/// PairDRegs - Insert a pair of double registers into an implicit def to
980/// form a quad register.
981SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
982  DebugLoc dl = V0.getNode()->getDebugLoc();
983  SDValue Undef =
984    SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
985  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
986  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
987  SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
988                                        VT, Undef, V0, SubReg0);
989  return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
990                                VT, SDValue(Pair, 0), V1, SubReg1);
991}
992
993/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
994/// for a 64-bit subregister of the vector.
995static EVT GetNEONSubregVT(EVT VT) {
996  switch (VT.getSimpleVT().SimpleTy) {
997  default: llvm_unreachable("unhandled NEON type");
998  case MVT::v16i8: return MVT::v8i8;
999  case MVT::v8i16: return MVT::v4i16;
1000  case MVT::v4f32: return MVT::v2f32;
1001  case MVT::v4i32: return MVT::v2i32;
1002  case MVT::v2i64: return MVT::v1i64;
1003  }
1004}
1005
1006SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
1007                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1008                                   unsigned *QOpcodes1) {
1009  assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1010  SDNode *N = Op.getNode();
1011  DebugLoc dl = N->getDebugLoc();
1012
1013  SDValue MemAddr, MemUpdate, MemOpc, Align;
1014  if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1015    return NULL;
1016
1017  SDValue Chain = N->getOperand(0);
1018  EVT VT = N->getValueType(0);
1019  bool is64BitVector = VT.is64BitVector();
1020
1021  unsigned OpcodeIndex;
1022  switch (VT.getSimpleVT().SimpleTy) {
1023  default: llvm_unreachable("unhandled vld type");
1024    // Double-register operations:
1025  case MVT::v8i8:  OpcodeIndex = 0; break;
1026  case MVT::v4i16: OpcodeIndex = 1; break;
1027  case MVT::v2f32:
1028  case MVT::v2i32: OpcodeIndex = 2; break;
1029  case MVT::v1i64: OpcodeIndex = 3; break;
1030    // Quad-register operations:
1031  case MVT::v16i8: OpcodeIndex = 0; break;
1032  case MVT::v8i16: OpcodeIndex = 1; break;
1033  case MVT::v4f32:
1034  case MVT::v4i32: OpcodeIndex = 2; break;
1035  }
1036
1037  if (is64BitVector) {
1038    unsigned Opc = DOpcodes[OpcodeIndex];
1039    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1040    std::vector<EVT> ResTys(NumVecs, VT);
1041    ResTys.push_back(MVT::Other);
1042    return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1043  }
1044
1045  EVT RegVT = GetNEONSubregVT(VT);
1046  if (NumVecs == 2) {
1047    // Quad registers are directly supported for VLD2,
1048    // loading 2 pairs of D regs.
1049    unsigned Opc = QOpcodes0[OpcodeIndex];
1050    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1051    std::vector<EVT> ResTys(4, VT);
1052    ResTys.push_back(MVT::Other);
1053    SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1054    Chain = SDValue(VLd, 4);
1055
1056    // Combine the even and odd subregs to produce the result.
1057    for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1058      SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
1059      ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1060    }
1061  } else {
1062    // Otherwise, quad registers are loaded with two separate instructions,
1063    // where one loads the even registers and the other loads the odd registers.
1064
1065    // Enable writeback to the address register.
1066    MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1067
1068    std::vector<EVT> ResTys(NumVecs, RegVT);
1069    ResTys.push_back(MemAddr.getValueType());
1070    ResTys.push_back(MVT::Other);
1071
1072    // Load the even subregs.
1073    unsigned Opc = QOpcodes0[OpcodeIndex];
1074    const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1075    SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 5);
1076    Chain = SDValue(VLdA, NumVecs+1);
1077
1078    // Load the odd subregs.
1079    Opc = QOpcodes1[OpcodeIndex];
1080    const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc,
1081                             Align, Chain };
1082    SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 5);
1083    Chain = SDValue(VLdB, NumVecs+1);
1084
1085    // Combine the even and odd subregs to produce the result.
1086    for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1087      SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
1088      ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1089    }
1090  }
1091  ReplaceUses(SDValue(N, NumVecs), Chain);
1092  return NULL;
1093}
1094
1095SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
1096                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1097                                   unsigned *QOpcodes1) {
1098  assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
1099  SDNode *N = Op.getNode();
1100  DebugLoc dl = N->getDebugLoc();
1101
1102  SDValue MemAddr, MemUpdate, MemOpc, Align;
1103  if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1104    return NULL;
1105
1106  SDValue Chain = N->getOperand(0);
1107  EVT VT = N->getOperand(3).getValueType();
1108  bool is64BitVector = VT.is64BitVector();
1109
1110  unsigned OpcodeIndex;
1111  switch (VT.getSimpleVT().SimpleTy) {
1112  default: llvm_unreachable("unhandled vst type");
1113    // Double-register operations:
1114  case MVT::v8i8:  OpcodeIndex = 0; break;
1115  case MVT::v4i16: OpcodeIndex = 1; break;
1116  case MVT::v2f32:
1117  case MVT::v2i32: OpcodeIndex = 2; break;
1118  case MVT::v1i64: OpcodeIndex = 3; break;
1119    // Quad-register operations:
1120  case MVT::v16i8: OpcodeIndex = 0; break;
1121  case MVT::v8i16: OpcodeIndex = 1; break;
1122  case MVT::v4f32:
1123  case MVT::v4i32: OpcodeIndex = 2; break;
1124  }
1125
1126  SmallVector<SDValue, 8> Ops;
1127  Ops.push_back(MemAddr);
1128  Ops.push_back(MemUpdate);
1129  Ops.push_back(MemOpc);
1130  Ops.push_back(Align);
1131
1132  if (is64BitVector) {
1133    unsigned Opc = DOpcodes[OpcodeIndex];
1134    for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1135      Ops.push_back(N->getOperand(Vec+3));
1136    Ops.push_back(Chain);
1137    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1138  }
1139
1140  EVT RegVT = GetNEONSubregVT(VT);
1141  if (NumVecs == 2) {
1142    // Quad registers are directly supported for VST2,
1143    // storing 2 pairs of D regs.
1144    unsigned Opc = QOpcodes0[OpcodeIndex];
1145    for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1146      Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1147                                                   N->getOperand(Vec+3)));
1148      Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1149                                                   N->getOperand(Vec+3)));
1150    }
1151    Ops.push_back(Chain);
1152    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9);
1153  }
1154
1155  // Otherwise, quad registers are stored with two separate instructions,
1156  // where one stores the even registers and the other stores the odd registers.
1157
1158  // Enable writeback to the address register.
1159  MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1160
1161  // Store the even subregs.
1162  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1163    Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1164                                                 N->getOperand(Vec+3)));
1165  Ops.push_back(Chain);
1166  unsigned Opc = QOpcodes0[OpcodeIndex];
1167  SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1168                                        MVT::Other, Ops.data(), NumVecs+5);
1169  Chain = SDValue(VStA, 1);
1170
1171  // Store the odd subregs.
1172  Ops[0] = SDValue(VStA, 0); // MemAddr
1173  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1174    Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1175                                                N->getOperand(Vec+3));
1176  Ops[NumVecs+4] = Chain;
1177  Opc = QOpcodes1[OpcodeIndex];
1178  SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1179                                        MVT::Other, Ops.data(), NumVecs+5);
1180  Chain = SDValue(VStB, 1);
1181  ReplaceUses(SDValue(N, 0), Chain);
1182  return NULL;
1183}
1184
1185SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
1186                                         unsigned NumVecs, unsigned *DOpcodes,
1187                                         unsigned *QOpcodes0,
1188                                         unsigned *QOpcodes1) {
1189  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1190  SDNode *N = Op.getNode();
1191  DebugLoc dl = N->getDebugLoc();
1192
1193  SDValue MemAddr, MemUpdate, MemOpc, Align;
1194  if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1195    return NULL;
1196
1197  SDValue Chain = N->getOperand(0);
1198  unsigned Lane =
1199    cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1200  EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1201  bool is64BitVector = VT.is64BitVector();
1202
1203  // Quad registers are handled by load/store of subregs. Find the subreg info.
1204  unsigned NumElts = 0;
1205  int SubregIdx = 0;
1206  EVT RegVT = VT;
1207  if (!is64BitVector) {
1208    RegVT = GetNEONSubregVT(VT);
1209    NumElts = RegVT.getVectorNumElements();
1210    SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1211  }
1212
1213  unsigned OpcodeIndex;
1214  switch (VT.getSimpleVT().SimpleTy) {
1215  default: llvm_unreachable("unhandled vld/vst lane type");
1216    // Double-register operations:
1217  case MVT::v8i8:  OpcodeIndex = 0; break;
1218  case MVT::v4i16: OpcodeIndex = 1; break;
1219  case MVT::v2f32:
1220  case MVT::v2i32: OpcodeIndex = 2; break;
1221    // Quad-register operations:
1222  case MVT::v8i16: OpcodeIndex = 0; break;
1223  case MVT::v4f32:
1224  case MVT::v4i32: OpcodeIndex = 1; break;
1225  }
1226
1227  SmallVector<SDValue, 9> Ops;
1228  Ops.push_back(MemAddr);
1229  Ops.push_back(MemUpdate);
1230  Ops.push_back(MemOpc);
1231  Ops.push_back(Align);
1232
1233  unsigned Opc = 0;
1234  if (is64BitVector) {
1235    Opc = DOpcodes[OpcodeIndex];
1236    for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1237      Ops.push_back(N->getOperand(Vec+3));
1238  } else {
1239    // Check if this is loading the even or odd subreg of a Q register.
1240    if (Lane < NumElts) {
1241      Opc = QOpcodes0[OpcodeIndex];
1242    } else {
1243      Lane -= NumElts;
1244      Opc = QOpcodes1[OpcodeIndex];
1245    }
1246    // Extract the subregs of the input vector.
1247    for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1248      Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1249                                                   N->getOperand(Vec+3)));
1250  }
1251  Ops.push_back(getI32Imm(Lane));
1252  Ops.push_back(Chain);
1253
1254  if (!IsLoad)
1255    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1256
1257  std::vector<EVT> ResTys(NumVecs, RegVT);
1258  ResTys.push_back(MVT::Other);
1259  SDNode *VLdLn =
1260    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+5);
1261  // For a 64-bit vector load to D registers, nothing more needs to be done.
1262  if (is64BitVector)
1263    return VLdLn;
1264
1265  // For 128-bit vectors, take the 64-bit results of the load and insert them
1266  // as subregs into the result.
1267  for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1268    SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1269                                                    N->getOperand(Vec+3),
1270                                                    SDValue(VLdLn, Vec));
1271    ReplaceUses(SDValue(N, Vec), QuadVec);
1272  }
1273
1274  Chain = SDValue(VLdLn, NumVecs);
1275  ReplaceUses(SDValue(N, NumVecs), Chain);
1276  return NULL;
1277}
1278
1279SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
1280                                                     unsigned Opc) {
1281  if (!Subtarget->hasV6T2Ops())
1282    return NULL;
1283
1284  unsigned Shl_imm = 0;
1285  if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){
1286    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1287    unsigned Srl_imm = 0;
1288    if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
1289      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1290      unsigned Width = 32 - Srl_imm;
1291      int LSB = Srl_imm - Shl_imm;
1292      if (LSB < 0)
1293        return NULL;
1294      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1295      SDValue Ops[] = { Op.getOperand(0).getOperand(0),
1296                        CurDAG->getTargetConstant(LSB, MVT::i32),
1297                        CurDAG->getTargetConstant(Width, MVT::i32),
1298                        getAL(CurDAG), Reg0 };
1299      return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32, Ops, 5);
1300    }
1301  }
1302  return NULL;
1303}
1304
1305SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
1306  SDNode *N = Op.getNode();
1307  DebugLoc dl = N->getDebugLoc();
1308
1309  if (N->isMachineOpcode())
1310    return NULL;   // Already selected.
1311
1312  switch (N->getOpcode()) {
1313  default: break;
1314  case ISD::Constant: {
1315    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1316    bool UseCP = true;
1317    if (Subtarget->hasThumb2())
1318      // Thumb2-aware targets have the MOVT instruction, so all immediates can
1319      // be done with MOV + MOVT, at worst.
1320      UseCP = 0;
1321    else {
1322      if (Subtarget->isThumb()) {
1323        UseCP = (Val > 255 &&                          // MOV
1324                 ~Val > 255 &&                         // MOV + MVN
1325                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
1326      } else
1327        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
1328                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
1329                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
1330    }
1331
1332    if (UseCP) {
1333      SDValue CPIdx =
1334        CurDAG->getTargetConstantPool(ConstantInt::get(
1335                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
1336                                      TLI.getPointerTy());
1337
1338      SDNode *ResNode;
1339      if (Subtarget->isThumb1Only()) {
1340        SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
1341        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1342        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1343        ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1344                                         Ops, 4);
1345      } else {
1346        SDValue Ops[] = {
1347          CPIdx,
1348          CurDAG->getRegister(0, MVT::i32),
1349          CurDAG->getTargetConstant(0, MVT::i32),
1350          getAL(CurDAG),
1351          CurDAG->getRegister(0, MVT::i32),
1352          CurDAG->getEntryNode()
1353        };
1354        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1355                                       Ops, 6);
1356      }
1357      ReplaceUses(Op, SDValue(ResNode, 0));
1358      return NULL;
1359    }
1360
1361    // Other cases are autogenerated.
1362    break;
1363  }
1364  case ISD::FrameIndex: {
1365    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1366    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1367    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1368    if (Subtarget->isThumb1Only()) {
1369      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1370                                  CurDAG->getTargetConstant(0, MVT::i32));
1371    } else {
1372      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1373                      ARM::t2ADDri : ARM::ADDri);
1374      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1375                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1376                        CurDAG->getRegister(0, MVT::i32) };
1377      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1378    }
1379  }
1380  case ARMISD::DYN_ALLOC:
1381    return SelectDYN_ALLOC(Op);
1382  case ISD::SRL:
1383    if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1384                      Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
1385      return I;
1386    break;
1387  case ISD::SRA:
1388    if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1389                      Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
1390      return I;
1391    break;
1392  case ISD::MUL:
1393    if (Subtarget->isThumb1Only())
1394      break;
1395    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1396      unsigned RHSV = C->getZExtValue();
1397      if (!RHSV) break;
1398      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
1399        unsigned ShImm = Log2_32(RHSV-1);
1400        if (ShImm >= 32)
1401          break;
1402        SDValue V = Op.getOperand(0);
1403        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1404        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1405        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1406        if (Subtarget->isThumb()) {
1407          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1408          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1409        } else {
1410          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1411          return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1412        }
1413      }
1414      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
1415        unsigned ShImm = Log2_32(RHSV+1);
1416        if (ShImm >= 32)
1417          break;
1418        SDValue V = Op.getOperand(0);
1419        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1420        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1421        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1422        if (Subtarget->isThumb()) {
1423          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1424          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1425        } else {
1426          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1427          return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1428        }
1429      }
1430    }
1431    break;
1432  case ISD::AND: {
1433    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1434    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1435    // are entirely contributed by c2 and lower 16-bits are entirely contributed
1436    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1437    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1438    EVT VT = Op.getValueType();
1439    if (VT != MVT::i32)
1440      break;
1441    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1442      ? ARM::t2MOVTi16
1443      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1444    if (!Opc)
1445      break;
1446    SDValue N0 = Op.getOperand(0), N1 = Op.getOperand(1);
1447    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1448    if (!N1C)
1449      break;
1450    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1451      SDValue N2 = N0.getOperand(1);
1452      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1453      if (!N2C)
1454        break;
1455      unsigned N1CVal = N1C->getZExtValue();
1456      unsigned N2CVal = N2C->getZExtValue();
1457      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1458          (N1CVal & 0xffffU) == 0xffffU &&
1459          (N2CVal & 0xffffU) == 0x0U) {
1460        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1461                                                  MVT::i32);
1462        SDValue Ops[] = { N0.getOperand(0), Imm16,
1463                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1464        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1465      }
1466    }
1467    break;
1468  }
1469  case ARMISD::VMOVRRD:
1470    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1471                                  Op.getOperand(0), getAL(CurDAG),
1472                                  CurDAG->getRegister(0, MVT::i32));
1473  case ISD::UMUL_LOHI: {
1474    if (Subtarget->isThumb1Only())
1475      break;
1476    if (Subtarget->isThumb()) {
1477      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1478                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1479                        CurDAG->getRegister(0, MVT::i32) };
1480      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1481    } else {
1482      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1483                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1484                        CurDAG->getRegister(0, MVT::i32) };
1485      return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1486    }
1487  }
1488  case ISD::SMUL_LOHI: {
1489    if (Subtarget->isThumb1Only())
1490      break;
1491    if (Subtarget->isThumb()) {
1492      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1493                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1494      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1495    } else {
1496      SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1497                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1498                        CurDAG->getRegister(0, MVT::i32) };
1499      return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1500    }
1501  }
1502  case ISD::LOAD: {
1503    SDNode *ResNode = 0;
1504    if (Subtarget->isThumb() && Subtarget->hasThumb2())
1505      ResNode = SelectT2IndexedLoad(Op);
1506    else
1507      ResNode = SelectARMIndexedLoad(Op);
1508    if (ResNode)
1509      return ResNode;
1510    // Other cases are autogenerated.
1511    break;
1512  }
1513  case ARMISD::BRCOND: {
1514    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1515    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1516    // Pattern complexity = 6  cost = 1  size = 0
1517
1518    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1519    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1520    // Pattern complexity = 6  cost = 1  size = 0
1521
1522    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1523    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1524    // Pattern complexity = 6  cost = 1  size = 0
1525
1526    unsigned Opc = Subtarget->isThumb() ?
1527      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1528    SDValue Chain = Op.getOperand(0);
1529    SDValue N1 = Op.getOperand(1);
1530    SDValue N2 = Op.getOperand(2);
1531    SDValue N3 = Op.getOperand(3);
1532    SDValue InFlag = Op.getOperand(4);
1533    assert(N1.getOpcode() == ISD::BasicBlock);
1534    assert(N2.getOpcode() == ISD::Constant);
1535    assert(N3.getOpcode() == ISD::Register);
1536
1537    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1538                               cast<ConstantSDNode>(N2)->getZExtValue()),
1539                               MVT::i32);
1540    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1541    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1542                                             MVT::Flag, Ops, 5);
1543    Chain = SDValue(ResNode, 0);
1544    if (Op.getNode()->getNumValues() == 2) {
1545      InFlag = SDValue(ResNode, 1);
1546      ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1547    }
1548    ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1549    return NULL;
1550  }
1551  case ARMISD::CMOV: {
1552    EVT VT = Op.getValueType();
1553    SDValue N0 = Op.getOperand(0);
1554    SDValue N1 = Op.getOperand(1);
1555    SDValue N2 = Op.getOperand(2);
1556    SDValue N3 = Op.getOperand(3);
1557    SDValue InFlag = Op.getOperand(4);
1558    assert(N2.getOpcode() == ISD::Constant);
1559    assert(N3.getOpcode() == ISD::Register);
1560
1561    if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1562      // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1563      // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1564      // Pattern complexity = 18  cost = 1  size = 0
1565      SDValue CPTmp0;
1566      SDValue CPTmp1;
1567      SDValue CPTmp2;
1568      if (Subtarget->isThumb()) {
1569        if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1570          unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1571          unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1572          unsigned Opc = 0;
1573          switch (SOShOp) {
1574          case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1575          case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1576          case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1577          case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1578          default:
1579            llvm_unreachable("Unknown so_reg opcode!");
1580            break;
1581          }
1582          SDValue SOShImm =
1583            CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1584          SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1585                                   cast<ConstantSDNode>(N2)->getZExtValue()),
1586                                   MVT::i32);
1587          SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1588          return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1589        }
1590      } else {
1591        if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1592          SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1593                                   cast<ConstantSDNode>(N2)->getZExtValue()),
1594                                   MVT::i32);
1595          SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1596          return CurDAG->SelectNodeTo(Op.getNode(),
1597                                      ARM::MOVCCs, MVT::i32, Ops, 7);
1598        }
1599      }
1600
1601      // Pattern: (ARMcmov:i32 GPR:i32:$false,
1602      //             (imm:i32)<<P:Predicate_so_imm>>:$true,
1603      //             (imm:i32):$cc)
1604      // Emits: (MOVCCi:i32 GPR:i32:$false,
1605      //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1606      // Pattern complexity = 10  cost = 1  size = 0
1607      if (N3.getOpcode() == ISD::Constant) {
1608        if (Subtarget->isThumb()) {
1609          if (Predicate_t2_so_imm(N3.getNode())) {
1610            SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1611                                     cast<ConstantSDNode>(N1)->getZExtValue()),
1612                                     MVT::i32);
1613            SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1614                                     cast<ConstantSDNode>(N2)->getZExtValue()),
1615                                     MVT::i32);
1616            SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1617            return CurDAG->SelectNodeTo(Op.getNode(),
1618                                        ARM::t2MOVCCi, MVT::i32, Ops, 5);
1619          }
1620        } else {
1621          if (Predicate_so_imm(N3.getNode())) {
1622            SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1623                                     cast<ConstantSDNode>(N1)->getZExtValue()),
1624                                     MVT::i32);
1625            SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1626                                     cast<ConstantSDNode>(N2)->getZExtValue()),
1627                                     MVT::i32);
1628            SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1629            return CurDAG->SelectNodeTo(Op.getNode(),
1630                                        ARM::MOVCCi, MVT::i32, Ops, 5);
1631          }
1632        }
1633      }
1634    }
1635
1636    // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1637    // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1638    // Pattern complexity = 6  cost = 1  size = 0
1639    //
1640    // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1641    // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1642    // Pattern complexity = 6  cost = 11  size = 0
1643    //
1644    // Also FCPYScc and FCPYDcc.
1645    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1646                               cast<ConstantSDNode>(N2)->getZExtValue()),
1647                               MVT::i32);
1648    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1649    unsigned Opc = 0;
1650    switch (VT.getSimpleVT().SimpleTy) {
1651    default: assert(false && "Illegal conditional move type!");
1652      break;
1653    case MVT::i32:
1654      Opc = Subtarget->isThumb()
1655        ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1656        : ARM::MOVCCr;
1657      break;
1658    case MVT::f32:
1659      Opc = ARM::VMOVScc;
1660      break;
1661    case MVT::f64:
1662      Opc = ARM::VMOVDcc;
1663      break;
1664    }
1665    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1666  }
1667  case ARMISD::CNEG: {
1668    EVT VT = Op.getValueType();
1669    SDValue N0 = Op.getOperand(0);
1670    SDValue N1 = Op.getOperand(1);
1671    SDValue N2 = Op.getOperand(2);
1672    SDValue N3 = Op.getOperand(3);
1673    SDValue InFlag = Op.getOperand(4);
1674    assert(N2.getOpcode() == ISD::Constant);
1675    assert(N3.getOpcode() == ISD::Register);
1676
1677    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1678                               cast<ConstantSDNode>(N2)->getZExtValue()),
1679                               MVT::i32);
1680    SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1681    unsigned Opc = 0;
1682    switch (VT.getSimpleVT().SimpleTy) {
1683    default: assert(false && "Illegal conditional move type!");
1684      break;
1685    case MVT::f32:
1686      Opc = ARM::VNEGScc;
1687      break;
1688    case MVT::f64:
1689      Opc = ARM::VNEGDcc;
1690      break;
1691    }
1692    return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1693  }
1694
1695  case ARMISD::VZIP: {
1696    unsigned Opc = 0;
1697    EVT VT = N->getValueType(0);
1698    switch (VT.getSimpleVT().SimpleTy) {
1699    default: return NULL;
1700    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
1701    case MVT::v4i16: Opc = ARM::VZIPd16; break;
1702    case MVT::v2f32:
1703    case MVT::v2i32: Opc = ARM::VZIPd32; break;
1704    case MVT::v16i8: Opc = ARM::VZIPq8; break;
1705    case MVT::v8i16: Opc = ARM::VZIPq16; break;
1706    case MVT::v4f32:
1707    case MVT::v4i32: Opc = ARM::VZIPq32; break;
1708    }
1709    return CurDAG->getMachineNode(Opc, dl, VT, VT,
1710                                  N->getOperand(0), N->getOperand(1));
1711  }
1712  case ARMISD::VUZP: {
1713    unsigned Opc = 0;
1714    EVT VT = N->getValueType(0);
1715    switch (VT.getSimpleVT().SimpleTy) {
1716    default: return NULL;
1717    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
1718    case MVT::v4i16: Opc = ARM::VUZPd16; break;
1719    case MVT::v2f32:
1720    case MVT::v2i32: Opc = ARM::VUZPd32; break;
1721    case MVT::v16i8: Opc = ARM::VUZPq8; break;
1722    case MVT::v8i16: Opc = ARM::VUZPq16; break;
1723    case MVT::v4f32:
1724    case MVT::v4i32: Opc = ARM::VUZPq32; break;
1725    }
1726    return CurDAG->getMachineNode(Opc, dl, VT, VT,
1727                                  N->getOperand(0), N->getOperand(1));
1728  }
1729  case ARMISD::VTRN: {
1730    unsigned Opc = 0;
1731    EVT VT = N->getValueType(0);
1732    switch (VT.getSimpleVT().SimpleTy) {
1733    default: return NULL;
1734    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
1735    case MVT::v4i16: Opc = ARM::VTRNd16; break;
1736    case MVT::v2f32:
1737    case MVT::v2i32: Opc = ARM::VTRNd32; break;
1738    case MVT::v16i8: Opc = ARM::VTRNq8; break;
1739    case MVT::v8i16: Opc = ARM::VTRNq16; break;
1740    case MVT::v4f32:
1741    case MVT::v4i32: Opc = ARM::VTRNq32; break;
1742    }
1743    return CurDAG->getMachineNode(Opc, dl, VT, VT,
1744                                  N->getOperand(0), N->getOperand(1));
1745  }
1746
1747  case ISD::INTRINSIC_VOID:
1748  case ISD::INTRINSIC_W_CHAIN: {
1749    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1750    switch (IntNo) {
1751    default:
1752      break;
1753
1754    case Intrinsic::arm_neon_vld2: {
1755      unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
1756                              ARM::VLD2d32, ARM::VLD2d64 };
1757      unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
1758      return SelectVLD(Op, 2, DOpcodes, QOpcodes, 0);
1759    }
1760
1761    case Intrinsic::arm_neon_vld3: {
1762      unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
1763                              ARM::VLD3d32, ARM::VLD3d64 };
1764      unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
1765      unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
1766      return SelectVLD(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1767    }
1768
1769    case Intrinsic::arm_neon_vld4: {
1770      unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
1771                              ARM::VLD4d32, ARM::VLD4d64 };
1772      unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
1773      unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
1774      return SelectVLD(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1775    }
1776
1777    case Intrinsic::arm_neon_vld2lane: {
1778      unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
1779      unsigned QOpcodes0[] = { ARM::VLD2LNq16a, ARM::VLD2LNq32a };
1780      unsigned QOpcodes1[] = { ARM::VLD2LNq16b, ARM::VLD2LNq32b };
1781      return SelectVLDSTLane(Op, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
1782    }
1783
1784    case Intrinsic::arm_neon_vld3lane: {
1785      unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
1786      unsigned QOpcodes0[] = { ARM::VLD3LNq16a, ARM::VLD3LNq32a };
1787      unsigned QOpcodes1[] = { ARM::VLD3LNq16b, ARM::VLD3LNq32b };
1788      return SelectVLDSTLane(Op, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
1789    }
1790
1791    case Intrinsic::arm_neon_vld4lane: {
1792      unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
1793      unsigned QOpcodes0[] = { ARM::VLD4LNq16a, ARM::VLD4LNq32a };
1794      unsigned QOpcodes1[] = { ARM::VLD4LNq16b, ARM::VLD4LNq32b };
1795      return SelectVLDSTLane(Op, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
1796    }
1797
1798    case Intrinsic::arm_neon_vst2: {
1799      unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
1800                              ARM::VST2d32, ARM::VST2d64 };
1801      unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
1802      return SelectVST(Op, 2, DOpcodes, QOpcodes, 0);
1803    }
1804
1805    case Intrinsic::arm_neon_vst3: {
1806      unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
1807                              ARM::VST3d32, ARM::VST3d64 };
1808      unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
1809      unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
1810      return SelectVST(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1811    }
1812
1813    case Intrinsic::arm_neon_vst4: {
1814      unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
1815                              ARM::VST4d32, ARM::VST4d64 };
1816      unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
1817      unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
1818      return SelectVST(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1819    }
1820
1821    case Intrinsic::arm_neon_vst2lane: {
1822      unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
1823      unsigned QOpcodes0[] = { ARM::VST2LNq16a, ARM::VST2LNq32a };
1824      unsigned QOpcodes1[] = { ARM::VST2LNq16b, ARM::VST2LNq32b };
1825      return SelectVLDSTLane(Op, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
1826    }
1827
1828    case Intrinsic::arm_neon_vst3lane: {
1829      unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
1830      unsigned QOpcodes0[] = { ARM::VST3LNq16a, ARM::VST3LNq32a };
1831      unsigned QOpcodes1[] = { ARM::VST3LNq16b, ARM::VST3LNq32b };
1832      return SelectVLDSTLane(Op, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
1833    }
1834
1835    case Intrinsic::arm_neon_vst4lane: {
1836      unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
1837      unsigned QOpcodes0[] = { ARM::VST4LNq16a, ARM::VST4LNq32a };
1838      unsigned QOpcodes1[] = { ARM::VST4LNq16b, ARM::VST4LNq32b };
1839      return SelectVLDSTLane(Op, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
1840    }
1841    }
1842  }
1843  }
1844
1845  return SelectCode(Op);
1846}
1847
1848bool ARMDAGToDAGISel::
1849SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1850                             std::vector<SDValue> &OutOps) {
1851  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1852  // Require the address to be in a register.  That is safe for all ARM
1853  // variants and it is hard to do anything much smarter without knowing
1854  // how the operand is used.
1855  OutOps.push_back(Op);
1856  return false;
1857}
1858
1859/// createARMISelDag - This pass converts a legalized DAG into a
1860/// ARM-specific DAG, ready for instruction scheduling.
1861///
1862FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1863                                     CodeGenOpt::Level OptLevel) {
1864  return new ARMDAGToDAGISel(TM, OptLevel);
1865}
1866