ARMISelDAGToDAG.cpp revision ffde080ae615906545eb33dab30e7bc47c2ac838
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the ARM target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "arm-isel" 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMTargetMachine.h" 18#include "llvm/CallingConv.h" 19#include "llvm/Constants.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/Intrinsics.h" 23#include "llvm/LLVMContext.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Compiler.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/raw_ostream.h" 36 37using namespace llvm; 38 39static cl::opt<bool> 40DisableShifterOp("disable-shifter-op", cl::Hidden, 41 cl::desc("Disable isel of shifter-op"), 42 cl::init(false)); 43 44//===--------------------------------------------------------------------===// 45/// ARMDAGToDAGISel - ARM specific code to select ARM machine 46/// instructions for SelectionDAG operations. 47/// 48namespace { 49class ARMDAGToDAGISel : public SelectionDAGISel { 50 ARMBaseTargetMachine &TM; 51 52 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 53 /// make the right decision when generating code for different targets. 54 const ARMSubtarget *Subtarget; 55 56public: 57 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, 58 CodeGenOpt::Level OptLevel) 59 : SelectionDAGISel(tm, OptLevel), TM(tm), 60 Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 61 } 62 63 virtual const char *getPassName() const { 64 return "ARM Instruction Selection"; 65 } 66 67 /// getI32Imm - Return a target constant of type i32 with the specified 68 /// value. 69 inline SDValue getI32Imm(unsigned Imm) { 70 return CurDAG->getTargetConstant(Imm, MVT::i32); 71 } 72 73 SDNode *Select(SDNode *N); 74 75 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A, 76 SDValue &B, SDValue &C); 77 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base, 78 SDValue &Offset, SDValue &Opc); 79 bool SelectAddrMode2Offset(SDNode *Op, SDValue N, 80 SDValue &Offset, SDValue &Opc); 81 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base, 82 SDValue &Offset, SDValue &Opc); 83 bool SelectAddrMode3Offset(SDNode *Op, SDValue N, 84 SDValue &Offset, SDValue &Opc); 85 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr, 86 SDValue &Mode); 87 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base, 88 SDValue &Offset); 89 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align); 90 91 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset, 92 SDValue &Label); 93 94 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base, 95 SDValue &Offset); 96 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale, 97 SDValue &Base, SDValue &OffImm, 98 SDValue &Offset); 99 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base, 100 SDValue &OffImm, SDValue &Offset); 101 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base, 102 SDValue &OffImm, SDValue &Offset); 103 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base, 104 SDValue &OffImm, SDValue &Offset); 105 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base, 106 SDValue &OffImm); 107 108 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N, 109 SDValue &BaseReg, SDValue &Opc); 110 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base, 111 SDValue &OffImm); 112 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base, 113 SDValue &OffImm); 114 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 115 SDValue &OffImm); 116 bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base, 117 SDValue &OffImm); 118 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base, 119 SDValue &OffReg, SDValue &ShImm); 120 121 inline bool Pred_so_imm(SDNode *inN) const { 122 ConstantSDNode *N = cast<ConstantSDNode>(inN); 123 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; 124 } 125 126 inline bool Pred_t2_so_imm(SDNode *inN) const { 127 ConstantSDNode *N = cast<ConstantSDNode>(inN); 128 return ARM_AM::getT2SOImmVal(N->getZExtValue()) != -1; 129 } 130 131 // Include the pieces autogenerated from the target description. 132#include "ARMGenDAGISel.inc" 133 134private: 135 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for 136 /// ARM. 137 SDNode *SelectARMIndexedLoad(SDNode *N); 138 SDNode *SelectT2IndexedLoad(SDNode *N); 139 140 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 141 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for 142 /// loads of D registers and even subregs and odd subregs of Q registers. 143 /// For NumVecs <= 2, QOpcodes1 is not used. 144 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes, 145 unsigned *QOpcodes0, unsigned *QOpcodes1); 146 147 /// SelectVST - Select NEON store intrinsics. NumVecs should 148 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for 149 /// stores of D registers and even subregs and odd subregs of Q registers. 150 /// For NumVecs <= 2, QOpcodes1 is not used. 151 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes, 152 unsigned *QOpcodes0, unsigned *QOpcodes1); 153 154 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 155 /// be 2, 3 or 4. The opcode arrays specify the instructions used for 156 /// load/store of D registers and even subregs and odd subregs of Q registers. 157 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs, 158 unsigned *DOpcodes, unsigned *QOpcodes0, 159 unsigned *QOpcodes1); 160 161 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2, 162 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be 163 /// generated to force the table registers to be consecutive. 164 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc); 165 166 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM. 167 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned); 168 169 /// SelectCMOVOp - Select CMOV instructions for ARM. 170 SDNode *SelectCMOVOp(SDNode *N); 171 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 172 ARMCC::CondCodes CCVal, SDValue CCR, 173 SDValue InFlag); 174 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 175 ARMCC::CondCodes CCVal, SDValue CCR, 176 SDValue InFlag); 177 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 178 ARMCC::CondCodes CCVal, SDValue CCR, 179 SDValue InFlag); 180 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 181 ARMCC::CondCodes CCVal, SDValue CCR, 182 SDValue InFlag); 183 184 SDNode *SelectConcatVector(SDNode *N); 185 186 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 187 /// inline asm expressions. 188 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 189 char ConstraintCode, 190 std::vector<SDValue> &OutOps); 191 192 // Form pairs of consecutive S, D, or Q registers. 193 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1); 194 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1); 195 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1); 196 197 // Form sequences of 4 consecutive S, D, or Q registers. 198 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 199 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 200 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3); 201 202 // Form sequences of 8 consecutive D registers. 203 SDNode *OctoDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3, 204 SDValue V4, SDValue V5, SDValue V6, SDValue V7); 205}; 206} 207 208/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 209/// operand. If so Imm will receive the 32-bit value. 210static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 211 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 212 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 213 return true; 214 } 215 return false; 216} 217 218// isInt32Immediate - This method tests to see if a constant operand. 219// If so Imm will receive the 32 bit value. 220static bool isInt32Immediate(SDValue N, unsigned &Imm) { 221 return isInt32Immediate(N.getNode(), Imm); 222} 223 224// isOpcWithIntImmediate - This method tests to see if the node is a specific 225// opcode and that it has a immediate integer right operand. 226// If so Imm will receive the 32 bit value. 227static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 228 return N->getOpcode() == Opc && 229 isInt32Immediate(N->getOperand(1).getNode(), Imm); 230} 231 232 233bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op, 234 SDValue N, 235 SDValue &BaseReg, 236 SDValue &ShReg, 237 SDValue &Opc) { 238 if (DisableShifterOp) 239 return false; 240 241 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 242 243 // Don't match base register only case. That is matched to a separate 244 // lower complexity pattern with explicit register operand. 245 if (ShOpcVal == ARM_AM::no_shift) return false; 246 247 BaseReg = N.getOperand(0); 248 unsigned ShImmVal = 0; 249 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 250 ShReg = CurDAG->getRegister(0, MVT::i32); 251 ShImmVal = RHS->getZExtValue() & 31; 252 } else { 253 ShReg = N.getOperand(1); 254 } 255 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), 256 MVT::i32); 257 return true; 258} 259 260bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N, 261 SDValue &Base, SDValue &Offset, 262 SDValue &Opc) { 263 if (N.getOpcode() == ISD::MUL) { 264 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 265 // X * [3,5,9] -> X + X * [2,4,8] etc. 266 int RHSC = (int)RHS->getZExtValue(); 267 if (RHSC & 1) { 268 RHSC = RHSC & ~1; 269 ARM_AM::AddrOpc AddSub = ARM_AM::add; 270 if (RHSC < 0) { 271 AddSub = ARM_AM::sub; 272 RHSC = - RHSC; 273 } 274 if (isPowerOf2_32(RHSC)) { 275 unsigned ShAmt = Log2_32(RHSC); 276 Base = Offset = N.getOperand(0); 277 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, 278 ARM_AM::lsl), 279 MVT::i32); 280 return true; 281 } 282 } 283 } 284 } 285 286 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) { 287 Base = N; 288 if (N.getOpcode() == ISD::FrameIndex) { 289 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 290 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 291 } else if (N.getOpcode() == ARMISD::Wrapper && 292 !(Subtarget->useMovt() && 293 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 294 Base = N.getOperand(0); 295 } 296 Offset = CurDAG->getRegister(0, MVT::i32); 297 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, 298 ARM_AM::no_shift), 299 MVT::i32); 300 return true; 301 } 302 303 // Match simple R +/- imm12 operands. 304 if (N.getOpcode() == ISD::ADD) 305 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 306 int RHSC = (int)RHS->getZExtValue(); 307 if ((RHSC >= 0 && RHSC < 0x1000) || 308 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits. 309 Base = N.getOperand(0); 310 if (Base.getOpcode() == ISD::FrameIndex) { 311 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 312 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 313 } 314 Offset = CurDAG->getRegister(0, MVT::i32); 315 316 ARM_AM::AddrOpc AddSub = ARM_AM::add; 317 if (RHSC < 0) { 318 AddSub = ARM_AM::sub; 319 RHSC = - RHSC; 320 } 321 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, 322 ARM_AM::no_shift), 323 MVT::i32); 324 return true; 325 } 326 } 327 328 // Otherwise this is R +/- [possibly shifted] R. 329 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub; 330 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1)); 331 unsigned ShAmt = 0; 332 333 Base = N.getOperand(0); 334 Offset = N.getOperand(1); 335 336 if (ShOpcVal != ARM_AM::no_shift) { 337 // Check to see if the RHS of the shift is a constant, if not, we can't fold 338 // it. 339 if (ConstantSDNode *Sh = 340 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) { 341 ShAmt = Sh->getZExtValue(); 342 Offset = N.getOperand(1).getOperand(0); 343 } else { 344 ShOpcVal = ARM_AM::no_shift; 345 } 346 } 347 348 // Try matching (R shl C) + (R). 349 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) { 350 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0)); 351 if (ShOpcVal != ARM_AM::no_shift) { 352 // Check to see if the RHS of the shift is a constant, if not, we can't 353 // fold it. 354 if (ConstantSDNode *Sh = 355 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) { 356 ShAmt = Sh->getZExtValue(); 357 Offset = N.getOperand(0).getOperand(0); 358 Base = N.getOperand(1); 359 } else { 360 ShOpcVal = ARM_AM::no_shift; 361 } 362 } 363 } 364 365 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 366 MVT::i32); 367 return true; 368} 369 370bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N, 371 SDValue &Offset, SDValue &Opc) { 372 unsigned Opcode = Op->getOpcode(); 373 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 374 ? cast<LoadSDNode>(Op)->getAddressingMode() 375 : cast<StoreSDNode>(Op)->getAddressingMode(); 376 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 377 ? ARM_AM::add : ARM_AM::sub; 378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 379 int Val = (int)C->getZExtValue(); 380 if (Val >= 0 && Val < 0x1000) { // 12 bits. 381 Offset = CurDAG->getRegister(0, MVT::i32); 382 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, 383 ARM_AM::no_shift), 384 MVT::i32); 385 return true; 386 } 387 } 388 389 Offset = N; 390 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 391 unsigned ShAmt = 0; 392 if (ShOpcVal != ARM_AM::no_shift) { 393 // Check to see if the RHS of the shift is a constant, if not, we can't fold 394 // it. 395 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 396 ShAmt = Sh->getZExtValue(); 397 Offset = N.getOperand(0); 398 } else { 399 ShOpcVal = ARM_AM::no_shift; 400 } 401 } 402 403 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), 404 MVT::i32); 405 return true; 406} 407 408 409bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N, 410 SDValue &Base, SDValue &Offset, 411 SDValue &Opc) { 412 if (N.getOpcode() == ISD::SUB) { 413 // X - C is canonicalize to X + -C, no need to handle it here. 414 Base = N.getOperand(0); 415 Offset = N.getOperand(1); 416 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32); 417 return true; 418 } 419 420 if (N.getOpcode() != ISD::ADD) { 421 Base = N; 422 if (N.getOpcode() == ISD::FrameIndex) { 423 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 424 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 425 } 426 Offset = CurDAG->getRegister(0, MVT::i32); 427 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32); 428 return true; 429 } 430 431 // If the RHS is +/- imm8, fold into addr mode. 432 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 433 int RHSC = (int)RHS->getZExtValue(); 434 if ((RHSC >= 0 && RHSC < 256) || 435 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 436 Base = N.getOperand(0); 437 if (Base.getOpcode() == ISD::FrameIndex) { 438 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 439 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 440 } 441 Offset = CurDAG->getRegister(0, MVT::i32); 442 443 ARM_AM::AddrOpc AddSub = ARM_AM::add; 444 if (RHSC < 0) { 445 AddSub = ARM_AM::sub; 446 RHSC = - RHSC; 447 } 448 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32); 449 return true; 450 } 451 } 452 453 Base = N.getOperand(0); 454 Offset = N.getOperand(1); 455 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32); 456 return true; 457} 458 459bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N, 460 SDValue &Offset, SDValue &Opc) { 461 unsigned Opcode = Op->getOpcode(); 462 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 463 ? cast<LoadSDNode>(Op)->getAddressingMode() 464 : cast<StoreSDNode>(Op)->getAddressingMode(); 465 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 466 ? ARM_AM::add : ARM_AM::sub; 467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { 468 int Val = (int)C->getZExtValue(); 469 if (Val >= 0 && Val < 256) { 470 Offset = CurDAG->getRegister(0, MVT::i32); 471 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32); 472 return true; 473 } 474 } 475 476 Offset = N; 477 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32); 478 return true; 479} 480 481bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N, 482 SDValue &Addr, SDValue &Mode) { 483 Addr = N; 484 Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32); 485 return true; 486} 487 488bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N, 489 SDValue &Base, SDValue &Offset) { 490 if (N.getOpcode() != ISD::ADD) { 491 Base = N; 492 if (N.getOpcode() == ISD::FrameIndex) { 493 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 494 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 495 } else if (N.getOpcode() == ARMISD::Wrapper && 496 !(Subtarget->useMovt() && 497 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 498 Base = N.getOperand(0); 499 } 500 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 501 MVT::i32); 502 return true; 503 } 504 505 // If the RHS is +/- imm8, fold into addr mode. 506 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 507 int RHSC = (int)RHS->getZExtValue(); 508 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4. 509 RHSC >>= 2; 510 if ((RHSC >= 0 && RHSC < 256) || 511 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed. 512 Base = N.getOperand(0); 513 if (Base.getOpcode() == ISD::FrameIndex) { 514 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 515 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 516 } 517 518 ARM_AM::AddrOpc AddSub = ARM_AM::add; 519 if (RHSC < 0) { 520 AddSub = ARM_AM::sub; 521 RHSC = - RHSC; 522 } 523 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC), 524 MVT::i32); 525 return true; 526 } 527 } 528 } 529 530 Base = N; 531 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), 532 MVT::i32); 533 return true; 534} 535 536bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N, 537 SDValue &Addr, SDValue &Align) { 538 Addr = N; 539 // Default to no alignment. 540 Align = CurDAG->getTargetConstant(0, MVT::i32); 541 return true; 542} 543 544bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N, 545 SDValue &Offset, SDValue &Label) { 546 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) { 547 Offset = N.getOperand(0); 548 SDValue N1 = N.getOperand(1); 549 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(), 550 MVT::i32); 551 return true; 552 } 553 return false; 554} 555 556bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N, 557 SDValue &Base, SDValue &Offset){ 558 // FIXME dl should come from the parent load or store, not the address 559 if (N.getOpcode() != ISD::ADD) { 560 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N); 561 if (!NC || !NC->isNullValue()) 562 return false; 563 564 Base = Offset = N; 565 return true; 566 } 567 568 Base = N.getOperand(0); 569 Offset = N.getOperand(1); 570 return true; 571} 572 573bool 574ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N, 575 unsigned Scale, SDValue &Base, 576 SDValue &OffImm, SDValue &Offset) { 577 if (Scale == 4) { 578 SDValue TmpBase, TmpOffImm; 579 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm)) 580 return false; // We want to select tLDRspi / tSTRspi instead. 581 if (N.getOpcode() == ARMISD::Wrapper && 582 N.getOperand(0).getOpcode() == ISD::TargetConstantPool) 583 return false; // We want to select tLDRpci instead. 584 } 585 586 if (N.getOpcode() != ISD::ADD) { 587 if (N.getOpcode() == ARMISD::Wrapper && 588 !(Subtarget->useMovt() && 589 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 590 Base = N.getOperand(0); 591 } else 592 Base = N; 593 594 Offset = CurDAG->getRegister(0, MVT::i32); 595 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 596 return true; 597 } 598 599 // Thumb does not have [sp, r] address mode. 600 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 601 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1)); 602 if ((LHSR && LHSR->getReg() == ARM::SP) || 603 (RHSR && RHSR->getReg() == ARM::SP)) { 604 Base = N; 605 Offset = CurDAG->getRegister(0, MVT::i32); 606 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 607 return true; 608 } 609 610 // If the RHS is + imm5 * scale, fold into addr mode. 611 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 612 int RHSC = (int)RHS->getZExtValue(); 613 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied. 614 RHSC /= Scale; 615 if (RHSC >= 0 && RHSC < 32) { 616 Base = N.getOperand(0); 617 Offset = CurDAG->getRegister(0, MVT::i32); 618 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 619 return true; 620 } 621 } 622 } 623 624 Base = N.getOperand(0); 625 Offset = N.getOperand(1); 626 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 627 return true; 628} 629 630bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N, 631 SDValue &Base, SDValue &OffImm, 632 SDValue &Offset) { 633 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset); 634} 635 636bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N, 637 SDValue &Base, SDValue &OffImm, 638 SDValue &Offset) { 639 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset); 640} 641 642bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N, 643 SDValue &Base, SDValue &OffImm, 644 SDValue &Offset) { 645 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset); 646} 647 648bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N, 649 SDValue &Base, SDValue &OffImm) { 650 if (N.getOpcode() == ISD::FrameIndex) { 651 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 652 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 653 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 654 return true; 655 } 656 657 if (N.getOpcode() != ISD::ADD) 658 return false; 659 660 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0)); 661 if (N.getOperand(0).getOpcode() == ISD::FrameIndex || 662 (LHSR && LHSR->getReg() == ARM::SP)) { 663 // If the RHS is + imm8 * scale, fold into addr mode. 664 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 665 int RHSC = (int)RHS->getZExtValue(); 666 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied. 667 RHSC >>= 2; 668 if (RHSC >= 0 && RHSC < 256) { 669 Base = N.getOperand(0); 670 if (Base.getOpcode() == ISD::FrameIndex) { 671 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 672 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 673 } 674 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 675 return true; 676 } 677 } 678 } 679 } 680 681 return false; 682} 683 684bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N, 685 SDValue &BaseReg, 686 SDValue &Opc) { 687 if (DisableShifterOp) 688 return false; 689 690 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); 691 692 // Don't match base register only case. That is matched to a separate 693 // lower complexity pattern with explicit register operand. 694 if (ShOpcVal == ARM_AM::no_shift) return false; 695 696 BaseReg = N.getOperand(0); 697 unsigned ShImmVal = 0; 698 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 699 ShImmVal = RHS->getZExtValue() & 31; 700 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal)); 701 return true; 702 } 703 704 return false; 705} 706 707bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N, 708 SDValue &Base, SDValue &OffImm) { 709 // Match simple R + imm12 operands. 710 711 // Base only. 712 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) { 713 if (N.getOpcode() == ISD::FrameIndex) { 714 // Match frame index... 715 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 716 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 717 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 718 return true; 719 } else if (N.getOpcode() == ARMISD::Wrapper && 720 !(Subtarget->useMovt() && 721 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { 722 Base = N.getOperand(0); 723 if (Base.getOpcode() == ISD::TargetConstantPool) 724 return false; // We want to select t2LDRpci instead. 725 } else 726 Base = N; 727 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 728 return true; 729 } 730 731 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 732 if (SelectT2AddrModeImm8(Op, N, Base, OffImm)) 733 // Let t2LDRi8 handle (R - imm8). 734 return false; 735 736 int RHSC = (int)RHS->getZExtValue(); 737 if (N.getOpcode() == ISD::SUB) 738 RHSC = -RHSC; 739 740 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned) 741 Base = N.getOperand(0); 742 if (Base.getOpcode() == ISD::FrameIndex) { 743 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 744 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 745 } 746 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 747 return true; 748 } 749 } 750 751 // Base only. 752 Base = N; 753 OffImm = CurDAG->getTargetConstant(0, MVT::i32); 754 return true; 755} 756 757bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N, 758 SDValue &Base, SDValue &OffImm) { 759 // Match simple R - imm8 operands. 760 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) { 761 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 762 int RHSC = (int)RHS->getSExtValue(); 763 if (N.getOpcode() == ISD::SUB) 764 RHSC = -RHSC; 765 766 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative) 767 Base = N.getOperand(0); 768 if (Base.getOpcode() == ISD::FrameIndex) { 769 int FI = cast<FrameIndexSDNode>(Base)->getIndex(); 770 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 771 } 772 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 773 return true; 774 } 775 } 776 } 777 778 return false; 779} 780 781bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, 782 SDValue &OffImm){ 783 unsigned Opcode = Op->getOpcode(); 784 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) 785 ? cast<LoadSDNode>(Op)->getAddressingMode() 786 : cast<StoreSDNode>(Op)->getAddressingMode(); 787 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) { 788 int RHSC = (int)RHS->getZExtValue(); 789 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits. 790 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) 791 ? CurDAG->getTargetConstant(RHSC, MVT::i32) 792 : CurDAG->getTargetConstant(-RHSC, MVT::i32); 793 return true; 794 } 795 } 796 797 return false; 798} 799 800bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, 801 SDValue &Base, SDValue &OffImm) { 802 if (N.getOpcode() == ISD::ADD) { 803 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 804 int RHSC = (int)RHS->getZExtValue(); 805 // 8 bits. 806 if (((RHSC & 0x3) == 0) && 807 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { 808 Base = N.getOperand(0); 809 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); 810 return true; 811 } 812 } 813 } else if (N.getOpcode() == ISD::SUB) { 814 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 815 int RHSC = (int)RHS->getZExtValue(); 816 // 8 bits. 817 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { 818 Base = N.getOperand(0); 819 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32); 820 return true; 821 } 822 } 823 } 824 825 return false; 826} 827 828bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N, 829 SDValue &Base, 830 SDValue &OffReg, SDValue &ShImm) { 831 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12. 832 if (N.getOpcode() != ISD::ADD) 833 return false; 834 835 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8. 836 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { 837 int RHSC = (int)RHS->getZExtValue(); 838 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned) 839 return false; 840 else if (RHSC < 0 && RHSC >= -255) // 8 bits 841 return false; 842 } 843 844 // Look for (R + R) or (R + (R << [1,2,3])). 845 unsigned ShAmt = 0; 846 Base = N.getOperand(0); 847 OffReg = N.getOperand(1); 848 849 // Swap if it is ((R << c) + R). 850 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg); 851 if (ShOpcVal != ARM_AM::lsl) { 852 ShOpcVal = ARM_AM::getShiftOpcForNode(Base); 853 if (ShOpcVal == ARM_AM::lsl) 854 std::swap(Base, OffReg); 855 } 856 857 if (ShOpcVal == ARM_AM::lsl) { 858 // Check to see if the RHS of the shift is a constant, if not, we can't fold 859 // it. 860 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) { 861 ShAmt = Sh->getZExtValue(); 862 if (ShAmt >= 4) { 863 ShAmt = 0; 864 ShOpcVal = ARM_AM::no_shift; 865 } else 866 OffReg = OffReg.getOperand(0); 867 } else { 868 ShOpcVal = ARM_AM::no_shift; 869 } 870 } 871 872 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32); 873 874 return true; 875} 876 877//===--------------------------------------------------------------------===// 878 879/// getAL - Returns a ARMCC::AL immediate node. 880static inline SDValue getAL(SelectionDAG *CurDAG) { 881 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); 882} 883 884SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) { 885 LoadSDNode *LD = cast<LoadSDNode>(N); 886 ISD::MemIndexedMode AM = LD->getAddressingMode(); 887 if (AM == ISD::UNINDEXED) 888 return NULL; 889 890 EVT LoadedVT = LD->getMemoryVT(); 891 SDValue Offset, AMOpc; 892 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 893 unsigned Opcode = 0; 894 bool Match = false; 895 if (LoadedVT == MVT::i32 && 896 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { 897 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST; 898 Match = true; 899 } else if (LoadedVT == MVT::i16 && 900 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 901 Match = true; 902 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) 903 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) 904 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); 905 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { 906 if (LD->getExtensionType() == ISD::SEXTLOAD) { 907 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) { 908 Match = true; 909 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; 910 } 911 } else { 912 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) { 913 Match = true; 914 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST; 915 } 916 } 917 } 918 919 if (Match) { 920 SDValue Chain = LD->getChain(); 921 SDValue Base = LD->getBasePtr(); 922 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), 923 CurDAG->getRegister(0, MVT::i32), Chain }; 924 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, 925 MVT::Other, Ops, 6); 926 } 927 928 return NULL; 929} 930 931SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) { 932 LoadSDNode *LD = cast<LoadSDNode>(N); 933 ISD::MemIndexedMode AM = LD->getAddressingMode(); 934 if (AM == ISD::UNINDEXED) 935 return NULL; 936 937 EVT LoadedVT = LD->getMemoryVT(); 938 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; 939 SDValue Offset; 940 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); 941 unsigned Opcode = 0; 942 bool Match = false; 943 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) { 944 switch (LoadedVT.getSimpleVT().SimpleTy) { 945 case MVT::i32: 946 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; 947 break; 948 case MVT::i16: 949 if (isSExtLd) 950 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; 951 else 952 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; 953 break; 954 case MVT::i8: 955 case MVT::i1: 956 if (isSExtLd) 957 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; 958 else 959 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; 960 break; 961 default: 962 return NULL; 963 } 964 Match = true; 965 } 966 967 if (Match) { 968 SDValue Chain = LD->getChain(); 969 SDValue Base = LD->getBasePtr(); 970 SDValue Ops[]= { Base, Offset, getAL(CurDAG), 971 CurDAG->getRegister(0, MVT::i32), Chain }; 972 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, 973 MVT::Other, Ops, 5); 974 } 975 976 return NULL; 977} 978 979/// PairSRegs - Form a D register from a pair of S registers. 980/// 981SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) { 982 DebugLoc dl = V0.getNode()->getDebugLoc(); 983 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); 984 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); 985 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 986 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 987} 988 989/// PairDRegs - Form a quad register from a pair of D registers. 990/// 991SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) { 992 DebugLoc dl = V0.getNode()->getDebugLoc(); 993 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 994 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 995 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 996 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 997} 998 999/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers. 1000/// 1001SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) { 1002 DebugLoc dl = V0.getNode()->getDebugLoc(); 1003 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 1004 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 1005 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 1006 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 1007} 1008 1009/// QuadSRegs - Form 4 consecutive S registers. 1010/// 1011SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1, 1012 SDValue V2, SDValue V3) { 1013 DebugLoc dl = V0.getNode()->getDebugLoc(); 1014 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); 1015 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); 1016 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32); 1017 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32); 1018 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1019 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1020} 1021 1022/// QuadDRegs - Form 4 consecutive D registers. 1023/// 1024SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1, 1025 SDValue V2, SDValue V3) { 1026 DebugLoc dl = V0.getNode()->getDebugLoc(); 1027 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1028 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1029 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); 1030 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); 1031 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1032 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1033} 1034 1035/// QuadQRegs - Form 4 consecutive Q registers. 1036/// 1037SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1, 1038 SDValue V2, SDValue V3) { 1039 DebugLoc dl = V0.getNode()->getDebugLoc(); 1040 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); 1041 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); 1042 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32); 1043 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32); 1044 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 }; 1045 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8); 1046} 1047 1048/// OctoDRegs - Form 8 consecutive D registers. 1049/// 1050SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1, 1051 SDValue V2, SDValue V3, 1052 SDValue V4, SDValue V5, 1053 SDValue V6, SDValue V7) { 1054 DebugLoc dl = V0.getNode()->getDebugLoc(); 1055 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1056 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1057 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32); 1058 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32); 1059 SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32); 1060 SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32); 1061 SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32); 1062 SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32); 1063 const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3, 1064 V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 }; 1065 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16); 1066} 1067 1068/// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type 1069/// for a 64-bit subregister of the vector. 1070static EVT GetNEONSubregVT(EVT VT) { 1071 switch (VT.getSimpleVT().SimpleTy) { 1072 default: llvm_unreachable("unhandled NEON type"); 1073 case MVT::v16i8: return MVT::v8i8; 1074 case MVT::v8i16: return MVT::v4i16; 1075 case MVT::v4f32: return MVT::v2f32; 1076 case MVT::v4i32: return MVT::v2i32; 1077 case MVT::v2i64: return MVT::v1i64; 1078 } 1079} 1080 1081SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs, 1082 unsigned *DOpcodes, unsigned *QOpcodes0, 1083 unsigned *QOpcodes1) { 1084 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); 1085 DebugLoc dl = N->getDebugLoc(); 1086 1087 SDValue MemAddr, Align; 1088 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1089 return NULL; 1090 1091 SDValue Chain = N->getOperand(0); 1092 EVT VT = N->getValueType(0); 1093 bool is64BitVector = VT.is64BitVector(); 1094 1095 unsigned OpcodeIndex; 1096 switch (VT.getSimpleVT().SimpleTy) { 1097 default: llvm_unreachable("unhandled vld type"); 1098 // Double-register operations: 1099 case MVT::v8i8: OpcodeIndex = 0; break; 1100 case MVT::v4i16: OpcodeIndex = 1; break; 1101 case MVT::v2f32: 1102 case MVT::v2i32: OpcodeIndex = 2; break; 1103 case MVT::v1i64: OpcodeIndex = 3; break; 1104 // Quad-register operations: 1105 case MVT::v16i8: OpcodeIndex = 0; break; 1106 case MVT::v8i16: OpcodeIndex = 1; break; 1107 case MVT::v4f32: 1108 case MVT::v4i32: OpcodeIndex = 2; break; 1109 case MVT::v2i64: OpcodeIndex = 3; 1110 assert(NumVecs == 1 && "v2i64 type only supported for VLD1"); 1111 break; 1112 } 1113 1114 SDValue Pred = getAL(CurDAG); 1115 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1116 if (is64BitVector) { 1117 unsigned Opc = DOpcodes[OpcodeIndex]; 1118 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; 1119 SDNode *VLd; 1120 if (NumVecs <= 2) { 1121 EVT ResTy; 1122 if (NumVecs == 1) 1123 ResTy = VT; 1124 else 1125 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs); 1126 VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); 1127 } else { 1128 std::vector<EVT> ResTys(NumVecs, VT); 1129 ResTys.push_back(MVT::Other); 1130 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); 1131 } 1132 if (NumVecs == 1) 1133 return VLd; 1134 1135 SDValue SuperReg; 1136 if (NumVecs <= 2) 1137 SuperReg = SDValue(VLd, 0); 1138 else { 1139 SDValue V0 = SDValue(VLd, 0); 1140 SDValue V1 = SDValue(VLd, 1); 1141 // Form a REG_SEQUENCE to force register allocation. 1142 SDValue V2 = SDValue(VLd, 2); 1143 // If it's a vld3, form a quad D-register but discard the last part. 1144 SDValue V3 = (NumVecs == 3) 1145 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1146 : SDValue(VLd, 3); 1147 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1148 } 1149 1150 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 1151 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1152 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec, 1153 dl, VT, SuperReg); 1154 ReplaceUses(SDValue(N, Vec), D); 1155 } 1156 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs <= 2 ? 1 : NumVecs)); 1157 return NULL; 1158 } 1159 1160 EVT RegVT = GetNEONSubregVT(VT); 1161 if (NumVecs <= 2) { 1162 // Quad registers are directly supported for VLD1 and VLD2, 1163 // loading pairs of D regs. 1164 unsigned Opc = QOpcodes0[OpcodeIndex]; 1165 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; 1166 1167 EVT ResTy; 1168 if (NumVecs == 1) 1169 ResTy = VT; 1170 else 1171 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, 2 * NumVecs); 1172 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); 1173 1174 // Combine the even and odd subregs to produce the result. 1175 if (NumVecs == 1) 1176 return VLd; 1177 1178 SDValue QQ = SDValue(VLd, 0); 1179 Chain = SDValue(VLd, 1); 1180 1181 SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ); 1182 SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ); 1183 ReplaceUses(SDValue(N, 0), Q0); 1184 ReplaceUses(SDValue(N, 1), Q1); 1185 } else { 1186 // Otherwise, quad registers are loaded with two separate instructions, 1187 // where one loads the even registers and the other loads the odd registers. 1188 1189 std::vector<EVT> ResTys(NumVecs, RegVT); 1190 ResTys.push_back(MemAddr.getValueType()); 1191 ResTys.push_back(MVT::Other); 1192 1193 // Load the even subregs. 1194 unsigned Opc = QOpcodes0[OpcodeIndex]; 1195 const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain }; 1196 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6); 1197 Chain = SDValue(VLdA, NumVecs+1); 1198 1199 // Load the odd subregs. 1200 Opc = QOpcodes1[OpcodeIndex]; 1201 const SDValue OpsB[] = { SDValue(VLdA, NumVecs), 1202 Align, Reg0, Pred, Reg0, Chain }; 1203 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6); 1204 Chain = SDValue(VLdB, NumVecs+1); 1205 1206 SDValue V0 = SDValue(VLdA, 0); 1207 SDValue V1 = SDValue(VLdB, 0); 1208 SDValue V2 = SDValue(VLdA, 1); 1209 SDValue V3 = SDValue(VLdB, 1); 1210 SDValue V4 = SDValue(VLdA, 2); 1211 SDValue V5 = SDValue(VLdB, 2); 1212 SDValue V6 = (NumVecs == 3) 1213 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0) 1214 : SDValue(VLdA, 3); 1215 SDValue V7 = (NumVecs == 3) 1216 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0) 1217 : SDValue(VLdB, 3); 1218 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3, 1219 V4, V5, V6, V7), 0); 1220 1221 // Extract out the 3 / 4 Q registers. 1222 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1223 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { 1224 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec, 1225 dl, VT, RegSeq); 1226 ReplaceUses(SDValue(N, Vec), Q); 1227 } 1228 } 1229 ReplaceUses(SDValue(N, NumVecs), Chain); 1230 return NULL; 1231} 1232 1233SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs, 1234 unsigned *DOpcodes, unsigned *QOpcodes0, 1235 unsigned *QOpcodes1) { 1236 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); 1237 DebugLoc dl = N->getDebugLoc(); 1238 1239 SDValue MemAddr, Align; 1240 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1241 return NULL; 1242 1243 SDValue Chain = N->getOperand(0); 1244 EVT VT = N->getOperand(3).getValueType(); 1245 bool is64BitVector = VT.is64BitVector(); 1246 1247 unsigned OpcodeIndex; 1248 switch (VT.getSimpleVT().SimpleTy) { 1249 default: llvm_unreachable("unhandled vst type"); 1250 // Double-register operations: 1251 case MVT::v8i8: OpcodeIndex = 0; break; 1252 case MVT::v4i16: OpcodeIndex = 1; break; 1253 case MVT::v2f32: 1254 case MVT::v2i32: OpcodeIndex = 2; break; 1255 case MVT::v1i64: OpcodeIndex = 3; break; 1256 // Quad-register operations: 1257 case MVT::v16i8: OpcodeIndex = 0; break; 1258 case MVT::v8i16: OpcodeIndex = 1; break; 1259 case MVT::v4f32: 1260 case MVT::v4i32: OpcodeIndex = 2; break; 1261 case MVT::v2i64: OpcodeIndex = 3; 1262 assert(NumVecs == 1 && "v2i64 type only supported for VST1"); 1263 break; 1264 } 1265 1266 SDValue Pred = getAL(CurDAG); 1267 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1268 1269 SmallVector<SDValue, 7> Ops; 1270 Ops.push_back(MemAddr); 1271 Ops.push_back(Align); 1272 1273 if (is64BitVector) { 1274 if (NumVecs == 1) { 1275 Ops.push_back(N->getOperand(3)); 1276 } else { 1277 SDValue RegSeq; 1278 SDValue V0 = N->getOperand(0+3); 1279 SDValue V1 = N->getOperand(1+3); 1280 1281 // Form a REG_SEQUENCE to force register allocation. 1282 if (NumVecs == 2) 1283 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1284 else { 1285 SDValue V2 = N->getOperand(2+3); 1286 // If it's a vld3, form a quad D-register and leave the last part as 1287 // an undef. 1288 SDValue V3 = (NumVecs == 3) 1289 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1290 : N->getOperand(3+3); 1291 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1292 } 1293 Ops.push_back(RegSeq); 1294 } 1295 Ops.push_back(Pred); 1296 Ops.push_back(Reg0); // predicate register 1297 Ops.push_back(Chain); 1298 unsigned Opc = DOpcodes[OpcodeIndex]; 1299 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6); 1300 } 1301 1302 if (NumVecs <= 2) { 1303 // Quad registers are directly supported for VST1 and VST2. 1304 unsigned Opc = QOpcodes0[OpcodeIndex]; 1305 if (NumVecs == 1) { 1306 Ops.push_back(N->getOperand(3)); 1307 } else { 1308 // Form a QQ register. 1309 SDValue Q0 = N->getOperand(3); 1310 SDValue Q1 = N->getOperand(4); 1311 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0)); 1312 } 1313 Ops.push_back(Pred); 1314 Ops.push_back(Reg0); // predicate register 1315 Ops.push_back(Chain); 1316 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6); 1317 } 1318 1319 // Otherwise, quad registers are stored with two separate instructions, 1320 // where one stores the even registers and the other stores the odd registers. 1321 1322 // Form the QQQQ REG_SEQUENCE. 1323 SDValue V0 = N->getOperand(0+3); 1324 SDValue V1 = N->getOperand(1+3); 1325 SDValue V2 = N->getOperand(2+3); 1326 SDValue V3 = (NumVecs == 3) 1327 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 1328 : N->getOperand(3+3); 1329 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1330 1331 // Store the even D registers. 1332 Ops.push_back(Reg0); // post-access address offset 1333 Ops.push_back(RegSeq); 1334 Ops.push_back(Pred); 1335 Ops.push_back(Reg0); // predicate register 1336 Ops.push_back(Chain); 1337 unsigned Opc = QOpcodes0[OpcodeIndex]; 1338 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1339 MVT::Other, Ops.data(), 7); 1340 Chain = SDValue(VStA, 1); 1341 1342 // Store the odd D registers. 1343 Ops[0] = SDValue(VStA, 0); // MemAddr 1344 Ops[6] = Chain; 1345 Opc = QOpcodes1[OpcodeIndex]; 1346 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), 1347 MVT::Other, Ops.data(), 7); 1348 Chain = SDValue(VStB, 1); 1349 ReplaceUses(SDValue(N, 0), Chain); 1350 return NULL; 1351} 1352 1353SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, 1354 unsigned NumVecs, unsigned *DOpcodes, 1355 unsigned *QOpcodes0, 1356 unsigned *QOpcodes1) { 1357 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range"); 1358 DebugLoc dl = N->getDebugLoc(); 1359 1360 SDValue MemAddr, Align; 1361 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align)) 1362 return NULL; 1363 1364 SDValue Chain = N->getOperand(0); 1365 unsigned Lane = 1366 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue(); 1367 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType(); 1368 bool is64BitVector = VT.is64BitVector(); 1369 1370 // Quad registers are handled by load/store of subregs. Find the subreg info. 1371 unsigned NumElts = 0; 1372 bool Even = false; 1373 EVT RegVT = VT; 1374 if (!is64BitVector) { 1375 RegVT = GetNEONSubregVT(VT); 1376 NumElts = RegVT.getVectorNumElements(); 1377 Even = Lane < NumElts; 1378 } 1379 1380 unsigned OpcodeIndex; 1381 switch (VT.getSimpleVT().SimpleTy) { 1382 default: llvm_unreachable("unhandled vld/vst lane type"); 1383 // Double-register operations: 1384 case MVT::v8i8: OpcodeIndex = 0; break; 1385 case MVT::v4i16: OpcodeIndex = 1; break; 1386 case MVT::v2f32: 1387 case MVT::v2i32: OpcodeIndex = 2; break; 1388 // Quad-register operations: 1389 case MVT::v8i16: OpcodeIndex = 0; break; 1390 case MVT::v4f32: 1391 case MVT::v4i32: OpcodeIndex = 1; break; 1392 } 1393 1394 SDValue Pred = getAL(CurDAG); 1395 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1396 1397 SmallVector<SDValue, 10> Ops; 1398 Ops.push_back(MemAddr); 1399 Ops.push_back(Align); 1400 1401 unsigned Opc = 0; 1402 if (is64BitVector) { 1403 Opc = DOpcodes[OpcodeIndex]; 1404 SDValue RegSeq; 1405 SDValue V0 = N->getOperand(0+3); 1406 SDValue V1 = N->getOperand(1+3); 1407 if (NumVecs == 2) { 1408 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1409 } else { 1410 SDValue V2 = N->getOperand(2+3); 1411 SDValue V3 = (NumVecs == 3) 1412 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1413 : N->getOperand(3+3); 1414 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1415 } 1416 1417 // Now extract the D registers back out. 1418 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq)); 1419 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq)); 1420 if (NumVecs > 2) 1421 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq)); 1422 if (NumVecs > 3) 1423 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq)); 1424 } else { 1425 // Check if this is loading the even or odd subreg of a Q register. 1426 if (Lane < NumElts) { 1427 Opc = QOpcodes0[OpcodeIndex]; 1428 } else { 1429 Lane -= NumElts; 1430 Opc = QOpcodes1[OpcodeIndex]; 1431 } 1432 1433 SDValue RegSeq; 1434 SDValue V0 = N->getOperand(0+3); 1435 SDValue V1 = N->getOperand(1+3); 1436 if (NumVecs == 2) { 1437 RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); 1438 } else { 1439 SDValue V2 = N->getOperand(2+3); 1440 SDValue V3 = (NumVecs == 3) 1441 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1442 : N->getOperand(3+3); 1443 RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1444 } 1445 1446 // Extract the subregs of the input vector. 1447 unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1; 1448 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1449 Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT, 1450 RegSeq)); 1451 } 1452 Ops.push_back(getI32Imm(Lane)); 1453 Ops.push_back(Pred); 1454 Ops.push_back(Reg0); 1455 Ops.push_back(Chain); 1456 1457 if (!IsLoad) 1458 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6); 1459 1460 std::vector<EVT> ResTys(NumVecs, RegVT); 1461 ResTys.push_back(MVT::Other); 1462 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6); 1463 1464 // Form a REG_SEQUENCE to force register allocation. 1465 SDValue RegSeq; 1466 if (is64BitVector) { 1467 SDValue V0 = SDValue(VLdLn, 0); 1468 SDValue V1 = SDValue(VLdLn, 1); 1469 if (NumVecs == 2) { 1470 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1471 } else { 1472 SDValue V2 = SDValue(VLdLn, 2); 1473 // If it's a vld3, form a quad D-register but discard the last part. 1474 SDValue V3 = (NumVecs == 3) 1475 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) 1476 : SDValue(VLdLn, 3); 1477 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1478 } 1479 } else { 1480 // For 128-bit vectors, take the 64-bit results of the load and insert 1481 // them as subregs into the result. 1482 SDValue V[8]; 1483 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { 1484 if (Even) { 1485 V[i] = SDValue(VLdLn, Vec); 1486 V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1487 dl, RegVT), 0); 1488 } else { 1489 V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1490 dl, RegVT), 0); 1491 V[i+1] = SDValue(VLdLn, Vec); 1492 } 1493 } 1494 if (NumVecs == 3) 1495 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1496 dl, RegVT), 0); 1497 1498 if (NumVecs == 2) 1499 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0); 1500 else 1501 RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], 1502 V[4], V[5], V[6], V[7]), 0); 1503 } 1504 1505 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 1506 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); 1507 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; 1508 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) 1509 ReplaceUses(SDValue(N, Vec), 1510 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq)); 1511 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs)); 1512 return NULL; 1513} 1514 1515SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, 1516 unsigned Opc) { 1517 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range"); 1518 DebugLoc dl = N->getDebugLoc(); 1519 EVT VT = N->getValueType(0); 1520 unsigned FirstTblReg = IsExt ? 2 : 1; 1521 1522 // Form a REG_SEQUENCE to force register allocation. 1523 SDValue RegSeq; 1524 SDValue V0 = N->getOperand(FirstTblReg + 0); 1525 SDValue V1 = N->getOperand(FirstTblReg + 1); 1526 if (NumVecs == 2) 1527 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0); 1528 else { 1529 SDValue V2 = N->getOperand(FirstTblReg + 2); 1530 // If it's a vtbl3, form a quad D-register and leave the last part as 1531 // an undef. 1532 SDValue V3 = (NumVecs == 3) 1533 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) 1534 : N->getOperand(FirstTblReg + 3); 1535 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1536 } 1537 1538 // Now extract the D registers back out. 1539 SmallVector<SDValue, 6> Ops; 1540 if (IsExt) 1541 Ops.push_back(N->getOperand(1)); 1542 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq)); 1543 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq)); 1544 if (NumVecs > 2) 1545 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, RegSeq)); 1546 if (NumVecs > 3) 1547 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, RegSeq)); 1548 1549 Ops.push_back(N->getOperand(FirstTblReg + NumVecs)); 1550 Ops.push_back(getAL(CurDAG)); // predicate 1551 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register 1552 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size()); 1553} 1554 1555SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N, 1556 bool isSigned) { 1557 if (!Subtarget->hasV6T2Ops()) 1558 return NULL; 1559 1560 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) 1561 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); 1562 1563 1564 // For unsigned extracts, check for a shift right and mask 1565 unsigned And_imm = 0; 1566 if (N->getOpcode() == ISD::AND) { 1567 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) { 1568 1569 // The immediate is a mask of the low bits iff imm & (imm+1) == 0 1570 if (And_imm & (And_imm + 1)) 1571 return NULL; 1572 1573 unsigned Srl_imm = 0; 1574 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, 1575 Srl_imm)) { 1576 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 1577 1578 unsigned Width = CountTrailingOnes_32(And_imm); 1579 unsigned LSB = Srl_imm; 1580 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1581 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1582 CurDAG->getTargetConstant(LSB, MVT::i32), 1583 CurDAG->getTargetConstant(Width, MVT::i32), 1584 getAL(CurDAG), Reg0 }; 1585 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1586 } 1587 } 1588 return NULL; 1589 } 1590 1591 // Otherwise, we're looking for a shift of a shift 1592 unsigned Shl_imm = 0; 1593 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) { 1594 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!"); 1595 unsigned Srl_imm = 0; 1596 if (isInt32Immediate(N->getOperand(1), Srl_imm)) { 1597 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!"); 1598 unsigned Width = 32 - Srl_imm; 1599 int LSB = Srl_imm - Shl_imm; 1600 if (LSB < 0) 1601 return NULL; 1602 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1603 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1604 CurDAG->getTargetConstant(LSB, MVT::i32), 1605 CurDAG->getTargetConstant(Width, MVT::i32), 1606 getAL(CurDAG), Reg0 }; 1607 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1608 } 1609 } 1610 return NULL; 1611} 1612 1613SDNode *ARMDAGToDAGISel:: 1614SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1615 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1616 SDValue CPTmp0; 1617 SDValue CPTmp1; 1618 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) { 1619 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue(); 1620 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal); 1621 unsigned Opc = 0; 1622 switch (SOShOp) { 1623 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break; 1624 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break; 1625 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break; 1626 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break; 1627 default: 1628 llvm_unreachable("Unknown so_reg opcode!"); 1629 break; 1630 } 1631 SDValue SOShImm = 1632 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); 1633 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1634 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag }; 1635 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6); 1636 } 1637 return 0; 1638} 1639 1640SDNode *ARMDAGToDAGISel:: 1641SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1642 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1643 SDValue CPTmp0; 1644 SDValue CPTmp1; 1645 SDValue CPTmp2; 1646 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) { 1647 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1648 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag }; 1649 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7); 1650 } 1651 return 0; 1652} 1653 1654SDNode *ARMDAGToDAGISel:: 1655SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1656 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1657 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 1658 if (!T) 1659 return 0; 1660 1661 if (Pred_t2_so_imm(TrueVal.getNode())) { 1662 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); 1663 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1664 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 1665 return CurDAG->SelectNodeTo(N, 1666 ARM::t2MOVCCi, MVT::i32, Ops, 5); 1667 } 1668 return 0; 1669} 1670 1671SDNode *ARMDAGToDAGISel:: 1672SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, 1673 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { 1674 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal); 1675 if (!T) 1676 return 0; 1677 1678 if (Pred_so_imm(TrueVal.getNode())) { 1679 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); 1680 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); 1681 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; 1682 return CurDAG->SelectNodeTo(N, 1683 ARM::MOVCCi, MVT::i32, Ops, 5); 1684 } 1685 return 0; 1686} 1687 1688SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) { 1689 EVT VT = N->getValueType(0); 1690 SDValue FalseVal = N->getOperand(0); 1691 SDValue TrueVal = N->getOperand(1); 1692 SDValue CC = N->getOperand(2); 1693 SDValue CCR = N->getOperand(3); 1694 SDValue InFlag = N->getOperand(4); 1695 assert(CC.getOpcode() == ISD::Constant); 1696 assert(CCR.getOpcode() == ISD::Register); 1697 ARMCC::CondCodes CCVal = 1698 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue(); 1699 1700 if (!Subtarget->isThumb1Only() && VT == MVT::i32) { 1701 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 1702 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) 1703 // Pattern complexity = 18 cost = 1 size = 0 1704 SDValue CPTmp0; 1705 SDValue CPTmp1; 1706 SDValue CPTmp2; 1707 if (Subtarget->isThumb()) { 1708 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal, 1709 CCVal, CCR, InFlag); 1710 if (!Res) 1711 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal, 1712 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1713 if (Res) 1714 return Res; 1715 } else { 1716 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal, 1717 CCVal, CCR, InFlag); 1718 if (!Res) 1719 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal, 1720 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1721 if (Res) 1722 return Res; 1723 } 1724 1725 // Pattern: (ARMcmov:i32 GPR:i32:$false, 1726 // (imm:i32)<<P:Pred_so_imm>>:$true, 1727 // (imm:i32):$cc) 1728 // Emits: (MOVCCi:i32 GPR:i32:$false, 1729 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc) 1730 // Pattern complexity = 10 cost = 1 size = 0 1731 if (Subtarget->isThumb()) { 1732 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal, 1733 CCVal, CCR, InFlag); 1734 if (!Res) 1735 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal, 1736 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1737 if (Res) 1738 return Res; 1739 } else { 1740 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal, 1741 CCVal, CCR, InFlag); 1742 if (!Res) 1743 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal, 1744 ARMCC::getOppositeCondition(CCVal), CCR, InFlag); 1745 if (Res) 1746 return Res; 1747 } 1748 } 1749 1750 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1751 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1752 // Pattern complexity = 6 cost = 1 size = 0 1753 // 1754 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1755 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc) 1756 // Pattern complexity = 6 cost = 11 size = 0 1757 // 1758 // Also FCPYScc and FCPYDcc. 1759 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32); 1760 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag }; 1761 unsigned Opc = 0; 1762 switch (VT.getSimpleVT().SimpleTy) { 1763 default: assert(false && "Illegal conditional move type!"); 1764 break; 1765 case MVT::i32: 1766 Opc = Subtarget->isThumb() 1767 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo) 1768 : ARM::MOVCCr; 1769 break; 1770 case MVT::f32: 1771 Opc = ARM::VMOVScc; 1772 break; 1773 case MVT::f64: 1774 Opc = ARM::VMOVDcc; 1775 break; 1776 } 1777 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); 1778} 1779 1780SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) { 1781 // The only time a CONCAT_VECTORS operation can have legal types is when 1782 // two 64-bit vectors are concatenated to a 128-bit vector. 1783 EVT VT = N->getValueType(0); 1784 if (!VT.is128BitVector() || N->getNumOperands() != 2) 1785 llvm_unreachable("unexpected CONCAT_VECTORS"); 1786 DebugLoc dl = N->getDebugLoc(); 1787 SDValue V0 = N->getOperand(0); 1788 SDValue V1 = N->getOperand(1); 1789 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); 1790 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); 1791 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; 1792 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); 1793} 1794 1795SDNode *ARMDAGToDAGISel::Select(SDNode *N) { 1796 DebugLoc dl = N->getDebugLoc(); 1797 1798 if (N->isMachineOpcode()) 1799 return NULL; // Already selected. 1800 1801 switch (N->getOpcode()) { 1802 default: break; 1803 case ISD::Constant: { 1804 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue(); 1805 bool UseCP = true; 1806 if (Subtarget->hasThumb2()) 1807 // Thumb2-aware targets have the MOVT instruction, so all immediates can 1808 // be done with MOV + MOVT, at worst. 1809 UseCP = 0; 1810 else { 1811 if (Subtarget->isThumb()) { 1812 UseCP = (Val > 255 && // MOV 1813 ~Val > 255 && // MOV + MVN 1814 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL 1815 } else 1816 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV 1817 ARM_AM::getSOImmVal(~Val) == -1 && // MVN 1818 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs. 1819 } 1820 1821 if (UseCP) { 1822 SDValue CPIdx = 1823 CurDAG->getTargetConstantPool(ConstantInt::get( 1824 Type::getInt32Ty(*CurDAG->getContext()), Val), 1825 TLI.getPointerTy()); 1826 1827 SDNode *ResNode; 1828 if (Subtarget->isThumb1Only()) { 1829 SDValue Pred = getAL(CurDAG); 1830 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 1831 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; 1832 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, 1833 Ops, 4); 1834 } else { 1835 SDValue Ops[] = { 1836 CPIdx, 1837 CurDAG->getRegister(0, MVT::i32), 1838 CurDAG->getTargetConstant(0, MVT::i32), 1839 getAL(CurDAG), 1840 CurDAG->getRegister(0, MVT::i32), 1841 CurDAG->getEntryNode() 1842 }; 1843 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, 1844 Ops, 6); 1845 } 1846 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0)); 1847 return NULL; 1848 } 1849 1850 // Other cases are autogenerated. 1851 break; 1852 } 1853 case ISD::FrameIndex: { 1854 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm. 1855 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 1856 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1857 if (Subtarget->isThumb1Only()) { 1858 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, 1859 CurDAG->getTargetConstant(0, MVT::i32)); 1860 } else { 1861 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? 1862 ARM::t2ADDri : ARM::ADDri); 1863 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), 1864 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1865 CurDAG->getRegister(0, MVT::i32) }; 1866 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); 1867 } 1868 } 1869 case ISD::SRL: 1870 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 1871 return I; 1872 break; 1873 case ISD::SRA: 1874 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true)) 1875 return I; 1876 break; 1877 case ISD::MUL: 1878 if (Subtarget->isThumb1Only()) 1879 break; 1880 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 1881 unsigned RHSV = C->getZExtValue(); 1882 if (!RHSV) break; 1883 if (isPowerOf2_32(RHSV-1)) { // 2^n+1? 1884 unsigned ShImm = Log2_32(RHSV-1); 1885 if (ShImm >= 32) 1886 break; 1887 SDValue V = N->getOperand(0); 1888 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 1889 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 1890 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1891 if (Subtarget->isThumb()) { 1892 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1893 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6); 1894 } else { 1895 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1896 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7); 1897 } 1898 } 1899 if (isPowerOf2_32(RHSV+1)) { // 2^n-1? 1900 unsigned ShImm = Log2_32(RHSV+1); 1901 if (ShImm >= 32) 1902 break; 1903 SDValue V = N->getOperand(0); 1904 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); 1905 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); 1906 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); 1907 if (Subtarget->isThumb()) { 1908 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1909 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6); 1910 } else { 1911 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; 1912 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7); 1913 } 1914 } 1915 } 1916 break; 1917 case ISD::AND: { 1918 // Check for unsigned bitfield extract 1919 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false)) 1920 return I; 1921 1922 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits 1923 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits 1924 // are entirely contributed by c2 and lower 16-bits are entirely contributed 1925 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)). 1926 // Select it to: "movt x, ((c1 & 0xffff) >> 16) 1927 EVT VT = N->getValueType(0); 1928 if (VT != MVT::i32) 1929 break; 1930 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) 1931 ? ARM::t2MOVTi16 1932 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); 1933 if (!Opc) 1934 break; 1935 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1936 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1937 if (!N1C) 1938 break; 1939 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) { 1940 SDValue N2 = N0.getOperand(1); 1941 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1942 if (!N2C) 1943 break; 1944 unsigned N1CVal = N1C->getZExtValue(); 1945 unsigned N2CVal = N2C->getZExtValue(); 1946 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) && 1947 (N1CVal & 0xffffU) == 0xffffU && 1948 (N2CVal & 0xffffU) == 0x0U) { 1949 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16, 1950 MVT::i32); 1951 SDValue Ops[] = { N0.getOperand(0), Imm16, 1952 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 1953 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4); 1954 } 1955 } 1956 break; 1957 } 1958 case ARMISD::VMOVRRD: 1959 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, 1960 N->getOperand(0), getAL(CurDAG), 1961 CurDAG->getRegister(0, MVT::i32)); 1962 case ISD::UMUL_LOHI: { 1963 if (Subtarget->isThumb1Only()) 1964 break; 1965 if (Subtarget->isThumb()) { 1966 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1967 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1968 CurDAG->getRegister(0, MVT::i32) }; 1969 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4); 1970 } else { 1971 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1972 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1973 CurDAG->getRegister(0, MVT::i32) }; 1974 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); 1975 } 1976 } 1977 case ISD::SMUL_LOHI: { 1978 if (Subtarget->isThumb1Only()) 1979 break; 1980 if (Subtarget->isThumb()) { 1981 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1982 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; 1983 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4); 1984 } else { 1985 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 1986 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), 1987 CurDAG->getRegister(0, MVT::i32) }; 1988 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); 1989 } 1990 } 1991 case ISD::LOAD: { 1992 SDNode *ResNode = 0; 1993 if (Subtarget->isThumb() && Subtarget->hasThumb2()) 1994 ResNode = SelectT2IndexedLoad(N); 1995 else 1996 ResNode = SelectARMIndexedLoad(N); 1997 if (ResNode) 1998 return ResNode; 1999 // Other cases are autogenerated. 2000 break; 2001 } 2002 case ARMISD::BRCOND: { 2003 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2004 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc) 2005 // Pattern complexity = 6 cost = 1 size = 0 2006 2007 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2008 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc) 2009 // Pattern complexity = 6 cost = 1 size = 0 2010 2011 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc) 2012 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc) 2013 // Pattern complexity = 6 cost = 1 size = 0 2014 2015 unsigned Opc = Subtarget->isThumb() ? 2016 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; 2017 SDValue Chain = N->getOperand(0); 2018 SDValue N1 = N->getOperand(1); 2019 SDValue N2 = N->getOperand(2); 2020 SDValue N3 = N->getOperand(3); 2021 SDValue InFlag = N->getOperand(4); 2022 assert(N1.getOpcode() == ISD::BasicBlock); 2023 assert(N2.getOpcode() == ISD::Constant); 2024 assert(N3.getOpcode() == ISD::Register); 2025 2026 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 2027 cast<ConstantSDNode>(N2)->getZExtValue()), 2028 MVT::i32); 2029 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; 2030 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other, 2031 MVT::Flag, Ops, 5); 2032 Chain = SDValue(ResNode, 0); 2033 if (N->getNumValues() == 2) { 2034 InFlag = SDValue(ResNode, 1); 2035 ReplaceUses(SDValue(N, 1), InFlag); 2036 } 2037 ReplaceUses(SDValue(N, 0), 2038 SDValue(Chain.getNode(), Chain.getResNo())); 2039 return NULL; 2040 } 2041 case ARMISD::CMOV: 2042 return SelectCMOVOp(N); 2043 case ARMISD::CNEG: { 2044 EVT VT = N->getValueType(0); 2045 SDValue N0 = N->getOperand(0); 2046 SDValue N1 = N->getOperand(1); 2047 SDValue N2 = N->getOperand(2); 2048 SDValue N3 = N->getOperand(3); 2049 SDValue InFlag = N->getOperand(4); 2050 assert(N2.getOpcode() == ISD::Constant); 2051 assert(N3.getOpcode() == ISD::Register); 2052 2053 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) 2054 cast<ConstantSDNode>(N2)->getZExtValue()), 2055 MVT::i32); 2056 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; 2057 unsigned Opc = 0; 2058 switch (VT.getSimpleVT().SimpleTy) { 2059 default: assert(false && "Illegal conditional move type!"); 2060 break; 2061 case MVT::f32: 2062 Opc = ARM::VNEGScc; 2063 break; 2064 case MVT::f64: 2065 Opc = ARM::VNEGDcc; 2066 break; 2067 } 2068 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5); 2069 } 2070 2071 case ARMISD::VZIP: { 2072 unsigned Opc = 0; 2073 EVT VT = N->getValueType(0); 2074 switch (VT.getSimpleVT().SimpleTy) { 2075 default: return NULL; 2076 case MVT::v8i8: Opc = ARM::VZIPd8; break; 2077 case MVT::v4i16: Opc = ARM::VZIPd16; break; 2078 case MVT::v2f32: 2079 case MVT::v2i32: Opc = ARM::VZIPd32; break; 2080 case MVT::v16i8: Opc = ARM::VZIPq8; break; 2081 case MVT::v8i16: Opc = ARM::VZIPq16; break; 2082 case MVT::v4f32: 2083 case MVT::v4i32: Opc = ARM::VZIPq32; break; 2084 } 2085 SDValue Pred = getAL(CurDAG); 2086 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2087 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2088 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2089 } 2090 case ARMISD::VUZP: { 2091 unsigned Opc = 0; 2092 EVT VT = N->getValueType(0); 2093 switch (VT.getSimpleVT().SimpleTy) { 2094 default: return NULL; 2095 case MVT::v8i8: Opc = ARM::VUZPd8; break; 2096 case MVT::v4i16: Opc = ARM::VUZPd16; break; 2097 case MVT::v2f32: 2098 case MVT::v2i32: Opc = ARM::VUZPd32; break; 2099 case MVT::v16i8: Opc = ARM::VUZPq8; break; 2100 case MVT::v8i16: Opc = ARM::VUZPq16; break; 2101 case MVT::v4f32: 2102 case MVT::v4i32: Opc = ARM::VUZPq32; break; 2103 } 2104 SDValue Pred = getAL(CurDAG); 2105 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2106 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2107 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2108 } 2109 case ARMISD::VTRN: { 2110 unsigned Opc = 0; 2111 EVT VT = N->getValueType(0); 2112 switch (VT.getSimpleVT().SimpleTy) { 2113 default: return NULL; 2114 case MVT::v8i8: Opc = ARM::VTRNd8; break; 2115 case MVT::v4i16: Opc = ARM::VTRNd16; break; 2116 case MVT::v2f32: 2117 case MVT::v2i32: Opc = ARM::VTRNd32; break; 2118 case MVT::v16i8: Opc = ARM::VTRNq8; break; 2119 case MVT::v8i16: Opc = ARM::VTRNq16; break; 2120 case MVT::v4f32: 2121 case MVT::v4i32: Opc = ARM::VTRNq32; break; 2122 } 2123 SDValue Pred = getAL(CurDAG); 2124 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); 2125 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; 2126 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); 2127 } 2128 case ARMISD::BUILD_VECTOR: { 2129 EVT VecVT = N->getValueType(0); 2130 EVT EltVT = VecVT.getVectorElementType(); 2131 unsigned NumElts = VecVT.getVectorNumElements(); 2132 if (EltVT.getSimpleVT() == MVT::f64) { 2133 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR"); 2134 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1)); 2135 } 2136 assert(EltVT.getSimpleVT() == MVT::f32 && 2137 "unexpected type for BUILD_VECTOR"); 2138 if (NumElts == 2) 2139 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1)); 2140 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR"); 2141 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1), 2142 N->getOperand(2), N->getOperand(3)); 2143 } 2144 2145 case ISD::INTRINSIC_VOID: 2146 case ISD::INTRINSIC_W_CHAIN: { 2147 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2148 switch (IntNo) { 2149 default: 2150 break; 2151 2152 case Intrinsic::arm_neon_vld1: { 2153 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, 2154 ARM::VLD1d32, ARM::VLD1d64 }; 2155 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo, 2156 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo }; 2157 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0); 2158 } 2159 2160 case Intrinsic::arm_neon_vld2: { 2161 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo, 2162 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo }; 2163 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, 2164 ARM::VLD2q32Pseudo }; 2165 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0); 2166 } 2167 2168 case Intrinsic::arm_neon_vld3: { 2169 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16, 2170 ARM::VLD3d32, ARM::VLD1d64T }; 2171 unsigned QOpcodes0[] = { ARM::VLD3q8_UPD, 2172 ARM::VLD3q16_UPD, 2173 ARM::VLD3q32_UPD }; 2174 unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD, 2175 ARM::VLD3q16odd_UPD, 2176 ARM::VLD3q32odd_UPD }; 2177 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1); 2178 } 2179 2180 case Intrinsic::arm_neon_vld4: { 2181 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16, 2182 ARM::VLD4d32, ARM::VLD1d64Q }; 2183 unsigned QOpcodes0[] = { ARM::VLD4q8_UPD, 2184 ARM::VLD4q16_UPD, 2185 ARM::VLD4q32_UPD }; 2186 unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD, 2187 ARM::VLD4q16odd_UPD, 2188 ARM::VLD4q32odd_UPD }; 2189 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1); 2190 } 2191 2192 case Intrinsic::arm_neon_vld2lane: { 2193 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 }; 2194 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 }; 2195 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd }; 2196 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1); 2197 } 2198 2199 case Intrinsic::arm_neon_vld3lane: { 2200 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 }; 2201 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 }; 2202 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd }; 2203 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1); 2204 } 2205 2206 case Intrinsic::arm_neon_vld4lane: { 2207 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 }; 2208 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 }; 2209 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd }; 2210 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1); 2211 } 2212 2213 case Intrinsic::arm_neon_vst1: { 2214 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, 2215 ARM::VST1d32, ARM::VST1d64 }; 2216 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo, 2217 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo }; 2218 return SelectVST(N, 1, DOpcodes, QOpcodes, 0); 2219 } 2220 2221 case Intrinsic::arm_neon_vst2: { 2222 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo, 2223 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo }; 2224 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo, 2225 ARM::VST2q32Pseudo }; 2226 return SelectVST(N, 2, DOpcodes, QOpcodes, 0); 2227 } 2228 2229 case Intrinsic::arm_neon_vst3: { 2230 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo, 2231 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo }; 2232 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, 2233 ARM::VST3q16Pseudo_UPD, 2234 ARM::VST3q32Pseudo_UPD }; 2235 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD, 2236 ARM::VST3q16oddPseudo_UPD, 2237 ARM::VST3q32oddPseudo_UPD }; 2238 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1); 2239 } 2240 2241 case Intrinsic::arm_neon_vst4: { 2242 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo, 2243 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo }; 2244 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, 2245 ARM::VST4q16Pseudo_UPD, 2246 ARM::VST4q32Pseudo_UPD }; 2247 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD, 2248 ARM::VST4q16oddPseudo_UPD, 2249 ARM::VST4q32oddPseudo_UPD }; 2250 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1); 2251 } 2252 2253 case Intrinsic::arm_neon_vst2lane: { 2254 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 }; 2255 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 }; 2256 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd }; 2257 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1); 2258 } 2259 2260 case Intrinsic::arm_neon_vst3lane: { 2261 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 }; 2262 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 }; 2263 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd }; 2264 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1); 2265 } 2266 2267 case Intrinsic::arm_neon_vst4lane: { 2268 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 }; 2269 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 }; 2270 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd }; 2271 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1); 2272 } 2273 } 2274 break; 2275 } 2276 2277 case ISD::INTRINSIC_WO_CHAIN: { 2278 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 2279 switch (IntNo) { 2280 default: 2281 break; 2282 2283 case Intrinsic::arm_neon_vtbl2: 2284 return SelectVTBL(N, false, 2, ARM::VTBL2); 2285 case Intrinsic::arm_neon_vtbl3: 2286 return SelectVTBL(N, false, 3, ARM::VTBL3); 2287 case Intrinsic::arm_neon_vtbl4: 2288 return SelectVTBL(N, false, 4, ARM::VTBL4); 2289 2290 case Intrinsic::arm_neon_vtbx2: 2291 return SelectVTBL(N, true, 2, ARM::VTBX2); 2292 case Intrinsic::arm_neon_vtbx3: 2293 return SelectVTBL(N, true, 3, ARM::VTBX3); 2294 case Intrinsic::arm_neon_vtbx4: 2295 return SelectVTBL(N, true, 4, ARM::VTBX4); 2296 } 2297 break; 2298 } 2299 2300 case ISD::CONCAT_VECTORS: 2301 return SelectConcatVector(N); 2302 } 2303 2304 return SelectCode(N); 2305} 2306 2307bool ARMDAGToDAGISel:: 2308SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 2309 std::vector<SDValue> &OutOps) { 2310 assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); 2311 // Require the address to be in a register. That is safe for all ARM 2312 // variants and it is hard to do anything much smarter without knowing 2313 // how the operand is used. 2314 OutOps.push_back(Op); 2315 return false; 2316} 2317 2318/// createARMISelDag - This pass converts a legalized DAG into a 2319/// ARM-specific DAG, ready for instruction scheduling. 2320/// 2321FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, 2322 CodeGenOpt::Level OptLevel) { 2323 return new ARMDAGToDAGISel(TM, OptLevel); 2324} 2325