MipsISelLowering.cpp revision 0d7d0b5cb7e41173b6fff2f0c2fbdcbebc9693fe
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/CallingConv.h" 26#include "InstPrinter/MipsInstPrinter.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/ValueTypes.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36using namespace llvm; 37 38const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 39 switch (Opcode) { 40 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 41 case MipsISD::Hi: return "MipsISD::Hi"; 42 case MipsISD::Lo: return "MipsISD::Lo"; 43 case MipsISD::GPRel: return "MipsISD::GPRel"; 44 case MipsISD::TlsGd: return "MipsISD::TlsGd"; 45 case MipsISD::TprelHi: return "MipsISD::TprelHi"; 46 case MipsISD::TprelLo: return "MipsISD::TprelLo"; 47 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 48 case MipsISD::Ret: return "MipsISD::Ret"; 49 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 50 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 51 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 52 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 53 case MipsISD::FPRound: return "MipsISD::FPRound"; 54 case MipsISD::MAdd: return "MipsISD::MAdd"; 55 case MipsISD::MAddu: return "MipsISD::MAddu"; 56 case MipsISD::MSub: return "MipsISD::MSub"; 57 case MipsISD::MSubu: return "MipsISD::MSubu"; 58 case MipsISD::DivRem: return "MipsISD::DivRem"; 59 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 60 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 61 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 62 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; 63 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 64 default: return NULL; 65 } 66} 67 68MipsTargetLowering:: 69MipsTargetLowering(MipsTargetMachine &TM) 70 : TargetLowering(TM, new MipsTargetObjectFile()) { 71 Subtarget = &TM.getSubtarget<MipsSubtarget>(); 72 73 // Mips does not have i1 type, so use i32 for 74 // setcc operations results (slt, sgt, ...). 75 setBooleanContents(ZeroOrOneBooleanContent); 76 77 // Set up the register classes 78 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 79 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 80 81 // When dealing with single precision only, use libcalls 82 if (!Subtarget->isSingleFloat()) 83 if (!Subtarget->isFP64bit()) 84 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 85 86 // Load extented operations for i1 types must be promoted 87 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 89 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 90 91 // MIPS doesn't have extending float->double load/store 92 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 93 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 94 95 // Used by legalize types to correctly generate the setcc result. 96 // Without this, every float setcc comes with a AND/OR with the result, 97 // we don't want this, since the fpcmp result goes to a flag register, 98 // which is used implicitly by brcond and select operations. 99 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 100 101 // Mips Custom Operations 102 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 103 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 104 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 105 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 106 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 107 setOperationAction(ISD::SELECT, MVT::f32, Custom); 108 setOperationAction(ISD::SELECT, MVT::f64, Custom); 109 setOperationAction(ISD::SELECT, MVT::i32, Custom); 110 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 111 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 112 setOperationAction(ISD::VASTART, MVT::Other, Custom); 113 114 setOperationAction(ISD::SDIV, MVT::i32, Expand); 115 setOperationAction(ISD::SREM, MVT::i32, Expand); 116 setOperationAction(ISD::UDIV, MVT::i32, Expand); 117 setOperationAction(ISD::UREM, MVT::i32, Expand); 118 119 // Operations not directly supported by Mips. 120 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 121 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 122 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 123 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 124 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 126 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 127 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 128 setOperationAction(ISD::ROTL, MVT::i32, Expand); 129 130 if (!Subtarget->isMips32r2()) 131 setOperationAction(ISD::ROTR, MVT::i32, Expand); 132 133 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 134 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 135 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 136 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 138 setOperationAction(ISD::FSIN, MVT::f32, Expand); 139 setOperationAction(ISD::FSIN, MVT::f64, Expand); 140 setOperationAction(ISD::FCOS, MVT::f32, Expand); 141 setOperationAction(ISD::FCOS, MVT::f64, Expand); 142 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 143 setOperationAction(ISD::FPOW, MVT::f32, Expand); 144 setOperationAction(ISD::FPOW, MVT::f64, Expand); 145 setOperationAction(ISD::FLOG, MVT::f32, Expand); 146 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 147 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 148 setOperationAction(ISD::FEXP, MVT::f32, Expand); 149 setOperationAction(ISD::FMA, MVT::f32, Expand); 150 setOperationAction(ISD::FMA, MVT::f64, Expand); 151 152 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 153 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 154 155 setOperationAction(ISD::VAARG, MVT::Other, Expand); 156 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 157 setOperationAction(ISD::VAEND, MVT::Other, Expand); 158 159 // Use the default for now 160 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 161 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 162 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 163 164 if (Subtarget->isSingleFloat()) 165 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 166 167 if (!Subtarget->hasSEInReg()) { 168 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 170 } 171 172 if (!Subtarget->hasBitCount()) 173 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 174 175 if (!Subtarget->hasSwap()) 176 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 177 178 setTargetDAGCombine(ISD::ADDE); 179 setTargetDAGCombine(ISD::SUBE); 180 setTargetDAGCombine(ISD::SDIVREM); 181 setTargetDAGCombine(ISD::UDIVREM); 182 setTargetDAGCombine(ISD::SETCC); 183 184 setMinFunctionAlignment(2); 185 186 setStackPointerRegisterToSaveRestore(Mips::SP); 187 computeRegisterProperties(); 188 189 setExceptionPointerRegister(Mips::A0); 190 setExceptionSelectorRegister(Mips::A1); 191} 192 193MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const { 194 return MVT::i32; 195} 196 197// SelectMadd - 198// Transforms a subgraph in CurDAG if the following pattern is found: 199// (addc multLo, Lo0), (adde multHi, Hi0), 200// where, 201// multHi/Lo: product of multiplication 202// Lo0: initial value of Lo register 203// Hi0: initial value of Hi register 204// Return true if pattern matching was successful. 205static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 206 // ADDENode's second operand must be a flag output of an ADDC node in order 207 // for the matching to be successful. 208 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 209 210 if (ADDCNode->getOpcode() != ISD::ADDC) 211 return false; 212 213 SDValue MultHi = ADDENode->getOperand(0); 214 SDValue MultLo = ADDCNode->getOperand(0); 215 SDNode* MultNode = MultHi.getNode(); 216 unsigned MultOpc = MultHi.getOpcode(); 217 218 // MultHi and MultLo must be generated by the same node, 219 if (MultLo.getNode() != MultNode) 220 return false; 221 222 // and it must be a multiplication. 223 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 224 return false; 225 226 // MultLo amd MultHi must be the first and second output of MultNode 227 // respectively. 228 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 229 return false; 230 231 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 232 // of the values of MultNode, in which case MultNode will be removed in later 233 // phases. 234 // If there exist users other than ADDENode or ADDCNode, this function returns 235 // here, which will result in MultNode being mapped to a single MULT 236 // instruction node rather than a pair of MULT and MADD instructions being 237 // produced. 238 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 239 return false; 240 241 SDValue Chain = CurDAG->getEntryNode(); 242 DebugLoc dl = ADDENode->getDebugLoc(); 243 244 // create MipsMAdd(u) node 245 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 246 247 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 248 MVT::Glue, 249 MultNode->getOperand(0),// Factor 0 250 MultNode->getOperand(1),// Factor 1 251 ADDCNode->getOperand(1),// Lo0 252 ADDENode->getOperand(1));// Hi0 253 254 // create CopyFromReg nodes 255 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 256 MAdd); 257 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 258 Mips::HI, MVT::i32, 259 CopyFromLo.getValue(2)); 260 261 // replace uses of adde and addc here 262 if (!SDValue(ADDCNode, 0).use_empty()) 263 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 264 265 if (!SDValue(ADDENode, 0).use_empty()) 266 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 267 268 return true; 269} 270 271// SelectMsub - 272// Transforms a subgraph in CurDAG if the following pattern is found: 273// (addc Lo0, multLo), (sube Hi0, multHi), 274// where, 275// multHi/Lo: product of multiplication 276// Lo0: initial value of Lo register 277// Hi0: initial value of Hi register 278// Return true if pattern matching was successful. 279static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 280 // SUBENode's second operand must be a flag output of an SUBC node in order 281 // for the matching to be successful. 282 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 283 284 if (SUBCNode->getOpcode() != ISD::SUBC) 285 return false; 286 287 SDValue MultHi = SUBENode->getOperand(1); 288 SDValue MultLo = SUBCNode->getOperand(1); 289 SDNode* MultNode = MultHi.getNode(); 290 unsigned MultOpc = MultHi.getOpcode(); 291 292 // MultHi and MultLo must be generated by the same node, 293 if (MultLo.getNode() != MultNode) 294 return false; 295 296 // and it must be a multiplication. 297 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 298 return false; 299 300 // MultLo amd MultHi must be the first and second output of MultNode 301 // respectively. 302 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 303 return false; 304 305 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 306 // of the values of MultNode, in which case MultNode will be removed in later 307 // phases. 308 // If there exist users other than SUBENode or SUBCNode, this function returns 309 // here, which will result in MultNode being mapped to a single MULT 310 // instruction node rather than a pair of MULT and MSUB instructions being 311 // produced. 312 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 313 return false; 314 315 SDValue Chain = CurDAG->getEntryNode(); 316 DebugLoc dl = SUBENode->getDebugLoc(); 317 318 // create MipsSub(u) node 319 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 320 321 SDValue MSub = CurDAG->getNode(MultOpc, dl, 322 MVT::Glue, 323 MultNode->getOperand(0),// Factor 0 324 MultNode->getOperand(1),// Factor 1 325 SUBCNode->getOperand(0),// Lo0 326 SUBENode->getOperand(0));// Hi0 327 328 // create CopyFromReg nodes 329 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 330 MSub); 331 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 332 Mips::HI, MVT::i32, 333 CopyFromLo.getValue(2)); 334 335 // replace uses of sube and subc here 336 if (!SDValue(SUBCNode, 0).use_empty()) 337 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 338 339 if (!SDValue(SUBENode, 0).use_empty()) 340 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 341 342 return true; 343} 344 345static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 346 TargetLowering::DAGCombinerInfo &DCI, 347 const MipsSubtarget* Subtarget) { 348 if (DCI.isBeforeLegalize()) 349 return SDValue(); 350 351 if (Subtarget->isMips32() && SelectMadd(N, &DAG)) 352 return SDValue(N, 0); 353 354 return SDValue(); 355} 356 357static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 358 TargetLowering::DAGCombinerInfo &DCI, 359 const MipsSubtarget* Subtarget) { 360 if (DCI.isBeforeLegalize()) 361 return SDValue(); 362 363 if (Subtarget->isMips32() && SelectMsub(N, &DAG)) 364 return SDValue(N, 0); 365 366 return SDValue(); 367} 368 369static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 370 TargetLowering::DAGCombinerInfo &DCI, 371 const MipsSubtarget* Subtarget) { 372 if (DCI.isBeforeLegalizeOps()) 373 return SDValue(); 374 375 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 376 MipsISD::DivRemU; 377 DebugLoc dl = N->getDebugLoc(); 378 379 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 380 N->getOperand(0), N->getOperand(1)); 381 SDValue InChain = DAG.getEntryNode(); 382 SDValue InGlue = DivRem; 383 384 // insert MFLO 385 if (N->hasAnyUseOfValue(0)) { 386 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32, 387 InGlue); 388 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 389 InChain = CopyFromLo.getValue(1); 390 InGlue = CopyFromLo.getValue(2); 391 } 392 393 // insert MFHI 394 if (N->hasAnyUseOfValue(1)) { 395 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 396 Mips::HI, MVT::i32, InGlue); 397 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 398 } 399 400 return SDValue(); 401} 402 403static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 404 switch (CC) { 405 default: llvm_unreachable("Unknown fp condition code!"); 406 case ISD::SETEQ: 407 case ISD::SETOEQ: return Mips::FCOND_OEQ; 408 case ISD::SETUNE: return Mips::FCOND_UNE; 409 case ISD::SETLT: 410 case ISD::SETOLT: return Mips::FCOND_OLT; 411 case ISD::SETGT: 412 case ISD::SETOGT: return Mips::FCOND_OGT; 413 case ISD::SETLE: 414 case ISD::SETOLE: return Mips::FCOND_OLE; 415 case ISD::SETGE: 416 case ISD::SETOGE: return Mips::FCOND_OGE; 417 case ISD::SETULT: return Mips::FCOND_ULT; 418 case ISD::SETULE: return Mips::FCOND_ULE; 419 case ISD::SETUGT: return Mips::FCOND_UGT; 420 case ISD::SETUGE: return Mips::FCOND_UGE; 421 case ISD::SETUO: return Mips::FCOND_UN; 422 case ISD::SETO: return Mips::FCOND_OR; 423 case ISD::SETNE: 424 case ISD::SETONE: return Mips::FCOND_ONE; 425 case ISD::SETUEQ: return Mips::FCOND_UEQ; 426 } 427} 428 429 430// Returns true if condition code has to be inverted. 431static bool InvertFPCondCode(Mips::CondCode CC) { 432 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 433 return false; 434 435 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 436 return true; 437 438 assert(false && "Illegal Condition Code"); 439 return false; 440} 441 442// Creates and returns an FPCmp node from a setcc node. 443// Returns Op if setcc is not a floating point comparison. 444static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 445 // must be a SETCC node 446 if (Op.getOpcode() != ISD::SETCC) 447 return Op; 448 449 SDValue LHS = Op.getOperand(0); 450 451 if (!LHS.getValueType().isFloatingPoint()) 452 return Op; 453 454 SDValue RHS = Op.getOperand(1); 455 DebugLoc dl = Op.getDebugLoc(); 456 457 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 458 // node if necessary. 459 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 460 461 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 462 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 463} 464 465// Creates and returns a CMovFPT/F node. 466static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 467 SDValue False, DebugLoc DL) { 468 bool invert = InvertFPCondCode((Mips::CondCode) 469 cast<ConstantSDNode>(Cond.getOperand(2)) 470 ->getSExtValue()); 471 472 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 473 True.getValueType(), True, False, Cond); 474} 475 476static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 477 TargetLowering::DAGCombinerInfo &DCI, 478 const MipsSubtarget* Subtarget) { 479 if (DCI.isBeforeLegalizeOps()) 480 return SDValue(); 481 482 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 483 484 if (Cond.getOpcode() != MipsISD::FPCmp) 485 return SDValue(); 486 487 SDValue True = DAG.getConstant(1, MVT::i32); 488 SDValue False = DAG.getConstant(0, MVT::i32); 489 490 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 491} 492 493SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 494 const { 495 SelectionDAG &DAG = DCI.DAG; 496 unsigned opc = N->getOpcode(); 497 498 switch (opc) { 499 default: break; 500 case ISD::ADDE: 501 return PerformADDECombine(N, DAG, DCI, Subtarget); 502 case ISD::SUBE: 503 return PerformSUBECombine(N, DAG, DCI, Subtarget); 504 case ISD::SDIVREM: 505 case ISD::UDIVREM: 506 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 507 case ISD::SETCC: 508 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 509 } 510 511 return SDValue(); 512} 513 514SDValue MipsTargetLowering:: 515LowerOperation(SDValue Op, SelectionDAG &DAG) const 516{ 517 switch (Op.getOpcode()) 518 { 519 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 520 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 521 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 522 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 523 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 524 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 525 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 526 case ISD::SELECT: return LowerSELECT(Op, DAG); 527 case ISD::VASTART: return LowerVASTART(Op, DAG); 528 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 529 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 530 } 531 return SDValue(); 532} 533 534//===----------------------------------------------------------------------===// 535// Lower helper functions 536//===----------------------------------------------------------------------===// 537 538// AddLiveIn - This helper function adds the specified physical register to the 539// MachineFunction as a live in value. It also creates a corresponding 540// virtual register for it. 541static unsigned 542AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 543{ 544 assert(RC->contains(PReg) && "Not the correct regclass!"); 545 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 546 MF.getRegInfo().addLiveIn(PReg, VReg); 547 return VReg; 548} 549 550// Get fp branch code (not opcode) from condition code. 551static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 552 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 553 return Mips::BRANCH_T; 554 555 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 556 return Mips::BRANCH_F; 557 558 return Mips::BRANCH_INVALID; 559} 560 561static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 562 DebugLoc dl, 563 const MipsSubtarget* Subtarget, 564 const TargetInstrInfo *TII, 565 bool isFPCmp, unsigned Opc) { 566 // There is no need to expand CMov instructions if target has 567 // conditional moves. 568 if (Subtarget->hasCondMov()) 569 return BB; 570 571 // To "insert" a SELECT_CC instruction, we actually have to insert the 572 // diamond control-flow pattern. The incoming instruction knows the 573 // destination vreg to set, the condition code register to branch on, the 574 // true/false values to select between, and a branch opcode to use. 575 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 576 MachineFunction::iterator It = BB; 577 ++It; 578 579 // thisMBB: 580 // ... 581 // TrueVal = ... 582 // setcc r1, r2, r3 583 // bNE r1, r0, copy1MBB 584 // fallthrough --> copy0MBB 585 MachineBasicBlock *thisMBB = BB; 586 MachineFunction *F = BB->getParent(); 587 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 588 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 589 F->insert(It, copy0MBB); 590 F->insert(It, sinkMBB); 591 592 // Transfer the remainder of BB and its successor edges to sinkMBB. 593 sinkMBB->splice(sinkMBB->begin(), BB, 594 llvm::next(MachineBasicBlock::iterator(MI)), 595 BB->end()); 596 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 597 598 // Next, add the true and fallthrough blocks as its successors. 599 BB->addSuccessor(copy0MBB); 600 BB->addSuccessor(sinkMBB); 601 602 // Emit the right instruction according to the type of the operands compared 603 if (isFPCmp) 604 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 605 else 606 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 607 .addReg(Mips::ZERO).addMBB(sinkMBB); 608 609 // copy0MBB: 610 // %FalseValue = ... 611 // # fallthrough to sinkMBB 612 BB = copy0MBB; 613 614 // Update machine-CFG edges 615 BB->addSuccessor(sinkMBB); 616 617 // sinkMBB: 618 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 619 // ... 620 BB = sinkMBB; 621 622 if (isFPCmp) 623 BuildMI(*BB, BB->begin(), dl, 624 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 625 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 626 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 627 else 628 BuildMI(*BB, BB->begin(), dl, 629 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 630 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 631 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 632 633 MI->eraseFromParent(); // The pseudo instruction is gone now. 634 return BB; 635} 636 637MachineBasicBlock * 638MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 639 MachineBasicBlock *BB) const { 640 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 641 DebugLoc dl = MI->getDebugLoc(); 642 643 switch (MI->getOpcode()) { 644 default: 645 assert(false && "Unexpected instr type to insert"); 646 return NULL; 647 case Mips::MOVT: 648 case Mips::MOVT_S: 649 case Mips::MOVT_D: 650 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F); 651 case Mips::MOVF: 652 case Mips::MOVF_S: 653 case Mips::MOVF_D: 654 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T); 655 case Mips::MOVZ_I: 656 case Mips::MOVZ_S: 657 case Mips::MOVZ_D: 658 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE); 659 case Mips::MOVN_I: 660 case Mips::MOVN_S: 661 case Mips::MOVN_D: 662 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ); 663 664 case Mips::ATOMIC_LOAD_ADD_I8: 665 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 666 case Mips::ATOMIC_LOAD_ADD_I16: 667 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 668 case Mips::ATOMIC_LOAD_ADD_I32: 669 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 670 671 case Mips::ATOMIC_LOAD_AND_I8: 672 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 673 case Mips::ATOMIC_LOAD_AND_I16: 674 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 675 case Mips::ATOMIC_LOAD_AND_I32: 676 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 677 678 case Mips::ATOMIC_LOAD_OR_I8: 679 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 680 case Mips::ATOMIC_LOAD_OR_I16: 681 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 682 case Mips::ATOMIC_LOAD_OR_I32: 683 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 684 685 case Mips::ATOMIC_LOAD_XOR_I8: 686 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 687 case Mips::ATOMIC_LOAD_XOR_I16: 688 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 689 case Mips::ATOMIC_LOAD_XOR_I32: 690 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 691 692 case Mips::ATOMIC_LOAD_NAND_I8: 693 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 694 case Mips::ATOMIC_LOAD_NAND_I16: 695 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 696 case Mips::ATOMIC_LOAD_NAND_I32: 697 return EmitAtomicBinary(MI, BB, 4, 0, true); 698 699 case Mips::ATOMIC_LOAD_SUB_I8: 700 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 701 case Mips::ATOMIC_LOAD_SUB_I16: 702 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 703 case Mips::ATOMIC_LOAD_SUB_I32: 704 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 705 706 case Mips::ATOMIC_SWAP_I8: 707 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 708 case Mips::ATOMIC_SWAP_I16: 709 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 710 case Mips::ATOMIC_SWAP_I32: 711 return EmitAtomicBinary(MI, BB, 4, 0); 712 713 case Mips::ATOMIC_CMP_SWAP_I8: 714 return EmitAtomicCmpSwapPartword(MI, BB, 1); 715 case Mips::ATOMIC_CMP_SWAP_I16: 716 return EmitAtomicCmpSwapPartword(MI, BB, 2); 717 case Mips::ATOMIC_CMP_SWAP_I32: 718 return EmitAtomicCmpSwap(MI, BB, 4); 719 } 720} 721 722// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 723// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 724MachineBasicBlock * 725MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 726 unsigned Size, unsigned BinOpcode, 727 bool Nand) const { 728 assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); 729 730 MachineFunction *MF = BB->getParent(); 731 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 732 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 733 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 734 DebugLoc dl = MI->getDebugLoc(); 735 736 unsigned Oldval = MI->getOperand(0).getReg(); 737 unsigned Ptr = MI->getOperand(1).getReg(); 738 unsigned Incr = MI->getOperand(2).getReg(); 739 740 unsigned Tmp1 = RegInfo.createVirtualRegister(RC); 741 unsigned Tmp2 = RegInfo.createVirtualRegister(RC); 742 unsigned Tmp3 = RegInfo.createVirtualRegister(RC); 743 744 // insert new blocks after the current block 745 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 746 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 747 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 748 MachineFunction::iterator It = BB; 749 ++It; 750 MF->insert(It, loopMBB); 751 MF->insert(It, exitMBB); 752 753 // Transfer the remainder of BB and its successor edges to exitMBB. 754 exitMBB->splice(exitMBB->begin(), BB, 755 llvm::next(MachineBasicBlock::iterator(MI)), 756 BB->end()); 757 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 758 759 // thisMBB: 760 // ... 761 // fallthrough --> loopMBB 762 BB->addSuccessor(loopMBB); 763 764 // loopMBB: 765 // ll oldval, 0(ptr) 766 // <binop> tmp1, oldval, incr 767 // sc tmp1, 0(ptr) 768 // beq tmp1, $0, loopMBB 769 BB = loopMBB; 770 BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0); 771 if (Nand) { 772 // and tmp2, oldval, incr 773 // nor tmp1, $0, tmp2 774 BuildMI(BB, dl, TII->get(Mips::AND), Tmp2).addReg(Oldval).addReg(Incr); 775 BuildMI(BB, dl, TII->get(Mips::NOR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); 776 } else if (BinOpcode) { 777 // <binop> tmp1, oldval, incr 778 BuildMI(BB, dl, TII->get(BinOpcode), Tmp1).addReg(Oldval).addReg(Incr); 779 } else { 780 Tmp1 = Incr; 781 } 782 BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); 783 BuildMI(BB, dl, TII->get(Mips::BEQ)) 784 .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loopMBB); 785 BB->addSuccessor(loopMBB); 786 BB->addSuccessor(exitMBB); 787 788 MI->eraseFromParent(); // The instruction is gone now. 789 790 return BB; 791} 792 793MachineBasicBlock * 794MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 795 MachineBasicBlock *BB, 796 unsigned Size, unsigned BinOpcode, 797 bool Nand) const { 798 assert((Size == 1 || Size == 2) && 799 "Unsupported size for EmitAtomicBinaryPartial."); 800 801 MachineFunction *MF = BB->getParent(); 802 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 803 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 804 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 805 DebugLoc dl = MI->getDebugLoc(); 806 807 unsigned Dest = MI->getOperand(0).getReg(); 808 unsigned Ptr = MI->getOperand(1).getReg(); 809 unsigned Incr = MI->getOperand(2).getReg(); 810 811 unsigned Addr = RegInfo.createVirtualRegister(RC); 812 unsigned Shift = RegInfo.createVirtualRegister(RC); 813 unsigned Mask = RegInfo.createVirtualRegister(RC); 814 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 815 unsigned Newval = RegInfo.createVirtualRegister(RC); 816 unsigned Oldval = RegInfo.createVirtualRegister(RC); 817 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 818 unsigned Tmp1 = RegInfo.createVirtualRegister(RC); 819 unsigned Tmp2 = RegInfo.createVirtualRegister(RC); 820 unsigned Tmp3 = RegInfo.createVirtualRegister(RC); 821 unsigned Tmp4 = RegInfo.createVirtualRegister(RC); 822 unsigned Tmp5 = RegInfo.createVirtualRegister(RC); 823 unsigned Tmp6 = RegInfo.createVirtualRegister(RC); 824 unsigned Tmp7 = RegInfo.createVirtualRegister(RC); 825 unsigned Tmp8 = RegInfo.createVirtualRegister(RC); 826 unsigned Tmp9 = RegInfo.createVirtualRegister(RC); 827 unsigned Tmp10 = RegInfo.createVirtualRegister(RC); 828 unsigned Tmp11 = RegInfo.createVirtualRegister(RC); 829 unsigned Tmp12 = RegInfo.createVirtualRegister(RC); 830 unsigned Tmp13 = RegInfo.createVirtualRegister(RC); 831 832 // insert new blocks after the current block 833 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 834 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 835 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 836 MachineFunction::iterator It = BB; 837 ++It; 838 MF->insert(It, loopMBB); 839 MF->insert(It, exitMBB); 840 841 // Transfer the remainder of BB and its successor edges to exitMBB. 842 exitMBB->splice(exitMBB->begin(), BB, 843 llvm::next(MachineBasicBlock::iterator(MI)), 844 BB->end()); 845 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 846 847 // thisMBB: 848 // addiu tmp1,$0,-4 # 0xfffffffc 849 // and addr,ptr,tmp1 850 // andi tmp2,ptr,3 851 // sll shift,tmp2,3 852 // ori tmp3,$0,255 # 0xff 853 // sll mask,tmp3,shift 854 // nor mask2,$0,mask 855 // andi tmp4,incr,255 856 // sll incr2,tmp4,shift 857 858 int64_t MaskImm = (Size == 1) ? 255 : 65535; 859 BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); 860 BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1); 861 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3); 862 BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3); 863 BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); 864 BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); 865 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 866 if (BinOpcode != Mips::SUBu) { 867 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm); 868 BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift); 869 } else { 870 BuildMI(BB, dl, TII->get(Mips::SUBu), Tmp4).addReg(Mips::ZERO).addReg(Incr); 871 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm); 872 BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift); 873 } 874 875 BB->addSuccessor(loopMBB); 876 877 // atomic.load.binop 878 // loopMBB: 879 // ll oldval,0(addr) 880 // binop tmp7,oldval,incr2 881 // and newval,tmp7,mask 882 // and tmp8,oldval,mask2 883 // or tmp9,tmp8,newval 884 // sc tmp9,0(addr) 885 // beq tmp9,$0,loopMBB 886 887 // atomic.swap 888 // loopMBB: 889 // ll oldval,0(addr) 890 // and tmp8,oldval,mask2 891 // or tmp9,tmp8,incr2 892 // sc tmp9,0(addr) 893 // beq tmp9,$0,loopMBB 894 895 BB = loopMBB; 896 BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0); 897 if (Nand) { 898 // and tmp6, oldval, incr2 899 // nor tmp7, $0, tmp6 900 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2); 901 BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); 902 } else if (BinOpcode == Mips::SUBu) { 903 // addu tmp7, oldval, incr2 904 BuildMI(BB, dl, TII->get(Mips::ADDu), Tmp7).addReg(Oldval).addReg(Incr2); 905 } else if (BinOpcode) { 906 // <binop> tmp7, oldval, incr2 907 BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2); 908 } 909 if (BinOpcode != 0 || Nand) 910 BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); 911 BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2); 912 if (BinOpcode != 0 || Nand) 913 BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); 914 else 915 BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Incr2); 916 BuildMI(BB, dl, TII->get(Mips::SC), Tmp13) 917 .addReg(Tmp9).addReg(Addr).addImm(0); 918 BuildMI(BB, dl, TII->get(Mips::BEQ)) 919 .addReg(Tmp13).addReg(Mips::ZERO).addMBB(loopMBB); 920 BB->addSuccessor(loopMBB); 921 BB->addSuccessor(exitMBB); 922 923 // exitMBB: 924 // and tmp10,oldval,mask 925 // srl tmp11,tmp10,shift 926 // sll tmp12,tmp11,24 927 // sra dest,tmp12,24 928 BB = exitMBB; 929 int64_t ShiftImm = (Size == 1) ? 24 : 16; 930 // reverse order 931 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) 932 .addReg(Tmp12).addImm(ShiftImm); 933 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12) 934 .addReg(Tmp11).addImm(ShiftImm); 935 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11) 936 .addReg(Tmp10).addReg(Shift); 937 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10) 938 .addReg(Oldval).addReg(Mask); 939 940 MI->eraseFromParent(); // The instruction is gone now. 941 942 return BB; 943} 944 945MachineBasicBlock * 946MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 947 MachineBasicBlock *BB, 948 unsigned Size) const { 949 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); 950 951 MachineFunction *MF = BB->getParent(); 952 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 953 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 954 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 955 DebugLoc dl = MI->getDebugLoc(); 956 957 unsigned Dest = MI->getOperand(0).getReg(); 958 unsigned Ptr = MI->getOperand(1).getReg(); 959 unsigned Oldval = MI->getOperand(2).getReg(); 960 unsigned Newval = MI->getOperand(3).getReg(); 961 962 unsigned Tmp1 = RegInfo.createVirtualRegister(RC); 963 unsigned Tmp3 = RegInfo.createVirtualRegister(RC); 964 965 // insert new blocks after the current block 966 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 967 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 968 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 969 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 970 MachineFunction::iterator It = BB; 971 ++It; 972 MF->insert(It, loop1MBB); 973 MF->insert(It, loop2MBB); 974 MF->insert(It, exitMBB); 975 976 // Transfer the remainder of BB and its successor edges to exitMBB. 977 exitMBB->splice(exitMBB->begin(), BB, 978 llvm::next(MachineBasicBlock::iterator(MI)), 979 BB->end()); 980 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 981 982 // thisMBB: 983 // ... 984 // fallthrough --> loop1MBB 985 BB->addSuccessor(loop1MBB); 986 987 // loop1MBB: 988 // ll dest, 0(ptr) 989 // bne dest, oldval, exitMBB 990 BB = loop1MBB; 991 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); 992 BuildMI(BB, dl, TII->get(Mips::BNE)) 993 .addReg(Dest).addReg(Oldval).addMBB(exitMBB); 994 BB->addSuccessor(exitMBB); 995 BB->addSuccessor(loop2MBB); 996 997 // loop2MBB: 998 // or tmp1, $0, newval 999 // sc tmp1, 0(ptr) 1000 // beq tmp1, $0, loop1MBB 1001 BB = loop2MBB; 1002 BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Newval); 1003 BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Tmp1).addReg(Ptr).addImm(0); 1004 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1005 .addReg(Tmp3).addReg(Mips::ZERO).addMBB(loop1MBB); 1006 BB->addSuccessor(loop1MBB); 1007 BB->addSuccessor(exitMBB); 1008 1009 MI->eraseFromParent(); // The instruction is gone now. 1010 1011 return BB; 1012} 1013 1014MachineBasicBlock * 1015MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1016 MachineBasicBlock *BB, 1017 unsigned Size) const { 1018 assert((Size == 1 || Size == 2) && 1019 "Unsupported size for EmitAtomicCmpSwapPartial."); 1020 1021 MachineFunction *MF = BB->getParent(); 1022 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1023 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1024 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1025 DebugLoc dl = MI->getDebugLoc(); 1026 1027 unsigned Dest = MI->getOperand(0).getReg(); 1028 unsigned Ptr = MI->getOperand(1).getReg(); 1029 unsigned Oldval = MI->getOperand(2).getReg(); 1030 unsigned Newval = MI->getOperand(3).getReg(); 1031 1032 unsigned Addr = RegInfo.createVirtualRegister(RC); 1033 unsigned Shift = RegInfo.createVirtualRegister(RC); 1034 unsigned Mask = RegInfo.createVirtualRegister(RC); 1035 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1036 unsigned Oldval2 = RegInfo.createVirtualRegister(RC); 1037 unsigned Oldval3 = RegInfo.createVirtualRegister(RC); 1038 unsigned Oldval4 = RegInfo.createVirtualRegister(RC); 1039 unsigned Newval2 = RegInfo.createVirtualRegister(RC); 1040 unsigned Tmp1 = RegInfo.createVirtualRegister(RC); 1041 unsigned Tmp2 = RegInfo.createVirtualRegister(RC); 1042 unsigned Tmp3 = RegInfo.createVirtualRegister(RC); 1043 unsigned Tmp4 = RegInfo.createVirtualRegister(RC); 1044 unsigned Tmp5 = RegInfo.createVirtualRegister(RC); 1045 unsigned Tmp6 = RegInfo.createVirtualRegister(RC); 1046 unsigned Tmp7 = RegInfo.createVirtualRegister(RC); 1047 unsigned Tmp8 = RegInfo.createVirtualRegister(RC); 1048 unsigned Tmp9 = RegInfo.createVirtualRegister(RC); 1049 unsigned Tmp10 = RegInfo.createVirtualRegister(RC); 1050 1051 // insert new blocks after the current block 1052 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1053 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1054 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1055 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1056 MachineFunction::iterator It = BB; 1057 ++It; 1058 MF->insert(It, loop1MBB); 1059 MF->insert(It, loop2MBB); 1060 MF->insert(It, exitMBB); 1061 1062 // Transfer the remainder of BB and its successor edges to exitMBB. 1063 exitMBB->splice(exitMBB->begin(), BB, 1064 llvm::next(MachineBasicBlock::iterator(MI)), 1065 BB->end()); 1066 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1067 1068 // thisMBB: 1069 // addiu tmp1,$0,-4 # 0xfffffffc 1070 // and addr,ptr,tmp1 1071 // andi tmp2,ptr,3 1072 // sll shift,tmp2,3 1073 // ori tmp3,$0,255 # 0xff 1074 // sll mask,tmp3,shift 1075 // nor mask2,$0,mask 1076 // andi tmp4,oldval,255 1077 // sll oldval2,tmp4,shift 1078 // andi tmp5,newval,255 1079 // sll newval2,tmp5,shift 1080 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1081 BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); 1082 BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1); 1083 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3); 1084 BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3); 1085 BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); 1086 BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); 1087 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1088 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Oldval).addImm(MaskImm); 1089 BuildMI(BB, dl, TII->get(Mips::SLL), Oldval2).addReg(Tmp4).addReg(Shift); 1090 BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Newval).addImm(MaskImm); 1091 BuildMI(BB, dl, TII->get(Mips::SLL), Newval2).addReg(Tmp5).addReg(Shift); 1092 BB->addSuccessor(loop1MBB); 1093 1094 // loop1MBB: 1095 // ll oldval3,0(addr) 1096 // and oldval4,oldval3,mask 1097 // bne oldval4,oldval2,exitMBB 1098 BB = loop1MBB; 1099 BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addReg(Addr).addImm(0); 1100 BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask); 1101 BuildMI(BB, dl, TII->get(Mips::BNE)) 1102 .addReg(Oldval4).addReg(Oldval2).addMBB(exitMBB); 1103 BB->addSuccessor(exitMBB); 1104 BB->addSuccessor(loop2MBB); 1105 1106 // loop2MBB: 1107 // and tmp6,oldval3,mask2 1108 // or tmp7,tmp6,newval2 1109 // sc tmp7,0(addr) 1110 // beq tmp7,$0,loop1MBB 1111 BB = loop2MBB; 1112 BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2); 1113 BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2); 1114 BuildMI(BB, dl, TII->get(Mips::SC), Tmp10) 1115 .addReg(Tmp7).addReg(Addr).addImm(0); 1116 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1117 .addReg(Tmp10).addReg(Mips::ZERO).addMBB(loop1MBB); 1118 BB->addSuccessor(loop1MBB); 1119 BB->addSuccessor(exitMBB); 1120 1121 // exitMBB: 1122 // srl tmp8,oldval4,shift 1123 // sll tmp9,tmp8,24 1124 // sra dest,tmp9,24 1125 BB = exitMBB; 1126 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1127 // reverse order 1128 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) 1129 .addReg(Tmp9).addImm(ShiftImm); 1130 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9) 1131 .addReg(Tmp8).addImm(ShiftImm); 1132 BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8) 1133 .addReg(Oldval4).addReg(Shift); 1134 1135 MI->eraseFromParent(); // The instruction is gone now. 1136 1137 return BB; 1138} 1139 1140//===----------------------------------------------------------------------===// 1141// Misc Lower Operation implementation 1142//===----------------------------------------------------------------------===// 1143SDValue MipsTargetLowering:: 1144LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1145{ 1146 MachineFunction &MF = DAG.getMachineFunction(); 1147 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1148 1149 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1150 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1151 "Cannot lower if the alignment of the allocated space is larger than \ 1152 that of the stack."); 1153 1154 SDValue Chain = Op.getOperand(0); 1155 SDValue Size = Op.getOperand(1); 1156 DebugLoc dl = Op.getDebugLoc(); 1157 1158 // Get a reference from Mips stack pointer 1159 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 1160 1161 // Subtract the dynamic size from the actual stack size to 1162 // obtain the new stack size. 1163 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 1164 1165 // The Sub result contains the new stack start address, so it 1166 // must be placed in the stack pointer register. 1167 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, 1168 SDValue()); 1169 1170 // This node always has two return values: a new stack pointer 1171 // value and a chain 1172 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); 1173 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1174 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1175 1176 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1177} 1178 1179SDValue MipsTargetLowering:: 1180LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1181{ 1182 // The first operand is the chain, the second is the condition, the third is 1183 // the block to branch to if the condition is true. 1184 SDValue Chain = Op.getOperand(0); 1185 SDValue Dest = Op.getOperand(2); 1186 DebugLoc dl = Op.getDebugLoc(); 1187 1188 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1189 1190 // Return if flag is not set by a floating point comparison. 1191 if (CondRes.getOpcode() != MipsISD::FPCmp) 1192 return Op; 1193 1194 SDValue CCNode = CondRes.getOperand(2); 1195 Mips::CondCode CC = 1196 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1197 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1198 1199 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1200 Dest, CondRes); 1201} 1202 1203SDValue MipsTargetLowering:: 1204LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1205{ 1206 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1207 1208 // Return if flag is not set by a floating point comparison. 1209 if (Cond.getOpcode() != MipsISD::FPCmp) 1210 return Op; 1211 1212 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1213 Op.getDebugLoc()); 1214} 1215 1216SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1217 SelectionDAG &DAG) const { 1218 // FIXME there isn't actually debug info here 1219 DebugLoc dl = Op.getDebugLoc(); 1220 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1221 1222 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1223 SDVTList VTs = DAG.getVTList(MVT::i32); 1224 1225 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1226 1227 // %gp_rel relocation 1228 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1229 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1230 MipsII::MO_GPREL); 1231 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1232 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1233 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1234 } 1235 // %hi/%lo relocation 1236 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1237 MipsII::MO_ABS_HI); 1238 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1239 MipsII::MO_ABS_LO); 1240 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1241 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1242 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1243 } 1244 1245 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1246 MipsII::MO_GOT); 1247 GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA); 1248 SDValue ResNode = DAG.getLoad(MVT::i32, dl, 1249 DAG.getEntryNode(), GA, MachinePointerInfo(), 1250 false, false, 0); 1251 // On functions and global targets not internal linked only 1252 // a load from got/GP is necessary for PIC to work. 1253 if (!GV->hasInternalLinkage() && 1254 (!GV->hasLocalLinkage() || isa<Function>(GV))) 1255 return ResNode; 1256 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1257 MipsII::MO_ABS_LO); 1258 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1259 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); 1260} 1261 1262SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1263 SelectionDAG &DAG) const { 1264 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1265 // FIXME there isn't actually debug info here 1266 DebugLoc dl = Op.getDebugLoc(); 1267 1268 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1269 // %hi/%lo relocation 1270 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 1271 MipsII::MO_ABS_HI); 1272 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 1273 MipsII::MO_ABS_LO); 1274 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1275 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1276 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1277 } 1278 1279 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1280 MipsII::MO_GOT); 1281 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset); 1282 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1283 MipsII::MO_ABS_LO); 1284 SDValue Load = DAG.getLoad(MVT::i32, dl, 1285 DAG.getEntryNode(), BAGOTOffset, 1286 MachinePointerInfo(), false, false, 0); 1287 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 1288 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1289} 1290 1291SDValue MipsTargetLowering:: 1292LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1293{ 1294 // If the relocation model is PIC, use the General Dynamic TLS Model, 1295 // otherwise use the Initial Exec or Local Exec TLS Model. 1296 // TODO: implement Local Dynamic TLS model 1297 1298 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1299 DebugLoc dl = GA->getDebugLoc(); 1300 const GlobalValue *GV = GA->getGlobal(); 1301 EVT PtrVT = getPointerTy(); 1302 1303 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1304 // General Dynamic TLS Model 1305 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 1306 0, MipsII::MO_TLSGD); 1307 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); 1308 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); 1309 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); 1310 1311 ArgListTy Args; 1312 ArgListEntry Entry; 1313 Entry.Node = Argument; 1314 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1315 Args.push_back(Entry); 1316 std::pair<SDValue, SDValue> CallResult = 1317 LowerCallTo(DAG.getEntryNode(), 1318 (Type *) Type::getInt32Ty(*DAG.getContext()), 1319 false, false, false, false, 0, CallingConv::C, false, true, 1320 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, 1321 dl); 1322 1323 return CallResult.first; 1324 } 1325 1326 SDValue Offset; 1327 if (GV->isDeclaration()) { 1328 // Initial Exec TLS Model 1329 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1330 MipsII::MO_GOTTPREL); 1331 Offset = DAG.getLoad(MVT::i32, dl, 1332 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1333 false, false, 0); 1334 } else { 1335 // Local Exec TLS Model 1336 SDVTList VTs = DAG.getVTList(MVT::i32); 1337 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1338 MipsII::MO_TPREL_HI); 1339 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1340 MipsII::MO_TPREL_LO); 1341 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); 1342 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); 1343 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1344 } 1345 1346 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1347 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1348} 1349 1350SDValue MipsTargetLowering:: 1351LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1352{ 1353 SDValue ResNode; 1354 SDValue HiPart; 1355 // FIXME there isn't actually debug info here 1356 DebugLoc dl = Op.getDebugLoc(); 1357 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1358 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 1359 1360 EVT PtrVT = Op.getValueType(); 1361 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1362 1363 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 1364 1365 if (!IsPIC) { 1366 SDValue Ops[] = { JTI }; 1367 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 1368 } else {// Emit Load from Global Pointer 1369 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); 1370 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 1371 MachinePointerInfo(), 1372 false, false, 0); 1373 } 1374 1375 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 1376 MipsII::MO_ABS_LO); 1377 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 1378 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1379 1380 return ResNode; 1381} 1382 1383SDValue MipsTargetLowering:: 1384LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1385{ 1386 SDValue ResNode; 1387 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1388 const Constant *C = N->getConstVal(); 1389 // FIXME there isn't actually debug info here 1390 DebugLoc dl = Op.getDebugLoc(); 1391 1392 // gp_rel relocation 1393 // FIXME: we should reference the constant pool using small data sections, 1394 // but the asm printer currently doesn't support this feature without 1395 // hacking it. This feature should come soon so we can uncomment the 1396 // stuff below. 1397 //if (IsInSmallSection(C->getType())) { 1398 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1399 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1400 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1401 1402 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1403 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1404 N->getOffset(), MipsII::MO_ABS_HI); 1405 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1406 N->getOffset(), MipsII::MO_ABS_LO); 1407 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1408 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1409 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1410 } else { 1411 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1412 N->getOffset(), MipsII::MO_GOT); 1413 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); 1414 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 1415 CP, MachinePointerInfo::getConstantPool(), 1416 false, false, 0); 1417 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1418 N->getOffset(), MipsII::MO_ABS_LO); 1419 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1420 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1421 } 1422 1423 return ResNode; 1424} 1425 1426SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1427 MachineFunction &MF = DAG.getMachineFunction(); 1428 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1429 1430 DebugLoc dl = Op.getDebugLoc(); 1431 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1432 getPointerTy()); 1433 1434 // vastart just stores the address of the VarArgsFrameIndex slot into the 1435 // memory location argument. 1436 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1437 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1438 MachinePointerInfo(SV), 1439 false, false, 0); 1440} 1441 1442static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 1443 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1444 DebugLoc dl = Op.getDebugLoc(); 1445 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 1446 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 1447 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 1448 DAG.getConstant(0x7fffffff, MVT::i32)); 1449 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 1450 DAG.getConstant(0x80000000, MVT::i32)); 1451 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1452 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 1453} 1454 1455static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1456 // FIXME: 1457 // Use ext/ins instructions if target architecture is Mips32r2. 1458 // Eliminate redundant mfc1 and mtc1 instructions. 1459 unsigned LoIdx = 0, HiIdx = 1; 1460 1461 if (!isLittle) 1462 std::swap(LoIdx, HiIdx); 1463 1464 DebugLoc dl = Op.getDebugLoc(); 1465 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1466 Op.getOperand(0), 1467 DAG.getConstant(LoIdx, MVT::i32)); 1468 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1469 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1470 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1471 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1472 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1473 DAG.getConstant(0x7fffffff, MVT::i32)); 1474 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1475 DAG.getConstant(0x80000000, MVT::i32)); 1476 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1477 1478 if (!isLittle) 1479 std::swap(Word0, Word1); 1480 1481 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1482} 1483 1484SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 1485 const { 1486 EVT Ty = Op.getValueType(); 1487 1488 assert(Ty == MVT::f32 || Ty == MVT::f64); 1489 1490 if (Ty == MVT::f32) 1491 return LowerFCOPYSIGN32(Op, DAG); 1492 else 1493 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 1494} 1495 1496SDValue MipsTargetLowering:: 1497LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1498 // check the depth 1499 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1500 "Frame address can only be determined for current frame."); 1501 1502 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1503 MFI->setFrameAddressIsTaken(true); 1504 EVT VT = Op.getValueType(); 1505 DebugLoc dl = Op.getDebugLoc(); 1506 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT); 1507 return FrameAddr; 1508} 1509 1510//===----------------------------------------------------------------------===// 1511// Calling Convention Implementation 1512//===----------------------------------------------------------------------===// 1513 1514#include "MipsGenCallingConv.inc" 1515 1516//===----------------------------------------------------------------------===// 1517// TODO: Implement a generic logic using tblgen that can support this. 1518// Mips O32 ABI rules: 1519// --- 1520// i32 - Passed in A0, A1, A2, A3 and stack 1521// f32 - Only passed in f32 registers if no int reg has been used yet to hold 1522// an argument. Otherwise, passed in A1, A2, A3 and stack. 1523// f64 - Only passed in two aliased f32 registers if no int reg has been used 1524// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1525// not used, it must be shadowed. If only A3 is avaiable, shadow it and 1526// go to stack. 1527// 1528// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1529//===----------------------------------------------------------------------===// 1530 1531static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1532 MVT LocVT, CCValAssign::LocInfo LocInfo, 1533 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1534 1535 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1536 1537 static const unsigned IntRegs[] = { 1538 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1539 }; 1540 static const unsigned F32Regs[] = { 1541 Mips::F12, Mips::F14 1542 }; 1543 static const unsigned F64Regs[] = { 1544 Mips::D6, Mips::D7 1545 }; 1546 1547 // ByVal Args 1548 if (ArgFlags.isByVal()) { 1549 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1550 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1551 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1552 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1553 r < std::min(IntRegsSize, NextReg); ++r) 1554 State.AllocateReg(IntRegs[r]); 1555 return false; 1556 } 1557 1558 // Promote i8 and i16 1559 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1560 LocVT = MVT::i32; 1561 if (ArgFlags.isSExt()) 1562 LocInfo = CCValAssign::SExt; 1563 else if (ArgFlags.isZExt()) 1564 LocInfo = CCValAssign::ZExt; 1565 else 1566 LocInfo = CCValAssign::AExt; 1567 } 1568 1569 unsigned Reg; 1570 1571 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1572 // is true: function is vararg, argument is 3rd or higher, there is previous 1573 // argument which is not f32 or f64. 1574 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1575 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1576 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1577 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1578 1579 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1580 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1581 // If this is the first part of an i64 arg, 1582 // the allocated register must be either A0 or A2. 1583 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1584 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1585 LocVT = MVT::i32; 1586 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1587 // Allocate int register and shadow next int register. If first 1588 // available register is Mips::A1 or Mips::A3, shadow it too. 1589 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1590 if (Reg == Mips::A1 || Reg == Mips::A3) 1591 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1592 State.AllocateReg(IntRegs, IntRegsSize); 1593 LocVT = MVT::i32; 1594 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1595 // we are guaranteed to find an available float register 1596 if (ValVT == MVT::f32) { 1597 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1598 // Shadow int register 1599 State.AllocateReg(IntRegs, IntRegsSize); 1600 } else { 1601 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1602 // Shadow int registers 1603 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1604 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1605 State.AllocateReg(IntRegs, IntRegsSize); 1606 State.AllocateReg(IntRegs, IntRegsSize); 1607 } 1608 } else 1609 llvm_unreachable("Cannot handle this ValVT."); 1610 1611 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1612 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1613 1614 if (!Reg) 1615 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1616 else 1617 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1618 1619 return false; // CC must always match 1620} 1621 1622//===----------------------------------------------------------------------===// 1623// Call Calling Convention Implementation 1624//===----------------------------------------------------------------------===// 1625 1626static const unsigned O32IntRegsSize = 4; 1627 1628static const unsigned O32IntRegs[] = { 1629 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1630}; 1631 1632// Write ByVal Arg to arg registers and stack. 1633static void 1634WriteByValArg(SDValue& Chain, DebugLoc dl, 1635 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1636 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1637 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1638 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1639 MVT PtrType) { 1640 unsigned FirstWord = VA.getLocMemOffset() / 4; 1641 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 1642 unsigned LastWord = FirstWord + NumWords; 1643 unsigned CurWord; 1644 1645 // copy the first 4 words of byval arg to registers A0 - A3 1646 for (CurWord = FirstWord; CurWord < std::min(LastWord, O32IntRegsSize); 1647 ++CurWord) { 1648 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1649 DAG.getConstant((CurWord - FirstWord) * 4, 1650 MVT::i32)); 1651 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1652 MachinePointerInfo(), 1653 false, false, 0); 1654 MemOpChains.push_back(LoadVal.getValue(1)); 1655 unsigned DstReg = O32IntRegs[CurWord]; 1656 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1657 } 1658 1659 // copy remaining part of byval arg to stack. 1660 if (CurWord < LastWord) { 1661 unsigned SizeInBytes = (LastWord - CurWord) * 4; 1662 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1663 DAG.getConstant((CurWord - FirstWord) * 4, 1664 MVT::i32)); 1665 LastFI = MFI->CreateFixedObject(SizeInBytes, CurWord * 4, true); 1666 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1667 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 1668 DAG.getConstant(SizeInBytes, MVT::i32), 1669 /*Align*/4, 1670 /*isVolatile=*/false, /*AlwaysInline=*/false, 1671 MachinePointerInfo(0), MachinePointerInfo(0)); 1672 MemOpChains.push_back(Chain); 1673 } 1674} 1675 1676/// LowerCall - functions arguments are copied from virtual regs to 1677/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1678/// TODO: isTailCall. 1679SDValue 1680MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1681 CallingConv::ID CallConv, bool isVarArg, 1682 bool &isTailCall, 1683 const SmallVectorImpl<ISD::OutputArg> &Outs, 1684 const SmallVectorImpl<SDValue> &OutVals, 1685 const SmallVectorImpl<ISD::InputArg> &Ins, 1686 DebugLoc dl, SelectionDAG &DAG, 1687 SmallVectorImpl<SDValue> &InVals) const { 1688 // MIPs target does not yet support tail call optimization. 1689 isTailCall = false; 1690 1691 MachineFunction &MF = DAG.getMachineFunction(); 1692 MachineFrameInfo *MFI = MF.getFrameInfo(); 1693 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1694 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1695 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1696 1697 // Analyze operands of the call, assigning locations to each operand. 1698 SmallVector<CCValAssign, 16> ArgLocs; 1699 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1700 getTargetMachine(), ArgLocs, *DAG.getContext()); 1701 1702 if (Subtarget->isABI_O32()) 1703 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1704 else 1705 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1706 1707 // Get a count of how many bytes are to be pushed on the stack. 1708 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1709 1710 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NextStackOffset, 1711 true)); 1712 1713 // If this is the first call, create a stack frame object that points to 1714 // a location to which .cprestore saves $gp. 1715 if (IsPIC && !MipsFI->getGPFI()) 1716 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1717 1718 // Get the frame index of the stack frame object that points to the location 1719 // of dynamically allocated area on the stack. 1720 int DynAllocFI = MipsFI->getDynAllocFI(); 1721 1722 // Update size of the maximum argument space. 1723 // For O32, a minimum of four words (16 bytes) of argument space is 1724 // allocated. 1725 if (Subtarget->isABI_O32()) 1726 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1727 1728 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1729 1730 if (MaxCallFrameSize < NextStackOffset) { 1731 MipsFI->setMaxCallFrameSize(NextStackOffset); 1732 1733 // Set the offsets relative to $sp of the $gp restore slot and dynamically 1734 // allocated stack space. These offsets must be aligned to a boundary 1735 // determined by the stack alignment of the ABI. 1736 unsigned StackAlignment = TFL->getStackAlignment(); 1737 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1738 StackAlignment * StackAlignment; 1739 1740 if (IsPIC) 1741 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 1742 1743 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 1744 } 1745 1746 // With EABI is it possible to have 16 args on registers. 1747 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1748 SmallVector<SDValue, 8> MemOpChains; 1749 1750 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1751 1752 // Walk the register/memloc assignments, inserting copies/loads. 1753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1754 SDValue Arg = OutVals[i]; 1755 CCValAssign &VA = ArgLocs[i]; 1756 1757 // Promote the value if needed. 1758 switch (VA.getLocInfo()) { 1759 default: llvm_unreachable("Unknown loc info!"); 1760 case CCValAssign::Full: 1761 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 1762 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 1763 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 1764 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 1765 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1766 Arg, DAG.getConstant(0, MVT::i32)); 1767 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1768 Arg, DAG.getConstant(1, MVT::i32)); 1769 if (!Subtarget->isLittle()) 1770 std::swap(Lo, Hi); 1771 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); 1772 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi)); 1773 continue; 1774 } 1775 } 1776 break; 1777 case CCValAssign::SExt: 1778 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1779 break; 1780 case CCValAssign::ZExt: 1781 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1782 break; 1783 case CCValAssign::AExt: 1784 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1785 break; 1786 } 1787 1788 // Arguments that can be passed on register must be kept at 1789 // RegsToPass vector 1790 if (VA.isRegLoc()) { 1791 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1792 continue; 1793 } 1794 1795 // Register can't get to this point... 1796 assert(VA.isMemLoc()); 1797 1798 // ByVal Arg. 1799 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1800 if (Flags.isByVal()) { 1801 assert(Subtarget->isABI_O32() && 1802 "No support for ByVal args by ABIs other than O32 yet."); 1803 assert(Flags.getByValSize() && 1804 "ByVal args of size 0 should have been ignored by front-end."); 1805 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg, 1806 VA, Flags, getPointerTy()); 1807 continue; 1808 } 1809 1810 // Create the frame index object for this incoming parameter 1811 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1812 VA.getLocMemOffset(), true); 1813 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 1814 1815 // emit ISD::STORE whichs stores the 1816 // parameter value to a stack Location 1817 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 1818 MachinePointerInfo(), 1819 false, false, 0)); 1820 } 1821 1822 // Extend range of indices of frame objects for outgoing arguments that were 1823 // created during this function call. Skip this step if no such objects were 1824 // created. 1825 if (LastFI) 1826 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 1827 1828 // Transform all store nodes into one single node because all store 1829 // nodes are independent of each other. 1830 if (!MemOpChains.empty()) 1831 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1832 &MemOpChains[0], MemOpChains.size()); 1833 1834 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1835 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1836 // node so that legalize doesn't hack it. 1837 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 1838 bool LoadSymAddr = false; 1839 SDValue CalleeLo; 1840 1841 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1842 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 1843 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1844 getPointerTy(), 0,MipsII:: MO_GOT); 1845 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 1846 0, MipsII::MO_ABS_LO); 1847 } else { 1848 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1849 getPointerTy(), 0, OpFlag); 1850 } 1851 1852 LoadSymAddr = true; 1853 } 1854 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1855 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 1856 getPointerTy(), OpFlag); 1857 LoadSymAddr = true; 1858 } 1859 1860 SDValue InFlag; 1861 1862 // Create nodes that load address of callee and copy it to T9 1863 if (IsPIC) { 1864 if (LoadSymAddr) { 1865 // Load callee address 1866 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee); 1867 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee, 1868 MachinePointerInfo::getGOT(), 1869 false, false, 0); 1870 1871 // Use GOT+LO if callee has internal linkage. 1872 if (CalleeLo.getNode()) { 1873 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 1874 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 1875 } else 1876 Callee = LoadValue; 1877 } 1878 1879 // copy to T9 1880 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 1881 InFlag = Chain.getValue(1); 1882 Callee = DAG.getRegister(Mips::T9, MVT::i32); 1883 } 1884 1885 // Build a sequence of copy-to-reg nodes chained together with token 1886 // chain and flag operands which copy the outgoing args into registers. 1887 // The InFlag in necessary since all emitted instructions must be 1888 // stuck together. 1889 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1890 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1891 RegsToPass[i].second, InFlag); 1892 InFlag = Chain.getValue(1); 1893 } 1894 1895 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 1896 // = Chain, Callee, Reg#1, Reg#2, ... 1897 // 1898 // Returns a chain & a flag for retval copy to use. 1899 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1900 SmallVector<SDValue, 8> Ops; 1901 Ops.push_back(Chain); 1902 Ops.push_back(Callee); 1903 1904 // Add argument registers to the end of the list so that they are 1905 // known live into the call. 1906 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1907 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1908 RegsToPass[i].second.getValueType())); 1909 1910 if (InFlag.getNode()) 1911 Ops.push_back(InFlag); 1912 1913 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 1914 InFlag = Chain.getValue(1); 1915 1916 // Create the CALLSEQ_END node. 1917 Chain = DAG.getCALLSEQ_END(Chain, 1918 DAG.getIntPtrConstant(NextStackOffset, true), 1919 DAG.getIntPtrConstant(0, true), InFlag); 1920 InFlag = Chain.getValue(1); 1921 1922 // Handle result values, copying them out of physregs into vregs that we 1923 // return. 1924 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 1925 Ins, dl, DAG, InVals); 1926} 1927 1928/// LowerCallResult - Lower the result values of a call into the 1929/// appropriate copies out of appropriate physical registers. 1930SDValue 1931MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1932 CallingConv::ID CallConv, bool isVarArg, 1933 const SmallVectorImpl<ISD::InputArg> &Ins, 1934 DebugLoc dl, SelectionDAG &DAG, 1935 SmallVectorImpl<SDValue> &InVals) const { 1936 // Assign locations to each value returned by this call. 1937 SmallVector<CCValAssign, 16> RVLocs; 1938 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1939 getTargetMachine(), RVLocs, *DAG.getContext()); 1940 1941 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 1942 1943 // Copy all of the result registers out of their specified physreg. 1944 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1945 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 1946 RVLocs[i].getValVT(), InFlag).getValue(1); 1947 InFlag = Chain.getValue(2); 1948 InVals.push_back(Chain.getValue(0)); 1949 } 1950 1951 return Chain; 1952} 1953 1954//===----------------------------------------------------------------------===// 1955// Formal Arguments Calling Convention Implementation 1956//===----------------------------------------------------------------------===// 1957static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 1958 std::vector<SDValue>& OutChains, 1959 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 1960 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 1961 unsigned LocMem = VA.getLocMemOffset(); 1962 unsigned FirstWord = LocMem / 4; 1963 1964 // copy register A0 - A3 to frame object 1965 for (unsigned i = 0; i < NumWords; ++i) { 1966 unsigned CurWord = FirstWord + i; 1967 if (CurWord >= O32IntRegsSize) 1968 break; 1969 1970 unsigned SrcReg = O32IntRegs[CurWord]; 1971 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 1972 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 1973 DAG.getConstant(i * 4, MVT::i32)); 1974 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 1975 StorePtr, MachinePointerInfo(), false, 1976 false, 0); 1977 OutChains.push_back(Store); 1978 } 1979} 1980 1981/// LowerFormalArguments - transform physical registers into virtual registers 1982/// and generate load operations for arguments places on the stack. 1983SDValue 1984MipsTargetLowering::LowerFormalArguments(SDValue Chain, 1985 CallingConv::ID CallConv, 1986 bool isVarArg, 1987 const SmallVectorImpl<ISD::InputArg> 1988 &Ins, 1989 DebugLoc dl, SelectionDAG &DAG, 1990 SmallVectorImpl<SDValue> &InVals) 1991 const { 1992 MachineFunction &MF = DAG.getMachineFunction(); 1993 MachineFrameInfo *MFI = MF.getFrameInfo(); 1994 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1995 1996 MipsFI->setVarArgsFrameIndex(0); 1997 1998 // Used with vargs to acumulate store chains. 1999 std::vector<SDValue> OutChains; 2000 2001 // Assign locations to all of the incoming arguments. 2002 SmallVector<CCValAssign, 16> ArgLocs; 2003 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2004 getTargetMachine(), ArgLocs, *DAG.getContext()); 2005 2006 if (Subtarget->isABI_O32()) 2007 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2008 else 2009 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2010 2011 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2012 2013 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2014 CCValAssign &VA = ArgLocs[i]; 2015 2016 // Arguments stored on registers 2017 if (VA.isRegLoc()) { 2018 EVT RegVT = VA.getLocVT(); 2019 unsigned ArgReg = VA.getLocReg(); 2020 TargetRegisterClass *RC = 0; 2021 2022 if (RegVT == MVT::i32) 2023 RC = Mips::CPURegsRegisterClass; 2024 else if (RegVT == MVT::f32) 2025 RC = Mips::FGR32RegisterClass; 2026 else if (RegVT == MVT::f64) { 2027 if (!Subtarget->isSingleFloat()) 2028 RC = Mips::AFGR64RegisterClass; 2029 } else 2030 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2031 2032 // Transform the arguments stored on 2033 // physical registers into virtual ones 2034 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2035 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2036 2037 // If this is an 8 or 16-bit value, it has been passed promoted 2038 // to 32 bits. Insert an assert[sz]ext to capture this, then 2039 // truncate to the right size. 2040 if (VA.getLocInfo() != CCValAssign::Full) { 2041 unsigned Opcode = 0; 2042 if (VA.getLocInfo() == CCValAssign::SExt) 2043 Opcode = ISD::AssertSext; 2044 else if (VA.getLocInfo() == CCValAssign::ZExt) 2045 Opcode = ISD::AssertZext; 2046 if (Opcode) 2047 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2048 DAG.getValueType(VA.getValVT())); 2049 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2050 } 2051 2052 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 2053 if (Subtarget->isABI_O32()) { 2054 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 2055 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 2056 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 2057 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2058 VA.getLocReg()+1, RC); 2059 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2060 if (!Subtarget->isLittle()) 2061 std::swap(ArgValue, ArgValue2); 2062 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2063 ArgValue, ArgValue2); 2064 } 2065 } 2066 2067 InVals.push_back(ArgValue); 2068 } else { // VA.isRegLoc() 2069 2070 // sanity check 2071 assert(VA.isMemLoc()); 2072 2073 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2074 2075 if (Flags.isByVal()) { 2076 assert(Subtarget->isABI_O32() && 2077 "No support for ByVal args by ABIs other than O32 yet."); 2078 assert(Flags.getByValSize() && 2079 "ByVal args of size 0 should have been ignored by front-end."); 2080 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2081 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2082 true); 2083 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2084 InVals.push_back(FIN); 2085 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2086 2087 continue; 2088 } 2089 2090 // The stack pointer offset is relative to the caller stack frame. 2091 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2092 VA.getLocMemOffset(), true); 2093 2094 // Create load nodes to retrieve arguments from the stack 2095 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2096 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2097 MachinePointerInfo::getFixedStack(LastFI), 2098 false, false, 0)); 2099 } 2100 } 2101 2102 // The mips ABIs for returning structs by value requires that we copy 2103 // the sret argument into $v0 for the return. Save the argument into 2104 // a virtual register so that we can access it from the return points. 2105 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2106 unsigned Reg = MipsFI->getSRetReturnReg(); 2107 if (!Reg) { 2108 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2109 MipsFI->setSRetReturnReg(Reg); 2110 } 2111 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2112 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2113 } 2114 2115 if (isVarArg && Subtarget->isABI_O32()) { 2116 // Record the frame index of the first variable argument 2117 // which is a value necessary to VASTART. 2118 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2119 assert(NextStackOffset % 4 == 0 && 2120 "NextStackOffset must be aligned to 4-byte boundaries."); 2121 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2122 MipsFI->setVarArgsFrameIndex(LastFI); 2123 2124 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 2125 // copy the integer registers that have not been used for argument passing 2126 // to the caller's stack frame. 2127 for (; NextStackOffset < 16; NextStackOffset += 4) { 2128 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 2129 unsigned Idx = NextStackOffset / 4; 2130 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 2131 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 2132 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2133 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2134 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2135 MachinePointerInfo(), 2136 false, false, 0)); 2137 } 2138 } 2139 2140 MipsFI->setLastInArgFI(LastFI); 2141 2142 // All stores are grouped in one node to allow the matching between 2143 // the size of Ins and InVals. This only happens when on varg functions 2144 if (!OutChains.empty()) { 2145 OutChains.push_back(Chain); 2146 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2147 &OutChains[0], OutChains.size()); 2148 } 2149 2150 return Chain; 2151} 2152 2153//===----------------------------------------------------------------------===// 2154// Return Value Calling Convention Implementation 2155//===----------------------------------------------------------------------===// 2156 2157SDValue 2158MipsTargetLowering::LowerReturn(SDValue Chain, 2159 CallingConv::ID CallConv, bool isVarArg, 2160 const SmallVectorImpl<ISD::OutputArg> &Outs, 2161 const SmallVectorImpl<SDValue> &OutVals, 2162 DebugLoc dl, SelectionDAG &DAG) const { 2163 2164 // CCValAssign - represent the assignment of 2165 // the return value to a location 2166 SmallVector<CCValAssign, 16> RVLocs; 2167 2168 // CCState - Info about the registers and stack slot. 2169 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2170 getTargetMachine(), RVLocs, *DAG.getContext()); 2171 2172 // Analize return values. 2173 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2174 2175 // If this is the first return lowered for this function, add 2176 // the regs to the liveout set for the function. 2177 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2178 for (unsigned i = 0; i != RVLocs.size(); ++i) 2179 if (RVLocs[i].isRegLoc()) 2180 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2181 } 2182 2183 SDValue Flag; 2184 2185 // Copy the result values into the output registers. 2186 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2187 CCValAssign &VA = RVLocs[i]; 2188 assert(VA.isRegLoc() && "Can only return in registers!"); 2189 2190 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2191 OutVals[i], Flag); 2192 2193 // guarantee that all emitted copies are 2194 // stuck together, avoiding something bad 2195 Flag = Chain.getValue(1); 2196 } 2197 2198 // The mips ABIs for returning structs by value requires that we copy 2199 // the sret argument into $v0 for the return. We saved the argument into 2200 // a virtual register in the entry block, so now we copy the value out 2201 // and into $v0. 2202 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2203 MachineFunction &MF = DAG.getMachineFunction(); 2204 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2205 unsigned Reg = MipsFI->getSRetReturnReg(); 2206 2207 if (!Reg) 2208 llvm_unreachable("sret virtual register not created in the entry block"); 2209 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2210 2211 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2212 Flag = Chain.getValue(1); 2213 } 2214 2215 // Return on Mips is always a "jr $ra" 2216 if (Flag.getNode()) 2217 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2218 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2219 else // Return Void 2220 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2221 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2222} 2223 2224//===----------------------------------------------------------------------===// 2225// Mips Inline Assembly Support 2226//===----------------------------------------------------------------------===// 2227 2228/// getConstraintType - Given a constraint letter, return the type of 2229/// constraint it is for this target. 2230MipsTargetLowering::ConstraintType MipsTargetLowering:: 2231getConstraintType(const std::string &Constraint) const 2232{ 2233 // Mips specific constrainy 2234 // GCC config/mips/constraints.md 2235 // 2236 // 'd' : An address register. Equivalent to r 2237 // unless generating MIPS16 code. 2238 // 'y' : Equivalent to r; retained for 2239 // backwards compatibility. 2240 // 'f' : Floating Point registers. 2241 if (Constraint.size() == 1) { 2242 switch (Constraint[0]) { 2243 default : break; 2244 case 'd': 2245 case 'y': 2246 case 'f': 2247 return C_RegisterClass; 2248 break; 2249 } 2250 } 2251 return TargetLowering::getConstraintType(Constraint); 2252} 2253 2254/// Examine constraint type and operand type and determine a weight value. 2255/// This object must already have been set up with the operand type 2256/// and the current alternative constraint selected. 2257TargetLowering::ConstraintWeight 2258MipsTargetLowering::getSingleConstraintMatchWeight( 2259 AsmOperandInfo &info, const char *constraint) const { 2260 ConstraintWeight weight = CW_Invalid; 2261 Value *CallOperandVal = info.CallOperandVal; 2262 // If we don't have a value, we can't do a match, 2263 // but allow it at the lowest weight. 2264 if (CallOperandVal == NULL) 2265 return CW_Default; 2266 Type *type = CallOperandVal->getType(); 2267 // Look at the constraint type. 2268 switch (*constraint) { 2269 default: 2270 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2271 break; 2272 case 'd': 2273 case 'y': 2274 if (type->isIntegerTy()) 2275 weight = CW_Register; 2276 break; 2277 case 'f': 2278 if (type->isFloatTy()) 2279 weight = CW_Register; 2280 break; 2281 } 2282 return weight; 2283} 2284 2285/// Given a register class constraint, like 'r', if this corresponds directly 2286/// to an LLVM register class, return a register of 0 and the register class 2287/// pointer. 2288std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2289getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2290{ 2291 if (Constraint.size() == 1) { 2292 switch (Constraint[0]) { 2293 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2294 case 'y': // Same as 'r'. Exists for compatibility. 2295 case 'r': 2296 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2297 case 'f': 2298 if (VT == MVT::f32) 2299 return std::make_pair(0U, Mips::FGR32RegisterClass); 2300 if (VT == MVT::f64) 2301 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 2302 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2303 break; 2304 } 2305 } 2306 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2307} 2308 2309bool 2310MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2311 // The Mips target isn't yet aware of offsets. 2312 return false; 2313} 2314 2315bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2316 if (VT != MVT::f32 && VT != MVT::f64) 2317 return false; 2318 if (Imm.isNegZero()) 2319 return false; 2320 return Imm.isZero(); 2321} 2322