MipsISelLowering.cpp revision 0f8d9c04d9feef86cee35cf5fecfb348a6b3de50
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Bruno Cardoso Lopes and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16 17#include "MipsISelLowering.h" 18#include "MipsMachineFunction.h" 19#include "MipsTargetMachine.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/Intrinsics.h" 23#include "llvm/CallingConv.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/CodeGen/SSARegMap.h" 30#include "llvm/CodeGen/ValueTypes.h" 31#include "llvm/Support/Debug.h" 32#include <queue> 33#include <set> 34 35using namespace llvm; 36 37const char *MipsTargetLowering:: 38getTargetNodeName(unsigned Opcode) const 39{ 40 switch (Opcode) 41 { 42 case MipsISD::JmpLink : return "MipsISD::JmpLink"; 43 case MipsISD::Hi : return "MipsISD::Hi"; 44 case MipsISD::Lo : return "MipsISD::Lo"; 45 case MipsISD::Ret : return "MipsISD::Ret"; 46 default : return NULL; 47 } 48} 49 50MipsTargetLowering:: 51MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) 52{ 53 // Mips does not have i1 type, so use i32 for 54 // setcc operations results (slt, sgt, ...). 55 setSetCCResultType(MVT::i32); 56 setSetCCResultContents(ZeroOrOneSetCCResult); 57 58 // JumpTable targets must use GOT when using PIC_ 59 setUsesGlobalOffsetTable(true); 60 61 // Set up the register classes 62 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 63 64 // Custom 65 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 66 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 67 setOperationAction(ISD::RET, MVT::Other, Custom); 68 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 69 70 // Load extented operations for i1 types must be promoted 71 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); 72 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); 73 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 74 75 // Store operations for i1 types must be promoted 76 setStoreXAction(MVT::i1, Promote); 77 78 // Mips does not have these NodeTypes below. 79 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 80 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 81 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 82 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 83 setOperationAction(ISD::SELECT, MVT::i32, Expand); 84 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 85 86 // Mips not supported intrinsics. 87 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 88 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 89 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 90 91 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 92 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 93 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 94 setOperationAction(ISD::ROTL , MVT::i32, Expand); 95 setOperationAction(ISD::ROTR , MVT::i32, Expand); 96 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 97 98 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 99 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 100 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 101 102 // We don't have line number support yet. 103 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 104 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 105 setOperationAction(ISD::LABEL, MVT::Other, Expand); 106 107 // Use the default for now 108 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 109 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 110 111 setStackPointerRegisterToSaveRestore(Mips::SP); 112 computeRegisterProperties(); 113} 114 115 116SDOperand MipsTargetLowering:: 117LowerOperation(SDOperand Op, SelectionDAG &DAG) 118{ 119 switch (Op.getOpcode()) 120 { 121 case ISD::CALL: return LowerCALL(Op, DAG); 122 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 123 case ISD::RET: return LowerRET(Op, DAG); 124 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 125 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 126 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 127 } 128 return SDOperand(); 129} 130 131//===----------------------------------------------------------------------===// 132// Lower helper functions 133//===----------------------------------------------------------------------===// 134 135// AddLiveIn - This helper function adds the specified physical register to the 136// MachineFunction as a live in value. It also creates a corresponding 137// virtual register for it. 138static unsigned 139AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 140{ 141 assert(RC->contains(PReg) && "Not the correct regclass!"); 142 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 143 MF.addLiveIn(PReg, VReg); 144 return VReg; 145} 146 147//===----------------------------------------------------------------------===// 148// Misc Lower Operation implementation 149//===----------------------------------------------------------------------===// 150SDOperand MipsTargetLowering:: 151LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) 152{ 153 SDOperand ResNode; 154 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 155 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 156 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_); 157 158 SDOperand HiPart; 159 if (!isPIC) { 160 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32); 161 SDOperand Ops[] = { GA }; 162 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); 163 } else // Emit Load from Global Pointer 164 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); 165 166 // On functions and global targets not internal linked only 167 // a load from got/GP is necessary for PIC to work. 168 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV)))) 169 return HiPart; 170 171 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); 172 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); 173 174 return ResNode; 175} 176 177SDOperand MipsTargetLowering:: 178LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) 179{ 180 assert(0 && "TLS not implemented for MIPS."); 181} 182 183SDOperand MipsTargetLowering:: 184LowerJumpTable(SDOperand Op, SelectionDAG &DAG) 185{ 186 SDOperand ResNode; 187 SDOperand HiPart; 188 189 MVT::ValueType PtrVT = Op.getValueType(); 190 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 191 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 192 193 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 194 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32); 195 SDOperand Ops[] = { JTI }; 196 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); 197 } else // Emit Load from Global Pointer 198 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0); 199 200 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI); 201 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); 202 203 return ResNode; 204} 205 206//===----------------------------------------------------------------------===// 207// Calling Convention Implementation 208// 209// The lower operations present on calling convention works on this order: 210// LowerCALL (virt regs --> phys regs, virt regs --> stack) 211// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs) 212// LowerRET (virt regs --> phys regs) 213// LowerCALL (phys regs --> virt regs) 214// 215//===----------------------------------------------------------------------===// 216 217#include "MipsGenCallingConv.inc" 218 219//===----------------------------------------------------------------------===// 220// CALL Calling Convention Implementation 221//===----------------------------------------------------------------------===// 222 223/// Mips custom CALL implementation 224SDOperand MipsTargetLowering:: 225LowerCALL(SDOperand Op, SelectionDAG &DAG) 226{ 227 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 228 229 // By now, only CallingConv::C implemented 230 switch (CallingConv) 231 { 232 default: 233 assert(0 && "Unsupported calling convention"); 234 case CallingConv::Fast: 235 case CallingConv::C: 236 return LowerCCCCallTo(Op, DAG, CallingConv); 237 } 238} 239 240/// LowerCCCCallTo - functions arguments are copied from virtual 241/// regs to (physical regs)/(stack frame), CALLSEQ_START and 242/// CALLSEQ_END are emitted. 243/// TODO: isVarArg, isTailCall, sret. 244SDOperand MipsTargetLowering:: 245LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) 246{ 247 MachineFunction &MF = DAG.getMachineFunction(); 248 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 249 250 SDOperand Chain = Op.getOperand(0); 251 SDOperand Callee = Op.getOperand(4); 252 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 253 254 MachineFrameInfo *MFI = MF.getFrameInfo(); 255 256 // Analyze operands of the call, assigning locations to each operand. 257 SmallVector<CCValAssign, 16> ArgLocs; 258 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 259 260 // To meet ABI, Mips must always allocate 16 bytes on 261 // the stack (even if less than 4 are used as arguments) 262 int VTsize = MVT::getSizeInBits(MVT::i32)/8; 263 MFI->CreateFixedObject(VTsize, (VTsize*3)); 264 265 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips); 266 267 // Get a count of how many bytes are to be pushed on the stack. 268 unsigned NumBytes = CCInfo.getNextStackOffset(); 269 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 270 getPointerTy())); 271 272 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; 273 SmallVector<SDOperand, 8> MemOpChains; 274 275 SDOperand StackPtr; 276 int LastStackLoc=0; 277 278 // Walk the register/memloc assignments, inserting copies/loads. 279 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 280 CCValAssign &VA = ArgLocs[i]; 281 282 // Arguments start after the 5 first operands of ISD::CALL 283 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 284 285 // Promote the value if needed. 286 switch (VA.getLocInfo()) { 287 default: assert(0 && "Unknown loc info!"); 288 case CCValAssign::Full: break; 289 case CCValAssign::SExt: 290 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 291 break; 292 case CCValAssign::ZExt: 293 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 294 break; 295 case CCValAssign::AExt: 296 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 297 break; 298 } 299 300 // Arguments that can be passed on register must be kept at 301 // RegsToPass vector 302 if (VA.isRegLoc()) { 303 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 304 } else { 305 306 assert(VA.isMemLoc()); 307 308 if (StackPtr.Val == 0) 309 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 310 311 // Create the frame index object for this incoming parameter 312 // This guarantees that when allocating Local Area the firsts 313 // 16 bytes which are alwayes reserved won't be overwritten. 314 LastStackLoc = (16 + VA.getLocMemOffset()); 315 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, 316 LastStackLoc); 317 318 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy()); 319 320 // emit ISD::STORE whichs stores the 321 // parameter value to a stack Location 322 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 323 } 324 } 325 326 // Transform all store nodes into one single node because 327 // all store nodes are independent of each other. 328 if (!MemOpChains.empty()) 329 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 330 &MemOpChains[0], MemOpChains.size()); 331 332 // Build a sequence of copy-to-reg nodes chained together with token 333 // chain and flag operands which copy the outgoing args into registers. 334 // The InFlag in necessary since all emited instructions must be 335 // stuck together. 336 SDOperand InFlag; 337 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 338 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, 339 RegsToPass[i].second, InFlag); 340 InFlag = Chain.getValue(1); 341 } 342 343 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 344 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 345 // node so that legalize doesn't hack it. 346 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 347 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 348 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 349 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 350 351 352 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 353 // = Chain, Callee, Reg#1, Reg#2, ... 354 // 355 // Returns a chain & a flag for retval copy to use. 356 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 357 SmallVector<SDOperand, 8> Ops; 358 Ops.push_back(Chain); 359 Ops.push_back(Callee); 360 361 // Add argument registers to the end of the list so that they are 362 // known live into the call. 363 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 364 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 365 RegsToPass[i].second.getValueType())); 366 367 if (InFlag.Val) 368 Ops.push_back(InFlag); 369 370 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); 371 InFlag = Chain.getValue(1); 372 373 // Create a stack location to hold GP when PIC is used. This stack 374 // location is used on function prologue to save GP and also after all 375 // emited CALL's to restore GP. 376 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 377 // Function can have an arbitrary number of calls, so 378 // hold the LastStackLoc with the biggest offset. 379 int FI; 380 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 381 if (LastStackLoc >= MipsFI->getGPStackOffset()) { 382 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4); 383 // Create the frame index only once. SPOffset here can be anything 384 // (this will be fixed on processFunctionBeforeFrameFinalized) 385 if (MipsFI->getGPStackOffset() == -1) { 386 FI = MFI->CreateFixedObject(4, 0); 387 MipsFI->setGPFI(FI); 388 } 389 MipsFI->setGPStackOffset(LastStackLoc); 390 } 391 392 // Reload GP value. 393 FI = MipsFI->getGPFI(); 394 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy()); 395 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); 396 Chain = GPLoad.getValue(1); 397 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32), 398 GPLoad, SDOperand(0,0)); 399 } 400 401 // Create the CALLSEQ_END node. 402 Chain = DAG.getCALLSEQ_END(Chain, 403 DAG.getConstant(NumBytes, getPointerTy()), 404 DAG.getConstant(0, getPointerTy()), 405 InFlag); 406 InFlag = Chain.getValue(1); 407 408 // Handle result values, copying them out of physregs into vregs that we 409 // return. 410 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 411} 412 413/// LowerCallResult - Lower the result values of an ISD::CALL into the 414/// appropriate copies out of appropriate physical registers. This assumes that 415/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 416/// being lowered. Returns a SDNode with the same number of values as the 417/// ISD::CALL. 418SDNode *MipsTargetLowering:: 419LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, 420 unsigned CallingConv, SelectionDAG &DAG) { 421 422 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; 423 424 // Assign locations to each value returned by this call. 425 SmallVector<CCValAssign, 16> RVLocs; 426 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 427 428 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips); 429 SmallVector<SDOperand, 8> ResultVals; 430 431 // Copy all of the result registers out of their specified physreg. 432 for (unsigned i = 0; i != RVLocs.size(); ++i) { 433 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 434 RVLocs[i].getValVT(), InFlag).getValue(1); 435 InFlag = Chain.getValue(2); 436 ResultVals.push_back(Chain.getValue(0)); 437 } 438 439 ResultVals.push_back(Chain); 440 441 // Merge everything together with a MERGE_VALUES node. 442 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), 443 &ResultVals[0], ResultVals.size()).Val; 444} 445 446//===----------------------------------------------------------------------===// 447// FORMAL_ARGUMENTS Calling Convention Implementation 448//===----------------------------------------------------------------------===// 449 450/// Mips custom FORMAL_ARGUMENTS implementation 451SDOperand MipsTargetLowering:: 452LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) 453{ 454 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 455 switch(CC) 456 { 457 default: 458 assert(0 && "Unsupported calling convention"); 459 case CallingConv::C: 460 return LowerCCCArguments(Op, DAG); 461 } 462} 463 464/// LowerCCCArguments - transform physical registers into 465/// virtual registers and generate load operations for 466/// arguments places on the stack. 467/// TODO: isVarArg, sret 468SDOperand MipsTargetLowering:: 469LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) 470{ 471 SDOperand Root = Op.getOperand(0); 472 MachineFunction &MF = DAG.getMachineFunction(); 473 MachineFrameInfo *MFI = MF.getFrameInfo(); 474 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 475 476 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 477 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 478 479 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 480 481 // GP holds the GOT address on PIC calls. 482 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 483 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass); 484 485 // Assign locations to all of the incoming arguments. 486 SmallVector<CCValAssign, 16> ArgLocs; 487 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 488 489 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips); 490 SmallVector<SDOperand, 8> ArgValues; 491 SDOperand StackPtr; 492 493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 494 495 CCValAssign &VA = ArgLocs[i]; 496 497 // Arguments stored on registers 498 if (VA.isRegLoc()) { 499 MVT::ValueType RegVT = VA.getLocVT(); 500 TargetRegisterClass *RC; 501 502 if (RegVT == MVT::i32) 503 RC = Mips::CPURegsRegisterClass; 504 else 505 assert(0 && "support only Mips::CPURegsRegisterClass"); 506 507 // Transform the arguments stored on 508 // physical registers into virtual ones 509 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 510 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 511 512 // If this is an 8 or 16-bit value, it is really passed promoted 513 // to 32 bits. Insert an assert[sz]ext to capture this, then 514 // truncate to the right size. 515 if (VA.getLocInfo() == CCValAssign::SExt) 516 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 517 DAG.getValueType(VA.getValVT())); 518 else if (VA.getLocInfo() == CCValAssign::ZExt) 519 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 520 DAG.getValueType(VA.getValVT())); 521 522 if (VA.getLocInfo() != CCValAssign::Full) 523 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 524 525 ArgValues.push_back(ArgValue); 526 527 // To meet ABI, when VARARGS are passed on registers, the registers 528 // must have their values written to the caller stack frame. 529 if (isVarArg) { 530 531 if (StackPtr.Val == 0) 532 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 533 534 // The stack pointer offset is relative to the caller stack frame. 535 // Since the real stack size is unknown here, a negative SPOffset 536 // is used so there's a way to adjust these offsets when the stack 537 // size get known (on EliminateFrameIndex). A dummy SPOffset is 538 // used instead of a direct negative address (which is recorded to 539 // be used on emitPrologue) to avoid mis-calc of the first stack 540 // offset on PEI::calculateFrameObjectOffsets. 541 // Arguments are always 32-bit. 542 int FI = MFI->CreateFixedObject(4, 0); 543 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4))); 544 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 545 546 // emit ISD::STORE whichs stores the 547 // parameter value to a stack Location 548 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0)); 549 } 550 551 } else { 552 // sanity check 553 assert(VA.isMemLoc()); 554 555 // The stack pointer offset is relative to the caller stack frame. 556 // Since the real stack size is unknown here, a negative SPOffset 557 // is used so there's a way to adjust these offsets when the stack 558 // size get known (on EliminateFrameIndex). A dummy SPOffset is 559 // used instead of a direct negative address (which is recorded to 560 // be used on emitPrologue) to avoid mis-calc of the first stack 561 // offset on PEI::calculateFrameObjectOffsets. 562 // Arguments are always 32-bit. 563 int FI = MFI->CreateFixedObject(4, 0); 564 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset()))); 565 566 // Create load nodes to retrieve arguments from the stack 567 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 568 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); 569 } 570 } 571 ArgValues.push_back(Root); 572 573 // Return the new list of results. 574 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 575 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); 576} 577 578//===----------------------------------------------------------------------===// 579// Return Value Calling Convention Implementation 580//===----------------------------------------------------------------------===// 581 582SDOperand MipsTargetLowering:: 583LowerRET(SDOperand Op, SelectionDAG &DAG) 584{ 585 // CCValAssign - represent the assignment of 586 // the return value to a location 587 SmallVector<CCValAssign, 16> RVLocs; 588 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 589 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 590 591 // CCState - Info about the registers and stack slot. 592 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 593 594 // Analize return values of ISD::RET 595 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips); 596 597 // If this is the first return lowered for this function, add 598 // the regs to the liveout set for the function. 599 if (DAG.getMachineFunction().liveout_empty()) { 600 for (unsigned i = 0; i != RVLocs.size(); ++i) 601 if (RVLocs[i].isRegLoc()) 602 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 603 } 604 605 // The chain is always operand #0 606 SDOperand Chain = Op.getOperand(0); 607 SDOperand Flag; 608 609 // Copy the result values into the output registers. 610 for (unsigned i = 0; i != RVLocs.size(); ++i) { 611 CCValAssign &VA = RVLocs[i]; 612 assert(VA.isRegLoc() && "Can only return in registers!"); 613 614 // ISD::RET => ret chain, (regnum1,val1), ... 615 // So i*2+1 index only the regnums 616 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 617 618 // guarantee that all emitted copies are 619 // stuck together, avoiding something bad 620 Flag = Chain.getValue(1); 621 } 622 623 // Return on Mips is always a "jr $ra" 624 if (Flag.Val) 625 return DAG.getNode(MipsISD::Ret, MVT::Other, 626 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 627 else // Return Void 628 return DAG.getNode(MipsISD::Ret, MVT::Other, 629 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 630} 631 632//===----------------------------------------------------------------------===// 633// Mips Inline Assembly Support 634//===----------------------------------------------------------------------===// 635 636/// getConstraintType - Given a constraint letter, return the type of 637/// constraint it is for this target. 638MipsTargetLowering::ConstraintType MipsTargetLowering:: 639getConstraintType(const std::string &Constraint) const 640{ 641 if (Constraint.size() == 1) { 642 // Mips specific constrainy 643 // GCC config/mips/constraints.md 644 // 645 // 'd' : An address register. Equivalent to r 646 // unless generating MIPS16 code. 647 // 'y' : Equivalent to r; retained for 648 // backwards compatibility. 649 // 650 switch (Constraint[0]) { 651 default : break; 652 case 'd': 653 case 'y': 654 return C_RegisterClass; 655 break; 656 } 657 } 658 return TargetLowering::getConstraintType(Constraint); 659} 660 661std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 662getRegForInlineAsmConstraint(const std::string &Constraint, 663 MVT::ValueType VT) const 664{ 665 if (Constraint.size() == 1) { 666 switch (Constraint[0]) { 667 case 'r': 668 return std::make_pair(0U, Mips::CPURegsRegisterClass); 669 break; 670 } 671 } 672 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 673} 674 675std::vector<unsigned> MipsTargetLowering:: 676getRegClassForInlineAsmConstraint(const std::string &Constraint, 677 MVT::ValueType VT) const 678{ 679 if (Constraint.size() != 1) 680 return std::vector<unsigned>(); 681 682 switch (Constraint[0]) { 683 default : break; 684 case 'r': 685 // GCC Mips Constraint Letters 686 case 'd': 687 case 'y': 688 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0, 689 Mips::A1, Mips::A2, Mips::A3, 690 Mips::T0, Mips::T1, Mips::T2, 691 Mips::T3, Mips::T4, Mips::T5, 692 Mips::T6, Mips::T7, Mips::S0, 693 Mips::S1, Mips::S2, Mips::S3, 694 Mips::S4, Mips::S5, Mips::S6, 695 Mips::S7, Mips::T8, Mips::T9, 0); 696 break; 697 } 698 return std::vector<unsigned>(); 699} 700