MipsISelLowering.cpp revision 1440e8b918d7116c3587cb95f4f7ac7a0a0b65ad
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/CallingConv.h" 26#include "llvm/CodeGen/CallingConvLower.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/SelectionDAGISel.h" 32#include "llvm/CodeGen/ValueTypes.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35using namespace llvm; 36 37const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 38 switch (Opcode) { 39 case MipsISD::JmpLink : return "MipsISD::JmpLink"; 40 case MipsISD::Hi : return "MipsISD::Hi"; 41 case MipsISD::Lo : return "MipsISD::Lo"; 42 case MipsISD::GPRel : return "MipsISD::GPRel"; 43 case MipsISD::Ret : return "MipsISD::Ret"; 44 case MipsISD::CMov : return "MipsISD::CMov"; 45 case MipsISD::SelectCC : return "MipsISD::SelectCC"; 46 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC"; 47 case MipsISD::FPBrcond : return "MipsISD::FPBrcond"; 48 case MipsISD::FPCmp : return "MipsISD::FPCmp"; 49 case MipsISD::FPRound : return "MipsISD::FPRound"; 50 default : return NULL; 51 } 52} 53 54MipsTargetLowering:: 55MipsTargetLowering(MipsTargetMachine &TM) 56 : TargetLowering(TM, new MipsTargetObjectFile()) { 57 Subtarget = &TM.getSubtarget<MipsSubtarget>(); 58 59 // Mips does not have i1 type, so use i32 for 60 // setcc operations results (slt, sgt, ...). 61 setBooleanContents(ZeroOrOneBooleanContent); 62 63 // Set up the register classes 64 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 65 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 66 67 // When dealing with single precision only, use libcalls 68 if (!Subtarget->isSingleFloat()) 69 if (!Subtarget->isFP64bit()) 70 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 71 72 // Load extented operations for i1 types must be promoted 73 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 74 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 75 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 76 77 // MIPS doesn't have extending float->double load/store 78 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 79 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 80 81 // Used by legalize types to correctly generate the setcc result. 82 // Without this, every float setcc comes with a AND/OR with the result, 83 // we don't want this, since the fpcmp result goes to a flag register, 84 // which is used implicitly by brcond and select operations. 85 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 86 87 // Mips Custom Operations 88 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 89 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 90 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 92 setOperationAction(ISD::SELECT, MVT::f32, Custom); 93 setOperationAction(ISD::SELECT, MVT::f64, Custom); 94 setOperationAction(ISD::SELECT, MVT::i32, Custom); 95 setOperationAction(ISD::SETCC, MVT::f32, Custom); 96 setOperationAction(ISD::SETCC, MVT::f64, Custom); 97 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 99 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 100 setOperationAction(ISD::VASTART, MVT::Other, Custom); 101 102 103 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors' 104 // with operands comming from setcc fp comparions. This is necessary since 105 // the result from these setcc are in a flag registers (FCR31). 106 setOperationAction(ISD::AND, MVT::i32, Custom); 107 setOperationAction(ISD::OR, MVT::i32, Custom); 108 109 // Operations not directly supported by Mips. 110 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 111 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 112 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 113 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 114 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 116 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 117 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 118 setOperationAction(ISD::ROTL, MVT::i32, Expand); 119 setOperationAction(ISD::ROTR, MVT::i32, Expand); 120 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 121 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 122 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 123 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 124 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 125 setOperationAction(ISD::FSIN, MVT::f32, Expand); 126 setOperationAction(ISD::FCOS, MVT::f32, Expand); 127 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 128 setOperationAction(ISD::FPOW, MVT::f32, Expand); 129 setOperationAction(ISD::FLOG, MVT::f32, Expand); 130 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 131 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 132 setOperationAction(ISD::FEXP, MVT::f32, Expand); 133 134 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 135 136 // Use the default for now 137 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 138 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 139 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 140 141 if (Subtarget->isSingleFloat()) 142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 143 144 if (!Subtarget->hasSEInReg()) { 145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 147 } 148 149 if (!Subtarget->hasBitCount()) 150 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 151 152 if (!Subtarget->hasSwap()) 153 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 154 155 setStackPointerRegisterToSaveRestore(Mips::SP); 156 computeRegisterProperties(); 157} 158 159MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const { 160 return MVT::i32; 161} 162 163/// getFunctionAlignment - Return the Log2 alignment of this function. 164unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const { 165 return 2; 166} 167 168SDValue MipsTargetLowering:: 169LowerOperation(SDValue Op, SelectionDAG &DAG) const 170{ 171 switch (Op.getOpcode()) 172 { 173 case ISD::AND: return LowerANDOR(Op, DAG); 174 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 175 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 176 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 177 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 178 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 179 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 180 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 181 case ISD::OR: return LowerANDOR(Op, DAG); 182 case ISD::SELECT: return LowerSELECT(Op, DAG); 183 case ISD::SETCC: return LowerSETCC(Op, DAG); 184 case ISD::VASTART: return LowerVASTART(Op, DAG); 185 } 186 return SDValue(); 187} 188 189//===----------------------------------------------------------------------===// 190// Lower helper functions 191//===----------------------------------------------------------------------===// 192 193// AddLiveIn - This helper function adds the specified physical register to the 194// MachineFunction as a live in value. It also creates a corresponding 195// virtual register for it. 196static unsigned 197AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 198{ 199 assert(RC->contains(PReg) && "Not the correct regclass!"); 200 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 201 MF.getRegInfo().addLiveIn(PReg, VReg); 202 return VReg; 203} 204 205// Get fp branch code (not opcode) from condition code. 206static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 207 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 208 return Mips::BRANCH_T; 209 210 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 211 return Mips::BRANCH_F; 212 213 return Mips::BRANCH_INVALID; 214} 215 216static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) { 217 switch(BC) { 218 default: 219 llvm_unreachable("Unknown branch code"); 220 case Mips::BRANCH_T : return Mips::BC1T; 221 case Mips::BRANCH_F : return Mips::BC1F; 222 case Mips::BRANCH_TL : return Mips::BC1TL; 223 case Mips::BRANCH_FL : return Mips::BC1FL; 224 } 225} 226 227static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 228 switch (CC) { 229 default: llvm_unreachable("Unknown fp condition code!"); 230 case ISD::SETEQ: 231 case ISD::SETOEQ: return Mips::FCOND_EQ; 232 case ISD::SETUNE: return Mips::FCOND_OGL; 233 case ISD::SETLT: 234 case ISD::SETOLT: return Mips::FCOND_OLT; 235 case ISD::SETGT: 236 case ISD::SETOGT: return Mips::FCOND_OGT; 237 case ISD::SETLE: 238 case ISD::SETOLE: return Mips::FCOND_OLE; 239 case ISD::SETGE: 240 case ISD::SETOGE: return Mips::FCOND_OGE; 241 case ISD::SETULT: return Mips::FCOND_ULT; 242 case ISD::SETULE: return Mips::FCOND_ULE; 243 case ISD::SETUGT: return Mips::FCOND_UGT; 244 case ISD::SETUGE: return Mips::FCOND_UGE; 245 case ISD::SETUO: return Mips::FCOND_UN; 246 case ISD::SETO: return Mips::FCOND_OR; 247 case ISD::SETNE: 248 case ISD::SETONE: return Mips::FCOND_NEQ; 249 case ISD::SETUEQ: return Mips::FCOND_UEQ; 250 } 251} 252 253MachineBasicBlock * 254MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 255 MachineBasicBlock *BB) const { 256 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 257 bool isFPCmp = false; 258 DebugLoc dl = MI->getDebugLoc(); 259 260 switch (MI->getOpcode()) { 261 default: assert(false && "Unexpected instr type to insert"); 262 case Mips::Select_FCC: 263 case Mips::Select_FCC_S32: 264 case Mips::Select_FCC_D32: 265 isFPCmp = true; // FALL THROUGH 266 case Mips::Select_CC: 267 case Mips::Select_CC_S32: 268 case Mips::Select_CC_D32: { 269 // To "insert" a SELECT_CC instruction, we actually have to insert the 270 // diamond control-flow pattern. The incoming instruction knows the 271 // destination vreg to set, the condition code register to branch on, the 272 // true/false values to select between, and a branch opcode to use. 273 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 274 MachineFunction::iterator It = BB; 275 ++It; 276 277 // thisMBB: 278 // ... 279 // TrueVal = ... 280 // setcc r1, r2, r3 281 // bNE r1, r0, copy1MBB 282 // fallthrough --> copy0MBB 283 MachineBasicBlock *thisMBB = BB; 284 MachineFunction *F = BB->getParent(); 285 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 286 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 287 F->insert(It, copy0MBB); 288 F->insert(It, sinkMBB); 289 290 // Transfer the remainder of BB and its successor edges to sinkMBB. 291 sinkMBB->splice(sinkMBB->begin(), BB, 292 llvm::next(MachineBasicBlock::iterator(MI)), 293 BB->end()); 294 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 295 296 // Next, add the true and fallthrough blocks as its successors. 297 BB->addSuccessor(copy0MBB); 298 BB->addSuccessor(sinkMBB); 299 300 // Emit the right instruction according to the type of the operands compared 301 if (isFPCmp) { 302 // Find the condiction code present in the setcc operation. 303 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm(); 304 // Get the branch opcode from the branch code. 305 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC)); 306 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 307 } else 308 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) 309 .addReg(Mips::ZERO).addMBB(sinkMBB); 310 311 // copy0MBB: 312 // %FalseValue = ... 313 // # fallthrough to sinkMBB 314 BB = copy0MBB; 315 316 // Update machine-CFG edges 317 BB->addSuccessor(sinkMBB); 318 319 // sinkMBB: 320 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 321 // ... 322 BB = sinkMBB; 323 BuildMI(*BB, BB->begin(), dl, 324 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 325 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 326 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB); 327 328 MI->eraseFromParent(); // The pseudo instruction is gone now. 329 return BB; 330 } 331 } 332} 333 334//===----------------------------------------------------------------------===// 335// Misc Lower Operation implementation 336//===----------------------------------------------------------------------===// 337 338SDValue MipsTargetLowering:: 339LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const 340{ 341 if (!Subtarget->isMips1()) 342 return Op; 343 344 MachineFunction &MF = DAG.getMachineFunction(); 345 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass); 346 347 SDValue Chain = DAG.getEntryNode(); 348 DebugLoc dl = Op.getDebugLoc(); 349 SDValue Src = Op.getOperand(0); 350 351 // Set the condition register 352 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32); 353 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg); 354 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32); 355 356 SDValue Cst = DAG.getConstant(3, MVT::i32); 357 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst); 358 Cst = DAG.getConstant(2, MVT::i32); 359 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst); 360 361 SDValue InFlag(0, 0); 362 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag); 363 364 // Emit the round instruction and bit convert to integer 365 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32, 366 Src, CondReg.getValue(1)); 367 SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc); 368 return BitCvt; 369} 370 371SDValue MipsTargetLowering:: 372LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 373{ 374 SDValue Chain = Op.getOperand(0); 375 SDValue Size = Op.getOperand(1); 376 DebugLoc dl = Op.getDebugLoc(); 377 378 // Get a reference from Mips stack pointer 379 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 380 381 // Subtract the dynamic size from the actual stack size to 382 // obtain the new stack size. 383 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 384 385 // The Sub result contains the new stack start address, so it 386 // must be placed in the stack pointer register. 387 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub); 388 389 // This node always has two return values: a new stack pointer 390 // value and a chain 391 SDValue Ops[2] = { Sub, Chain }; 392 return DAG.getMergeValues(Ops, 2, dl); 393} 394 395SDValue MipsTargetLowering:: 396LowerANDOR(SDValue Op, SelectionDAG &DAG) const 397{ 398 SDValue LHS = Op.getOperand(0); 399 SDValue RHS = Op.getOperand(1); 400 DebugLoc dl = Op.getDebugLoc(); 401 402 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp) 403 return Op; 404 405 SDValue True = DAG.getConstant(1, MVT::i32); 406 SDValue False = DAG.getConstant(0, MVT::i32); 407 408 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), 409 LHS, True, False, LHS.getOperand(2)); 410 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), 411 RHS, True, False, RHS.getOperand(2)); 412 413 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL); 414} 415 416SDValue MipsTargetLowering:: 417LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 418{ 419 // The first operand is the chain, the second is the condition, the third is 420 // the block to branch to if the condition is true. 421 SDValue Chain = Op.getOperand(0); 422 SDValue Dest = Op.getOperand(2); 423 DebugLoc dl = Op.getDebugLoc(); 424 425 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp) 426 return Op; 427 428 SDValue CondRes = Op.getOperand(1); 429 SDValue CCNode = CondRes.getOperand(2); 430 Mips::CondCode CC = 431 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 432 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 433 434 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 435 Dest, CondRes); 436} 437 438SDValue MipsTargetLowering:: 439LowerSETCC(SDValue Op, SelectionDAG &DAG) const 440{ 441 // The operands to this are the left and right operands to compare (ops #0, 442 // and #1) and the condition code to compare them with (op #2) as a 443 // CondCodeSDNode. 444 SDValue LHS = Op.getOperand(0); 445 SDValue RHS = Op.getOperand(1); 446 DebugLoc dl = Op.getDebugLoc(); 447 448 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 449 450 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS, 451 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 452} 453 454SDValue MipsTargetLowering:: 455LowerSELECT(SDValue Op, SelectionDAG &DAG) const 456{ 457 SDValue Cond = Op.getOperand(0); 458 SDValue True = Op.getOperand(1); 459 SDValue False = Op.getOperand(2); 460 DebugLoc dl = Op.getDebugLoc(); 461 462 // if the incomming condition comes from a integer compare, the select 463 // operation must be SelectCC or a conditional move if the subtarget 464 // supports it. 465 if (Cond.getOpcode() != MipsISD::FPCmp) { 466 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint()) 467 return Op; 468 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(), 469 Cond, True, False); 470 } 471 472 // if the incomming condition comes from fpcmp, the select 473 // operation must use FPSelectCC. 474 SDValue CCNode = Cond.getOperand(2); 475 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), 476 Cond, True, False, CCNode); 477} 478 479SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 480 SelectionDAG &DAG) const { 481 // FIXME there isn't actually debug info here 482 DebugLoc dl = Op.getDebugLoc(); 483 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 484 485 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 486 SDVTList VTs = DAG.getVTList(MVT::i32); 487 488 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 489 490 // %gp_rel relocation 491 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 492 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 493 MipsII::MO_GPREL); 494 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 495 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 496 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 497 } 498 // %hi/%lo relocation 499 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 500 MipsII::MO_ABS_HILO); 501 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1); 502 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); 503 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 504 505 } else { 506 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 507 MipsII::MO_GOT); 508 SDValue ResNode = DAG.getLoad(MVT::i32, dl, 509 DAG.getEntryNode(), GA, MachinePointerInfo(), 510 false, false, 0); 511 // On functions and global targets not internal linked only 512 // a load from got/GP is necessary for PIC to work. 513 if (!GV->hasLocalLinkage() || isa<Function>(GV)) 514 return ResNode; 515 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); 516 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); 517 } 518 519 llvm_unreachable("Dont know how to handle GlobalAddress"); 520 return SDValue(0,0); 521} 522 523SDValue MipsTargetLowering:: 524LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 525{ 526 llvm_unreachable("TLS not implemented for MIPS."); 527 return SDValue(); // Not reached 528} 529 530SDValue MipsTargetLowering:: 531LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 532{ 533 SDValue ResNode; 534 SDValue HiPart; 535 // FIXME there isn't actually debug info here 536 DebugLoc dl = Op.getDebugLoc(); 537 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 538 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO; 539 540 EVT PtrVT = Op.getValueType(); 541 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 542 543 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 544 545 if (!IsPIC) { 546 SDValue Ops[] = { JTI }; 547 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 548 } else // Emit Load from Global Pointer 549 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 550 MachinePointerInfo(), 551 false, false, 0); 552 553 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI); 554 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 555 556 return ResNode; 557} 558 559SDValue MipsTargetLowering:: 560LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 561{ 562 SDValue ResNode; 563 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 564 const Constant *C = N->getConstVal(); 565 // FIXME there isn't actually debug info here 566 DebugLoc dl = Op.getDebugLoc(); 567 568 // gp_rel relocation 569 // FIXME: we should reference the constant pool using small data sections, 570 // but the asm printer currently doens't support this feature without 571 // hacking it. This feature should come soon so we can uncomment the 572 // stuff below. 573 //if (IsInSmallSection(C->getType())) { 574 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 575 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 576 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 577 578 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 579 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 580 N->getOffset(), MipsII::MO_ABS_HILO); 581 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP); 582 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP); 583 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 584 } else { 585 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 586 N->getOffset(), MipsII::MO_GOT); 587 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 588 CP, MachinePointerInfo::getConstantPool(), 589 false, false, 0); 590 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP); 591 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 592 } 593 594 return ResNode; 595} 596 597SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 598 MachineFunction &MF = DAG.getMachineFunction(); 599 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 600 601 DebugLoc dl = Op.getDebugLoc(); 602 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 603 getPointerTy()); 604 605 // vastart just stores the address of the VarArgsFrameIndex slot into the 606 // memory location argument. 607 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 608 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 609 MachinePointerInfo(SV), 610 false, false, 0); 611} 612 613//===----------------------------------------------------------------------===// 614// Calling Convention Implementation 615//===----------------------------------------------------------------------===// 616 617#include "MipsGenCallingConv.inc" 618 619//===----------------------------------------------------------------------===// 620// TODO: Implement a generic logic using tblgen that can support this. 621// Mips O32 ABI rules: 622// --- 623// i32 - Passed in A0, A1, A2, A3 and stack 624// f32 - Only passed in f32 registers if no int reg has been used yet to hold 625// an argument. Otherwise, passed in A1, A2, A3 and stack. 626// f64 - Only passed in two aliased f32 registers if no int reg has been used 627// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 628// not used, it must be shadowed. If only A3 is avaiable, shadow it and 629// go to stack. 630//===----------------------------------------------------------------------===// 631 632static bool CC_MipsO32(unsigned ValNo, EVT ValVT, 633 MVT LocVT, CCValAssign::LocInfo LocInfo, 634 ISD::ArgFlagsTy ArgFlags, CCState &State) { 635 636 static const unsigned IntRegsSize=4, FloatRegsSize=2; 637 638 static const unsigned IntRegs[] = { 639 Mips::A0, Mips::A1, Mips::A2, Mips::A3 640 }; 641 static const unsigned F32Regs[] = { 642 Mips::F12, Mips::F14 643 }; 644 static const unsigned F64Regs[] = { 645 Mips::D6, Mips::D7 646 }; 647 648 unsigned Reg=0; 649 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize); 650 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0))); 651 652 // Promote i8 and i16 653 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 654 LocVT = MVT::i32; 655 if (ArgFlags.isSExt()) 656 LocInfo = CCValAssign::SExt; 657 else if (ArgFlags.isZExt()) 658 LocInfo = CCValAssign::ZExt; 659 else 660 LocInfo = CCValAssign::AExt; 661 } 662 663 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) { 664 Reg = State.AllocateReg(IntRegs, IntRegsSize); 665 IntRegUsed = true; 666 LocVT = MVT::i32; 667 } 668 669 if (ValVT.isFloatingPoint() && !IntRegUsed) { 670 if (ValVT == MVT::f32) 671 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 672 else 673 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 674 } 675 676 if (ValVT == MVT::f64 && IntRegUsed) { 677 if (UnallocIntReg != IntRegsSize) { 678 // If we hit register A3 as the first not allocated, we must 679 // mark it as allocated (shadow) and use the stack instead. 680 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3))) 681 Reg = Mips::A2; 682 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg) 683 State.AllocateReg(UnallocIntReg); 684 } 685 LocVT = MVT::i32; 686 } 687 688 if (!Reg) { 689 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 690 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes); 691 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 692 } else 693 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 694 695 return false; // CC must always match 696} 697 698static bool CC_MipsO32_VarArgs(unsigned ValNo, EVT ValVT, 699 MVT LocVT, CCValAssign::LocInfo LocInfo, 700 ISD::ArgFlagsTy ArgFlags, CCState &State) { 701 702 static const unsigned IntRegsSize=4; 703 704 static const unsigned IntRegs[] = { 705 Mips::A0, Mips::A1, Mips::A2, Mips::A3 706 }; 707 708 // Promote i8 and i16 709 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 710 LocVT = MVT::i32; 711 if (ArgFlags.isSExt()) 712 LocInfo = CCValAssign::SExt; 713 else if (ArgFlags.isZExt()) 714 LocInfo = CCValAssign::ZExt; 715 else 716 LocInfo = CCValAssign::AExt; 717 } 718 719 if (ValVT == MVT::i32 || ValVT == MVT::f32) { 720 if (unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize)) { 721 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); 722 return false; 723 } 724 unsigned Off = State.AllocateStack(4, 4); 725 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo)); 726 return false; 727 } 728 729 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize); 730 if (ValVT == MVT::f64) { 731 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A1))) { 732 // A1 can't be used anymore, because 64 bit arguments 733 // must be aligned when copied back to the caller stack 734 State.AllocateReg(IntRegs, IntRegsSize); 735 UnallocIntReg++; 736 } 737 738 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A0)) || 739 IntRegs[UnallocIntReg] == (unsigned (Mips::A2))) { 740 unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize); 741 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); 742 // Shadow the next register so it can be used 743 // later to get the other 32bit part. 744 State.AllocateReg(IntRegs, IntRegsSize); 745 return false; 746 } 747 748 // Register is shadowed to preserve alignment, and the 749 // argument goes to a stack location. 750 if (UnallocIntReg != IntRegsSize) 751 State.AllocateReg(IntRegs, IntRegsSize); 752 753 unsigned Off = State.AllocateStack(8, 8); 754 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo)); 755 return false; 756 } 757 758 return true; // CC didn't match 759} 760 761//===----------------------------------------------------------------------===// 762// Call Calling Convention Implementation 763//===----------------------------------------------------------------------===// 764 765/// LowerCall - functions arguments are copied from virtual regs to 766/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 767/// TODO: isTailCall. 768SDValue 769MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 770 CallingConv::ID CallConv, bool isVarArg, 771 bool &isTailCall, 772 const SmallVectorImpl<ISD::OutputArg> &Outs, 773 const SmallVectorImpl<SDValue> &OutVals, 774 const SmallVectorImpl<ISD::InputArg> &Ins, 775 DebugLoc dl, SelectionDAG &DAG, 776 SmallVectorImpl<SDValue> &InVals) const { 777 // MIPs target does not yet support tail call optimization. 778 isTailCall = false; 779 780 MachineFunction &MF = DAG.getMachineFunction(); 781 MachineFrameInfo *MFI = MF.getFrameInfo(); 782 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 783 784 // Analyze operands of the call, assigning locations to each operand. 785 SmallVector<CCValAssign, 16> ArgLocs; 786 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 787 *DAG.getContext()); 788 789 // To meet O32 ABI, Mips must always allocate 16 bytes on 790 // the stack (even if less than 4 are used as arguments) 791 if (Subtarget->isABI_O32()) { 792 int VTsize = EVT(MVT::i32).getSizeInBits()/8; 793 MFI->CreateFixedObject(VTsize, (VTsize*3), true); 794 CCInfo.AnalyzeCallOperands(Outs, 795 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32); 796 } else 797 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 798 799 // Get a count of how many bytes are to be pushed on the stack. 800 unsigned NumBytes = CCInfo.getNextStackOffset(); 801 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 802 803 // With EABI is it possible to have 16 args on registers. 804 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 805 SmallVector<SDValue, 8> MemOpChains; 806 807 // First/LastArgStackLoc contains the first/last 808 // "at stack" argument location. 809 int LastArgStackLoc = 0; 810 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16); 811 812 // Walk the register/memloc assignments, inserting copies/loads. 813 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 814 SDValue Arg = OutVals[i]; 815 CCValAssign &VA = ArgLocs[i]; 816 817 // Promote the value if needed. 818 switch (VA.getLocInfo()) { 819 default: llvm_unreachable("Unknown loc info!"); 820 case CCValAssign::Full: 821 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 822 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 823 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg); 824 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 825 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 826 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, 827 DAG.getConstant(0, getPointerTy())); 828 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, 829 DAG.getConstant(1, getPointerTy())); 830 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); 831 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi)); 832 continue; 833 } 834 } 835 break; 836 case CCValAssign::SExt: 837 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 838 break; 839 case CCValAssign::ZExt: 840 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 841 break; 842 case CCValAssign::AExt: 843 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 844 break; 845 } 846 847 // Arguments that can be passed on register must be kept at 848 // RegsToPass vector 849 if (VA.isRegLoc()) { 850 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 851 continue; 852 } 853 854 // Register can't get to this point... 855 assert(VA.isMemLoc()); 856 857 // Create the frame index object for this incoming parameter 858 // This guarantees that when allocating Local Area the firsts 859 // 16 bytes which are alwayes reserved won't be overwritten 860 // if O32 ABI is used. For EABI the first address is zero. 861 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset()); 862 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 863 LastArgStackLoc, true); 864 865 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy()); 866 867 // emit ISD::STORE whichs stores the 868 // parameter value to a stack Location 869 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 870 MachinePointerInfo(), 871 false, false, 0)); 872 } 873 874 // Transform all store nodes into one single node because all store 875 // nodes are independent of each other. 876 if (!MemOpChains.empty()) 877 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 878 &MemOpChains[0], MemOpChains.size()); 879 880 // Build a sequence of copy-to-reg nodes chained together with token 881 // chain and flag operands which copy the outgoing args into registers. 882 // The InFlag in necessary since all emited instructions must be 883 // stuck together. 884 SDValue InFlag; 885 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 886 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 887 RegsToPass[i].second, InFlag); 888 InFlag = Chain.getValue(1); 889 } 890 891 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 892 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 893 // node so that legalize doesn't hack it. 894 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 895 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 896 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 897 getPointerTy(), 0, OpFlag); 898 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 899 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 900 getPointerTy(), OpFlag); 901 902 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 903 // = Chain, Callee, Reg#1, Reg#2, ... 904 // 905 // Returns a chain & a flag for retval copy to use. 906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 907 SmallVector<SDValue, 8> Ops; 908 Ops.push_back(Chain); 909 Ops.push_back(Callee); 910 911 // Add argument registers to the end of the list so that they are 912 // known live into the call. 913 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 914 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 915 RegsToPass[i].second.getValueType())); 916 917 if (InFlag.getNode()) 918 Ops.push_back(InFlag); 919 920 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 921 InFlag = Chain.getValue(1); 922 923 // Create a stack location to hold GP when PIC is used. This stack 924 // location is used on function prologue to save GP and also after all 925 // emited CALL's to restore GP. 926 if (IsPIC) { 927 // Function can have an arbitrary number of calls, so 928 // hold the LastArgStackLoc with the biggest offset. 929 int FI; 930 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 931 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) { 932 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4); 933 // Create the frame index only once. SPOffset here can be anything 934 // (this will be fixed on processFunctionBeforeFrameFinalized) 935 if (MipsFI->getGPStackOffset() == -1) { 936 FI = MFI->CreateFixedObject(4, 0, true); 937 MipsFI->setGPFI(FI); 938 } 939 MipsFI->setGPStackOffset(LastArgStackLoc); 940 } 941 942 // Reload GP value. 943 FI = MipsFI->getGPFI(); 944 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 945 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, 946 MachinePointerInfo::getFixedStack(FI), 947 false, false, 0); 948 Chain = GPLoad.getValue(1); 949 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32), 950 GPLoad, SDValue(0,0)); 951 InFlag = Chain.getValue(1); 952 } 953 954 // Create the CALLSEQ_END node. 955 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 956 DAG.getIntPtrConstant(0, true), InFlag); 957 InFlag = Chain.getValue(1); 958 959 // Handle result values, copying them out of physregs into vregs that we 960 // return. 961 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 962 Ins, dl, DAG, InVals); 963} 964 965/// LowerCallResult - Lower the result values of a call into the 966/// appropriate copies out of appropriate physical registers. 967SDValue 968MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 969 CallingConv::ID CallConv, bool isVarArg, 970 const SmallVectorImpl<ISD::InputArg> &Ins, 971 DebugLoc dl, SelectionDAG &DAG, 972 SmallVectorImpl<SDValue> &InVals) const { 973 974 // Assign locations to each value returned by this call. 975 SmallVector<CCValAssign, 16> RVLocs; 976 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 977 RVLocs, *DAG.getContext()); 978 979 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 980 981 // Copy all of the result registers out of their specified physreg. 982 for (unsigned i = 0; i != RVLocs.size(); ++i) { 983 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 984 RVLocs[i].getValVT(), InFlag).getValue(1); 985 InFlag = Chain.getValue(2); 986 InVals.push_back(Chain.getValue(0)); 987 } 988 989 return Chain; 990} 991 992//===----------------------------------------------------------------------===// 993// Formal Arguments Calling Convention Implementation 994//===----------------------------------------------------------------------===// 995 996/// LowerFormalArguments - transform physical registers into virtual registers 997/// and generate load operations for arguments places on the stack. 998SDValue 999MipsTargetLowering::LowerFormalArguments(SDValue Chain, 1000 CallingConv::ID CallConv, bool isVarArg, 1001 const SmallVectorImpl<ISD::InputArg> 1002 &Ins, 1003 DebugLoc dl, SelectionDAG &DAG, 1004 SmallVectorImpl<SDValue> &InVals) 1005 const { 1006 1007 MachineFunction &MF = DAG.getMachineFunction(); 1008 MachineFrameInfo *MFI = MF.getFrameInfo(); 1009 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1010 1011 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 1012 MipsFI->setVarArgsFrameIndex(0); 1013 1014 // Used with vargs to acumulate store chains. 1015 std::vector<SDValue> OutChains; 1016 1017 // Keep track of the last register used for arguments 1018 unsigned ArgRegEnd = 0; 1019 1020 // Assign locations to all of the incoming arguments. 1021 SmallVector<CCValAssign, 16> ArgLocs; 1022 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1023 ArgLocs, *DAG.getContext()); 1024 1025 if (Subtarget->isABI_O32()) 1026 CCInfo.AnalyzeFormalArguments(Ins, 1027 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32); 1028 else 1029 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 1030 1031 SDValue StackPtr; 1032 1033 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16); 1034 1035 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1036 CCValAssign &VA = ArgLocs[i]; 1037 1038 // Arguments stored on registers 1039 if (VA.isRegLoc()) { 1040 EVT RegVT = VA.getLocVT(); 1041 ArgRegEnd = VA.getLocReg(); 1042 TargetRegisterClass *RC = 0; 1043 1044 if (RegVT == MVT::i32) 1045 RC = Mips::CPURegsRegisterClass; 1046 else if (RegVT == MVT::f32) 1047 RC = Mips::FGR32RegisterClass; 1048 else if (RegVT == MVT::f64) { 1049 if (!Subtarget->isSingleFloat()) 1050 RC = Mips::AFGR64RegisterClass; 1051 } else 1052 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 1053 1054 // Transform the arguments stored on 1055 // physical registers into virtual ones 1056 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC); 1057 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1058 1059 // If this is an 8 or 16-bit value, it has been passed promoted 1060 // to 32 bits. Insert an assert[sz]ext to capture this, then 1061 // truncate to the right size. 1062 if (VA.getLocInfo() != CCValAssign::Full) { 1063 unsigned Opcode = 0; 1064 if (VA.getLocInfo() == CCValAssign::SExt) 1065 Opcode = ISD::AssertSext; 1066 else if (VA.getLocInfo() == CCValAssign::ZExt) 1067 Opcode = ISD::AssertZext; 1068 if (Opcode) 1069 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 1070 DAG.getValueType(VA.getValVT())); 1071 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1072 } 1073 1074 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 1075 if (Subtarget->isABI_O32()) { 1076 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 1077 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); 1078 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 1079 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 1080 VA.getLocReg()+1, RC); 1081 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 1082 SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); 1083 SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2); 1084 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi); 1085 } 1086 } 1087 1088 InVals.push_back(ArgValue); 1089 } else { // VA.isRegLoc() 1090 1091 // sanity check 1092 assert(VA.isMemLoc()); 1093 1094 // The last argument is not a register anymore 1095 ArgRegEnd = 0; 1096 1097 // The stack pointer offset is relative to the caller stack frame. 1098 // Since the real stack size is unknown here, a negative SPOffset 1099 // is used so there's a way to adjust these offsets when the stack 1100 // size get known (on EliminateFrameIndex). A dummy SPOffset is 1101 // used instead of a direct negative address (which is recorded to 1102 // be used on emitPrologue) to avoid mis-calc of the first stack 1103 // offset on PEI::calculateFrameObjectOffsets. 1104 // Arguments are always 32-bit. 1105 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 1106 int FI = MFI->CreateFixedObject(ArgSize, 0, true); 1107 MipsFI->recordLoadArgsFI(FI, -(ArgSize+ 1108 (FirstStackArgLoc + VA.getLocMemOffset()))); 1109 1110 // Create load nodes to retrieve arguments from the stack 1111 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1112 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1113 MachinePointerInfo::getFixedStack(FI), 1114 false, false, 0)); 1115 } 1116 } 1117 1118 // The mips ABIs for returning structs by value requires that we copy 1119 // the sret argument into $v0 for the return. Save the argument into 1120 // a virtual register so that we can access it from the return points. 1121 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1122 unsigned Reg = MipsFI->getSRetReturnReg(); 1123 if (!Reg) { 1124 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 1125 MipsFI->setSRetReturnReg(Reg); 1126 } 1127 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1128 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1129 } 1130 1131 // To meet ABI, when VARARGS are passed on registers, the registers 1132 // must have their values written to the caller stack frame. If the last 1133 // argument was placed in the stack, there's no need to save any register. 1134 if ((isVarArg) && (Subtarget->isABI_O32() && ArgRegEnd)) { 1135 if (StackPtr.getNode() == 0) 1136 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 1137 1138 // The last register argument that must be saved is Mips::A3 1139 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 1140 unsigned StackLoc = ArgLocs.size()-1; 1141 1142 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd, ++StackLoc) { 1143 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC); 1144 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 1145 1146 int FI = MFI->CreateFixedObject(4, 0, true); 1147 MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4))); 1148 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 1149 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 1150 MachinePointerInfo(), 1151 false, false, 0)); 1152 1153 // Record the frame index of the first variable argument 1154 // which is a value necessary to VASTART. 1155 if (!MipsFI->getVarArgsFrameIndex()) 1156 MipsFI->setVarArgsFrameIndex(FI); 1157 } 1158 } 1159 1160 // All stores are grouped in one node to allow the matching between 1161 // the size of Ins and InVals. This only happens when on varg functions 1162 if (!OutChains.empty()) { 1163 OutChains.push_back(Chain); 1164 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1165 &OutChains[0], OutChains.size()); 1166 } 1167 1168 return Chain; 1169} 1170 1171//===----------------------------------------------------------------------===// 1172// Return Value Calling Convention Implementation 1173//===----------------------------------------------------------------------===// 1174 1175SDValue 1176MipsTargetLowering::LowerReturn(SDValue Chain, 1177 CallingConv::ID CallConv, bool isVarArg, 1178 const SmallVectorImpl<ISD::OutputArg> &Outs, 1179 const SmallVectorImpl<SDValue> &OutVals, 1180 DebugLoc dl, SelectionDAG &DAG) const { 1181 1182 // CCValAssign - represent the assignment of 1183 // the return value to a location 1184 SmallVector<CCValAssign, 16> RVLocs; 1185 1186 // CCState - Info about the registers and stack slot. 1187 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1188 RVLocs, *DAG.getContext()); 1189 1190 // Analize return values. 1191 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 1192 1193 // If this is the first return lowered for this function, add 1194 // the regs to the liveout set for the function. 1195 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1196 for (unsigned i = 0; i != RVLocs.size(); ++i) 1197 if (RVLocs[i].isRegLoc()) 1198 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1199 } 1200 1201 SDValue Flag; 1202 1203 // Copy the result values into the output registers. 1204 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1205 CCValAssign &VA = RVLocs[i]; 1206 assert(VA.isRegLoc() && "Can only return in registers!"); 1207 1208 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1209 OutVals[i], Flag); 1210 1211 // guarantee that all emitted copies are 1212 // stuck together, avoiding something bad 1213 Flag = Chain.getValue(1); 1214 } 1215 1216 // The mips ABIs for returning structs by value requires that we copy 1217 // the sret argument into $v0 for the return. We saved the argument into 1218 // a virtual register in the entry block, so now we copy the value out 1219 // and into $v0. 1220 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1221 MachineFunction &MF = DAG.getMachineFunction(); 1222 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1223 unsigned Reg = MipsFI->getSRetReturnReg(); 1224 1225 if (!Reg) 1226 llvm_unreachable("sret virtual register not created in the entry block"); 1227 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1228 1229 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 1230 Flag = Chain.getValue(1); 1231 } 1232 1233 // Return on Mips is always a "jr $ra" 1234 if (Flag.getNode()) 1235 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 1236 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 1237 else // Return Void 1238 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 1239 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 1240} 1241 1242//===----------------------------------------------------------------------===// 1243// Mips Inline Assembly Support 1244//===----------------------------------------------------------------------===// 1245 1246/// getConstraintType - Given a constraint letter, return the type of 1247/// constraint it is for this target. 1248MipsTargetLowering::ConstraintType MipsTargetLowering:: 1249getConstraintType(const std::string &Constraint) const 1250{ 1251 // Mips specific constrainy 1252 // GCC config/mips/constraints.md 1253 // 1254 // 'd' : An address register. Equivalent to r 1255 // unless generating MIPS16 code. 1256 // 'y' : Equivalent to r; retained for 1257 // backwards compatibility. 1258 // 'f' : Floating Point registers. 1259 if (Constraint.size() == 1) { 1260 switch (Constraint[0]) { 1261 default : break; 1262 case 'd': 1263 case 'y': 1264 case 'f': 1265 return C_RegisterClass; 1266 break; 1267 } 1268 } 1269 return TargetLowering::getConstraintType(Constraint); 1270} 1271 1272/// Examine constraint type and operand type and determine a weight value. 1273/// This object must already have been set up with the operand type 1274/// and the current alternative constraint selected. 1275TargetLowering::ConstraintWeight 1276MipsTargetLowering::getSingleConstraintMatchWeight( 1277 AsmOperandInfo &info, const char *constraint) const { 1278 ConstraintWeight weight = CW_Invalid; 1279 Value *CallOperandVal = info.CallOperandVal; 1280 // If we don't have a value, we can't do a match, 1281 // but allow it at the lowest weight. 1282 if (CallOperandVal == NULL) 1283 return CW_Default; 1284 const Type *type = CallOperandVal->getType(); 1285 // Look at the constraint type. 1286 switch (*constraint) { 1287 default: 1288 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1289 break; 1290 case 'd': 1291 case 'y': 1292 if (type->isIntegerTy()) 1293 weight = CW_Register; 1294 break; 1295 case 'f': 1296 if (type->isFloatTy()) 1297 weight = CW_Register; 1298 break; 1299 } 1300 return weight; 1301} 1302 1303/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1304/// return a list of registers that can be used to satisfy the constraint. 1305/// This should only be used for C_RegisterClass constraints. 1306std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 1307getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 1308{ 1309 if (Constraint.size() == 1) { 1310 switch (Constraint[0]) { 1311 case 'r': 1312 return std::make_pair(0U, Mips::CPURegsRegisterClass); 1313 case 'f': 1314 if (VT == MVT::f32) 1315 return std::make_pair(0U, Mips::FGR32RegisterClass); 1316 if (VT == MVT::f64) 1317 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1318 return std::make_pair(0U, Mips::AFGR64RegisterClass); 1319 } 1320 } 1321 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1322} 1323 1324/// Given a register class constraint, like 'r', if this corresponds directly 1325/// to an LLVM register class, return a register of 0 and the register class 1326/// pointer. 1327std::vector<unsigned> MipsTargetLowering:: 1328getRegClassForInlineAsmConstraint(const std::string &Constraint, 1329 EVT VT) const 1330{ 1331 if (Constraint.size() != 1) 1332 return std::vector<unsigned>(); 1333 1334 switch (Constraint[0]) { 1335 default : break; 1336 case 'r': 1337 // GCC Mips Constraint Letters 1338 case 'd': 1339 case 'y': 1340 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3, 1341 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, 1342 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, 1343 Mips::T8, 0); 1344 1345 case 'f': 1346 if (VT == MVT::f32) { 1347 if (Subtarget->isSingleFloat()) 1348 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5, 1349 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, 1350 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, 1351 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, 1352 Mips::F30, Mips::F31, 0); 1353 else 1354 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8, 1355 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26, 1356 Mips::F28, Mips::F30, 0); 1357 } 1358 1359 if (VT == MVT::f64) 1360 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1361 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4, 1362 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13, 1363 Mips::D14, Mips::D15, 0); 1364 } 1365 return std::vector<unsigned>(); 1366} 1367 1368bool 1369MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1370 // The Mips target isn't yet aware of offsets. 1371 return false; 1372} 1373 1374bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 1375 if (VT != MVT::f32 && VT != MVT::f64) 1376 return false; 1377 return Imm.isZero(); 1378} 1379