MipsISelLowering.cpp revision 1cc6333161be8bbeb516bc7c74d4400dca58b997
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "InstPrinter/MipsInstPrinter.h" 22#include "MCTargetDesc/MipsBaseInfo.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Function.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/CallingConv.h" 28#include "llvm/CodeGen/CallingConvLower.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAGISel.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37using namespace llvm; 38 39// If I is a shifted mask, set the size (Size) and the first bit of the 40// mask (Pos), and return true. 41// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 42static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 43 if (!isShiftedMask_64(I)) 44 return false; 45 46 Size = CountPopulation_64(I); 47 Pos = CountTrailingZeros_64(I); 48 return true; 49} 50 51static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 52 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 53 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 54} 55 56const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 57 switch (Opcode) { 58 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 59 case MipsISD::Hi: return "MipsISD::Hi"; 60 case MipsISD::Lo: return "MipsISD::Lo"; 61 case MipsISD::GPRel: return "MipsISD::GPRel"; 62 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 63 case MipsISD::Ret: return "MipsISD::Ret"; 64 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 65 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 66 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 67 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 68 case MipsISD::FPRound: return "MipsISD::FPRound"; 69 case MipsISD::MAdd: return "MipsISD::MAdd"; 70 case MipsISD::MAddu: return "MipsISD::MAddu"; 71 case MipsISD::MSub: return "MipsISD::MSub"; 72 case MipsISD::MSubu: return "MipsISD::MSubu"; 73 case MipsISD::DivRem: return "MipsISD::DivRem"; 74 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 75 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 76 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 77 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 78 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 79 case MipsISD::Sync: return "MipsISD::Sync"; 80 case MipsISD::Ext: return "MipsISD::Ext"; 81 case MipsISD::Ins: return "MipsISD::Ins"; 82 default: return NULL; 83 } 84} 85 86MipsTargetLowering:: 87MipsTargetLowering(MipsTargetMachine &TM) 88 : TargetLowering(TM, new MipsTargetObjectFile()), 89 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 90 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 91 IsO32(Subtarget->isABI_O32()) { 92 93 // Mips does not have i1 type, so use i32 for 94 // setcc operations results (slt, sgt, ...). 95 setBooleanContents(ZeroOrOneBooleanContent); 96 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 97 98 // Set up the register classes 99 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 100 101 if (HasMips64) 102 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); 103 104 if (!TM.Options.UseSoftFloat) { 105 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 106 107 // When dealing with single precision only, use libcalls 108 if (!Subtarget->isSingleFloat()) { 109 if (HasMips64) 110 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); 111 else 112 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 113 } 114 } 115 116 // Load extented operations for i1 types must be promoted 117 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 120 121 // MIPS doesn't have extending float->double load/store 122 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 123 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 124 125 // Used by legalize types to correctly generate the setcc result. 126 // Without this, every float setcc comes with a AND/OR with the result, 127 // we don't want this, since the fpcmp result goes to a flag register, 128 // which is used implicitly by brcond and select operations. 129 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 130 131 // Mips Custom Operations 132 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 133 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 134 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 135 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 136 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 137 setOperationAction(ISD::SELECT, MVT::f32, Custom); 138 setOperationAction(ISD::SELECT, MVT::f64, Custom); 139 setOperationAction(ISD::SELECT, MVT::i32, Custom); 140 setOperationAction(ISD::SETCC, MVT::f32, Custom); 141 setOperationAction(ISD::SETCC, MVT::f64, Custom); 142 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 143 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 144 setOperationAction(ISD::VASTART, MVT::Other, Custom); 145 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 146 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 147 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 148 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 149 150 if (!TM.Options.NoNaNsFPMath) { 151 setOperationAction(ISD::FABS, MVT::f32, Custom); 152 setOperationAction(ISD::FABS, MVT::f64, Custom); 153 } 154 155 if (HasMips64) { 156 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 157 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 158 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 159 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 160 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 161 setOperationAction(ISD::SELECT, MVT::i64, Custom); 162 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 163 } 164 165 setOperationAction(ISD::SDIV, MVT::i32, Expand); 166 setOperationAction(ISD::SREM, MVT::i32, Expand); 167 setOperationAction(ISD::UDIV, MVT::i32, Expand); 168 setOperationAction(ISD::UREM, MVT::i32, Expand); 169 setOperationAction(ISD::SDIV, MVT::i64, Expand); 170 setOperationAction(ISD::SREM, MVT::i64, Expand); 171 setOperationAction(ISD::UDIV, MVT::i64, Expand); 172 setOperationAction(ISD::UREM, MVT::i64, Expand); 173 174 // Operations not directly supported by Mips. 175 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 176 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 177 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 178 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 179 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 180 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 181 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 182 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 183 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 184 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 185 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 186 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 187 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 188 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 189 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 191 setOperationAction(ISD::ROTL, MVT::i32, Expand); 192 setOperationAction(ISD::ROTL, MVT::i64, Expand); 193 194 if (!Subtarget->hasMips32r2()) 195 setOperationAction(ISD::ROTR, MVT::i32, Expand); 196 197 if (!Subtarget->hasMips64r2()) 198 setOperationAction(ISD::ROTR, MVT::i64, Expand); 199 200 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 201 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 202 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 203 setOperationAction(ISD::FSIN, MVT::f32, Expand); 204 setOperationAction(ISD::FSIN, MVT::f64, Expand); 205 setOperationAction(ISD::FCOS, MVT::f32, Expand); 206 setOperationAction(ISD::FCOS, MVT::f64, Expand); 207 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 208 setOperationAction(ISD::FPOW, MVT::f32, Expand); 209 setOperationAction(ISD::FPOW, MVT::f64, Expand); 210 setOperationAction(ISD::FLOG, MVT::f32, Expand); 211 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 212 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 213 setOperationAction(ISD::FEXP, MVT::f32, Expand); 214 setOperationAction(ISD::FMA, MVT::f32, Expand); 215 setOperationAction(ISD::FMA, MVT::f64, Expand); 216 setOperationAction(ISD::FREM, MVT::f32, Expand); 217 setOperationAction(ISD::FREM, MVT::f64, Expand); 218 219 if (!TM.Options.NoNaNsFPMath) { 220 setOperationAction(ISD::FNEG, MVT::f32, Expand); 221 setOperationAction(ISD::FNEG, MVT::f64, Expand); 222 } 223 224 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 225 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 226 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 227 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 228 229 setOperationAction(ISD::VAARG, MVT::Other, Expand); 230 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 231 setOperationAction(ISD::VAEND, MVT::Other, Expand); 232 233 // Use the default for now 234 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 235 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 236 237 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 238 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 239 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 240 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 241 242 setInsertFencesForAtomic(true); 243 244 if (Subtarget->isSingleFloat()) 245 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 246 247 if (!Subtarget->hasSEInReg()) { 248 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 249 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 250 } 251 252 if (!Subtarget->hasBitCount()) { 253 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 254 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 255 } 256 257 if (!Subtarget->hasSwap()) { 258 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 259 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 260 } 261 262 setTargetDAGCombine(ISD::ADDE); 263 setTargetDAGCombine(ISD::SUBE); 264 setTargetDAGCombine(ISD::SDIVREM); 265 setTargetDAGCombine(ISD::UDIVREM); 266 setTargetDAGCombine(ISD::SELECT); 267 setTargetDAGCombine(ISD::AND); 268 setTargetDAGCombine(ISD::OR); 269 270 setMinFunctionAlignment(HasMips64 ? 3 : 2); 271 272 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 273 computeRegisterProperties(); 274 275 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 276 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 277} 278 279bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 280 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 281 282 switch (SVT) { 283 case MVT::i64: 284 case MVT::i32: 285 case MVT::i16: 286 return true; 287 case MVT::f32: 288 return Subtarget->hasMips32r2Or64(); 289 default: 290 return false; 291 } 292} 293 294EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 295 return MVT::i32; 296} 297 298// SelectMadd - 299// Transforms a subgraph in CurDAG if the following pattern is found: 300// (addc multLo, Lo0), (adde multHi, Hi0), 301// where, 302// multHi/Lo: product of multiplication 303// Lo0: initial value of Lo register 304// Hi0: initial value of Hi register 305// Return true if pattern matching was successful. 306static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 307 // ADDENode's second operand must be a flag output of an ADDC node in order 308 // for the matching to be successful. 309 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 310 311 if (ADDCNode->getOpcode() != ISD::ADDC) 312 return false; 313 314 SDValue MultHi = ADDENode->getOperand(0); 315 SDValue MultLo = ADDCNode->getOperand(0); 316 SDNode* MultNode = MultHi.getNode(); 317 unsigned MultOpc = MultHi.getOpcode(); 318 319 // MultHi and MultLo must be generated by the same node, 320 if (MultLo.getNode() != MultNode) 321 return false; 322 323 // and it must be a multiplication. 324 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 325 return false; 326 327 // MultLo amd MultHi must be the first and second output of MultNode 328 // respectively. 329 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 330 return false; 331 332 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 333 // of the values of MultNode, in which case MultNode will be removed in later 334 // phases. 335 // If there exist users other than ADDENode or ADDCNode, this function returns 336 // here, which will result in MultNode being mapped to a single MULT 337 // instruction node rather than a pair of MULT and MADD instructions being 338 // produced. 339 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 340 return false; 341 342 SDValue Chain = CurDAG->getEntryNode(); 343 DebugLoc dl = ADDENode->getDebugLoc(); 344 345 // create MipsMAdd(u) node 346 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 347 348 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 349 MultNode->getOperand(0),// Factor 0 350 MultNode->getOperand(1),// Factor 1 351 ADDCNode->getOperand(1),// Lo0 352 ADDENode->getOperand(1));// Hi0 353 354 // create CopyFromReg nodes 355 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 356 MAdd); 357 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 358 Mips::HI, MVT::i32, 359 CopyFromLo.getValue(2)); 360 361 // replace uses of adde and addc here 362 if (!SDValue(ADDCNode, 0).use_empty()) 363 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 364 365 if (!SDValue(ADDENode, 0).use_empty()) 366 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 367 368 return true; 369} 370 371// SelectMsub - 372// Transforms a subgraph in CurDAG if the following pattern is found: 373// (addc Lo0, multLo), (sube Hi0, multHi), 374// where, 375// multHi/Lo: product of multiplication 376// Lo0: initial value of Lo register 377// Hi0: initial value of Hi register 378// Return true if pattern matching was successful. 379static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 380 // SUBENode's second operand must be a flag output of an SUBC node in order 381 // for the matching to be successful. 382 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 383 384 if (SUBCNode->getOpcode() != ISD::SUBC) 385 return false; 386 387 SDValue MultHi = SUBENode->getOperand(1); 388 SDValue MultLo = SUBCNode->getOperand(1); 389 SDNode* MultNode = MultHi.getNode(); 390 unsigned MultOpc = MultHi.getOpcode(); 391 392 // MultHi and MultLo must be generated by the same node, 393 if (MultLo.getNode() != MultNode) 394 return false; 395 396 // and it must be a multiplication. 397 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 398 return false; 399 400 // MultLo amd MultHi must be the first and second output of MultNode 401 // respectively. 402 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 403 return false; 404 405 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 406 // of the values of MultNode, in which case MultNode will be removed in later 407 // phases. 408 // If there exist users other than SUBENode or SUBCNode, this function returns 409 // here, which will result in MultNode being mapped to a single MULT 410 // instruction node rather than a pair of MULT and MSUB instructions being 411 // produced. 412 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 413 return false; 414 415 SDValue Chain = CurDAG->getEntryNode(); 416 DebugLoc dl = SUBENode->getDebugLoc(); 417 418 // create MipsSub(u) node 419 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 420 421 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 422 MultNode->getOperand(0),// Factor 0 423 MultNode->getOperand(1),// Factor 1 424 SUBCNode->getOperand(0),// Lo0 425 SUBENode->getOperand(0));// Hi0 426 427 // create CopyFromReg nodes 428 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 429 MSub); 430 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 431 Mips::HI, MVT::i32, 432 CopyFromLo.getValue(2)); 433 434 // replace uses of sube and subc here 435 if (!SDValue(SUBCNode, 0).use_empty()) 436 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 437 438 if (!SDValue(SUBENode, 0).use_empty()) 439 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 440 441 return true; 442} 443 444static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 445 TargetLowering::DAGCombinerInfo &DCI, 446 const MipsSubtarget* Subtarget) { 447 if (DCI.isBeforeLegalize()) 448 return SDValue(); 449 450 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 451 SelectMadd(N, &DAG)) 452 return SDValue(N, 0); 453 454 return SDValue(); 455} 456 457static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 458 TargetLowering::DAGCombinerInfo &DCI, 459 const MipsSubtarget* Subtarget) { 460 if (DCI.isBeforeLegalize()) 461 return SDValue(); 462 463 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 464 SelectMsub(N, &DAG)) 465 return SDValue(N, 0); 466 467 return SDValue(); 468} 469 470static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 471 TargetLowering::DAGCombinerInfo &DCI, 472 const MipsSubtarget* Subtarget) { 473 if (DCI.isBeforeLegalizeOps()) 474 return SDValue(); 475 476 EVT Ty = N->getValueType(0); 477 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 478 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 479 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 480 MipsISD::DivRemU; 481 DebugLoc dl = N->getDebugLoc(); 482 483 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 484 N->getOperand(0), N->getOperand(1)); 485 SDValue InChain = DAG.getEntryNode(); 486 SDValue InGlue = DivRem; 487 488 // insert MFLO 489 if (N->hasAnyUseOfValue(0)) { 490 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 491 InGlue); 492 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 493 InChain = CopyFromLo.getValue(1); 494 InGlue = CopyFromLo.getValue(2); 495 } 496 497 // insert MFHI 498 if (N->hasAnyUseOfValue(1)) { 499 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 500 HI, Ty, InGlue); 501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 502 } 503 504 return SDValue(); 505} 506 507static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 508 switch (CC) { 509 default: llvm_unreachable("Unknown fp condition code!"); 510 case ISD::SETEQ: 511 case ISD::SETOEQ: return Mips::FCOND_OEQ; 512 case ISD::SETUNE: return Mips::FCOND_UNE; 513 case ISD::SETLT: 514 case ISD::SETOLT: return Mips::FCOND_OLT; 515 case ISD::SETGT: 516 case ISD::SETOGT: return Mips::FCOND_OGT; 517 case ISD::SETLE: 518 case ISD::SETOLE: return Mips::FCOND_OLE; 519 case ISD::SETGE: 520 case ISD::SETOGE: return Mips::FCOND_OGE; 521 case ISD::SETULT: return Mips::FCOND_ULT; 522 case ISD::SETULE: return Mips::FCOND_ULE; 523 case ISD::SETUGT: return Mips::FCOND_UGT; 524 case ISD::SETUGE: return Mips::FCOND_UGE; 525 case ISD::SETUO: return Mips::FCOND_UN; 526 case ISD::SETO: return Mips::FCOND_OR; 527 case ISD::SETNE: 528 case ISD::SETONE: return Mips::FCOND_ONE; 529 case ISD::SETUEQ: return Mips::FCOND_UEQ; 530 } 531} 532 533 534// Returns true if condition code has to be inverted. 535static bool InvertFPCondCode(Mips::CondCode CC) { 536 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 537 return false; 538 539 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 540 "Illegal Condition Code"); 541 542 return true; 543} 544 545// Creates and returns an FPCmp node from a setcc node. 546// Returns Op if setcc is not a floating point comparison. 547static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 548 // must be a SETCC node 549 if (Op.getOpcode() != ISD::SETCC) 550 return Op; 551 552 SDValue LHS = Op.getOperand(0); 553 554 if (!LHS.getValueType().isFloatingPoint()) 555 return Op; 556 557 SDValue RHS = Op.getOperand(1); 558 DebugLoc dl = Op.getDebugLoc(); 559 560 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 561 // node if necessary. 562 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 563 564 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 565 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 566} 567 568// Creates and returns a CMovFPT/F node. 569static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 570 SDValue False, DebugLoc DL) { 571 bool invert = InvertFPCondCode((Mips::CondCode) 572 cast<ConstantSDNode>(Cond.getOperand(2)) 573 ->getSExtValue()); 574 575 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 576 True.getValueType(), True, False, Cond); 577} 578 579static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG& DAG, 580 TargetLowering::DAGCombinerInfo &DCI, 581 const MipsSubtarget* Subtarget) { 582 if (DCI.isBeforeLegalizeOps()) 583 return SDValue(); 584 585 SDValue SetCC = N->getOperand(0); 586 587 if ((SetCC.getOpcode() != ISD::SETCC) || 588 !SetCC.getOperand(0).getValueType().isInteger()) 589 return SDValue(); 590 591 SDValue False = N->getOperand(2); 592 EVT FalseTy = False.getValueType(); 593 594 if (!FalseTy.isInteger()) 595 return SDValue(); 596 597 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 598 599 if (!CN || CN->getZExtValue()) 600 return SDValue(); 601 602 const DebugLoc DL = N->getDebugLoc(); 603 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 604 SDValue True = N->getOperand(1); 605 606 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 607 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 608 609 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 610} 611 612static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 613 TargetLowering::DAGCombinerInfo &DCI, 614 const MipsSubtarget* Subtarget) { 615 // Pattern match EXT. 616 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 617 // => ext $dst, $src, size, pos 618 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 619 return SDValue(); 620 621 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 622 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 623 624 // Op's first operand must be a shift right. 625 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 626 return SDValue(); 627 628 // The second operand of the shift must be an immediate. 629 ConstantSDNode *CN; 630 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 631 return SDValue(); 632 633 uint64_t Pos = CN->getZExtValue(); 634 uint64_t SMPos, SMSize; 635 636 // Op's second operand must be a shifted mask. 637 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 638 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 639 return SDValue(); 640 641 // Return if the shifted mask does not start at bit 0 or the sum of its size 642 // and Pos exceeds the word's size. 643 EVT ValTy = N->getValueType(0); 644 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 645 return SDValue(); 646 647 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 648 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 649 DAG.getConstant(SMSize, MVT::i32)); 650} 651 652static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 653 TargetLowering::DAGCombinerInfo &DCI, 654 const MipsSubtarget* Subtarget) { 655 // Pattern match INS. 656 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 657 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 658 // => ins $dst, $src, size, pos, $src1 659 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 660 return SDValue(); 661 662 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 663 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 664 ConstantSDNode *CN; 665 666 // See if Op's first operand matches (and $src1 , mask0). 667 if (And0.getOpcode() != ISD::AND) 668 return SDValue(); 669 670 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 671 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 672 return SDValue(); 673 674 // See if Op's second operand matches (and (shl $src, pos), mask1). 675 if (And1.getOpcode() != ISD::AND) 676 return SDValue(); 677 678 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 679 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 680 return SDValue(); 681 682 // The shift masks must have the same position and size. 683 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 684 return SDValue(); 685 686 SDValue Shl = And1.getOperand(0); 687 if (Shl.getOpcode() != ISD::SHL) 688 return SDValue(); 689 690 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 691 return SDValue(); 692 693 unsigned Shamt = CN->getZExtValue(); 694 695 // Return if the shift amount and the first bit position of mask are not the 696 // same. 697 EVT ValTy = N->getValueType(0); 698 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 699 return SDValue(); 700 701 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 702 DAG.getConstant(SMPos0, MVT::i32), 703 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 704} 705 706SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 707 const { 708 SelectionDAG &DAG = DCI.DAG; 709 unsigned opc = N->getOpcode(); 710 711 switch (opc) { 712 default: break; 713 case ISD::ADDE: 714 return PerformADDECombine(N, DAG, DCI, Subtarget); 715 case ISD::SUBE: 716 return PerformSUBECombine(N, DAG, DCI, Subtarget); 717 case ISD::SDIVREM: 718 case ISD::UDIVREM: 719 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 720 case ISD::SELECT: 721 return PerformSELECTCombine(N, DAG, DCI, Subtarget); 722 case ISD::AND: 723 return PerformANDCombine(N, DAG, DCI, Subtarget); 724 case ISD::OR: 725 return PerformORCombine(N, DAG, DCI, Subtarget); 726 } 727 728 return SDValue(); 729} 730 731SDValue MipsTargetLowering:: 732LowerOperation(SDValue Op, SelectionDAG &DAG) const 733{ 734 switch (Op.getOpcode()) 735 { 736 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 737 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 738 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 739 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 740 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 741 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 742 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 743 case ISD::SELECT: return LowerSELECT(Op, DAG); 744 case ISD::SETCC: return LowerSETCC(Op, DAG); 745 case ISD::VASTART: return LowerVASTART(Op, DAG); 746 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 747 case ISD::FABS: return LowerFABS(Op, DAG); 748 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 749 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 750 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 751 } 752 return SDValue(); 753} 754 755//===----------------------------------------------------------------------===// 756// Lower helper functions 757//===----------------------------------------------------------------------===// 758 759// AddLiveIn - This helper function adds the specified physical register to the 760// MachineFunction as a live in value. It also creates a corresponding 761// virtual register for it. 762static unsigned 763AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 764{ 765 assert(RC->contains(PReg) && "Not the correct regclass!"); 766 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 767 MF.getRegInfo().addLiveIn(PReg, VReg); 768 return VReg; 769} 770 771// Get fp branch code (not opcode) from condition code. 772static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 773 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 774 return Mips::BRANCH_T; 775 776 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 777 "Invalid CondCode."); 778 779 return Mips::BRANCH_F; 780} 781 782/* 783static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 784 DebugLoc dl, 785 const MipsSubtarget* Subtarget, 786 const TargetInstrInfo *TII, 787 bool isFPCmp, unsigned Opc) { 788 // There is no need to expand CMov instructions if target has 789 // conditional moves. 790 if (Subtarget->hasCondMov()) 791 return BB; 792 793 // To "insert" a SELECT_CC instruction, we actually have to insert the 794 // diamond control-flow pattern. The incoming instruction knows the 795 // destination vreg to set, the condition code register to branch on, the 796 // true/false values to select between, and a branch opcode to use. 797 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 798 MachineFunction::iterator It = BB; 799 ++It; 800 801 // thisMBB: 802 // ... 803 // TrueVal = ... 804 // setcc r1, r2, r3 805 // bNE r1, r0, copy1MBB 806 // fallthrough --> copy0MBB 807 MachineBasicBlock *thisMBB = BB; 808 MachineFunction *F = BB->getParent(); 809 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 810 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 811 F->insert(It, copy0MBB); 812 F->insert(It, sinkMBB); 813 814 // Transfer the remainder of BB and its successor edges to sinkMBB. 815 sinkMBB->splice(sinkMBB->begin(), BB, 816 llvm::next(MachineBasicBlock::iterator(MI)), 817 BB->end()); 818 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 819 820 // Next, add the true and fallthrough blocks as its successors. 821 BB->addSuccessor(copy0MBB); 822 BB->addSuccessor(sinkMBB); 823 824 // Emit the right instruction according to the type of the operands compared 825 if (isFPCmp) 826 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 827 else 828 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 829 .addReg(Mips::ZERO).addMBB(sinkMBB); 830 831 // copy0MBB: 832 // %FalseValue = ... 833 // # fallthrough to sinkMBB 834 BB = copy0MBB; 835 836 // Update machine-CFG edges 837 BB->addSuccessor(sinkMBB); 838 839 // sinkMBB: 840 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 841 // ... 842 BB = sinkMBB; 843 844 if (isFPCmp) 845 BuildMI(*BB, BB->begin(), dl, 846 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 847 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 848 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 849 else 850 BuildMI(*BB, BB->begin(), dl, 851 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 852 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 853 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 854 855 MI->eraseFromParent(); // The pseudo instruction is gone now. 856 return BB; 857} 858*/ 859MachineBasicBlock * 860MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 861 MachineBasicBlock *BB) const { 862 switch (MI->getOpcode()) { 863 default: llvm_unreachable("Unexpected instr type to insert"); 864 case Mips::ATOMIC_LOAD_ADD_I8: 865 case Mips::ATOMIC_LOAD_ADD_I8_P8: 866 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 867 case Mips::ATOMIC_LOAD_ADD_I16: 868 case Mips::ATOMIC_LOAD_ADD_I16_P8: 869 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 870 case Mips::ATOMIC_LOAD_ADD_I32: 871 case Mips::ATOMIC_LOAD_ADD_I32_P8: 872 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 873 case Mips::ATOMIC_LOAD_ADD_I64: 874 case Mips::ATOMIC_LOAD_ADD_I64_P8: 875 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 876 877 case Mips::ATOMIC_LOAD_AND_I8: 878 case Mips::ATOMIC_LOAD_AND_I8_P8: 879 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 880 case Mips::ATOMIC_LOAD_AND_I16: 881 case Mips::ATOMIC_LOAD_AND_I16_P8: 882 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 883 case Mips::ATOMIC_LOAD_AND_I32: 884 case Mips::ATOMIC_LOAD_AND_I32_P8: 885 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 886 case Mips::ATOMIC_LOAD_AND_I64: 887 case Mips::ATOMIC_LOAD_AND_I64_P8: 888 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 889 890 case Mips::ATOMIC_LOAD_OR_I8: 891 case Mips::ATOMIC_LOAD_OR_I8_P8: 892 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 893 case Mips::ATOMIC_LOAD_OR_I16: 894 case Mips::ATOMIC_LOAD_OR_I16_P8: 895 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 896 case Mips::ATOMIC_LOAD_OR_I32: 897 case Mips::ATOMIC_LOAD_OR_I32_P8: 898 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 899 case Mips::ATOMIC_LOAD_OR_I64: 900 case Mips::ATOMIC_LOAD_OR_I64_P8: 901 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 902 903 case Mips::ATOMIC_LOAD_XOR_I8: 904 case Mips::ATOMIC_LOAD_XOR_I8_P8: 905 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 906 case Mips::ATOMIC_LOAD_XOR_I16: 907 case Mips::ATOMIC_LOAD_XOR_I16_P8: 908 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 909 case Mips::ATOMIC_LOAD_XOR_I32: 910 case Mips::ATOMIC_LOAD_XOR_I32_P8: 911 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 912 case Mips::ATOMIC_LOAD_XOR_I64: 913 case Mips::ATOMIC_LOAD_XOR_I64_P8: 914 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 915 916 case Mips::ATOMIC_LOAD_NAND_I8: 917 case Mips::ATOMIC_LOAD_NAND_I8_P8: 918 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 919 case Mips::ATOMIC_LOAD_NAND_I16: 920 case Mips::ATOMIC_LOAD_NAND_I16_P8: 921 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 922 case Mips::ATOMIC_LOAD_NAND_I32: 923 case Mips::ATOMIC_LOAD_NAND_I32_P8: 924 return EmitAtomicBinary(MI, BB, 4, 0, true); 925 case Mips::ATOMIC_LOAD_NAND_I64: 926 case Mips::ATOMIC_LOAD_NAND_I64_P8: 927 return EmitAtomicBinary(MI, BB, 8, 0, true); 928 929 case Mips::ATOMIC_LOAD_SUB_I8: 930 case Mips::ATOMIC_LOAD_SUB_I8_P8: 931 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 932 case Mips::ATOMIC_LOAD_SUB_I16: 933 case Mips::ATOMIC_LOAD_SUB_I16_P8: 934 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 935 case Mips::ATOMIC_LOAD_SUB_I32: 936 case Mips::ATOMIC_LOAD_SUB_I32_P8: 937 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 938 case Mips::ATOMIC_LOAD_SUB_I64: 939 case Mips::ATOMIC_LOAD_SUB_I64_P8: 940 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 941 942 case Mips::ATOMIC_SWAP_I8: 943 case Mips::ATOMIC_SWAP_I8_P8: 944 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 945 case Mips::ATOMIC_SWAP_I16: 946 case Mips::ATOMIC_SWAP_I16_P8: 947 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 948 case Mips::ATOMIC_SWAP_I32: 949 case Mips::ATOMIC_SWAP_I32_P8: 950 return EmitAtomicBinary(MI, BB, 4, 0); 951 case Mips::ATOMIC_SWAP_I64: 952 case Mips::ATOMIC_SWAP_I64_P8: 953 return EmitAtomicBinary(MI, BB, 8, 0); 954 955 case Mips::ATOMIC_CMP_SWAP_I8: 956 case Mips::ATOMIC_CMP_SWAP_I8_P8: 957 return EmitAtomicCmpSwapPartword(MI, BB, 1); 958 case Mips::ATOMIC_CMP_SWAP_I16: 959 case Mips::ATOMIC_CMP_SWAP_I16_P8: 960 return EmitAtomicCmpSwapPartword(MI, BB, 2); 961 case Mips::ATOMIC_CMP_SWAP_I32: 962 case Mips::ATOMIC_CMP_SWAP_I32_P8: 963 return EmitAtomicCmpSwap(MI, BB, 4); 964 case Mips::ATOMIC_CMP_SWAP_I64: 965 case Mips::ATOMIC_CMP_SWAP_I64_P8: 966 return EmitAtomicCmpSwap(MI, BB, 8); 967 } 968} 969 970// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 971// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 972MachineBasicBlock * 973MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 974 unsigned Size, unsigned BinOpcode, 975 bool Nand) const { 976 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 977 978 MachineFunction *MF = BB->getParent(); 979 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 980 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 981 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 982 DebugLoc dl = MI->getDebugLoc(); 983 unsigned LL, SC, AND, NOR, ZERO, BEQ; 984 985 if (Size == 4) { 986 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 987 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 988 AND = Mips::AND; 989 NOR = Mips::NOR; 990 ZERO = Mips::ZERO; 991 BEQ = Mips::BEQ; 992 } 993 else { 994 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 995 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 996 AND = Mips::AND64; 997 NOR = Mips::NOR64; 998 ZERO = Mips::ZERO_64; 999 BEQ = Mips::BEQ64; 1000 } 1001 1002 unsigned OldVal = MI->getOperand(0).getReg(); 1003 unsigned Ptr = MI->getOperand(1).getReg(); 1004 unsigned Incr = MI->getOperand(2).getReg(); 1005 1006 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1007 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1008 unsigned Success = RegInfo.createVirtualRegister(RC); 1009 1010 // insert new blocks after the current block 1011 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1012 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1013 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1014 MachineFunction::iterator It = BB; 1015 ++It; 1016 MF->insert(It, loopMBB); 1017 MF->insert(It, exitMBB); 1018 1019 // Transfer the remainder of BB and its successor edges to exitMBB. 1020 exitMBB->splice(exitMBB->begin(), BB, 1021 llvm::next(MachineBasicBlock::iterator(MI)), 1022 BB->end()); 1023 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1024 1025 // thisMBB: 1026 // ... 1027 // fallthrough --> loopMBB 1028 BB->addSuccessor(loopMBB); 1029 loopMBB->addSuccessor(loopMBB); 1030 loopMBB->addSuccessor(exitMBB); 1031 1032 // loopMBB: 1033 // ll oldval, 0(ptr) 1034 // <binop> storeval, oldval, incr 1035 // sc success, storeval, 0(ptr) 1036 // beq success, $0, loopMBB 1037 BB = loopMBB; 1038 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1039 if (Nand) { 1040 // and andres, oldval, incr 1041 // nor storeval, $0, andres 1042 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1043 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1044 } else if (BinOpcode) { 1045 // <binop> storeval, oldval, incr 1046 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1047 } else { 1048 StoreVal = Incr; 1049 } 1050 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1051 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1052 1053 MI->eraseFromParent(); // The instruction is gone now. 1054 1055 return exitMBB; 1056} 1057 1058MachineBasicBlock * 1059MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1060 MachineBasicBlock *BB, 1061 unsigned Size, unsigned BinOpcode, 1062 bool Nand) const { 1063 assert((Size == 1 || Size == 2) && 1064 "Unsupported size for EmitAtomicBinaryPartial."); 1065 1066 MachineFunction *MF = BB->getParent(); 1067 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1068 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1069 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1070 DebugLoc dl = MI->getDebugLoc(); 1071 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1072 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1073 1074 unsigned Dest = MI->getOperand(0).getReg(); 1075 unsigned Ptr = MI->getOperand(1).getReg(); 1076 unsigned Incr = MI->getOperand(2).getReg(); 1077 1078 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1079 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1080 unsigned Mask = RegInfo.createVirtualRegister(RC); 1081 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1082 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1083 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1084 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1085 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1086 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1087 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1088 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1089 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1090 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1091 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1092 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1093 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1094 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1095 unsigned Success = RegInfo.createVirtualRegister(RC); 1096 1097 // insert new blocks after the current block 1098 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1099 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1100 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1101 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1102 MachineFunction::iterator It = BB; 1103 ++It; 1104 MF->insert(It, loopMBB); 1105 MF->insert(It, sinkMBB); 1106 MF->insert(It, exitMBB); 1107 1108 // Transfer the remainder of BB and its successor edges to exitMBB. 1109 exitMBB->splice(exitMBB->begin(), BB, 1110 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1111 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1112 1113 BB->addSuccessor(loopMBB); 1114 loopMBB->addSuccessor(loopMBB); 1115 loopMBB->addSuccessor(sinkMBB); 1116 sinkMBB->addSuccessor(exitMBB); 1117 1118 // thisMBB: 1119 // addiu masklsb2,$0,-4 # 0xfffffffc 1120 // and alignedaddr,ptr,masklsb2 1121 // andi ptrlsb2,ptr,3 1122 // sll shiftamt,ptrlsb2,3 1123 // ori maskupper,$0,255 # 0xff 1124 // sll mask,maskupper,shiftamt 1125 // nor mask2,$0,mask 1126 // sll incr2,incr,shiftamt 1127 1128 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1129 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1130 .addReg(Mips::ZERO).addImm(-4); 1131 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1132 .addReg(Ptr).addReg(MaskLSB2); 1133 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1134 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1135 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1136 .addReg(Mips::ZERO).addImm(MaskImm); 1137 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1138 .addReg(ShiftAmt).addReg(MaskUpper); 1139 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1140 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1141 1142 // atomic.load.binop 1143 // loopMBB: 1144 // ll oldval,0(alignedaddr) 1145 // binop binopres,oldval,incr2 1146 // and newval,binopres,mask 1147 // and maskedoldval0,oldval,mask2 1148 // or storeval,maskedoldval0,newval 1149 // sc success,storeval,0(alignedaddr) 1150 // beq success,$0,loopMBB 1151 1152 // atomic.swap 1153 // loopMBB: 1154 // ll oldval,0(alignedaddr) 1155 // and newval,incr2,mask 1156 // and maskedoldval0,oldval,mask2 1157 // or storeval,maskedoldval0,newval 1158 // sc success,storeval,0(alignedaddr) 1159 // beq success,$0,loopMBB 1160 1161 BB = loopMBB; 1162 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1163 if (Nand) { 1164 // and andres, oldval, incr2 1165 // nor binopres, $0, andres 1166 // and newval, binopres, mask 1167 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1168 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1169 .addReg(Mips::ZERO).addReg(AndRes); 1170 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1171 } else if (BinOpcode) { 1172 // <binop> binopres, oldval, incr2 1173 // and newval, binopres, mask 1174 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1175 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1176 } else {// atomic.swap 1177 // and newval, incr2, mask 1178 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1179 } 1180 1181 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1182 .addReg(OldVal).addReg(Mask2); 1183 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1184 .addReg(MaskedOldVal0).addReg(NewVal); 1185 BuildMI(BB, dl, TII->get(SC), Success) 1186 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1187 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1188 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1189 1190 // sinkMBB: 1191 // and maskedoldval1,oldval,mask 1192 // srl srlres,maskedoldval1,shiftamt 1193 // sll sllres,srlres,24 1194 // sra dest,sllres,24 1195 BB = sinkMBB; 1196 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1197 1198 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1199 .addReg(OldVal).addReg(Mask); 1200 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1201 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1202 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1203 .addReg(SrlRes).addImm(ShiftImm); 1204 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1205 .addReg(SllRes).addImm(ShiftImm); 1206 1207 MI->eraseFromParent(); // The instruction is gone now. 1208 1209 return exitMBB; 1210} 1211 1212MachineBasicBlock * 1213MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1214 MachineBasicBlock *BB, 1215 unsigned Size) const { 1216 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1217 1218 MachineFunction *MF = BB->getParent(); 1219 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1220 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1221 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1222 DebugLoc dl = MI->getDebugLoc(); 1223 unsigned LL, SC, ZERO, BNE, BEQ; 1224 1225 if (Size == 4) { 1226 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1227 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1228 ZERO = Mips::ZERO; 1229 BNE = Mips::BNE; 1230 BEQ = Mips::BEQ; 1231 } 1232 else { 1233 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1234 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1235 ZERO = Mips::ZERO_64; 1236 BNE = Mips::BNE64; 1237 BEQ = Mips::BEQ64; 1238 } 1239 1240 unsigned Dest = MI->getOperand(0).getReg(); 1241 unsigned Ptr = MI->getOperand(1).getReg(); 1242 unsigned OldVal = MI->getOperand(2).getReg(); 1243 unsigned NewVal = MI->getOperand(3).getReg(); 1244 1245 unsigned Success = RegInfo.createVirtualRegister(RC); 1246 1247 // insert new blocks after the current block 1248 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1249 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1250 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1251 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1252 MachineFunction::iterator It = BB; 1253 ++It; 1254 MF->insert(It, loop1MBB); 1255 MF->insert(It, loop2MBB); 1256 MF->insert(It, exitMBB); 1257 1258 // Transfer the remainder of BB and its successor edges to exitMBB. 1259 exitMBB->splice(exitMBB->begin(), BB, 1260 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1261 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1262 1263 // thisMBB: 1264 // ... 1265 // fallthrough --> loop1MBB 1266 BB->addSuccessor(loop1MBB); 1267 loop1MBB->addSuccessor(exitMBB); 1268 loop1MBB->addSuccessor(loop2MBB); 1269 loop2MBB->addSuccessor(loop1MBB); 1270 loop2MBB->addSuccessor(exitMBB); 1271 1272 // loop1MBB: 1273 // ll dest, 0(ptr) 1274 // bne dest, oldval, exitMBB 1275 BB = loop1MBB; 1276 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1277 BuildMI(BB, dl, TII->get(BNE)) 1278 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1279 1280 // loop2MBB: 1281 // sc success, newval, 0(ptr) 1282 // beq success, $0, loop1MBB 1283 BB = loop2MBB; 1284 BuildMI(BB, dl, TII->get(SC), Success) 1285 .addReg(NewVal).addReg(Ptr).addImm(0); 1286 BuildMI(BB, dl, TII->get(BEQ)) 1287 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1288 1289 MI->eraseFromParent(); // The instruction is gone now. 1290 1291 return exitMBB; 1292} 1293 1294MachineBasicBlock * 1295MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1296 MachineBasicBlock *BB, 1297 unsigned Size) const { 1298 assert((Size == 1 || Size == 2) && 1299 "Unsupported size for EmitAtomicCmpSwapPartial."); 1300 1301 MachineFunction *MF = BB->getParent(); 1302 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1303 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1304 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1305 DebugLoc dl = MI->getDebugLoc(); 1306 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1307 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1308 1309 unsigned Dest = MI->getOperand(0).getReg(); 1310 unsigned Ptr = MI->getOperand(1).getReg(); 1311 unsigned CmpVal = MI->getOperand(2).getReg(); 1312 unsigned NewVal = MI->getOperand(3).getReg(); 1313 1314 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1315 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1316 unsigned Mask = RegInfo.createVirtualRegister(RC); 1317 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1318 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1319 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1320 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1321 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1322 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1323 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1324 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1325 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1326 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1327 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1328 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1329 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1330 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1331 unsigned Success = RegInfo.createVirtualRegister(RC); 1332 1333 // insert new blocks after the current block 1334 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1335 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1336 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1337 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1338 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1339 MachineFunction::iterator It = BB; 1340 ++It; 1341 MF->insert(It, loop1MBB); 1342 MF->insert(It, loop2MBB); 1343 MF->insert(It, sinkMBB); 1344 MF->insert(It, exitMBB); 1345 1346 // Transfer the remainder of BB and its successor edges to exitMBB. 1347 exitMBB->splice(exitMBB->begin(), BB, 1348 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1349 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1350 1351 BB->addSuccessor(loop1MBB); 1352 loop1MBB->addSuccessor(sinkMBB); 1353 loop1MBB->addSuccessor(loop2MBB); 1354 loop2MBB->addSuccessor(loop1MBB); 1355 loop2MBB->addSuccessor(sinkMBB); 1356 sinkMBB->addSuccessor(exitMBB); 1357 1358 // FIXME: computation of newval2 can be moved to loop2MBB. 1359 // thisMBB: 1360 // addiu masklsb2,$0,-4 # 0xfffffffc 1361 // and alignedaddr,ptr,masklsb2 1362 // andi ptrlsb2,ptr,3 1363 // sll shiftamt,ptrlsb2,3 1364 // ori maskupper,$0,255 # 0xff 1365 // sll mask,maskupper,shiftamt 1366 // nor mask2,$0,mask 1367 // andi maskedcmpval,cmpval,255 1368 // sll shiftedcmpval,maskedcmpval,shiftamt 1369 // andi maskednewval,newval,255 1370 // sll shiftednewval,maskednewval,shiftamt 1371 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1372 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1373 .addReg(Mips::ZERO).addImm(-4); 1374 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1375 .addReg(Ptr).addReg(MaskLSB2); 1376 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1377 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1378 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1379 .addReg(Mips::ZERO).addImm(MaskImm); 1380 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1381 .addReg(ShiftAmt).addReg(MaskUpper); 1382 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1383 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1384 .addReg(CmpVal).addImm(MaskImm); 1385 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1386 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1387 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1388 .addReg(NewVal).addImm(MaskImm); 1389 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1390 .addReg(ShiftAmt).addReg(MaskedNewVal); 1391 1392 // loop1MBB: 1393 // ll oldval,0(alginedaddr) 1394 // and maskedoldval0,oldval,mask 1395 // bne maskedoldval0,shiftedcmpval,sinkMBB 1396 BB = loop1MBB; 1397 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1398 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1399 .addReg(OldVal).addReg(Mask); 1400 BuildMI(BB, dl, TII->get(Mips::BNE)) 1401 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1402 1403 // loop2MBB: 1404 // and maskedoldval1,oldval,mask2 1405 // or storeval,maskedoldval1,shiftednewval 1406 // sc success,storeval,0(alignedaddr) 1407 // beq success,$0,loop1MBB 1408 BB = loop2MBB; 1409 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1410 .addReg(OldVal).addReg(Mask2); 1411 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1412 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1413 BuildMI(BB, dl, TII->get(SC), Success) 1414 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1415 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1416 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1417 1418 // sinkMBB: 1419 // srl srlres,maskedoldval0,shiftamt 1420 // sll sllres,srlres,24 1421 // sra dest,sllres,24 1422 BB = sinkMBB; 1423 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1424 1425 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1426 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1427 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1428 .addReg(SrlRes).addImm(ShiftImm); 1429 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1430 .addReg(SllRes).addImm(ShiftImm); 1431 1432 MI->eraseFromParent(); // The instruction is gone now. 1433 1434 return exitMBB; 1435} 1436 1437//===----------------------------------------------------------------------===// 1438// Misc Lower Operation implementation 1439//===----------------------------------------------------------------------===// 1440SDValue MipsTargetLowering:: 1441LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1442{ 1443 MachineFunction &MF = DAG.getMachineFunction(); 1444 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1445 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP; 1446 1447 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1448 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1449 "Cannot lower if the alignment of the allocated space is larger than \ 1450 that of the stack."); 1451 1452 SDValue Chain = Op.getOperand(0); 1453 SDValue Size = Op.getOperand(1); 1454 DebugLoc dl = Op.getDebugLoc(); 1455 1456 // Get a reference from Mips stack pointer 1457 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy()); 1458 1459 // Subtract the dynamic size from the actual stack size to 1460 // obtain the new stack size. 1461 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size); 1462 1463 // The Sub result contains the new stack start address, so it 1464 // must be placed in the stack pointer register. 1465 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue()); 1466 1467 // This node always has two return values: a new stack pointer 1468 // value and a chain 1469 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other); 1470 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1471 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1472 1473 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1474} 1475 1476SDValue MipsTargetLowering:: 1477LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1478{ 1479 // The first operand is the chain, the second is the condition, the third is 1480 // the block to branch to if the condition is true. 1481 SDValue Chain = Op.getOperand(0); 1482 SDValue Dest = Op.getOperand(2); 1483 DebugLoc dl = Op.getDebugLoc(); 1484 1485 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1486 1487 // Return if flag is not set by a floating point comparison. 1488 if (CondRes.getOpcode() != MipsISD::FPCmp) 1489 return Op; 1490 1491 SDValue CCNode = CondRes.getOperand(2); 1492 Mips::CondCode CC = 1493 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1494 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1495 1496 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1497 Dest, CondRes); 1498} 1499 1500SDValue MipsTargetLowering:: 1501LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1502{ 1503 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1504 1505 // Return if flag is not set by a floating point comparison. 1506 if (Cond.getOpcode() != MipsISD::FPCmp) 1507 return Op; 1508 1509 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1510 Op.getDebugLoc()); 1511} 1512 1513SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1514 SDValue Cond = CreateFPCmp(DAG, Op); 1515 1516 assert(Cond.getOpcode() == MipsISD::FPCmp && 1517 "Floating point operand expected."); 1518 1519 SDValue True = DAG.getConstant(1, MVT::i32); 1520 SDValue False = DAG.getConstant(0, MVT::i32); 1521 1522 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc()); 1523} 1524 1525SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1526 SelectionDAG &DAG) const { 1527 // FIXME there isn't actually debug info here 1528 DebugLoc dl = Op.getDebugLoc(); 1529 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1530 1531 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1532 SDVTList VTs = DAG.getVTList(MVT::i32); 1533 1534 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1535 1536 // %gp_rel relocation 1537 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1538 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1539 MipsII::MO_GPREL); 1540 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1541 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1542 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1543 } 1544 // %hi/%lo relocation 1545 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1546 MipsII::MO_ABS_HI); 1547 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1548 MipsII::MO_ABS_LO); 1549 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1550 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1551 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1552 } 1553 1554 EVT ValTy = Op.getValueType(); 1555 bool HasGotOfst = (GV->hasInternalLinkage() || 1556 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1557 unsigned GotFlag = HasMips64 ? 1558 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1559 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); 1560 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1561 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA); 1562 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, 1563 MachinePointerInfo(), false, false, false, 0); 1564 // On functions and global targets not internal linked only 1565 // a load from got/GP is necessary for PIC to work. 1566 if (!HasGotOfst) 1567 return ResNode; 1568 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1569 HasMips64 ? MipsII::MO_GOT_OFST : 1570 MipsII::MO_ABS_LO); 1571 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1572 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1573} 1574 1575SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1576 SelectionDAG &DAG) const { 1577 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1578 // FIXME there isn't actually debug info here 1579 DebugLoc dl = Op.getDebugLoc(); 1580 1581 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1582 // %hi/%lo relocation 1583 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI); 1584 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO); 1585 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1586 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1587 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1588 } 1589 1590 EVT ValTy = Op.getValueType(); 1591 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1592 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1593 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag); 1594 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, 1595 GetGlobalReg(DAG, ValTy), BAGOTOffset); 1596 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag); 1597 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset, 1598 MachinePointerInfo(), false, false, false, 0); 1599 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); 1600 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1601} 1602 1603SDValue MipsTargetLowering:: 1604LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1605{ 1606 // If the relocation model is PIC, use the General Dynamic TLS Model or 1607 // Local Dynamic TLS model, otherwise use the Initial Exec or 1608 // Local Exec TLS Model. 1609 1610 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1611 DebugLoc dl = GA->getDebugLoc(); 1612 const GlobalValue *GV = GA->getGlobal(); 1613 EVT PtrVT = getPointerTy(); 1614 1615 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1616 // General Dynamic TLS Model 1617 bool LocalDynamic = GV->hasInternalLinkage(); 1618 unsigned Flag = LocalDynamic ? MipsII::MO_TLSLDM :MipsII::MO_TLSGD; 1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1620 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1621 GetGlobalReg(DAG, PtrVT), TGA); 1622 unsigned PtrSize = PtrVT.getSizeInBits(); 1623 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1624 1625 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1626 1627 ArgListTy Args; 1628 ArgListEntry Entry; 1629 Entry.Node = Argument; 1630 Entry.Ty = PtrTy; 1631 Args.push_back(Entry); 1632 1633 std::pair<SDValue, SDValue> CallResult = 1634 LowerCallTo(DAG.getEntryNode(), PtrTy, 1635 false, false, false, false, 0, CallingConv::C, 1636 /*isTailCall=*/false, /*doesNotRet=*/false, 1637 /*isReturnValueUsed=*/true, 1638 TlsGetAddr, Args, DAG, dl); 1639 1640 SDValue Ret = CallResult.first; 1641 1642 if (!LocalDynamic) 1643 return Ret; 1644 1645 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1646 MipsII::MO_DTPREL_HI); 1647 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1648 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1649 MipsII::MO_DTPREL_LO); 1650 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1651 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1652 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1653 } 1654 1655 SDValue Offset; 1656 if (GV->isDeclaration()) { 1657 // Initial Exec TLS Model 1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1659 MipsII::MO_GOTTPREL); 1660 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1661 TGA); 1662 Offset = DAG.getLoad(PtrVT, dl, 1663 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1664 false, false, false, 0); 1665 } else { 1666 // Local Exec TLS Model 1667 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1668 MipsII::MO_TPREL_HI); 1669 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1670 MipsII::MO_TPREL_LO); 1671 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1672 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1673 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1674 } 1675 1676 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1677 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1678} 1679 1680SDValue MipsTargetLowering:: 1681LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1682{ 1683 SDValue HiPart, JTI, JTILo; 1684 // FIXME there isn't actually debug info here 1685 DebugLoc dl = Op.getDebugLoc(); 1686 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1687 EVT PtrVT = Op.getValueType(); 1688 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1689 1690 if (!IsPIC && !IsN64) { 1691 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); 1692 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); 1693 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); 1694 } else {// Emit Load from Global Pointer 1695 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1696 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1697 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); 1698 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1699 JTI); 1700 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, 1701 MachinePointerInfo(), false, false, false, 0); 1702 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); 1703 } 1704 1705 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); 1706 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); 1707} 1708 1709SDValue MipsTargetLowering:: 1710LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1711{ 1712 SDValue ResNode; 1713 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1714 const Constant *C = N->getConstVal(); 1715 // FIXME there isn't actually debug info here 1716 DebugLoc dl = Op.getDebugLoc(); 1717 1718 // gp_rel relocation 1719 // FIXME: we should reference the constant pool using small data sections, 1720 // but the asm printer currently doesn't support this feature without 1721 // hacking it. This feature should come soon so we can uncomment the 1722 // stuff below. 1723 //if (IsInSmallSection(C->getType())) { 1724 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1725 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1726 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1727 1728 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1729 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1730 N->getOffset(), MipsII::MO_ABS_HI); 1731 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1732 N->getOffset(), MipsII::MO_ABS_LO); 1733 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1734 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1735 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1736 } else { 1737 EVT ValTy = Op.getValueType(); 1738 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1739 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1740 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1741 N->getOffset(), GOTFlag); 1742 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP); 1743 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP, 1744 MachinePointerInfo::getConstantPool(), false, 1745 false, false, 0); 1746 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1747 N->getOffset(), OFSTFlag); 1748 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); 1749 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1750 } 1751 1752 return ResNode; 1753} 1754 1755SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1756 MachineFunction &MF = DAG.getMachineFunction(); 1757 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1758 1759 DebugLoc dl = Op.getDebugLoc(); 1760 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1761 getPointerTy()); 1762 1763 // vastart just stores the address of the VarArgsFrameIndex slot into the 1764 // memory location argument. 1765 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1766 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1767 MachinePointerInfo(SV), false, false, 0); 1768} 1769 1770static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1771 EVT TyX = Op.getOperand(0).getValueType(); 1772 EVT TyY = Op.getOperand(1).getValueType(); 1773 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1774 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1775 DebugLoc DL = Op.getDebugLoc(); 1776 SDValue Res; 1777 1778 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1779 // to i32. 1780 SDValue X = (TyX == MVT::f32) ? 1781 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1782 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1783 Const1); 1784 SDValue Y = (TyY == MVT::f32) ? 1785 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1786 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1787 Const1); 1788 1789 if (HasR2) { 1790 // ext E, Y, 31, 1 ; extract bit31 of Y 1791 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1792 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1793 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1794 } else { 1795 // sll SllX, X, 1 1796 // srl SrlX, SllX, 1 1797 // srl SrlY, Y, 31 1798 // sll SllY, SrlX, 31 1799 // or Or, SrlX, SllY 1800 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1801 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1802 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1803 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1804 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1805 } 1806 1807 if (TyX == MVT::f32) 1808 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1809 1810 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1811 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1812 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1813} 1814 1815static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1816 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1817 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1818 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1819 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1820 DebugLoc DL = Op.getDebugLoc(); 1821 1822 // Bitcast to integer nodes. 1823 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1824 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1825 1826 if (HasR2) { 1827 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1828 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1829 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1830 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1831 1832 if (WidthX > WidthY) 1833 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1834 else if (WidthY > WidthX) 1835 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1836 1837 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1838 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1839 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1840 } 1841 1842 // (d)sll SllX, X, 1 1843 // (d)srl SrlX, SllX, 1 1844 // (d)srl SrlY, Y, width(Y)-1 1845 // (d)sll SllY, SrlX, width(Y)-1 1846 // or Or, SrlX, SllY 1847 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1848 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1849 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1850 DAG.getConstant(WidthY - 1, MVT::i32)); 1851 1852 if (WidthX > WidthY) 1853 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1854 else if (WidthY > WidthX) 1855 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1856 1857 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1858 DAG.getConstant(WidthX - 1, MVT::i32)); 1859 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1860 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1861} 1862 1863SDValue 1864MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1865 if (Subtarget->hasMips64()) 1866 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 1867 1868 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 1869} 1870 1871static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1872 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1873 DebugLoc DL = Op.getDebugLoc(); 1874 1875 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1876 // to i32. 1877 SDValue X = (Op.getValueType() == MVT::f32) ? 1878 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1879 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1880 Const1); 1881 1882 // Clear MSB. 1883 if (HasR2) 1884 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1885 DAG.getRegister(Mips::ZERO, MVT::i32), 1886 DAG.getConstant(31, MVT::i32), Const1, X); 1887 else { 1888 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1889 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1890 } 1891 1892 if (Op.getValueType() == MVT::f32) 1893 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1894 1895 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1896 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1897 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1898} 1899 1900static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1901 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1902 DebugLoc DL = Op.getDebugLoc(); 1903 1904 // Bitcast to integer node. 1905 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1906 1907 // Clear MSB. 1908 if (HasR2) 1909 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1910 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1911 DAG.getConstant(63, MVT::i32), Const1, X); 1912 else { 1913 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1914 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1915 } 1916 1917 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1918} 1919 1920SDValue 1921MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 1922 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1923 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 1924 1925 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 1926} 1927 1928SDValue MipsTargetLowering:: 1929LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1930 // check the depth 1931 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1932 "Frame address can only be determined for current frame."); 1933 1934 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1935 MFI->setFrameAddressIsTaken(true); 1936 EVT VT = Op.getValueType(); 1937 DebugLoc dl = Op.getDebugLoc(); 1938 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1939 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1940 return FrameAddr; 1941} 1942 1943// TODO: set SType according to the desired memory barrier behavior. 1944SDValue 1945MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const { 1946 unsigned SType = 0; 1947 DebugLoc dl = Op.getDebugLoc(); 1948 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1949 DAG.getConstant(SType, MVT::i32)); 1950} 1951 1952SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1953 SelectionDAG& DAG) const { 1954 // FIXME: Need pseudo-fence for 'singlethread' fences 1955 // FIXME: Set SType for weaker fences where supported/appropriate. 1956 unsigned SType = 0; 1957 DebugLoc dl = Op.getDebugLoc(); 1958 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1959 DAG.getConstant(SType, MVT::i32)); 1960} 1961 1962//===----------------------------------------------------------------------===// 1963// Calling Convention Implementation 1964//===----------------------------------------------------------------------===// 1965 1966//===----------------------------------------------------------------------===// 1967// TODO: Implement a generic logic using tblgen that can support this. 1968// Mips O32 ABI rules: 1969// --- 1970// i32 - Passed in A0, A1, A2, A3 and stack 1971// f32 - Only passed in f32 registers if no int reg has been used yet to hold 1972// an argument. Otherwise, passed in A1, A2, A3 and stack. 1973// f64 - Only passed in two aliased f32 registers if no int reg has been used 1974// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1975// not used, it must be shadowed. If only A3 is avaiable, shadow it and 1976// go to stack. 1977// 1978// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1979//===----------------------------------------------------------------------===// 1980 1981static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1982 MVT LocVT, CCValAssign::LocInfo LocInfo, 1983 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1984 1985 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1986 1987 static const uint16_t IntRegs[] = { 1988 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1989 }; 1990 static const uint16_t F32Regs[] = { 1991 Mips::F12, Mips::F14 1992 }; 1993 static const uint16_t F64Regs[] = { 1994 Mips::D6, Mips::D7 1995 }; 1996 1997 // ByVal Args 1998 if (ArgFlags.isByVal()) { 1999 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 2000 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 2001 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 2002 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 2003 r < std::min(IntRegsSize, NextReg); ++r) 2004 State.AllocateReg(IntRegs[r]); 2005 return false; 2006 } 2007 2008 // Promote i8 and i16 2009 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2010 LocVT = MVT::i32; 2011 if (ArgFlags.isSExt()) 2012 LocInfo = CCValAssign::SExt; 2013 else if (ArgFlags.isZExt()) 2014 LocInfo = CCValAssign::ZExt; 2015 else 2016 LocInfo = CCValAssign::AExt; 2017 } 2018 2019 unsigned Reg; 2020 2021 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2022 // is true: function is vararg, argument is 3rd or higher, there is previous 2023 // argument which is not f32 or f64. 2024 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2025 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2026 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2027 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2028 2029 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2030 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2031 // If this is the first part of an i64 arg, 2032 // the allocated register must be either A0 or A2. 2033 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2034 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2035 LocVT = MVT::i32; 2036 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2037 // Allocate int register and shadow next int register. If first 2038 // available register is Mips::A1 or Mips::A3, shadow it too. 2039 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2040 if (Reg == Mips::A1 || Reg == Mips::A3) 2041 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2042 State.AllocateReg(IntRegs, IntRegsSize); 2043 LocVT = MVT::i32; 2044 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2045 // we are guaranteed to find an available float register 2046 if (ValVT == MVT::f32) { 2047 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2048 // Shadow int register 2049 State.AllocateReg(IntRegs, IntRegsSize); 2050 } else { 2051 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2052 // Shadow int registers 2053 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2054 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2055 State.AllocateReg(IntRegs, IntRegsSize); 2056 State.AllocateReg(IntRegs, IntRegsSize); 2057 } 2058 } else 2059 llvm_unreachable("Cannot handle this ValVT."); 2060 2061 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 2062 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 2063 2064 if (!Reg) 2065 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2066 else 2067 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2068 2069 return false; // CC must always match 2070} 2071 2072static const uint16_t Mips64IntRegs[8] = 2073 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 2074 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; 2075static const uint16_t Mips64DPRegs[8] = 2076 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 2077 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64}; 2078 2079static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT, 2080 CCValAssign::LocInfo LocInfo, 2081 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2082 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8); 2083 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8; 2084 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8); 2085 2086 assert(Align <= 16 && "Cannot handle alignments larger than 16."); 2087 2088 // If byval is 16-byte aligned, the first arg register must be even. 2089 if ((Align == 16) && (FirstIdx % 2)) { 2090 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]); 2091 ++FirstIdx; 2092 } 2093 2094 // Mark the registers allocated. 2095 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I) 2096 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]); 2097 2098 // Allocate space on caller's stack. 2099 unsigned Offset = State.AllocateStack(Size, Align); 2100 2101 if (FirstIdx < 8) 2102 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx], 2103 LocVT, LocInfo)); 2104 else 2105 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2106 2107 return true; 2108} 2109 2110#include "MipsGenCallingConv.inc" 2111 2112static void 2113AnalyzeMips64CallOperands(CCState &CCInfo, 2114 const SmallVectorImpl<ISD::OutputArg> &Outs) { 2115 unsigned NumOps = Outs.size(); 2116 for (unsigned i = 0; i != NumOps; ++i) { 2117 MVT ArgVT = Outs[i].VT; 2118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2119 bool R; 2120 2121 if (Outs[i].IsFixed) 2122 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2123 else 2124 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2125 2126 if (R) { 2127#ifndef NDEBUG 2128 dbgs() << "Call operand #" << i << " has unhandled type " 2129 << EVT(ArgVT).getEVTString(); 2130#endif 2131 llvm_unreachable(0); 2132 } 2133 } 2134} 2135 2136//===----------------------------------------------------------------------===// 2137// Call Calling Convention Implementation 2138//===----------------------------------------------------------------------===// 2139 2140static const unsigned O32IntRegsSize = 4; 2141 2142static const uint16_t O32IntRegs[] = { 2143 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2144}; 2145 2146// Return next O32 integer argument register. 2147static unsigned getNextIntArgReg(unsigned Reg) { 2148 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2149 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2150} 2151 2152// Write ByVal Arg to arg registers and stack. 2153static void 2154WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 2155 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 2156 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 2157 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2158 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2159 MVT PtrType, bool isLittle) { 2160 unsigned LocMemOffset = VA.getLocMemOffset(); 2161 unsigned Offset = 0; 2162 uint32_t RemainingSize = Flags.getByValSize(); 2163 unsigned ByValAlign = Flags.getByValAlign(); 2164 2165 // Copy the first 4 words of byval arg to registers A0 - A3. 2166 // FIXME: Use a stricter alignment if it enables better optimization in passes 2167 // run later. 2168 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 2169 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 2170 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2171 DAG.getConstant(Offset, MVT::i32)); 2172 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 2173 MachinePointerInfo(), false, false, false, 2174 std::min(ByValAlign, (unsigned )4)); 2175 MemOpChains.push_back(LoadVal.getValue(1)); 2176 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2177 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2178 } 2179 2180 if (RemainingSize == 0) 2181 return; 2182 2183 // If there still is a register available for argument passing, write the 2184 // remaining part of the structure to it using subword loads and shifts. 2185 if (LocMemOffset < 4 * 4) { 2186 assert(RemainingSize <= 3 && RemainingSize >= 1 && 2187 "There must be one to three bytes remaining."); 2188 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 2189 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2190 DAG.getConstant(Offset, MVT::i32)); 2191 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 2192 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2193 LoadPtr, MachinePointerInfo(), 2194 MVT::getIntegerVT(LoadSize * 8), false, 2195 false, Alignment); 2196 MemOpChains.push_back(LoadVal.getValue(1)); 2197 2198 // If target is big endian, shift it to the most significant half-word or 2199 // byte. 2200 if (!isLittle) 2201 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 2202 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 2203 2204 Offset += LoadSize; 2205 RemainingSize -= LoadSize; 2206 2207 // Read second subword if necessary. 2208 if (RemainingSize != 0) { 2209 assert(RemainingSize == 1 && "There must be one byte remaining."); 2210 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2211 DAG.getConstant(Offset, MVT::i32)); 2212 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 2213 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2214 LoadPtr, MachinePointerInfo(), 2215 MVT::i8, false, false, Alignment); 2216 MemOpChains.push_back(Subword.getValue(1)); 2217 // Insert the loaded byte to LoadVal. 2218 // FIXME: Use INS if supported by target. 2219 unsigned ShiftAmt = isLittle ? 16 : 8; 2220 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 2221 DAG.getConstant(ShiftAmt, MVT::i32)); 2222 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 2223 } 2224 2225 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2226 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2227 return; 2228 } 2229 2230 // Create a fixed object on stack at offset LocMemOffset and copy 2231 // remaining part of byval arg to it using memcpy. 2232 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2233 DAG.getConstant(Offset, MVT::i32)); 2234 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 2235 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 2236 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 2237 DAG.getConstant(RemainingSize, MVT::i32), 2238 std::min(ByValAlign, (unsigned)4), 2239 /*isVolatile=*/false, /*AlwaysInline=*/false, 2240 MachinePointerInfo(0), MachinePointerInfo(0)); 2241} 2242 2243// Copy Mips64 byVal arg to registers and stack. 2244void static 2245PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 2246 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 2247 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 2248 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2249 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2250 EVT PtrTy, bool isLittle) { 2251 unsigned ByValSize = Flags.getByValSize(); 2252 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8); 2253 bool IsRegLoc = VA.isRegLoc(); 2254 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 2255 unsigned LocMemOffset = 0; 2256 unsigned MemCpySize = ByValSize; 2257 2258 if (!IsRegLoc) 2259 LocMemOffset = VA.getLocMemOffset(); 2260 else { 2261 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, 2262 VA.getLocReg()); 2263 const uint16_t *RegEnd = Mips64IntRegs + 8; 2264 2265 // Copy double words to registers. 2266 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) { 2267 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2268 DAG.getConstant(Offset, PtrTy)); 2269 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr, 2270 MachinePointerInfo(), false, false, false, 2271 Alignment); 2272 MemOpChains.push_back(LoadVal.getValue(1)); 2273 RegsToPass.push_back(std::make_pair(*Reg, LoadVal)); 2274 } 2275 2276 // Return if the struct has been fully copied. 2277 if (!(MemCpySize = ByValSize - Offset)) 2278 return; 2279 2280 // If there is an argument register available, copy the remainder of the 2281 // byval argument with sub-doubleword loads and shifts. 2282 if (Reg != RegEnd) { 2283 assert((ByValSize < Offset + 8) && 2284 "Size of the remainder should be smaller than 8-byte."); 2285 SDValue Val; 2286 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) { 2287 unsigned RemSize = ByValSize - Offset; 2288 2289 if (RemSize < LoadSize) 2290 continue; 2291 2292 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2293 DAG.getConstant(Offset, PtrTy)); 2294 SDValue LoadVal = 2295 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr, 2296 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 2297 false, false, Alignment); 2298 MemOpChains.push_back(LoadVal.getValue(1)); 2299 2300 // Offset in number of bits from double word boundary. 2301 unsigned OffsetDW = (Offset % 8) * 8; 2302 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8); 2303 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal, 2304 DAG.getConstant(Shamt, MVT::i32)); 2305 2306 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) : 2307 Shift; 2308 Offset += LoadSize; 2309 Alignment = std::min(Alignment, LoadSize); 2310 } 2311 2312 RegsToPass.push_back(std::make_pair(*Reg, Val)); 2313 return; 2314 } 2315 } 2316 2317 assert(MemCpySize && "MemCpySize must not be zero."); 2318 2319 // Create a fixed object on stack at offset LocMemOffset and copy 2320 // remainder of byval arg to it with memcpy. 2321 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2322 DAG.getConstant(Offset, PtrTy)); 2323 LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true); 2324 SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy); 2325 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 2326 DAG.getConstant(MemCpySize, PtrTy), Alignment, 2327 /*isVolatile=*/false, /*AlwaysInline=*/false, 2328 MachinePointerInfo(0), MachinePointerInfo(0)); 2329} 2330 2331/// LowerCall - functions arguments are copied from virtual regs to 2332/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2333/// TODO: isTailCall. 2334SDValue 2335MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee, 2336 CallingConv::ID CallConv, bool isVarArg, 2337 bool doesNotRet, bool &isTailCall, 2338 const SmallVectorImpl<ISD::OutputArg> &Outs, 2339 const SmallVectorImpl<SDValue> &OutVals, 2340 const SmallVectorImpl<ISD::InputArg> &Ins, 2341 DebugLoc dl, SelectionDAG &DAG, 2342 SmallVectorImpl<SDValue> &InVals) const { 2343 // MIPs target does not yet support tail call optimization. 2344 isTailCall = false; 2345 2346 MachineFunction &MF = DAG.getMachineFunction(); 2347 MachineFrameInfo *MFI = MF.getFrameInfo(); 2348 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2349 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2350 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2351 2352 // Analyze operands of the call, assigning locations to each operand. 2353 SmallVector<CCValAssign, 16> ArgLocs; 2354 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2355 getTargetMachine(), ArgLocs, *DAG.getContext()); 2356 2357 if (IsO32) 2358 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 2359 else if (HasMips64) 2360 AnalyzeMips64CallOperands(CCInfo, Outs); 2361 else 2362 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 2363 2364 // Get a count of how many bytes are to be pushed on the stack. 2365 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2366 2367 // Chain is the output chain of the last Load/Store or CopyToReg node. 2368 // ByValChain is the output chain of the last Memcpy node created for copying 2369 // byval arguments to the stack. 2370 SDValue Chain, CallSeqStart, ByValChain; 2371 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2372 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal); 2373 ByValChain = InChain; 2374 2375 // If this is the first call, create a stack frame object that points to 2376 // a location to which .cprestore saves $gp. 2377 if (IsO32 && IsPIC && MipsFI->globalBaseRegFixed() && !MipsFI->getGPFI()) 2378 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 2379 2380 // Get the frame index of the stack frame object that points to the location 2381 // of dynamically allocated area on the stack. 2382 int DynAllocFI = MipsFI->getDynAllocFI(); 2383 2384 // Update size of the maximum argument space. 2385 // For O32, a minimum of four words (16 bytes) of argument space is 2386 // allocated. 2387 if (IsO32) 2388 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 2389 2390 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 2391 2392 if (MaxCallFrameSize < NextStackOffset) { 2393 MipsFI->setMaxCallFrameSize(NextStackOffset); 2394 2395 // Set the offsets relative to $sp of the $gp restore slot and dynamically 2396 // allocated stack space. These offsets must be aligned to a boundary 2397 // determined by the stack alignment of the ABI. 2398 unsigned StackAlignment = TFL->getStackAlignment(); 2399 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 2400 StackAlignment * StackAlignment; 2401 2402 if (MipsFI->needGPSaveRestore()) 2403 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 2404 2405 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 2406 } 2407 2408 // With EABI is it possible to have 16 args on registers. 2409 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2410 SmallVector<SDValue, 8> MemOpChains; 2411 2412 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 2413 2414 // Walk the register/memloc assignments, inserting copies/loads. 2415 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2416 SDValue Arg = OutVals[i]; 2417 CCValAssign &VA = ArgLocs[i]; 2418 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2419 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2420 2421 // ByVal Arg. 2422 if (Flags.isByVal()) { 2423 assert(Flags.getByValSize() && 2424 "ByVal args of size 0 should have been ignored by front-end."); 2425 if (IsO32) 2426 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, 2427 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2428 Subtarget->isLittle()); 2429 else 2430 PassByValArg64(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, 2431 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2432 Subtarget->isLittle()); 2433 continue; 2434 } 2435 2436 // Promote the value if needed. 2437 switch (VA.getLocInfo()) { 2438 default: llvm_unreachable("Unknown loc info!"); 2439 case CCValAssign::Full: 2440 if (VA.isRegLoc()) { 2441 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2442 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2443 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2444 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2445 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2446 Arg, DAG.getConstant(0, MVT::i32)); 2447 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2448 Arg, DAG.getConstant(1, MVT::i32)); 2449 if (!Subtarget->isLittle()) 2450 std::swap(Lo, Hi); 2451 unsigned LocRegLo = VA.getLocReg(); 2452 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2453 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2454 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2455 continue; 2456 } 2457 } 2458 break; 2459 case CCValAssign::SExt: 2460 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2461 break; 2462 case CCValAssign::ZExt: 2463 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2464 break; 2465 case CCValAssign::AExt: 2466 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2467 break; 2468 } 2469 2470 // Arguments that can be passed on register must be kept at 2471 // RegsToPass vector 2472 if (VA.isRegLoc()) { 2473 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2474 continue; 2475 } 2476 2477 // Register can't get to this point... 2478 assert(VA.isMemLoc()); 2479 2480 // Create the frame index object for this incoming parameter 2481 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2482 VA.getLocMemOffset(), true); 2483 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2484 2485 // emit ISD::STORE whichs stores the 2486 // parameter value to a stack Location 2487 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2488 MachinePointerInfo(), false, false, 0)); 2489 } 2490 2491 // Extend range of indices of frame objects for outgoing arguments that were 2492 // created during this function call. Skip this step if no such objects were 2493 // created. 2494 if (LastFI) 2495 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2496 2497 // If a memcpy has been created to copy a byval arg to a stack, replace the 2498 // chain input of CallSeqStart with ByValChain. 2499 if (InChain != ByValChain) 2500 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain, 2501 NextStackOffsetVal); 2502 2503 // Transform all store nodes into one single node because all store 2504 // nodes are independent of each other. 2505 if (!MemOpChains.empty()) 2506 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2507 &MemOpChains[0], MemOpChains.size()); 2508 2509 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2510 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2511 // node so that legalize doesn't hack it. 2512 unsigned char OpFlag; 2513 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2514 bool GlobalOrExternal = false; 2515 SDValue CalleeLo; 2516 2517 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2518 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2519 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2520 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2521 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2522 OpFlag); 2523 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2524 0, LoFlag); 2525 } else { 2526 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2527 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2528 getPointerTy(), 0, OpFlag); 2529 } 2530 2531 GlobalOrExternal = true; 2532 } 2533 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2534 if (IsN64 || (!IsO32 && IsPIC)) 2535 OpFlag = MipsII::MO_GOT_DISP; 2536 else if (!IsPIC) // !N64 && static 2537 OpFlag = MipsII::MO_NO_FLAG; 2538 else // O32 & PIC 2539 OpFlag = MipsII::MO_GOT_CALL; 2540 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2541 OpFlag); 2542 GlobalOrExternal = true; 2543 } 2544 2545 SDValue InFlag; 2546 2547 // Create nodes that load address of callee and copy it to T9 2548 if (IsPICCall) { 2549 if (GlobalOrExternal) { 2550 // Load callee address 2551 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(), 2552 GetGlobalReg(DAG, getPointerTy()), Callee); 2553 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2554 Callee, MachinePointerInfo::getGOT(), 2555 false, false, false, 0); 2556 2557 // Use GOT+LO if callee has internal linkage. 2558 if (CalleeLo.getNode()) { 2559 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2560 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2561 } else 2562 Callee = LoadValue; 2563 } 2564 } 2565 2566 // T9 should contain the address of the callee function if 2567 // -reloction-model=pic or it is an indirect call. 2568 if (IsPICCall || !GlobalOrExternal) { 2569 // copy to T9 2570 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2571 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2572 InFlag = Chain.getValue(1); 2573 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2574 } 2575 2576 // Build a sequence of copy-to-reg nodes chained together with token 2577 // chain and flag operands which copy the outgoing args into registers. 2578 // The InFlag in necessary since all emitted instructions must be 2579 // stuck together. 2580 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2581 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2582 RegsToPass[i].second, InFlag); 2583 InFlag = Chain.getValue(1); 2584 } 2585 2586 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2587 // = Chain, Callee, Reg#1, Reg#2, ... 2588 // 2589 // Returns a chain & a flag for retval copy to use. 2590 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2591 SmallVector<SDValue, 8> Ops; 2592 Ops.push_back(Chain); 2593 Ops.push_back(Callee); 2594 2595 // Add argument registers to the end of the list so that they are 2596 // known live into the call. 2597 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2598 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2599 RegsToPass[i].second.getValueType())); 2600 2601 // Add a register mask operand representing the call-preserved registers. 2602 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2603 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2604 assert(Mask && "Missing call preserved mask for calling convention"); 2605 Ops.push_back(DAG.getRegisterMask(Mask)); 2606 2607 if (InFlag.getNode()) 2608 Ops.push_back(InFlag); 2609 2610 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2611 InFlag = Chain.getValue(1); 2612 2613 // Create the CALLSEQ_END node. 2614 Chain = DAG.getCALLSEQ_END(Chain, 2615 DAG.getIntPtrConstant(NextStackOffset, true), 2616 DAG.getIntPtrConstant(0, true), InFlag); 2617 InFlag = Chain.getValue(1); 2618 2619 // Handle result values, copying them out of physregs into vregs that we 2620 // return. 2621 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2622 Ins, dl, DAG, InVals); 2623} 2624 2625/// LowerCallResult - Lower the result values of a call into the 2626/// appropriate copies out of appropriate physical registers. 2627SDValue 2628MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2629 CallingConv::ID CallConv, bool isVarArg, 2630 const SmallVectorImpl<ISD::InputArg> &Ins, 2631 DebugLoc dl, SelectionDAG &DAG, 2632 SmallVectorImpl<SDValue> &InVals) const { 2633 // Assign locations to each value returned by this call. 2634 SmallVector<CCValAssign, 16> RVLocs; 2635 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2636 getTargetMachine(), RVLocs, *DAG.getContext()); 2637 2638 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2639 2640 // Copy all of the result registers out of their specified physreg. 2641 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2642 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2643 RVLocs[i].getValVT(), InFlag).getValue(1); 2644 InFlag = Chain.getValue(2); 2645 InVals.push_back(Chain.getValue(0)); 2646 } 2647 2648 return Chain; 2649} 2650 2651//===----------------------------------------------------------------------===// 2652// Formal Arguments Calling Convention Implementation 2653//===----------------------------------------------------------------------===// 2654static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2655 std::vector<SDValue>& OutChains, 2656 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2657 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2658 const Argument *FuncArg) { 2659 unsigned LocMem = VA.getLocMemOffset(); 2660 unsigned FirstWord = LocMem / 4; 2661 2662 // copy register A0 - A3 to frame object 2663 for (unsigned i = 0; i < NumWords; ++i) { 2664 unsigned CurWord = FirstWord + i; 2665 if (CurWord >= O32IntRegsSize) 2666 break; 2667 2668 unsigned SrcReg = O32IntRegs[CurWord]; 2669 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2670 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2671 DAG.getConstant(i * 4, MVT::i32)); 2672 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2673 StorePtr, MachinePointerInfo(FuncArg, i * 4), 2674 false, false, 0); 2675 OutChains.push_back(Store); 2676 } 2677} 2678 2679// Create frame object on stack and copy registers used for byval passing to it. 2680static unsigned 2681CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2682 std::vector<SDValue>& OutChains, SelectionDAG &DAG, 2683 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2684 MachineFrameInfo *MFI, bool IsRegLoc, 2685 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, 2686 EVT PtrTy, const Argument *FuncArg) { 2687 const uint16_t *Reg = Mips64IntRegs + 8; 2688 int FOOffset; // Frame object offset from virtual frame pointer. 2689 2690 if (IsRegLoc) { 2691 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg()); 2692 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8; 2693 } 2694 else 2695 FOOffset = VA.getLocMemOffset(); 2696 2697 // Create frame object. 2698 unsigned NumRegs = (Flags.getByValSize() + 7) / 8; 2699 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true); 2700 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy); 2701 InVals.push_back(FIN); 2702 2703 // Copy arg registers. 2704 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs); 2705 ++Reg, ++I) { 2706 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass); 2707 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN, 2708 DAG.getConstant(I * 8, PtrTy)); 2709 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64), 2710 StorePtr, MachinePointerInfo(FuncArg, I * 8), 2711 false, false, 0); 2712 OutChains.push_back(Store); 2713 } 2714 2715 return LastFI; 2716} 2717 2718/// LowerFormalArguments - transform physical registers into virtual registers 2719/// and generate load operations for arguments places on the stack. 2720SDValue 2721MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2722 CallingConv::ID CallConv, 2723 bool isVarArg, 2724 const SmallVectorImpl<ISD::InputArg> &Ins, 2725 DebugLoc dl, SelectionDAG &DAG, 2726 SmallVectorImpl<SDValue> &InVals) 2727 const { 2728 MachineFunction &MF = DAG.getMachineFunction(); 2729 MachineFrameInfo *MFI = MF.getFrameInfo(); 2730 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2731 2732 MipsFI->setVarArgsFrameIndex(0); 2733 2734 // Used with vargs to acumulate store chains. 2735 std::vector<SDValue> OutChains; 2736 2737 // Assign locations to all of the incoming arguments. 2738 SmallVector<CCValAssign, 16> ArgLocs; 2739 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2740 getTargetMachine(), ArgLocs, *DAG.getContext()); 2741 2742 if (IsO32) 2743 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2744 else 2745 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2746 2747 Function::const_arg_iterator FuncArg = 2748 DAG.getMachineFunction().getFunction()->arg_begin(); 2749 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2750 2751 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) { 2752 CCValAssign &VA = ArgLocs[i]; 2753 EVT ValVT = VA.getValVT(); 2754 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2755 bool IsRegLoc = VA.isRegLoc(); 2756 2757 if (Flags.isByVal()) { 2758 assert(Flags.getByValSize() && 2759 "ByVal args of size 0 should have been ignored by front-end."); 2760 if (IsO32) { 2761 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2762 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2763 true); 2764 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2765 InVals.push_back(FIN); 2766 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags, 2767 &*FuncArg); 2768 } else // N32/64 2769 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags, 2770 MFI, IsRegLoc, InVals, MipsFI, 2771 getPointerTy(), &*FuncArg); 2772 continue; 2773 } 2774 2775 // Arguments stored on registers 2776 if (IsRegLoc) { 2777 EVT RegVT = VA.getLocVT(); 2778 unsigned ArgReg = VA.getLocReg(); 2779 const TargetRegisterClass *RC; 2780 2781 if (RegVT == MVT::i32) 2782 RC = Mips::CPURegsRegisterClass; 2783 else if (RegVT == MVT::i64) 2784 RC = Mips::CPU64RegsRegisterClass; 2785 else if (RegVT == MVT::f32) 2786 RC = Mips::FGR32RegisterClass; 2787 else if (RegVT == MVT::f64) 2788 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; 2789 else 2790 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2791 2792 // Transform the arguments stored on 2793 // physical registers into virtual ones 2794 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2795 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2796 2797 // If this is an 8 or 16-bit value, it has been passed promoted 2798 // to 32 bits. Insert an assert[sz]ext to capture this, then 2799 // truncate to the right size. 2800 if (VA.getLocInfo() != CCValAssign::Full) { 2801 unsigned Opcode = 0; 2802 if (VA.getLocInfo() == CCValAssign::SExt) 2803 Opcode = ISD::AssertSext; 2804 else if (VA.getLocInfo() == CCValAssign::ZExt) 2805 Opcode = ISD::AssertZext; 2806 if (Opcode) 2807 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2808 DAG.getValueType(ValVT)); 2809 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 2810 } 2811 2812 // Handle floating point arguments passed in integer registers. 2813 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2814 (RegVT == MVT::i64 && ValVT == MVT::f64)) 2815 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 2816 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2817 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2818 getNextIntArgReg(ArgReg), RC); 2819 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2820 if (!Subtarget->isLittle()) 2821 std::swap(ArgValue, ArgValue2); 2822 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2823 ArgValue, ArgValue2); 2824 } 2825 2826 InVals.push_back(ArgValue); 2827 } else { // VA.isRegLoc() 2828 2829 // sanity check 2830 assert(VA.isMemLoc()); 2831 2832 // The stack pointer offset is relative to the caller stack frame. 2833 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2834 VA.getLocMemOffset(), true); 2835 2836 // Create load nodes to retrieve arguments from the stack 2837 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2838 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 2839 MachinePointerInfo::getFixedStack(LastFI), 2840 false, false, false, 0)); 2841 } 2842 } 2843 2844 // The mips ABIs for returning structs by value requires that we copy 2845 // the sret argument into $v0 for the return. Save the argument into 2846 // a virtual register so that we can access it from the return points. 2847 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2848 unsigned Reg = MipsFI->getSRetReturnReg(); 2849 if (!Reg) { 2850 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2851 MipsFI->setSRetReturnReg(Reg); 2852 } 2853 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2854 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2855 } 2856 2857 if (isVarArg) { 2858 unsigned NumOfRegs = IsO32 ? 4 : 8; 2859 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs; 2860 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs); 2861 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot. 2862 const TargetRegisterClass *RC 2863 = IsO32 ? Mips::CPURegsRegisterClass : Mips::CPU64RegsRegisterClass; 2864 unsigned RegSize = RC->getSize(); 2865 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize; 2866 2867 // Offset of the first variable argument from stack pointer. 2868 int FirstVaArgOffset; 2869 2870 if (IsO32 || (Idx == NumOfRegs)) { 2871 FirstVaArgOffset = 2872 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize; 2873 } else 2874 FirstVaArgOffset = RegSlotOffset; 2875 2876 // Record the frame index of the first variable argument 2877 // which is a value necessary to VASTART. 2878 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true); 2879 MipsFI->setVarArgsFrameIndex(LastFI); 2880 2881 // Copy the integer registers that have not been used for argument passing 2882 // to the argument register save area. For O32, the save area is allocated 2883 // in the caller's stack frame, while for N32/64, it is allocated in the 2884 // callee's stack frame. 2885 for (int StackOffset = RegSlotOffset; 2886 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) { 2887 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC); 2888 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, 2889 MVT::getIntegerVT(RegSize * 8)); 2890 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true); 2891 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2892 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2893 MachinePointerInfo(), false, false, 0)); 2894 } 2895 } 2896 2897 MipsFI->setLastInArgFI(LastFI); 2898 2899 // All stores are grouped in one node to allow the matching between 2900 // the size of Ins and InVals. This only happens when on varg functions 2901 if (!OutChains.empty()) { 2902 OutChains.push_back(Chain); 2903 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2904 &OutChains[0], OutChains.size()); 2905 } 2906 2907 return Chain; 2908} 2909 2910//===----------------------------------------------------------------------===// 2911// Return Value Calling Convention Implementation 2912//===----------------------------------------------------------------------===// 2913 2914SDValue 2915MipsTargetLowering::LowerReturn(SDValue Chain, 2916 CallingConv::ID CallConv, bool isVarArg, 2917 const SmallVectorImpl<ISD::OutputArg> &Outs, 2918 const SmallVectorImpl<SDValue> &OutVals, 2919 DebugLoc dl, SelectionDAG &DAG) const { 2920 2921 // CCValAssign - represent the assignment of 2922 // the return value to a location 2923 SmallVector<CCValAssign, 16> RVLocs; 2924 2925 // CCState - Info about the registers and stack slot. 2926 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2927 getTargetMachine(), RVLocs, *DAG.getContext()); 2928 2929 // Analize return values. 2930 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2931 2932 // If this is the first return lowered for this function, add 2933 // the regs to the liveout set for the function. 2934 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2935 for (unsigned i = 0; i != RVLocs.size(); ++i) 2936 if (RVLocs[i].isRegLoc()) 2937 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2938 } 2939 2940 SDValue Flag; 2941 2942 // Copy the result values into the output registers. 2943 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2944 CCValAssign &VA = RVLocs[i]; 2945 assert(VA.isRegLoc() && "Can only return in registers!"); 2946 2947 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 2948 2949 // guarantee that all emitted copies are 2950 // stuck together, avoiding something bad 2951 Flag = Chain.getValue(1); 2952 } 2953 2954 // The mips ABIs for returning structs by value requires that we copy 2955 // the sret argument into $v0 for the return. We saved the argument into 2956 // a virtual register in the entry block, so now we copy the value out 2957 // and into $v0. 2958 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2959 MachineFunction &MF = DAG.getMachineFunction(); 2960 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2961 unsigned Reg = MipsFI->getSRetReturnReg(); 2962 2963 if (!Reg) 2964 llvm_unreachable("sret virtual register not created in the entry block"); 2965 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2966 2967 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2968 Flag = Chain.getValue(1); 2969 } 2970 2971 // Return on Mips is always a "jr $ra" 2972 if (Flag.getNode()) 2973 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2974 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2975 else // Return Void 2976 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2977 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2978} 2979 2980//===----------------------------------------------------------------------===// 2981// Mips Inline Assembly Support 2982//===----------------------------------------------------------------------===// 2983 2984/// getConstraintType - Given a constraint letter, return the type of 2985/// constraint it is for this target. 2986MipsTargetLowering::ConstraintType MipsTargetLowering:: 2987getConstraintType(const std::string &Constraint) const 2988{ 2989 // Mips specific constrainy 2990 // GCC config/mips/constraints.md 2991 // 2992 // 'd' : An address register. Equivalent to r 2993 // unless generating MIPS16 code. 2994 // 'y' : Equivalent to r; retained for 2995 // backwards compatibility. 2996 // 'f' : Floating Point registers. 2997 if (Constraint.size() == 1) { 2998 switch (Constraint[0]) { 2999 default : break; 3000 case 'd': 3001 case 'y': 3002 case 'f': 3003 return C_RegisterClass; 3004 } 3005 } 3006 return TargetLowering::getConstraintType(Constraint); 3007} 3008 3009/// Examine constraint type and operand type and determine a weight value. 3010/// This object must already have been set up with the operand type 3011/// and the current alternative constraint selected. 3012TargetLowering::ConstraintWeight 3013MipsTargetLowering::getSingleConstraintMatchWeight( 3014 AsmOperandInfo &info, const char *constraint) const { 3015 ConstraintWeight weight = CW_Invalid; 3016 Value *CallOperandVal = info.CallOperandVal; 3017 // If we don't have a value, we can't do a match, 3018 // but allow it at the lowest weight. 3019 if (CallOperandVal == NULL) 3020 return CW_Default; 3021 Type *type = CallOperandVal->getType(); 3022 // Look at the constraint type. 3023 switch (*constraint) { 3024 default: 3025 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3026 break; 3027 case 'd': 3028 case 'y': 3029 if (type->isIntegerTy()) 3030 weight = CW_Register; 3031 break; 3032 case 'f': 3033 if (type->isFloatTy()) 3034 weight = CW_Register; 3035 break; 3036 } 3037 return weight; 3038} 3039 3040/// Given a register class constraint, like 'r', if this corresponds directly 3041/// to an LLVM register class, return a register of 0 and the register class 3042/// pointer. 3043std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3044getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 3045{ 3046 if (Constraint.size() == 1) { 3047 switch (Constraint[0]) { 3048 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3049 case 'y': // Same as 'r'. Exists for compatibility. 3050 case 'r': 3051 if (VT == MVT::i32) 3052 return std::make_pair(0U, Mips::CPURegsRegisterClass); 3053 assert(VT == MVT::i64 && "Unexpected type."); 3054 return std::make_pair(0U, Mips::CPU64RegsRegisterClass); 3055 case 'f': 3056 if (VT == MVT::f32) 3057 return std::make_pair(0U, Mips::FGR32RegisterClass); 3058 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3059 if (Subtarget->isFP64bit()) 3060 return std::make_pair(0U, Mips::FGR64RegisterClass); 3061 else 3062 return std::make_pair(0U, Mips::AFGR64RegisterClass); 3063 } 3064 } 3065 } 3066 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3067} 3068 3069bool 3070MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3071 // The Mips target isn't yet aware of offsets. 3072 return false; 3073} 3074 3075bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3076 if (VT != MVT::f32 && VT != MVT::f64) 3077 return false; 3078 if (Imm.isNegZero()) 3079 return false; 3080 return Imm.isZero(); 3081} 3082 3083unsigned MipsTargetLowering::getJumpTableEncoding() const { 3084 if (IsN64) 3085 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3086 3087 return TargetLowering::getJumpTableEncoding(); 3088} 3089