MipsISelLowering.cpp revision 33458fedb607e64c46af6797057fbf0b4973a6f6
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16//#include <algorithm> 17#include "MipsISelLowering.h" 18#include "MipsMachineFunction.h" 19#include "MipsTargetMachine.h" 20#include "MipsTargetObjectFile.h" 21#include "MipsSubtarget.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/CallingConv.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/ValueTypes.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36using namespace llvm; 37 38const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 39 switch (Opcode) { 40 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 41 case MipsISD::Hi: return "MipsISD::Hi"; 42 case MipsISD::Lo: return "MipsISD::Lo"; 43 case MipsISD::GPRel: return "MipsISD::GPRel"; 44 case MipsISD::Ret: return "MipsISD::Ret"; 45 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 46 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 47 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 48 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 49 case MipsISD::FPRound: return "MipsISD::FPRound"; 50 case MipsISD::MAdd: return "MipsISD::MAdd"; 51 case MipsISD::MAddu: return "MipsISD::MAddu"; 52 case MipsISD::MSub: return "MipsISD::MSub"; 53 case MipsISD::MSubu: return "MipsISD::MSubu"; 54 case MipsISD::DivRem: return "MipsISD::DivRem"; 55 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 56 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 57 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 58 default: return NULL; 59 } 60} 61 62MipsTargetLowering:: 63MipsTargetLowering(MipsTargetMachine &TM) 64 : TargetLowering(TM, new MipsTargetObjectFile()) { 65 Subtarget = &TM.getSubtarget<MipsSubtarget>(); 66 67 // Mips does not have i1 type, so use i32 for 68 // setcc operations results (slt, sgt, ...). 69 setBooleanContents(ZeroOrOneBooleanContent); 70 71 // Set up the register classes 72 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 73 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 74 75 // When dealing with single precision only, use libcalls 76 if (!Subtarget->isSingleFloat()) 77 if (!Subtarget->isFP64bit()) 78 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 79 80 // Load extented operations for i1 types must be promoted 81 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 82 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 84 85 // MIPS doesn't have extending float->double load/store 86 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 87 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 88 89 // Used by legalize types to correctly generate the setcc result. 90 // Without this, every float setcc comes with a AND/OR with the result, 91 // we don't want this, since the fpcmp result goes to a flag register, 92 // which is used implicitly by brcond and select operations. 93 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 94 95 // Mips Custom Operations 96 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 97 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 98 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 99 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 100 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 101 setOperationAction(ISD::SELECT, MVT::f32, Custom); 102 setOperationAction(ISD::SELECT, MVT::f64, Custom); 103 setOperationAction(ISD::SELECT, MVT::i32, Custom); 104 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 105 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 106 setOperationAction(ISD::VASTART, MVT::Other, Custom); 107 108 setOperationAction(ISD::SDIV, MVT::i32, Expand); 109 setOperationAction(ISD::SREM, MVT::i32, Expand); 110 setOperationAction(ISD::UDIV, MVT::i32, Expand); 111 setOperationAction(ISD::UREM, MVT::i32, Expand); 112 113 // Operations not directly supported by Mips. 114 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 115 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 120 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 121 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 122 setOperationAction(ISD::ROTL, MVT::i32, Expand); 123 124 if (!Subtarget->isMips32r2()) 125 setOperationAction(ISD::ROTR, MVT::i32, Expand); 126 127 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 128 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 129 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 131 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 132 setOperationAction(ISD::FSIN, MVT::f32, Expand); 133 setOperationAction(ISD::FSIN, MVT::f64, Expand); 134 setOperationAction(ISD::FCOS, MVT::f32, Expand); 135 setOperationAction(ISD::FCOS, MVT::f64, Expand); 136 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 137 setOperationAction(ISD::FPOW, MVT::f32, Expand); 138 setOperationAction(ISD::FPOW, MVT::f64, Expand); 139 setOperationAction(ISD::FLOG, MVT::f32, Expand); 140 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 141 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 142 setOperationAction(ISD::FEXP, MVT::f32, Expand); 143 144 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 145 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 146 147 setOperationAction(ISD::VAARG, MVT::Other, Expand); 148 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 149 setOperationAction(ISD::VAEND, MVT::Other, Expand); 150 151 // Use the default for now 152 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 153 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 154 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 155 156 if (Subtarget->isSingleFloat()) 157 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 158 159 if (!Subtarget->hasSEInReg()) { 160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 162 } 163 164 if (!Subtarget->hasBitCount()) 165 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 166 167 if (!Subtarget->hasSwap()) 168 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 169 170 setTargetDAGCombine(ISD::ADDE); 171 setTargetDAGCombine(ISD::SUBE); 172 setTargetDAGCombine(ISD::SDIVREM); 173 setTargetDAGCombine(ISD::UDIVREM); 174 setTargetDAGCombine(ISD::SETCC); 175 176 setMinFunctionAlignment(2); 177 178 setStackPointerRegisterToSaveRestore(Mips::SP); 179 computeRegisterProperties(); 180 181 setExceptionPointerRegister(Mips::A0); 182 setExceptionSelectorRegister(Mips::A1); 183} 184 185MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const { 186 return MVT::i32; 187} 188 189// SelectMadd - 190// Transforms a subgraph in CurDAG if the following pattern is found: 191// (addc multLo, Lo0), (adde multHi, Hi0), 192// where, 193// multHi/Lo: product of multiplication 194// Lo0: initial value of Lo register 195// Hi0: initial value of Hi register 196// Return true if pattern matching was successful. 197static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 198 // ADDENode's second operand must be a flag output of an ADDC node in order 199 // for the matching to be successful. 200 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 201 202 if (ADDCNode->getOpcode() != ISD::ADDC) 203 return false; 204 205 SDValue MultHi = ADDENode->getOperand(0); 206 SDValue MultLo = ADDCNode->getOperand(0); 207 SDNode* MultNode = MultHi.getNode(); 208 unsigned MultOpc = MultHi.getOpcode(); 209 210 // MultHi and MultLo must be generated by the same node, 211 if (MultLo.getNode() != MultNode) 212 return false; 213 214 // and it must be a multiplication. 215 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 216 return false; 217 218 // MultLo amd MultHi must be the first and second output of MultNode 219 // respectively. 220 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 221 return false; 222 223 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 224 // of the values of MultNode, in which case MultNode will be removed in later 225 // phases. 226 // If there exist users other than ADDENode or ADDCNode, this function returns 227 // here, which will result in MultNode being mapped to a single MULT 228 // instruction node rather than a pair of MULT and MADD instructions being 229 // produced. 230 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 231 return false; 232 233 SDValue Chain = CurDAG->getEntryNode(); 234 DebugLoc dl = ADDENode->getDebugLoc(); 235 236 // create MipsMAdd(u) node 237 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 238 239 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 240 MVT::Glue, 241 MultNode->getOperand(0),// Factor 0 242 MultNode->getOperand(1),// Factor 1 243 ADDCNode->getOperand(1),// Lo0 244 ADDENode->getOperand(1));// Hi0 245 246 // create CopyFromReg nodes 247 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 248 MAdd); 249 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 250 Mips::HI, MVT::i32, 251 CopyFromLo.getValue(2)); 252 253 // replace uses of adde and addc here 254 if (!SDValue(ADDCNode, 0).use_empty()) 255 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 256 257 if (!SDValue(ADDENode, 0).use_empty()) 258 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 259 260 return true; 261} 262 263// SelectMsub - 264// Transforms a subgraph in CurDAG if the following pattern is found: 265// (addc Lo0, multLo), (sube Hi0, multHi), 266// where, 267// multHi/Lo: product of multiplication 268// Lo0: initial value of Lo register 269// Hi0: initial value of Hi register 270// Return true if pattern matching was successful. 271static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 272 // SUBENode's second operand must be a flag output of an SUBC node in order 273 // for the matching to be successful. 274 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 275 276 if (SUBCNode->getOpcode() != ISD::SUBC) 277 return false; 278 279 SDValue MultHi = SUBENode->getOperand(1); 280 SDValue MultLo = SUBCNode->getOperand(1); 281 SDNode* MultNode = MultHi.getNode(); 282 unsigned MultOpc = MultHi.getOpcode(); 283 284 // MultHi and MultLo must be generated by the same node, 285 if (MultLo.getNode() != MultNode) 286 return false; 287 288 // and it must be a multiplication. 289 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 290 return false; 291 292 // MultLo amd MultHi must be the first and second output of MultNode 293 // respectively. 294 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 295 return false; 296 297 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 298 // of the values of MultNode, in which case MultNode will be removed in later 299 // phases. 300 // If there exist users other than SUBENode or SUBCNode, this function returns 301 // here, which will result in MultNode being mapped to a single MULT 302 // instruction node rather than a pair of MULT and MSUB instructions being 303 // produced. 304 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 305 return false; 306 307 SDValue Chain = CurDAG->getEntryNode(); 308 DebugLoc dl = SUBENode->getDebugLoc(); 309 310 // create MipsSub(u) node 311 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 312 313 SDValue MSub = CurDAG->getNode(MultOpc, dl, 314 MVT::Glue, 315 MultNode->getOperand(0),// Factor 0 316 MultNode->getOperand(1),// Factor 1 317 SUBCNode->getOperand(0),// Lo0 318 SUBENode->getOperand(0));// Hi0 319 320 // create CopyFromReg nodes 321 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 322 MSub); 323 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 324 Mips::HI, MVT::i32, 325 CopyFromLo.getValue(2)); 326 327 // replace uses of sube and subc here 328 if (!SDValue(SUBCNode, 0).use_empty()) 329 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 330 331 if (!SDValue(SUBENode, 0).use_empty()) 332 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 333 334 return true; 335} 336 337static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 338 TargetLowering::DAGCombinerInfo &DCI, 339 const MipsSubtarget* Subtarget) { 340 if (DCI.isBeforeLegalize()) 341 return SDValue(); 342 343 if (Subtarget->isMips32() && SelectMadd(N, &DAG)) 344 return SDValue(N, 0); 345 346 return SDValue(); 347} 348 349static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 350 TargetLowering::DAGCombinerInfo &DCI, 351 const MipsSubtarget* Subtarget) { 352 if (DCI.isBeforeLegalize()) 353 return SDValue(); 354 355 if (Subtarget->isMips32() && SelectMsub(N, &DAG)) 356 return SDValue(N, 0); 357 358 return SDValue(); 359} 360 361static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 362 TargetLowering::DAGCombinerInfo &DCI, 363 const MipsSubtarget* Subtarget) { 364 if (DCI.isBeforeLegalizeOps()) 365 return SDValue(); 366 367 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 368 MipsISD::DivRemU; 369 DebugLoc dl = N->getDebugLoc(); 370 371 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 372 N->getOperand(0), N->getOperand(1)); 373 SDValue InChain = DAG.getEntryNode(); 374 SDValue InGlue = DivRem; 375 376 // insert MFLO 377 if (N->hasAnyUseOfValue(0)) { 378 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32, 379 InGlue); 380 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 381 InChain = CopyFromLo.getValue(1); 382 InGlue = CopyFromLo.getValue(2); 383 } 384 385 // insert MFHI 386 if (N->hasAnyUseOfValue(1)) { 387 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 388 Mips::HI, MVT::i32, InGlue); 389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 390 } 391 392 return SDValue(); 393} 394 395static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 396 switch (CC) { 397 default: llvm_unreachable("Unknown fp condition code!"); 398 case ISD::SETEQ: 399 case ISD::SETOEQ: return Mips::FCOND_OEQ; 400 case ISD::SETUNE: return Mips::FCOND_UNE; 401 case ISD::SETLT: 402 case ISD::SETOLT: return Mips::FCOND_OLT; 403 case ISD::SETGT: 404 case ISD::SETOGT: return Mips::FCOND_OGT; 405 case ISD::SETLE: 406 case ISD::SETOLE: return Mips::FCOND_OLE; 407 case ISD::SETGE: 408 case ISD::SETOGE: return Mips::FCOND_OGE; 409 case ISD::SETULT: return Mips::FCOND_ULT; 410 case ISD::SETULE: return Mips::FCOND_ULE; 411 case ISD::SETUGT: return Mips::FCOND_UGT; 412 case ISD::SETUGE: return Mips::FCOND_UGE; 413 case ISD::SETUO: return Mips::FCOND_UN; 414 case ISD::SETO: return Mips::FCOND_OR; 415 case ISD::SETNE: 416 case ISD::SETONE: return Mips::FCOND_ONE; 417 case ISD::SETUEQ: return Mips::FCOND_UEQ; 418 } 419} 420 421 422// Returns true if condition code has to be inverted. 423static bool InvertFPCondCode(Mips::CondCode CC) { 424 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 425 return false; 426 427 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 428 return true; 429 430 assert(false && "Illegal Condition Code"); 431 return false; 432} 433 434// Creates and returns an FPCmp node from a setcc node. 435// Returns Op if setcc is not a floating point comparison. 436static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 437 // must be a SETCC node 438 if (Op.getOpcode() != ISD::SETCC) 439 return Op; 440 441 SDValue LHS = Op.getOperand(0); 442 443 if (!LHS.getValueType().isFloatingPoint()) 444 return Op; 445 446 SDValue RHS = Op.getOperand(1); 447 DebugLoc dl = Op.getDebugLoc(); 448 449 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 450 // node if necessary. 451 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 452 453 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 454 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 455} 456 457// Creates and returns a CMovFPT/F node. 458static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 459 SDValue False, DebugLoc DL) { 460 bool invert = InvertFPCondCode((Mips::CondCode) 461 cast<ConstantSDNode>(Cond.getOperand(2)) 462 ->getSExtValue()); 463 464 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 465 True.getValueType(), True, False, Cond); 466} 467 468static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 469 TargetLowering::DAGCombinerInfo &DCI, 470 const MipsSubtarget* Subtarget) { 471 if (DCI.isBeforeLegalizeOps()) 472 return SDValue(); 473 474 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 475 476 if (Cond.getOpcode() != MipsISD::FPCmp) 477 return SDValue(); 478 479 SDValue True = DAG.getConstant(1, MVT::i32); 480 SDValue False = DAG.getConstant(0, MVT::i32); 481 482 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 483} 484 485SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 486 const { 487 SelectionDAG &DAG = DCI.DAG; 488 unsigned opc = N->getOpcode(); 489 490 switch (opc) { 491 default: break; 492 case ISD::ADDE: 493 return PerformADDECombine(N, DAG, DCI, Subtarget); 494 case ISD::SUBE: 495 return PerformSUBECombine(N, DAG, DCI, Subtarget); 496 case ISD::SDIVREM: 497 case ISD::UDIVREM: 498 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 499 case ISD::SETCC: 500 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 501 } 502 503 return SDValue(); 504} 505 506SDValue MipsTargetLowering:: 507LowerOperation(SDValue Op, SelectionDAG &DAG) const 508{ 509 switch (Op.getOpcode()) 510 { 511 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 512 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 513 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 514 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 515 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 516 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 517 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 518 case ISD::SELECT: return LowerSELECT(Op, DAG); 519 case ISD::VASTART: return LowerVASTART(Op, DAG); 520 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 521 } 522 return SDValue(); 523} 524 525//===----------------------------------------------------------------------===// 526// Lower helper functions 527//===----------------------------------------------------------------------===// 528 529// AddLiveIn - This helper function adds the specified physical register to the 530// MachineFunction as a live in value. It also creates a corresponding 531// virtual register for it. 532static unsigned 533AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 534{ 535 assert(RC->contains(PReg) && "Not the correct regclass!"); 536 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 537 MF.getRegInfo().addLiveIn(PReg, VReg); 538 return VReg; 539} 540 541// Get fp branch code (not opcode) from condition code. 542static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 543 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 544 return Mips::BRANCH_T; 545 546 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 547 return Mips::BRANCH_F; 548 549 return Mips::BRANCH_INVALID; 550} 551 552MachineBasicBlock * 553MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 554 MachineBasicBlock *BB) const { 555 // There is no need to expand CMov instructions if target has 556 // conditional moves. 557 if (Subtarget->hasCondMov()) 558 return BB; 559 560 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 561 bool isFPCmp = false; 562 DebugLoc dl = MI->getDebugLoc(); 563 unsigned Opc; 564 565 switch (MI->getOpcode()) { 566 default: assert(false && "Unexpected instr type to insert"); 567 case Mips::MOVT: 568 case Mips::MOVT_S: 569 case Mips::MOVT_D: 570 isFPCmp = true; 571 Opc = Mips::BC1F; 572 break; 573 case Mips::MOVF: 574 case Mips::MOVF_S: 575 case Mips::MOVF_D: 576 isFPCmp = true; 577 Opc = Mips::BC1T; 578 break; 579 case Mips::MOVZ_I: 580 case Mips::MOVZ_S: 581 case Mips::MOVZ_D: 582 Opc = Mips::BNE; 583 break; 584 case Mips::MOVN_I: 585 case Mips::MOVN_S: 586 case Mips::MOVN_D: 587 Opc = Mips::BEQ; 588 break; 589 } 590 591 // To "insert" a SELECT_CC instruction, we actually have to insert the 592 // diamond control-flow pattern. The incoming instruction knows the 593 // destination vreg to set, the condition code register to branch on, the 594 // true/false values to select between, and a branch opcode to use. 595 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 596 MachineFunction::iterator It = BB; 597 ++It; 598 599 // thisMBB: 600 // ... 601 // TrueVal = ... 602 // setcc r1, r2, r3 603 // bNE r1, r0, copy1MBB 604 // fallthrough --> copy0MBB 605 MachineBasicBlock *thisMBB = BB; 606 MachineFunction *F = BB->getParent(); 607 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 608 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 609 F->insert(It, copy0MBB); 610 F->insert(It, sinkMBB); 611 612 // Transfer the remainder of BB and its successor edges to sinkMBB. 613 sinkMBB->splice(sinkMBB->begin(), BB, 614 llvm::next(MachineBasicBlock::iterator(MI)), 615 BB->end()); 616 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 617 618 // Next, add the true and fallthrough blocks as its successors. 619 BB->addSuccessor(copy0MBB); 620 BB->addSuccessor(sinkMBB); 621 622 // Emit the right instruction according to the type of the operands compared 623 if (isFPCmp) 624 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 625 else 626 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 627 .addReg(Mips::ZERO).addMBB(sinkMBB); 628 629 630 // copy0MBB: 631 // %FalseValue = ... 632 // # fallthrough to sinkMBB 633 BB = copy0MBB; 634 635 // Update machine-CFG edges 636 BB->addSuccessor(sinkMBB); 637 638 // sinkMBB: 639 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 640 // ... 641 BB = sinkMBB; 642 643 if (isFPCmp) 644 BuildMI(*BB, BB->begin(), dl, 645 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 646 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 647 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 648 else 649 BuildMI(*BB, BB->begin(), dl, 650 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 651 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 652 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 653 654 MI->eraseFromParent(); // The pseudo instruction is gone now. 655 return BB; 656} 657 658//===----------------------------------------------------------------------===// 659// Misc Lower Operation implementation 660//===----------------------------------------------------------------------===// 661SDValue MipsTargetLowering:: 662LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 663{ 664 unsigned StackAlignment = 665 getTargetMachine().getFrameLowering()->getStackAlignment(); 666 assert(StackAlignment >= 667 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 668 "Cannot lower if the alignment of the allocated space is larger than \ 669 that of the stack."); 670 671 SDValue Chain = Op.getOperand(0); 672 SDValue Size = Op.getOperand(1); 673 DebugLoc dl = Op.getDebugLoc(); 674 675 // Get a reference from Mips stack pointer 676 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 677 678 // Subtract the dynamic size from the actual stack size to 679 // obtain the new stack size. 680 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 681 682 // The Sub result contains the new stack start address, so it 683 // must be placed in the stack pointer register. 684 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, 685 SDValue()); 686 // Retrieve updated $sp. There is a glue input to prevent instructions that 687 // clobber $sp from being inserted between copytoreg and copyfromreg. 688 SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32, 689 Chain.getValue(1)); 690 691 // The stack space reserved by alloca is located right above the argument 692 // area. It is aligned on a boundary that is a multiple of StackAlignment. 693 MachineFunction &MF = DAG.getMachineFunction(); 694 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 695 unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) / 696 StackAlignment * StackAlignment; 697 SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 698 DAG.getConstant(SPOffset, MVT::i32)); 699 700 // This node always has two return values: a new stack pointer 701 // value and a chain 702 SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) }; 703 return DAG.getMergeValues(Ops, 2, dl); 704} 705 706SDValue MipsTargetLowering:: 707LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 708{ 709 // The first operand is the chain, the second is the condition, the third is 710 // the block to branch to if the condition is true. 711 SDValue Chain = Op.getOperand(0); 712 SDValue Dest = Op.getOperand(2); 713 DebugLoc dl = Op.getDebugLoc(); 714 715 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 716 717 // Return if flag is not set by a floating point comparison. 718 if (CondRes.getOpcode() != MipsISD::FPCmp) 719 return Op; 720 721 SDValue CCNode = CondRes.getOperand(2); 722 Mips::CondCode CC = 723 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 724 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 725 726 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 727 Dest, CondRes); 728} 729 730SDValue MipsTargetLowering:: 731LowerSELECT(SDValue Op, SelectionDAG &DAG) const 732{ 733 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 734 735 // Return if flag is not set by a floating point comparison. 736 if (Cond.getOpcode() != MipsISD::FPCmp) 737 return Op; 738 739 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 740 Op.getDebugLoc()); 741} 742 743SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 744 SelectionDAG &DAG) const { 745 // FIXME there isn't actually debug info here 746 DebugLoc dl = Op.getDebugLoc(); 747 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 748 749 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 750 SDVTList VTs = DAG.getVTList(MVT::i32); 751 752 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 753 754 // %gp_rel relocation 755 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 756 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 757 MipsII::MO_GPREL); 758 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 759 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 760 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 761 } 762 // %hi/%lo relocation 763 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 764 MipsII::MO_ABS_HI); 765 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 766 MipsII::MO_ABS_LO); 767 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 768 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 769 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 770 } else { 771 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 772 MipsII::MO_GOT); 773 SDValue ResNode = DAG.getLoad(MVT::i32, dl, 774 DAG.getEntryNode(), GA, MachinePointerInfo(), 775 false, false, 0); 776 // On functions and global targets not internal linked only 777 // a load from got/GP is necessary for PIC to work. 778 if (!GV->hasInternalLinkage() && 779 (!GV->hasLocalLinkage() || isa<Function>(GV))) 780 return ResNode; 781 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 782 MipsII::MO_ABS_LO); 783 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 784 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); 785 } 786 787 llvm_unreachable("Dont know how to handle GlobalAddress"); 788 return SDValue(0,0); 789} 790 791SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 792 SelectionDAG &DAG) const { 793 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 794 // FIXME there isn't actually debug info here 795 DebugLoc dl = Op.getDebugLoc(); 796 797 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 798 // %hi/%lo relocation 799 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 800 MipsII::MO_ABS_HI); 801 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 802 MipsII::MO_ABS_LO); 803 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 804 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 805 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 806 } 807 808 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 809 MipsII::MO_GOT); 810 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 811 MipsII::MO_ABS_LO); 812 SDValue Load = DAG.getLoad(MVT::i32, dl, 813 DAG.getEntryNode(), BAGOTOffset, 814 MachinePointerInfo(), false, false, 0); 815 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 816 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 817} 818 819SDValue MipsTargetLowering:: 820LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 821{ 822 llvm_unreachable("TLS not implemented for MIPS."); 823 return SDValue(); // Not reached 824} 825 826SDValue MipsTargetLowering:: 827LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 828{ 829 SDValue ResNode; 830 SDValue HiPart; 831 // FIXME there isn't actually debug info here 832 DebugLoc dl = Op.getDebugLoc(); 833 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 834 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 835 836 EVT PtrVT = Op.getValueType(); 837 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 838 839 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 840 841 if (!IsPIC) { 842 SDValue Ops[] = { JTI }; 843 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 844 } else // Emit Load from Global Pointer 845 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 846 MachinePointerInfo(), 847 false, false, 0); 848 849 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 850 MipsII::MO_ABS_LO); 851 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 852 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 853 854 return ResNode; 855} 856 857SDValue MipsTargetLowering:: 858LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 859{ 860 SDValue ResNode; 861 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 862 const Constant *C = N->getConstVal(); 863 // FIXME there isn't actually debug info here 864 DebugLoc dl = Op.getDebugLoc(); 865 866 // gp_rel relocation 867 // FIXME: we should reference the constant pool using small data sections, 868 // but the asm printer currently doesn't support this feature without 869 // hacking it. This feature should come soon so we can uncomment the 870 // stuff below. 871 //if (IsInSmallSection(C->getType())) { 872 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 873 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 874 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 875 876 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 877 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 878 N->getOffset(), MipsII::MO_ABS_HI); 879 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 880 N->getOffset(), MipsII::MO_ABS_LO); 881 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 882 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 883 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 884 } else { 885 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 886 N->getOffset(), MipsII::MO_GOT); 887 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 888 CP, MachinePointerInfo::getConstantPool(), 889 false, false, 0); 890 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 891 N->getOffset(), MipsII::MO_ABS_LO); 892 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 893 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 894 } 895 896 return ResNode; 897} 898 899SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 900 MachineFunction &MF = DAG.getMachineFunction(); 901 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 902 903 DebugLoc dl = Op.getDebugLoc(); 904 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 905 getPointerTy()); 906 907 // vastart just stores the address of the VarArgsFrameIndex slot into the 908 // memory location argument. 909 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 910 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 911 MachinePointerInfo(SV), 912 false, false, 0); 913} 914 915static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 916 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 917 DebugLoc dl = Op.getDebugLoc(); 918 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 919 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 920 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 921 DAG.getConstant(0x7fffffff, MVT::i32)); 922 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 923 DAG.getConstant(0x80000000, MVT::i32)); 924 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 925 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 926} 927 928static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 929 // FIXME: 930 // Use ext/ins instructions if target architecture is Mips32r2. 931 // Eliminate redundant mfc1 and mtc1 instructions. 932 unsigned LoIdx = 0, HiIdx = 1; 933 934 if (!isLittle) 935 std::swap(LoIdx, HiIdx); 936 937 DebugLoc dl = Op.getDebugLoc(); 938 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 939 Op.getOperand(0), 940 DAG.getConstant(LoIdx, MVT::i32)); 941 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 942 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 943 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 944 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 945 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 946 DAG.getConstant(0x7fffffff, MVT::i32)); 947 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 948 DAG.getConstant(0x80000000, MVT::i32)); 949 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 950 951 if (!isLittle) 952 std::swap(Word0, Word1); 953 954 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 955} 956 957SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 958 const { 959 EVT Ty = Op.getValueType(); 960 961 assert(Ty == MVT::f32 || Ty == MVT::f64); 962 963 if (Ty == MVT::f32) 964 return LowerFCOPYSIGN32(Op, DAG); 965 else 966 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 967} 968 969//===----------------------------------------------------------------------===// 970// Calling Convention Implementation 971//===----------------------------------------------------------------------===// 972 973#include "MipsGenCallingConv.inc" 974 975//===----------------------------------------------------------------------===// 976// TODO: Implement a generic logic using tblgen that can support this. 977// Mips O32 ABI rules: 978// --- 979// i32 - Passed in A0, A1, A2, A3 and stack 980// f32 - Only passed in f32 registers if no int reg has been used yet to hold 981// an argument. Otherwise, passed in A1, A2, A3 and stack. 982// f64 - Only passed in two aliased f32 registers if no int reg has been used 983// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 984// not used, it must be shadowed. If only A3 is avaiable, shadow it and 985// go to stack. 986// 987// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 988//===----------------------------------------------------------------------===// 989 990static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 991 MVT LocVT, CCValAssign::LocInfo LocInfo, 992 ISD::ArgFlagsTy ArgFlags, CCState &State) { 993 994 static const unsigned IntRegsSize=4, FloatRegsSize=2; 995 996 static const unsigned IntRegs[] = { 997 Mips::A0, Mips::A1, Mips::A2, Mips::A3 998 }; 999 static const unsigned F32Regs[] = { 1000 Mips::F12, Mips::F14 1001 }; 1002 static const unsigned F64Regs[] = { 1003 Mips::D6, Mips::D7 1004 }; 1005 1006 // ByVal Args 1007 if (ArgFlags.isByVal()) { 1008 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1009 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1010 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1011 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1012 r < std::min(IntRegsSize, NextReg); ++r) 1013 State.AllocateReg(IntRegs[r]); 1014 return false; 1015 } 1016 1017 // Promote i8 and i16 1018 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1019 LocVT = MVT::i32; 1020 if (ArgFlags.isSExt()) 1021 LocInfo = CCValAssign::SExt; 1022 else if (ArgFlags.isZExt()) 1023 LocInfo = CCValAssign::ZExt; 1024 else 1025 LocInfo = CCValAssign::AExt; 1026 } 1027 1028 unsigned Reg; 1029 1030 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1031 // is true: function is vararg, argument is 3rd or higher, there is previous 1032 // argument which is not f32 or f64. 1033 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1034 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1035 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1036 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1037 1038 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1039 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1040 // If this is the first part of an i64 arg, 1041 // the allocated register must be either A0 or A2. 1042 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1043 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1044 LocVT = MVT::i32; 1045 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1046 // Allocate int register and shadow next int register. If first 1047 // available register is Mips::A1 or Mips::A3, shadow it too. 1048 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1049 if (Reg == Mips::A1 || Reg == Mips::A3) 1050 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1051 State.AllocateReg(IntRegs, IntRegsSize); 1052 LocVT = MVT::i32; 1053 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1054 // we are guaranteed to find an available float register 1055 if (ValVT == MVT::f32) { 1056 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1057 // Shadow int register 1058 State.AllocateReg(IntRegs, IntRegsSize); 1059 } else { 1060 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1061 // Shadow int registers 1062 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1063 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1064 State.AllocateReg(IntRegs, IntRegsSize); 1065 State.AllocateReg(IntRegs, IntRegsSize); 1066 } 1067 } else 1068 llvm_unreachable("Cannot handle this ValVT."); 1069 1070 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1071 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1072 1073 if (!Reg) 1074 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1075 else 1076 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1077 1078 return false; // CC must always match 1079} 1080 1081//===----------------------------------------------------------------------===// 1082// Call Calling Convention Implementation 1083//===----------------------------------------------------------------------===// 1084 1085static const unsigned O32IntRegsSize = 4; 1086 1087static const unsigned O32IntRegs[] = { 1088 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1089}; 1090 1091// Write ByVal Arg to arg registers and stack. 1092static void 1093WriteByValArg(SDValue& Chain, DebugLoc dl, 1094 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1095 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1096 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1097 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1098 MVT PtrType) { 1099 unsigned FirstWord = VA.getLocMemOffset() / 4; 1100 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 1101 unsigned LastWord = FirstWord + NumWords; 1102 unsigned CurWord; 1103 1104 // copy the first 4 words of byval arg to registers A0 - A3 1105 for (CurWord = FirstWord; CurWord < std::min(LastWord, O32IntRegsSize); 1106 ++CurWord) { 1107 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1108 DAG.getConstant((CurWord - FirstWord) * 4, 1109 MVT::i32)); 1110 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1111 MachinePointerInfo(), 1112 false, false, 0); 1113 MemOpChains.push_back(LoadVal.getValue(1)); 1114 unsigned DstReg = O32IntRegs[CurWord]; 1115 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1116 } 1117 1118 // copy remaining part of byval arg to stack. 1119 if (CurWord < LastWord) { 1120 unsigned SizeInBytes = (LastWord - CurWord) * 4; 1121 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1122 DAG.getConstant((CurWord - FirstWord) * 4, 1123 MVT::i32)); 1124 LastFI = MFI->CreateFixedObject(SizeInBytes, CurWord * 4, true); 1125 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1126 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 1127 DAG.getConstant(SizeInBytes, MVT::i32), 1128 /*Align*/4, 1129 /*isVolatile=*/false, /*AlwaysInline=*/false, 1130 MachinePointerInfo(0), MachinePointerInfo(0)); 1131 MemOpChains.push_back(Chain); 1132 } 1133} 1134 1135/// LowerCall - functions arguments are copied from virtual regs to 1136/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1137/// TODO: isTailCall. 1138SDValue 1139MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1140 CallingConv::ID CallConv, bool isVarArg, 1141 bool &isTailCall, 1142 const SmallVectorImpl<ISD::OutputArg> &Outs, 1143 const SmallVectorImpl<SDValue> &OutVals, 1144 const SmallVectorImpl<ISD::InputArg> &Ins, 1145 DebugLoc dl, SelectionDAG &DAG, 1146 SmallVectorImpl<SDValue> &InVals) const { 1147 // MIPs target does not yet support tail call optimization. 1148 isTailCall = false; 1149 1150 MachineFunction &MF = DAG.getMachineFunction(); 1151 MachineFrameInfo *MFI = MF.getFrameInfo(); 1152 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1153 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1154 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1155 1156 // Analyze operands of the call, assigning locations to each operand. 1157 SmallVector<CCValAssign, 16> ArgLocs; 1158 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1159 *DAG.getContext()); 1160 1161 if (Subtarget->isABI_O32()) 1162 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1163 else 1164 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1165 1166 // Get a count of how many bytes are to be pushed on the stack. 1167 unsigned NumBytes = CCInfo.getNextStackOffset(); 1168 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1169 1170 // With EABI is it possible to have 16 args on registers. 1171 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1172 SmallVector<SDValue, 8> MemOpChains; 1173 1174 // If this is the first call, create a stack frame object that points to 1175 // a location to which .cprestore saves $gp. The offset of this frame object 1176 // is set to 0, since we know nothing about the size of the argument area at 1177 // this point. 1178 if (IsPIC && !MipsFI->getGPFI()) 1179 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1180 1181 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1182 1183 // Walk the register/memloc assignments, inserting copies/loads. 1184 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1185 SDValue Arg = OutVals[i]; 1186 CCValAssign &VA = ArgLocs[i]; 1187 1188 // Promote the value if needed. 1189 switch (VA.getLocInfo()) { 1190 default: llvm_unreachable("Unknown loc info!"); 1191 case CCValAssign::Full: 1192 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 1193 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 1194 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 1195 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 1196 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1197 Arg, DAG.getConstant(0, MVT::i32)); 1198 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1199 Arg, DAG.getConstant(1, MVT::i32)); 1200 if (!Subtarget->isLittle()) 1201 std::swap(Lo, Hi); 1202 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); 1203 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi)); 1204 continue; 1205 } 1206 } 1207 break; 1208 case CCValAssign::SExt: 1209 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1210 break; 1211 case CCValAssign::ZExt: 1212 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1213 break; 1214 case CCValAssign::AExt: 1215 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1216 break; 1217 } 1218 1219 // Arguments that can be passed on register must be kept at 1220 // RegsToPass vector 1221 if (VA.isRegLoc()) { 1222 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1223 continue; 1224 } 1225 1226 // Register can't get to this point... 1227 assert(VA.isMemLoc()); 1228 1229 // ByVal Arg. 1230 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1231 if (Flags.isByVal()) { 1232 assert(Subtarget->isABI_O32() && 1233 "No support for ByVal args by ABIs other than O32 yet."); 1234 assert(Flags.getByValSize() && 1235 "ByVal args of size 0 should have been ignored by front-end."); 1236 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg, 1237 VA, Flags, getPointerTy()); 1238 continue; 1239 } 1240 1241 // Create the frame index object for this incoming parameter 1242 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1243 VA.getLocMemOffset(), true); 1244 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 1245 1246 // emit ISD::STORE whichs stores the 1247 // parameter value to a stack Location 1248 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 1249 MachinePointerInfo(), 1250 false, false, 0)); 1251 } 1252 1253 // Transform all store nodes into one single node because all store 1254 // nodes are independent of each other. 1255 if (!MemOpChains.empty()) 1256 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1257 &MemOpChains[0], MemOpChains.size()); 1258 1259 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1260 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1261 // node so that legalize doesn't hack it. 1262 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 1263 bool LoadSymAddr = false; 1264 SDValue CalleeLo; 1265 1266 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1267 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 1268 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1269 getPointerTy(), 0,MipsII:: MO_GOT); 1270 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 1271 0, MipsII::MO_ABS_LO); 1272 } else { 1273 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1274 getPointerTy(), 0, OpFlag); 1275 } 1276 1277 LoadSymAddr = true; 1278 } 1279 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1280 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 1281 getPointerTy(), OpFlag); 1282 LoadSymAddr = true; 1283 } 1284 1285 SDValue InFlag; 1286 1287 // Create nodes that load address of callee and copy it to T9 1288 if (IsPIC) { 1289 if (LoadSymAddr) { 1290 // Load callee address 1291 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee, 1292 MachinePointerInfo::getGOT(), 1293 false, false, 0); 1294 1295 // Use GOT+LO if callee has internal linkage. 1296 if (CalleeLo.getNode()) { 1297 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 1298 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 1299 } else 1300 Callee = LoadValue; 1301 1302 // Use chain output from LoadValue 1303 Chain = LoadValue.getValue(1); 1304 } 1305 1306 // copy to T9 1307 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 1308 InFlag = Chain.getValue(1); 1309 Callee = DAG.getRegister(Mips::T9, MVT::i32); 1310 } 1311 1312 // Build a sequence of copy-to-reg nodes chained together with token 1313 // chain and flag operands which copy the outgoing args into registers. 1314 // The InFlag in necessary since all emitted instructions must be 1315 // stuck together. 1316 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1317 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1318 RegsToPass[i].second, InFlag); 1319 InFlag = Chain.getValue(1); 1320 } 1321 1322 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 1323 // = Chain, Callee, Reg#1, Reg#2, ... 1324 // 1325 // Returns a chain & a flag for retval copy to use. 1326 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1327 SmallVector<SDValue, 8> Ops; 1328 Ops.push_back(Chain); 1329 Ops.push_back(Callee); 1330 1331 // Add argument registers to the end of the list so that they are 1332 // known live into the call. 1333 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1334 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1335 RegsToPass[i].second.getValueType())); 1336 1337 if (InFlag.getNode()) 1338 Ops.push_back(InFlag); 1339 1340 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 1341 InFlag = Chain.getValue(1); 1342 1343 // Function can have an arbitrary number of calls, so 1344 // hold the LastArgStackLoc with the biggest offset. 1345 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1346 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1347 1348 // For O32, a minimum of four words (16 bytes) of argument space is 1349 // allocated. 1350 if (Subtarget->isABI_O32()) 1351 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1352 1353 if (MaxCallFrameSize < NextStackOffset) { 1354 MipsFI->setMaxCallFrameSize(NextStackOffset); 1355 1356 if (IsPIC) { 1357 // $gp restore slot must be aligned. 1358 unsigned StackAlignment = TFL->getStackAlignment(); 1359 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1360 StackAlignment * StackAlignment; 1361 int GPFI = MipsFI->getGPFI(); 1362 MFI->setObjectOffset(GPFI, NextStackOffset); 1363 } 1364 } 1365 1366 // Extend range of indices of frame objects for outgoing arguments that were 1367 // created during this function call. Skip this step if no such objects were 1368 // created. 1369 if (LastFI) 1370 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 1371 1372 // Create the CALLSEQ_END node. 1373 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1374 DAG.getIntPtrConstant(0, true), InFlag); 1375 InFlag = Chain.getValue(1); 1376 1377 // Handle result values, copying them out of physregs into vregs that we 1378 // return. 1379 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 1380 Ins, dl, DAG, InVals); 1381} 1382 1383/// LowerCallResult - Lower the result values of a call into the 1384/// appropriate copies out of appropriate physical registers. 1385SDValue 1386MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1387 CallingConv::ID CallConv, bool isVarArg, 1388 const SmallVectorImpl<ISD::InputArg> &Ins, 1389 DebugLoc dl, SelectionDAG &DAG, 1390 SmallVectorImpl<SDValue> &InVals) const { 1391 1392 // Assign locations to each value returned by this call. 1393 SmallVector<CCValAssign, 16> RVLocs; 1394 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1395 RVLocs, *DAG.getContext()); 1396 1397 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 1398 1399 // Copy all of the result registers out of their specified physreg. 1400 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1401 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 1402 RVLocs[i].getValVT(), InFlag).getValue(1); 1403 InFlag = Chain.getValue(2); 1404 InVals.push_back(Chain.getValue(0)); 1405 } 1406 1407 return Chain; 1408} 1409 1410//===----------------------------------------------------------------------===// 1411// Formal Arguments Calling Convention Implementation 1412//===----------------------------------------------------------------------===// 1413static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 1414 std::vector<SDValue>& OutChains, 1415 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 1416 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 1417 unsigned LocMem = VA.getLocMemOffset(); 1418 unsigned FirstWord = LocMem / 4; 1419 1420 // copy register A0 - A3 to frame object 1421 for (unsigned i = 0; i < NumWords; ++i) { 1422 unsigned CurWord = FirstWord + i; 1423 if (CurWord >= O32IntRegsSize) 1424 break; 1425 1426 unsigned SrcReg = O32IntRegs[CurWord]; 1427 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 1428 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 1429 DAG.getConstant(i * 4, MVT::i32)); 1430 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 1431 StorePtr, MachinePointerInfo(), false, 1432 false, 0); 1433 OutChains.push_back(Store); 1434 } 1435} 1436 1437/// LowerFormalArguments - transform physical registers into virtual registers 1438/// and generate load operations for arguments places on the stack. 1439SDValue 1440MipsTargetLowering::LowerFormalArguments(SDValue Chain, 1441 CallingConv::ID CallConv, 1442 bool isVarArg, 1443 const SmallVectorImpl<ISD::InputArg> 1444 &Ins, 1445 DebugLoc dl, SelectionDAG &DAG, 1446 SmallVectorImpl<SDValue> &InVals) 1447 const { 1448 MachineFunction &MF = DAG.getMachineFunction(); 1449 MachineFrameInfo *MFI = MF.getFrameInfo(); 1450 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1451 1452 MipsFI->setVarArgsFrameIndex(0); 1453 1454 // Used with vargs to acumulate store chains. 1455 std::vector<SDValue> OutChains; 1456 1457 // Assign locations to all of the incoming arguments. 1458 SmallVector<CCValAssign, 16> ArgLocs; 1459 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1460 ArgLocs, *DAG.getContext()); 1461 1462 if (Subtarget->isABI_O32()) 1463 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 1464 else 1465 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 1466 1467 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 1468 1469 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1470 CCValAssign &VA = ArgLocs[i]; 1471 1472 // Arguments stored on registers 1473 if (VA.isRegLoc()) { 1474 EVT RegVT = VA.getLocVT(); 1475 unsigned ArgReg = VA.getLocReg(); 1476 TargetRegisterClass *RC = 0; 1477 1478 if (RegVT == MVT::i32) 1479 RC = Mips::CPURegsRegisterClass; 1480 else if (RegVT == MVT::f32) 1481 RC = Mips::FGR32RegisterClass; 1482 else if (RegVT == MVT::f64) { 1483 if (!Subtarget->isSingleFloat()) 1484 RC = Mips::AFGR64RegisterClass; 1485 } else 1486 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 1487 1488 // Transform the arguments stored on 1489 // physical registers into virtual ones 1490 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 1491 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1492 1493 // If this is an 8 or 16-bit value, it has been passed promoted 1494 // to 32 bits. Insert an assert[sz]ext to capture this, then 1495 // truncate to the right size. 1496 if (VA.getLocInfo() != CCValAssign::Full) { 1497 unsigned Opcode = 0; 1498 if (VA.getLocInfo() == CCValAssign::SExt) 1499 Opcode = ISD::AssertSext; 1500 else if (VA.getLocInfo() == CCValAssign::ZExt) 1501 Opcode = ISD::AssertZext; 1502 if (Opcode) 1503 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 1504 DAG.getValueType(VA.getValVT())); 1505 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1506 } 1507 1508 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 1509 if (Subtarget->isABI_O32()) { 1510 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 1511 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 1512 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 1513 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 1514 VA.getLocReg()+1, RC); 1515 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 1516 if (!Subtarget->isLittle()) 1517 std::swap(ArgValue, ArgValue2); 1518 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 1519 ArgValue, ArgValue2); 1520 } 1521 } 1522 1523 InVals.push_back(ArgValue); 1524 } else { // VA.isRegLoc() 1525 1526 // sanity check 1527 assert(VA.isMemLoc()); 1528 1529 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1530 1531 if (Flags.isByVal()) { 1532 assert(Subtarget->isABI_O32() && 1533 "No support for ByVal args by ABIs other than O32 yet."); 1534 assert(Flags.getByValSize() && 1535 "ByVal args of size 0 should have been ignored by front-end."); 1536 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 1537 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 1538 true); 1539 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 1540 InVals.push_back(FIN); 1541 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 1542 1543 continue; 1544 } 1545 1546 // The stack pointer offset is relative to the caller stack frame. 1547 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1548 VA.getLocMemOffset(), true); 1549 1550 // Create load nodes to retrieve arguments from the stack 1551 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 1552 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1553 MachinePointerInfo::getFixedStack(LastFI), 1554 false, false, 0)); 1555 } 1556 } 1557 1558 // The mips ABIs for returning structs by value requires that we copy 1559 // the sret argument into $v0 for the return. Save the argument into 1560 // a virtual register so that we can access it from the return points. 1561 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1562 unsigned Reg = MipsFI->getSRetReturnReg(); 1563 if (!Reg) { 1564 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 1565 MipsFI->setSRetReturnReg(Reg); 1566 } 1567 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1568 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1569 } 1570 1571 if (isVarArg && Subtarget->isABI_O32()) { 1572 // Record the frame index of the first variable argument 1573 // which is a value necessary to VASTART. 1574 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1575 assert(NextStackOffset % 4 == 0 && 1576 "NextStackOffset must be aligned to 4-byte boundaries."); 1577 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 1578 MipsFI->setVarArgsFrameIndex(LastFI); 1579 1580 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 1581 // copy the integer registers that have not been used for argument passing 1582 // to the caller's stack frame. 1583 for (; NextStackOffset < 16; NextStackOffset += 4) { 1584 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 1585 unsigned Idx = NextStackOffset / 4; 1586 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 1587 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 1588 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 1589 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 1590 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 1591 MachinePointerInfo(), 1592 false, false, 0)); 1593 } 1594 } 1595 1596 MipsFI->setLastInArgFI(LastFI); 1597 1598 // All stores are grouped in one node to allow the matching between 1599 // the size of Ins and InVals. This only happens when on varg functions 1600 if (!OutChains.empty()) { 1601 OutChains.push_back(Chain); 1602 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1603 &OutChains[0], OutChains.size()); 1604 } 1605 1606 return Chain; 1607} 1608 1609//===----------------------------------------------------------------------===// 1610// Return Value Calling Convention Implementation 1611//===----------------------------------------------------------------------===// 1612 1613SDValue 1614MipsTargetLowering::LowerReturn(SDValue Chain, 1615 CallingConv::ID CallConv, bool isVarArg, 1616 const SmallVectorImpl<ISD::OutputArg> &Outs, 1617 const SmallVectorImpl<SDValue> &OutVals, 1618 DebugLoc dl, SelectionDAG &DAG) const { 1619 1620 // CCValAssign - represent the assignment of 1621 // the return value to a location 1622 SmallVector<CCValAssign, 16> RVLocs; 1623 1624 // CCState - Info about the registers and stack slot. 1625 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1626 RVLocs, *DAG.getContext()); 1627 1628 // Analize return values. 1629 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 1630 1631 // If this is the first return lowered for this function, add 1632 // the regs to the liveout set for the function. 1633 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1634 for (unsigned i = 0; i != RVLocs.size(); ++i) 1635 if (RVLocs[i].isRegLoc()) 1636 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1637 } 1638 1639 SDValue Flag; 1640 1641 // Copy the result values into the output registers. 1642 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1643 CCValAssign &VA = RVLocs[i]; 1644 assert(VA.isRegLoc() && "Can only return in registers!"); 1645 1646 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1647 OutVals[i], Flag); 1648 1649 // guarantee that all emitted copies are 1650 // stuck together, avoiding something bad 1651 Flag = Chain.getValue(1); 1652 } 1653 1654 // The mips ABIs for returning structs by value requires that we copy 1655 // the sret argument into $v0 for the return. We saved the argument into 1656 // a virtual register in the entry block, so now we copy the value out 1657 // and into $v0. 1658 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1659 MachineFunction &MF = DAG.getMachineFunction(); 1660 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1661 unsigned Reg = MipsFI->getSRetReturnReg(); 1662 1663 if (!Reg) 1664 llvm_unreachable("sret virtual register not created in the entry block"); 1665 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1666 1667 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 1668 Flag = Chain.getValue(1); 1669 } 1670 1671 // Return on Mips is always a "jr $ra" 1672 if (Flag.getNode()) 1673 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 1674 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 1675 else // Return Void 1676 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 1677 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 1678} 1679 1680//===----------------------------------------------------------------------===// 1681// Mips Inline Assembly Support 1682//===----------------------------------------------------------------------===// 1683 1684/// getConstraintType - Given a constraint letter, return the type of 1685/// constraint it is for this target. 1686MipsTargetLowering::ConstraintType MipsTargetLowering:: 1687getConstraintType(const std::string &Constraint) const 1688{ 1689 // Mips specific constrainy 1690 // GCC config/mips/constraints.md 1691 // 1692 // 'd' : An address register. Equivalent to r 1693 // unless generating MIPS16 code. 1694 // 'y' : Equivalent to r; retained for 1695 // backwards compatibility. 1696 // 'f' : Floating Point registers. 1697 if (Constraint.size() == 1) { 1698 switch (Constraint[0]) { 1699 default : break; 1700 case 'd': 1701 case 'y': 1702 case 'f': 1703 return C_RegisterClass; 1704 break; 1705 } 1706 } 1707 return TargetLowering::getConstraintType(Constraint); 1708} 1709 1710/// Examine constraint type and operand type and determine a weight value. 1711/// This object must already have been set up with the operand type 1712/// and the current alternative constraint selected. 1713TargetLowering::ConstraintWeight 1714MipsTargetLowering::getSingleConstraintMatchWeight( 1715 AsmOperandInfo &info, const char *constraint) const { 1716 ConstraintWeight weight = CW_Invalid; 1717 Value *CallOperandVal = info.CallOperandVal; 1718 // If we don't have a value, we can't do a match, 1719 // but allow it at the lowest weight. 1720 if (CallOperandVal == NULL) 1721 return CW_Default; 1722 const Type *type = CallOperandVal->getType(); 1723 // Look at the constraint type. 1724 switch (*constraint) { 1725 default: 1726 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1727 break; 1728 case 'd': 1729 case 'y': 1730 if (type->isIntegerTy()) 1731 weight = CW_Register; 1732 break; 1733 case 'f': 1734 if (type->isFloatTy()) 1735 weight = CW_Register; 1736 break; 1737 } 1738 return weight; 1739} 1740 1741/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1742/// return a list of registers that can be used to satisfy the constraint. 1743/// This should only be used for C_RegisterClass constraints. 1744std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 1745getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 1746{ 1747 if (Constraint.size() == 1) { 1748 switch (Constraint[0]) { 1749 case 'r': 1750 return std::make_pair(0U, Mips::CPURegsRegisterClass); 1751 case 'f': 1752 if (VT == MVT::f32) 1753 return std::make_pair(0U, Mips::FGR32RegisterClass); 1754 if (VT == MVT::f64) 1755 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1756 return std::make_pair(0U, Mips::AFGR64RegisterClass); 1757 } 1758 } 1759 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1760} 1761 1762/// Given a register class constraint, like 'r', if this corresponds directly 1763/// to an LLVM register class, return a register of 0 and the register class 1764/// pointer. 1765std::vector<unsigned> MipsTargetLowering:: 1766getRegClassForInlineAsmConstraint(const std::string &Constraint, 1767 EVT VT) const 1768{ 1769 if (Constraint.size() != 1) 1770 return std::vector<unsigned>(); 1771 1772 switch (Constraint[0]) { 1773 default : break; 1774 case 'r': 1775 // GCC Mips Constraint Letters 1776 case 'd': 1777 case 'y': 1778 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3, 1779 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, 1780 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, 1781 Mips::T8, 0); 1782 1783 case 'f': 1784 if (VT == MVT::f32) { 1785 if (Subtarget->isSingleFloat()) 1786 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5, 1787 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, 1788 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, 1789 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, 1790 Mips::F30, Mips::F31, 0); 1791 else 1792 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8, 1793 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26, 1794 Mips::F28, Mips::F30, 0); 1795 } 1796 1797 if (VT == MVT::f64) 1798 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1799 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4, 1800 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13, 1801 Mips::D14, Mips::D15, 0); 1802 } 1803 return std::vector<unsigned>(); 1804} 1805 1806bool 1807MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1808 // The Mips target isn't yet aware of offsets. 1809 return false; 1810} 1811 1812bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 1813 if (VT != MVT::f32 && VT != MVT::f64) 1814 return false; 1815 if (Imm.isNegZero()) 1816 return false; 1817 return Imm.isZero(); 1818} 1819