MipsISelLowering.cpp revision 44d23825d61d530b8d562329ec8fc2d4f843bb8d
1//=== --MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/CallingConv.h" 26#include "InstPrinter/MipsInstPrinter.h" 27#include "MCTargetDesc/MipsBaseInfo.h" 28#include "llvm/CodeGen/CallingConvLower.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAGISel.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37using namespace llvm; 38 39// If I is a shifted mask, set the size (Size) and the first bit of the 40// mask (Pos), and return true. 41// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 42static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 43 if (!isShiftedMask_64(I)) 44 return false; 45 46 Size = CountPopulation_64(I); 47 Pos = CountTrailingZeros_64(I); 48 return true; 49} 50 51const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 52 switch (Opcode) { 53 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 54 case MipsISD::Hi: return "MipsISD::Hi"; 55 case MipsISD::Lo: return "MipsISD::Lo"; 56 case MipsISD::GPRel: return "MipsISD::GPRel"; 57 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 58 case MipsISD::Ret: return "MipsISD::Ret"; 59 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 60 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 61 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 62 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 63 case MipsISD::FPRound: return "MipsISD::FPRound"; 64 case MipsISD::MAdd: return "MipsISD::MAdd"; 65 case MipsISD::MAddu: return "MipsISD::MAddu"; 66 case MipsISD::MSub: return "MipsISD::MSub"; 67 case MipsISD::MSubu: return "MipsISD::MSubu"; 68 case MipsISD::DivRem: return "MipsISD::DivRem"; 69 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 70 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 71 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 72 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 73 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 74 case MipsISD::Sync: return "MipsISD::Sync"; 75 case MipsISD::Ext: return "MipsISD::Ext"; 76 case MipsISD::Ins: return "MipsISD::Ins"; 77 default: return NULL; 78 } 79} 80 81MipsTargetLowering:: 82MipsTargetLowering(MipsTargetMachine &TM) 83 : TargetLowering(TM, new MipsTargetObjectFile()), 84 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 85 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 86 IsO32(Subtarget->isABI_O32()) { 87 88 // Mips does not have i1 type, so use i32 for 89 // setcc operations results (slt, sgt, ...). 90 setBooleanContents(ZeroOrOneBooleanContent); 91 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 92 93 // Set up the register classes 94 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 95 96 if (HasMips64) 97 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); 98 99 if (!TM.Options.UseSoftFloat) { 100 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 101 102 // When dealing with single precision only, use libcalls 103 if (!Subtarget->isSingleFloat()) { 104 if (HasMips64) 105 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); 106 else 107 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 108 } 109 } 110 111 // Load extented operations for i1 types must be promoted 112 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 113 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 114 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 115 116 // MIPS doesn't have extending float->double load/store 117 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 118 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 119 120 // Used by legalize types to correctly generate the setcc result. 121 // Without this, every float setcc comes with a AND/OR with the result, 122 // we don't want this, since the fpcmp result goes to a flag register, 123 // which is used implicitly by brcond and select operations. 124 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 125 126 // Mips Custom Operations 127 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 128 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 129 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 130 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 131 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 132 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 133 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 134 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 135 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 136 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 137 setOperationAction(ISD::SELECT, MVT::f32, Custom); 138 setOperationAction(ISD::SELECT, MVT::f64, Custom); 139 setOperationAction(ISD::SELECT, MVT::i32, Custom); 140 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 141 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 142 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 143 setOperationAction(ISD::VASTART, MVT::Other, Custom); 144 145 setOperationAction(ISD::SDIV, MVT::i32, Expand); 146 setOperationAction(ISD::SREM, MVT::i32, Expand); 147 setOperationAction(ISD::UDIV, MVT::i32, Expand); 148 setOperationAction(ISD::UREM, MVT::i32, Expand); 149 setOperationAction(ISD::SDIV, MVT::i64, Expand); 150 setOperationAction(ISD::SREM, MVT::i64, Expand); 151 setOperationAction(ISD::UDIV, MVT::i64, Expand); 152 setOperationAction(ISD::UREM, MVT::i64, Expand); 153 154 // Operations not directly supported by Mips. 155 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 156 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 157 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 158 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 159 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 160 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 161 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 163 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 164 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 165 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 166 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 167 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 168 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 169 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 170 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 171 setOperationAction(ISD::ROTL, MVT::i32, Expand); 172 setOperationAction(ISD::ROTL, MVT::i64, Expand); 173 174 if (!Subtarget->hasMips32r2()) 175 setOperationAction(ISD::ROTR, MVT::i32, Expand); 176 177 if (!Subtarget->hasMips64r2()) 178 setOperationAction(ISD::ROTR, MVT::i64, Expand); 179 180 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 181 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 182 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 183 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 184 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 185 setOperationAction(ISD::FSIN, MVT::f32, Expand); 186 setOperationAction(ISD::FSIN, MVT::f64, Expand); 187 setOperationAction(ISD::FCOS, MVT::f32, Expand); 188 setOperationAction(ISD::FCOS, MVT::f64, Expand); 189 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 190 setOperationAction(ISD::FPOW, MVT::f32, Expand); 191 setOperationAction(ISD::FPOW, MVT::f64, Expand); 192 setOperationAction(ISD::FLOG, MVT::f32, Expand); 193 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 194 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 195 setOperationAction(ISD::FEXP, MVT::f32, Expand); 196 setOperationAction(ISD::FMA, MVT::f32, Expand); 197 setOperationAction(ISD::FMA, MVT::f64, Expand); 198 199 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 200 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 201 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 202 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 203 204 setOperationAction(ISD::VAARG, MVT::Other, Expand); 205 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 206 setOperationAction(ISD::VAEND, MVT::Other, Expand); 207 208 // Use the default for now 209 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 210 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 211 212 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 213 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 214 215 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 216 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 217 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 218 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 219 220 setInsertFencesForAtomic(true); 221 222 if (Subtarget->isSingleFloat()) 223 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 224 225 if (!Subtarget->hasSEInReg()) { 226 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 227 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 228 } 229 230 if (!Subtarget->hasBitCount()) { 231 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 232 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 233 } 234 235 if (!Subtarget->hasSwap()) { 236 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 237 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 238 } 239 240 setTargetDAGCombine(ISD::ADDE); 241 setTargetDAGCombine(ISD::SUBE); 242 setTargetDAGCombine(ISD::SDIVREM); 243 setTargetDAGCombine(ISD::UDIVREM); 244 setTargetDAGCombine(ISD::SETCC); 245 setTargetDAGCombine(ISD::AND); 246 setTargetDAGCombine(ISD::OR); 247 248 setMinFunctionAlignment(2); 249 250 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 251 computeRegisterProperties(); 252 253 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 254 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 255} 256 257bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 258 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 259 return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16; 260} 261 262EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 263 return MVT::i32; 264} 265 266// SelectMadd - 267// Transforms a subgraph in CurDAG if the following pattern is found: 268// (addc multLo, Lo0), (adde multHi, Hi0), 269// where, 270// multHi/Lo: product of multiplication 271// Lo0: initial value of Lo register 272// Hi0: initial value of Hi register 273// Return true if pattern matching was successful. 274static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 275 // ADDENode's second operand must be a flag output of an ADDC node in order 276 // for the matching to be successful. 277 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 278 279 if (ADDCNode->getOpcode() != ISD::ADDC) 280 return false; 281 282 SDValue MultHi = ADDENode->getOperand(0); 283 SDValue MultLo = ADDCNode->getOperand(0); 284 SDNode* MultNode = MultHi.getNode(); 285 unsigned MultOpc = MultHi.getOpcode(); 286 287 // MultHi and MultLo must be generated by the same node, 288 if (MultLo.getNode() != MultNode) 289 return false; 290 291 // and it must be a multiplication. 292 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 293 return false; 294 295 // MultLo amd MultHi must be the first and second output of MultNode 296 // respectively. 297 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 298 return false; 299 300 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 301 // of the values of MultNode, in which case MultNode will be removed in later 302 // phases. 303 // If there exist users other than ADDENode or ADDCNode, this function returns 304 // here, which will result in MultNode being mapped to a single MULT 305 // instruction node rather than a pair of MULT and MADD instructions being 306 // produced. 307 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 308 return false; 309 310 SDValue Chain = CurDAG->getEntryNode(); 311 DebugLoc dl = ADDENode->getDebugLoc(); 312 313 // create MipsMAdd(u) node 314 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 315 316 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 317 MultNode->getOperand(0),// Factor 0 318 MultNode->getOperand(1),// Factor 1 319 ADDCNode->getOperand(1),// Lo0 320 ADDENode->getOperand(1));// Hi0 321 322 // create CopyFromReg nodes 323 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 324 MAdd); 325 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 326 Mips::HI, MVT::i32, 327 CopyFromLo.getValue(2)); 328 329 // replace uses of adde and addc here 330 if (!SDValue(ADDCNode, 0).use_empty()) 331 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 332 333 if (!SDValue(ADDENode, 0).use_empty()) 334 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 335 336 return true; 337} 338 339// SelectMsub - 340// Transforms a subgraph in CurDAG if the following pattern is found: 341// (addc Lo0, multLo), (sube Hi0, multHi), 342// where, 343// multHi/Lo: product of multiplication 344// Lo0: initial value of Lo register 345// Hi0: initial value of Hi register 346// Return true if pattern matching was successful. 347static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 348 // SUBENode's second operand must be a flag output of an SUBC node in order 349 // for the matching to be successful. 350 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 351 352 if (SUBCNode->getOpcode() != ISD::SUBC) 353 return false; 354 355 SDValue MultHi = SUBENode->getOperand(1); 356 SDValue MultLo = SUBCNode->getOperand(1); 357 SDNode* MultNode = MultHi.getNode(); 358 unsigned MultOpc = MultHi.getOpcode(); 359 360 // MultHi and MultLo must be generated by the same node, 361 if (MultLo.getNode() != MultNode) 362 return false; 363 364 // and it must be a multiplication. 365 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 366 return false; 367 368 // MultLo amd MultHi must be the first and second output of MultNode 369 // respectively. 370 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 371 return false; 372 373 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 374 // of the values of MultNode, in which case MultNode will be removed in later 375 // phases. 376 // If there exist users other than SUBENode or SUBCNode, this function returns 377 // here, which will result in MultNode being mapped to a single MULT 378 // instruction node rather than a pair of MULT and MSUB instructions being 379 // produced. 380 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 381 return false; 382 383 SDValue Chain = CurDAG->getEntryNode(); 384 DebugLoc dl = SUBENode->getDebugLoc(); 385 386 // create MipsSub(u) node 387 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 388 389 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 390 MultNode->getOperand(0),// Factor 0 391 MultNode->getOperand(1),// Factor 1 392 SUBCNode->getOperand(0),// Lo0 393 SUBENode->getOperand(0));// Hi0 394 395 // create CopyFromReg nodes 396 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 397 MSub); 398 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 399 Mips::HI, MVT::i32, 400 CopyFromLo.getValue(2)); 401 402 // replace uses of sube and subc here 403 if (!SDValue(SUBCNode, 0).use_empty()) 404 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 405 406 if (!SDValue(SUBENode, 0).use_empty()) 407 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 408 409 return true; 410} 411 412static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 413 TargetLowering::DAGCombinerInfo &DCI, 414 const MipsSubtarget* Subtarget) { 415 if (DCI.isBeforeLegalize()) 416 return SDValue(); 417 418 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 419 SelectMadd(N, &DAG)) 420 return SDValue(N, 0); 421 422 return SDValue(); 423} 424 425static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 426 TargetLowering::DAGCombinerInfo &DCI, 427 const MipsSubtarget* Subtarget) { 428 if (DCI.isBeforeLegalize()) 429 return SDValue(); 430 431 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 432 SelectMsub(N, &DAG)) 433 return SDValue(N, 0); 434 435 return SDValue(); 436} 437 438static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 439 TargetLowering::DAGCombinerInfo &DCI, 440 const MipsSubtarget* Subtarget) { 441 if (DCI.isBeforeLegalizeOps()) 442 return SDValue(); 443 444 EVT Ty = N->getValueType(0); 445 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 446 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 447 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 448 MipsISD::DivRemU; 449 DebugLoc dl = N->getDebugLoc(); 450 451 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 452 N->getOperand(0), N->getOperand(1)); 453 SDValue InChain = DAG.getEntryNode(); 454 SDValue InGlue = DivRem; 455 456 // insert MFLO 457 if (N->hasAnyUseOfValue(0)) { 458 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 459 InGlue); 460 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 461 InChain = CopyFromLo.getValue(1); 462 InGlue = CopyFromLo.getValue(2); 463 } 464 465 // insert MFHI 466 if (N->hasAnyUseOfValue(1)) { 467 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 468 HI, Ty, InGlue); 469 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 470 } 471 472 return SDValue(); 473} 474 475static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 476 switch (CC) { 477 default: llvm_unreachable("Unknown fp condition code!"); 478 case ISD::SETEQ: 479 case ISD::SETOEQ: return Mips::FCOND_OEQ; 480 case ISD::SETUNE: return Mips::FCOND_UNE; 481 case ISD::SETLT: 482 case ISD::SETOLT: return Mips::FCOND_OLT; 483 case ISD::SETGT: 484 case ISD::SETOGT: return Mips::FCOND_OGT; 485 case ISD::SETLE: 486 case ISD::SETOLE: return Mips::FCOND_OLE; 487 case ISD::SETGE: 488 case ISD::SETOGE: return Mips::FCOND_OGE; 489 case ISD::SETULT: return Mips::FCOND_ULT; 490 case ISD::SETULE: return Mips::FCOND_ULE; 491 case ISD::SETUGT: return Mips::FCOND_UGT; 492 case ISD::SETUGE: return Mips::FCOND_UGE; 493 case ISD::SETUO: return Mips::FCOND_UN; 494 case ISD::SETO: return Mips::FCOND_OR; 495 case ISD::SETNE: 496 case ISD::SETONE: return Mips::FCOND_ONE; 497 case ISD::SETUEQ: return Mips::FCOND_UEQ; 498 } 499} 500 501 502// Returns true if condition code has to be inverted. 503static bool InvertFPCondCode(Mips::CondCode CC) { 504 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 505 return false; 506 507 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 508 "Illegal Condition Code"); 509 510 return true; 511} 512 513// Creates and returns an FPCmp node from a setcc node. 514// Returns Op if setcc is not a floating point comparison. 515static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 516 // must be a SETCC node 517 if (Op.getOpcode() != ISD::SETCC) 518 return Op; 519 520 SDValue LHS = Op.getOperand(0); 521 522 if (!LHS.getValueType().isFloatingPoint()) 523 return Op; 524 525 SDValue RHS = Op.getOperand(1); 526 DebugLoc dl = Op.getDebugLoc(); 527 528 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 529 // node if necessary. 530 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 531 532 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 533 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 534} 535 536// Creates and returns a CMovFPT/F node. 537static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 538 SDValue False, DebugLoc DL) { 539 bool invert = InvertFPCondCode((Mips::CondCode) 540 cast<ConstantSDNode>(Cond.getOperand(2)) 541 ->getSExtValue()); 542 543 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 544 True.getValueType(), True, False, Cond); 545} 546 547static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 548 TargetLowering::DAGCombinerInfo &DCI, 549 const MipsSubtarget* Subtarget) { 550 if (DCI.isBeforeLegalizeOps()) 551 return SDValue(); 552 553 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 554 555 if (Cond.getOpcode() != MipsISD::FPCmp) 556 return SDValue(); 557 558 SDValue True = DAG.getConstant(1, MVT::i32); 559 SDValue False = DAG.getConstant(0, MVT::i32); 560 561 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 562} 563 564static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 565 TargetLowering::DAGCombinerInfo &DCI, 566 const MipsSubtarget* Subtarget) { 567 // Pattern match EXT. 568 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 569 // => ext $dst, $src, size, pos 570 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 571 return SDValue(); 572 573 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 574 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 575 576 // Op's first operand must be a shift right. 577 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 578 return SDValue(); 579 580 // The second operand of the shift must be an immediate. 581 ConstantSDNode *CN; 582 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 583 return SDValue(); 584 585 uint64_t Pos = CN->getZExtValue(); 586 uint64_t SMPos, SMSize; 587 588 // Op's second operand must be a shifted mask. 589 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 590 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 591 return SDValue(); 592 593 // Return if the shifted mask does not start at bit 0 or the sum of its size 594 // and Pos exceeds the word's size. 595 EVT ValTy = N->getValueType(0); 596 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 597 return SDValue(); 598 599 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 600 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 601 DAG.getConstant(SMSize, MVT::i32)); 602} 603 604static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 605 TargetLowering::DAGCombinerInfo &DCI, 606 const MipsSubtarget* Subtarget) { 607 // Pattern match INS. 608 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 609 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 610 // => ins $dst, $src, size, pos, $src1 611 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 612 return SDValue(); 613 614 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 615 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 616 ConstantSDNode *CN; 617 618 // See if Op's first operand matches (and $src1 , mask0). 619 if (And0.getOpcode() != ISD::AND) 620 return SDValue(); 621 622 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 623 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 624 return SDValue(); 625 626 // See if Op's second operand matches (and (shl $src, pos), mask1). 627 if (And1.getOpcode() != ISD::AND) 628 return SDValue(); 629 630 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 631 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 632 return SDValue(); 633 634 // The shift masks must have the same position and size. 635 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 636 return SDValue(); 637 638 SDValue Shl = And1.getOperand(0); 639 if (Shl.getOpcode() != ISD::SHL) 640 return SDValue(); 641 642 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 643 return SDValue(); 644 645 unsigned Shamt = CN->getZExtValue(); 646 647 // Return if the shift amount and the first bit position of mask are not the 648 // same. 649 EVT ValTy = N->getValueType(0); 650 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 651 return SDValue(); 652 653 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 654 DAG.getConstant(SMPos0, MVT::i32), 655 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 656} 657 658SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 659 const { 660 SelectionDAG &DAG = DCI.DAG; 661 unsigned opc = N->getOpcode(); 662 663 switch (opc) { 664 default: break; 665 case ISD::ADDE: 666 return PerformADDECombine(N, DAG, DCI, Subtarget); 667 case ISD::SUBE: 668 return PerformSUBECombine(N, DAG, DCI, Subtarget); 669 case ISD::SDIVREM: 670 case ISD::UDIVREM: 671 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 672 case ISD::SETCC: 673 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 674 case ISD::AND: 675 return PerformANDCombine(N, DAG, DCI, Subtarget); 676 case ISD::OR: 677 return PerformORCombine(N, DAG, DCI, Subtarget); 678 } 679 680 return SDValue(); 681} 682 683SDValue MipsTargetLowering:: 684LowerOperation(SDValue Op, SelectionDAG &DAG) const 685{ 686 switch (Op.getOpcode()) 687 { 688 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 689 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 690 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 691 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 692 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 693 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 694 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 695 case ISD::SELECT: return LowerSELECT(Op, DAG); 696 case ISD::VASTART: return LowerVASTART(Op, DAG); 697 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 698 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 699 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 700 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 701 } 702 return SDValue(); 703} 704 705//===----------------------------------------------------------------------===// 706// Lower helper functions 707//===----------------------------------------------------------------------===// 708 709// AddLiveIn - This helper function adds the specified physical register to the 710// MachineFunction as a live in value. It also creates a corresponding 711// virtual register for it. 712static unsigned 713AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 714{ 715 assert(RC->contains(PReg) && "Not the correct regclass!"); 716 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 717 MF.getRegInfo().addLiveIn(PReg, VReg); 718 return VReg; 719} 720 721// Get fp branch code (not opcode) from condition code. 722static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 723 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 724 return Mips::BRANCH_T; 725 726 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 727 "Invalid CondCode."); 728 729 return Mips::BRANCH_F; 730} 731 732/* 733static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 734 DebugLoc dl, 735 const MipsSubtarget* Subtarget, 736 const TargetInstrInfo *TII, 737 bool isFPCmp, unsigned Opc) { 738 // There is no need to expand CMov instructions if target has 739 // conditional moves. 740 if (Subtarget->hasCondMov()) 741 return BB; 742 743 // To "insert" a SELECT_CC instruction, we actually have to insert the 744 // diamond control-flow pattern. The incoming instruction knows the 745 // destination vreg to set, the condition code register to branch on, the 746 // true/false values to select between, and a branch opcode to use. 747 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 748 MachineFunction::iterator It = BB; 749 ++It; 750 751 // thisMBB: 752 // ... 753 // TrueVal = ... 754 // setcc r1, r2, r3 755 // bNE r1, r0, copy1MBB 756 // fallthrough --> copy0MBB 757 MachineBasicBlock *thisMBB = BB; 758 MachineFunction *F = BB->getParent(); 759 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 760 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 761 F->insert(It, copy0MBB); 762 F->insert(It, sinkMBB); 763 764 // Transfer the remainder of BB and its successor edges to sinkMBB. 765 sinkMBB->splice(sinkMBB->begin(), BB, 766 llvm::next(MachineBasicBlock::iterator(MI)), 767 BB->end()); 768 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 769 770 // Next, add the true and fallthrough blocks as its successors. 771 BB->addSuccessor(copy0MBB); 772 BB->addSuccessor(sinkMBB); 773 774 // Emit the right instruction according to the type of the operands compared 775 if (isFPCmp) 776 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 777 else 778 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 779 .addReg(Mips::ZERO).addMBB(sinkMBB); 780 781 // copy0MBB: 782 // %FalseValue = ... 783 // # fallthrough to sinkMBB 784 BB = copy0MBB; 785 786 // Update machine-CFG edges 787 BB->addSuccessor(sinkMBB); 788 789 // sinkMBB: 790 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 791 // ... 792 BB = sinkMBB; 793 794 if (isFPCmp) 795 BuildMI(*BB, BB->begin(), dl, 796 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 797 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 798 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 799 else 800 BuildMI(*BB, BB->begin(), dl, 801 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 802 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 803 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 804 805 MI->eraseFromParent(); // The pseudo instruction is gone now. 806 return BB; 807} 808*/ 809MachineBasicBlock * 810MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 811 MachineBasicBlock *BB) const { 812 switch (MI->getOpcode()) { 813 default: llvm_unreachable("Unexpected instr type to insert"); 814 case Mips::ATOMIC_LOAD_ADD_I8: 815 case Mips::ATOMIC_LOAD_ADD_I8_P8: 816 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 817 case Mips::ATOMIC_LOAD_ADD_I16: 818 case Mips::ATOMIC_LOAD_ADD_I16_P8: 819 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 820 case Mips::ATOMIC_LOAD_ADD_I32: 821 case Mips::ATOMIC_LOAD_ADD_I32_P8: 822 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 823 case Mips::ATOMIC_LOAD_ADD_I64: 824 case Mips::ATOMIC_LOAD_ADD_I64_P8: 825 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 826 827 case Mips::ATOMIC_LOAD_AND_I8: 828 case Mips::ATOMIC_LOAD_AND_I8_P8: 829 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 830 case Mips::ATOMIC_LOAD_AND_I16: 831 case Mips::ATOMIC_LOAD_AND_I16_P8: 832 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 833 case Mips::ATOMIC_LOAD_AND_I32: 834 case Mips::ATOMIC_LOAD_AND_I32_P8: 835 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 836 case Mips::ATOMIC_LOAD_AND_I64: 837 case Mips::ATOMIC_LOAD_AND_I64_P8: 838 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 839 840 case Mips::ATOMIC_LOAD_OR_I8: 841 case Mips::ATOMIC_LOAD_OR_I8_P8: 842 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 843 case Mips::ATOMIC_LOAD_OR_I16: 844 case Mips::ATOMIC_LOAD_OR_I16_P8: 845 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 846 case Mips::ATOMIC_LOAD_OR_I32: 847 case Mips::ATOMIC_LOAD_OR_I32_P8: 848 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 849 case Mips::ATOMIC_LOAD_OR_I64: 850 case Mips::ATOMIC_LOAD_OR_I64_P8: 851 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 852 853 case Mips::ATOMIC_LOAD_XOR_I8: 854 case Mips::ATOMIC_LOAD_XOR_I8_P8: 855 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 856 case Mips::ATOMIC_LOAD_XOR_I16: 857 case Mips::ATOMIC_LOAD_XOR_I16_P8: 858 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 859 case Mips::ATOMIC_LOAD_XOR_I32: 860 case Mips::ATOMIC_LOAD_XOR_I32_P8: 861 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 862 case Mips::ATOMIC_LOAD_XOR_I64: 863 case Mips::ATOMIC_LOAD_XOR_I64_P8: 864 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 865 866 case Mips::ATOMIC_LOAD_NAND_I8: 867 case Mips::ATOMIC_LOAD_NAND_I8_P8: 868 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 869 case Mips::ATOMIC_LOAD_NAND_I16: 870 case Mips::ATOMIC_LOAD_NAND_I16_P8: 871 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 872 case Mips::ATOMIC_LOAD_NAND_I32: 873 case Mips::ATOMIC_LOAD_NAND_I32_P8: 874 return EmitAtomicBinary(MI, BB, 4, 0, true); 875 case Mips::ATOMIC_LOAD_NAND_I64: 876 case Mips::ATOMIC_LOAD_NAND_I64_P8: 877 return EmitAtomicBinary(MI, BB, 8, 0, true); 878 879 case Mips::ATOMIC_LOAD_SUB_I8: 880 case Mips::ATOMIC_LOAD_SUB_I8_P8: 881 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 882 case Mips::ATOMIC_LOAD_SUB_I16: 883 case Mips::ATOMIC_LOAD_SUB_I16_P8: 884 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 885 case Mips::ATOMIC_LOAD_SUB_I32: 886 case Mips::ATOMIC_LOAD_SUB_I32_P8: 887 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 888 case Mips::ATOMIC_LOAD_SUB_I64: 889 case Mips::ATOMIC_LOAD_SUB_I64_P8: 890 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 891 892 case Mips::ATOMIC_SWAP_I8: 893 case Mips::ATOMIC_SWAP_I8_P8: 894 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 895 case Mips::ATOMIC_SWAP_I16: 896 case Mips::ATOMIC_SWAP_I16_P8: 897 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 898 case Mips::ATOMIC_SWAP_I32: 899 case Mips::ATOMIC_SWAP_I32_P8: 900 return EmitAtomicBinary(MI, BB, 4, 0); 901 case Mips::ATOMIC_SWAP_I64: 902 case Mips::ATOMIC_SWAP_I64_P8: 903 return EmitAtomicBinary(MI, BB, 8, 0); 904 905 case Mips::ATOMIC_CMP_SWAP_I8: 906 case Mips::ATOMIC_CMP_SWAP_I8_P8: 907 return EmitAtomicCmpSwapPartword(MI, BB, 1); 908 case Mips::ATOMIC_CMP_SWAP_I16: 909 case Mips::ATOMIC_CMP_SWAP_I16_P8: 910 return EmitAtomicCmpSwapPartword(MI, BB, 2); 911 case Mips::ATOMIC_CMP_SWAP_I32: 912 case Mips::ATOMIC_CMP_SWAP_I32_P8: 913 return EmitAtomicCmpSwap(MI, BB, 4); 914 case Mips::ATOMIC_CMP_SWAP_I64: 915 case Mips::ATOMIC_CMP_SWAP_I64_P8: 916 return EmitAtomicCmpSwap(MI, BB, 8); 917 } 918} 919 920// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 921// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 922MachineBasicBlock * 923MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 924 unsigned Size, unsigned BinOpcode, 925 bool Nand) const { 926 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 927 928 MachineFunction *MF = BB->getParent(); 929 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 930 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 931 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 932 DebugLoc dl = MI->getDebugLoc(); 933 unsigned LL, SC, AND, NOR, ZERO, BEQ; 934 935 if (Size == 4) { 936 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 937 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 938 AND = Mips::AND; 939 NOR = Mips::NOR; 940 ZERO = Mips::ZERO; 941 BEQ = Mips::BEQ; 942 } 943 else { 944 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 945 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 946 AND = Mips::AND64; 947 NOR = Mips::NOR64; 948 ZERO = Mips::ZERO_64; 949 BEQ = Mips::BEQ64; 950 } 951 952 unsigned OldVal = MI->getOperand(0).getReg(); 953 unsigned Ptr = MI->getOperand(1).getReg(); 954 unsigned Incr = MI->getOperand(2).getReg(); 955 956 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 957 unsigned AndRes = RegInfo.createVirtualRegister(RC); 958 unsigned Success = RegInfo.createVirtualRegister(RC); 959 960 // insert new blocks after the current block 961 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 962 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 963 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 964 MachineFunction::iterator It = BB; 965 ++It; 966 MF->insert(It, loopMBB); 967 MF->insert(It, exitMBB); 968 969 // Transfer the remainder of BB and its successor edges to exitMBB. 970 exitMBB->splice(exitMBB->begin(), BB, 971 llvm::next(MachineBasicBlock::iterator(MI)), 972 BB->end()); 973 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 974 975 // thisMBB: 976 // ... 977 // fallthrough --> loopMBB 978 BB->addSuccessor(loopMBB); 979 loopMBB->addSuccessor(loopMBB); 980 loopMBB->addSuccessor(exitMBB); 981 982 // loopMBB: 983 // ll oldval, 0(ptr) 984 // <binop> storeval, oldval, incr 985 // sc success, storeval, 0(ptr) 986 // beq success, $0, loopMBB 987 BB = loopMBB; 988 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 989 if (Nand) { 990 // and andres, oldval, incr 991 // nor storeval, $0, andres 992 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 993 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 994 } else if (BinOpcode) { 995 // <binop> storeval, oldval, incr 996 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 997 } else { 998 StoreVal = Incr; 999 } 1000 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1001 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1002 1003 MI->eraseFromParent(); // The instruction is gone now. 1004 1005 return exitMBB; 1006} 1007 1008MachineBasicBlock * 1009MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1010 MachineBasicBlock *BB, 1011 unsigned Size, unsigned BinOpcode, 1012 bool Nand) const { 1013 assert((Size == 1 || Size == 2) && 1014 "Unsupported size for EmitAtomicBinaryPartial."); 1015 1016 MachineFunction *MF = BB->getParent(); 1017 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1018 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1019 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1020 DebugLoc dl = MI->getDebugLoc(); 1021 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1022 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1023 1024 unsigned Dest = MI->getOperand(0).getReg(); 1025 unsigned Ptr = MI->getOperand(1).getReg(); 1026 unsigned Incr = MI->getOperand(2).getReg(); 1027 1028 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1029 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1030 unsigned Mask = RegInfo.createVirtualRegister(RC); 1031 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1032 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1033 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1034 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1035 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1036 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1037 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1038 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1039 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1040 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1041 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1042 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1043 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1044 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1045 unsigned Success = RegInfo.createVirtualRegister(RC); 1046 1047 // insert new blocks after the current block 1048 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1049 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1050 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1051 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1052 MachineFunction::iterator It = BB; 1053 ++It; 1054 MF->insert(It, loopMBB); 1055 MF->insert(It, sinkMBB); 1056 MF->insert(It, exitMBB); 1057 1058 // Transfer the remainder of BB and its successor edges to exitMBB. 1059 exitMBB->splice(exitMBB->begin(), BB, 1060 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1061 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1062 1063 BB->addSuccessor(loopMBB); 1064 loopMBB->addSuccessor(loopMBB); 1065 loopMBB->addSuccessor(sinkMBB); 1066 sinkMBB->addSuccessor(exitMBB); 1067 1068 // thisMBB: 1069 // addiu masklsb2,$0,-4 # 0xfffffffc 1070 // and alignedaddr,ptr,masklsb2 1071 // andi ptrlsb2,ptr,3 1072 // sll shiftamt,ptrlsb2,3 1073 // ori maskupper,$0,255 # 0xff 1074 // sll mask,maskupper,shiftamt 1075 // nor mask2,$0,mask 1076 // sll incr2,incr,shiftamt 1077 1078 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1079 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1080 .addReg(Mips::ZERO).addImm(-4); 1081 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1082 .addReg(Ptr).addReg(MaskLSB2); 1083 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1084 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1085 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1086 .addReg(Mips::ZERO).addImm(MaskImm); 1087 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1088 .addReg(ShiftAmt).addReg(MaskUpper); 1089 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1090 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1091 1092 // atomic.load.binop 1093 // loopMBB: 1094 // ll oldval,0(alignedaddr) 1095 // binop binopres,oldval,incr2 1096 // and newval,binopres,mask 1097 // and maskedoldval0,oldval,mask2 1098 // or storeval,maskedoldval0,newval 1099 // sc success,storeval,0(alignedaddr) 1100 // beq success,$0,loopMBB 1101 1102 // atomic.swap 1103 // loopMBB: 1104 // ll oldval,0(alignedaddr) 1105 // and newval,incr2,mask 1106 // and maskedoldval0,oldval,mask2 1107 // or storeval,maskedoldval0,newval 1108 // sc success,storeval,0(alignedaddr) 1109 // beq success,$0,loopMBB 1110 1111 BB = loopMBB; 1112 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1113 if (Nand) { 1114 // and andres, oldval, incr2 1115 // nor binopres, $0, andres 1116 // and newval, binopres, mask 1117 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1118 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1119 .addReg(Mips::ZERO).addReg(AndRes); 1120 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1121 } else if (BinOpcode) { 1122 // <binop> binopres, oldval, incr2 1123 // and newval, binopres, mask 1124 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1125 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1126 } else {// atomic.swap 1127 // and newval, incr2, mask 1128 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1129 } 1130 1131 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1132 .addReg(OldVal).addReg(Mask2); 1133 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1134 .addReg(MaskedOldVal0).addReg(NewVal); 1135 BuildMI(BB, dl, TII->get(SC), Success) 1136 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1137 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1138 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1139 1140 // sinkMBB: 1141 // and maskedoldval1,oldval,mask 1142 // srl srlres,maskedoldval1,shiftamt 1143 // sll sllres,srlres,24 1144 // sra dest,sllres,24 1145 BB = sinkMBB; 1146 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1147 1148 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1149 .addReg(OldVal).addReg(Mask); 1150 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1151 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1152 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1153 .addReg(SrlRes).addImm(ShiftImm); 1154 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1155 .addReg(SllRes).addImm(ShiftImm); 1156 1157 MI->eraseFromParent(); // The instruction is gone now. 1158 1159 return exitMBB; 1160} 1161 1162MachineBasicBlock * 1163MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1164 MachineBasicBlock *BB, 1165 unsigned Size) const { 1166 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1167 1168 MachineFunction *MF = BB->getParent(); 1169 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1170 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1171 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1172 DebugLoc dl = MI->getDebugLoc(); 1173 unsigned LL, SC, ZERO, BNE, BEQ; 1174 1175 if (Size == 4) { 1176 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1177 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1178 ZERO = Mips::ZERO; 1179 BNE = Mips::BNE; 1180 BEQ = Mips::BEQ; 1181 } 1182 else { 1183 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1184 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1185 ZERO = Mips::ZERO_64; 1186 BNE = Mips::BNE64; 1187 BEQ = Mips::BEQ64; 1188 } 1189 1190 unsigned Dest = MI->getOperand(0).getReg(); 1191 unsigned Ptr = MI->getOperand(1).getReg(); 1192 unsigned OldVal = MI->getOperand(2).getReg(); 1193 unsigned NewVal = MI->getOperand(3).getReg(); 1194 1195 unsigned Success = RegInfo.createVirtualRegister(RC); 1196 1197 // insert new blocks after the current block 1198 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1199 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1200 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1201 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1202 MachineFunction::iterator It = BB; 1203 ++It; 1204 MF->insert(It, loop1MBB); 1205 MF->insert(It, loop2MBB); 1206 MF->insert(It, exitMBB); 1207 1208 // Transfer the remainder of BB and its successor edges to exitMBB. 1209 exitMBB->splice(exitMBB->begin(), BB, 1210 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1211 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1212 1213 // thisMBB: 1214 // ... 1215 // fallthrough --> loop1MBB 1216 BB->addSuccessor(loop1MBB); 1217 loop1MBB->addSuccessor(exitMBB); 1218 loop1MBB->addSuccessor(loop2MBB); 1219 loop2MBB->addSuccessor(loop1MBB); 1220 loop2MBB->addSuccessor(exitMBB); 1221 1222 // loop1MBB: 1223 // ll dest, 0(ptr) 1224 // bne dest, oldval, exitMBB 1225 BB = loop1MBB; 1226 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1227 BuildMI(BB, dl, TII->get(BNE)) 1228 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1229 1230 // loop2MBB: 1231 // sc success, newval, 0(ptr) 1232 // beq success, $0, loop1MBB 1233 BB = loop2MBB; 1234 BuildMI(BB, dl, TII->get(SC), Success) 1235 .addReg(NewVal).addReg(Ptr).addImm(0); 1236 BuildMI(BB, dl, TII->get(BEQ)) 1237 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1238 1239 MI->eraseFromParent(); // The instruction is gone now. 1240 1241 return exitMBB; 1242} 1243 1244MachineBasicBlock * 1245MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1246 MachineBasicBlock *BB, 1247 unsigned Size) const { 1248 assert((Size == 1 || Size == 2) && 1249 "Unsupported size for EmitAtomicCmpSwapPartial."); 1250 1251 MachineFunction *MF = BB->getParent(); 1252 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1253 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1254 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1255 DebugLoc dl = MI->getDebugLoc(); 1256 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1257 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1258 1259 unsigned Dest = MI->getOperand(0).getReg(); 1260 unsigned Ptr = MI->getOperand(1).getReg(); 1261 unsigned CmpVal = MI->getOperand(2).getReg(); 1262 unsigned NewVal = MI->getOperand(3).getReg(); 1263 1264 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1265 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1266 unsigned Mask = RegInfo.createVirtualRegister(RC); 1267 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1268 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1269 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1270 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1271 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1272 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1273 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1274 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1275 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1276 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1277 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1278 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1279 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1280 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1281 unsigned Success = RegInfo.createVirtualRegister(RC); 1282 1283 // insert new blocks after the current block 1284 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1285 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1286 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1287 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1288 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1289 MachineFunction::iterator It = BB; 1290 ++It; 1291 MF->insert(It, loop1MBB); 1292 MF->insert(It, loop2MBB); 1293 MF->insert(It, sinkMBB); 1294 MF->insert(It, exitMBB); 1295 1296 // Transfer the remainder of BB and its successor edges to exitMBB. 1297 exitMBB->splice(exitMBB->begin(), BB, 1298 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1299 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1300 1301 BB->addSuccessor(loop1MBB); 1302 loop1MBB->addSuccessor(sinkMBB); 1303 loop1MBB->addSuccessor(loop2MBB); 1304 loop2MBB->addSuccessor(loop1MBB); 1305 loop2MBB->addSuccessor(sinkMBB); 1306 sinkMBB->addSuccessor(exitMBB); 1307 1308 // FIXME: computation of newval2 can be moved to loop2MBB. 1309 // thisMBB: 1310 // addiu masklsb2,$0,-4 # 0xfffffffc 1311 // and alignedaddr,ptr,masklsb2 1312 // andi ptrlsb2,ptr,3 1313 // sll shiftamt,ptrlsb2,3 1314 // ori maskupper,$0,255 # 0xff 1315 // sll mask,maskupper,shiftamt 1316 // nor mask2,$0,mask 1317 // andi maskedcmpval,cmpval,255 1318 // sll shiftedcmpval,maskedcmpval,shiftamt 1319 // andi maskednewval,newval,255 1320 // sll shiftednewval,maskednewval,shiftamt 1321 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1322 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1323 .addReg(Mips::ZERO).addImm(-4); 1324 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1325 .addReg(Ptr).addReg(MaskLSB2); 1326 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1327 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1328 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1329 .addReg(Mips::ZERO).addImm(MaskImm); 1330 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1331 .addReg(ShiftAmt).addReg(MaskUpper); 1332 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1333 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1334 .addReg(CmpVal).addImm(MaskImm); 1335 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1336 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1337 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1338 .addReg(NewVal).addImm(MaskImm); 1339 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1340 .addReg(ShiftAmt).addReg(MaskedNewVal); 1341 1342 // loop1MBB: 1343 // ll oldval,0(alginedaddr) 1344 // and maskedoldval0,oldval,mask 1345 // bne maskedoldval0,shiftedcmpval,sinkMBB 1346 BB = loop1MBB; 1347 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1348 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1349 .addReg(OldVal).addReg(Mask); 1350 BuildMI(BB, dl, TII->get(Mips::BNE)) 1351 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1352 1353 // loop2MBB: 1354 // and maskedoldval1,oldval,mask2 1355 // or storeval,maskedoldval1,shiftednewval 1356 // sc success,storeval,0(alignedaddr) 1357 // beq success,$0,loop1MBB 1358 BB = loop2MBB; 1359 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1360 .addReg(OldVal).addReg(Mask2); 1361 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1362 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1363 BuildMI(BB, dl, TII->get(SC), Success) 1364 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1365 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1366 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1367 1368 // sinkMBB: 1369 // srl srlres,maskedoldval0,shiftamt 1370 // sll sllres,srlres,24 1371 // sra dest,sllres,24 1372 BB = sinkMBB; 1373 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1374 1375 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1376 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1377 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1378 .addReg(SrlRes).addImm(ShiftImm); 1379 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1380 .addReg(SllRes).addImm(ShiftImm); 1381 1382 MI->eraseFromParent(); // The instruction is gone now. 1383 1384 return exitMBB; 1385} 1386 1387//===----------------------------------------------------------------------===// 1388// Misc Lower Operation implementation 1389//===----------------------------------------------------------------------===// 1390SDValue MipsTargetLowering:: 1391LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1392{ 1393 MachineFunction &MF = DAG.getMachineFunction(); 1394 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1395 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP; 1396 1397 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1398 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1399 "Cannot lower if the alignment of the allocated space is larger than \ 1400 that of the stack."); 1401 1402 SDValue Chain = Op.getOperand(0); 1403 SDValue Size = Op.getOperand(1); 1404 DebugLoc dl = Op.getDebugLoc(); 1405 1406 // Get a reference from Mips stack pointer 1407 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy()); 1408 1409 // Subtract the dynamic size from the actual stack size to 1410 // obtain the new stack size. 1411 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size); 1412 1413 // The Sub result contains the new stack start address, so it 1414 // must be placed in the stack pointer register. 1415 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue()); 1416 1417 // This node always has two return values: a new stack pointer 1418 // value and a chain 1419 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other); 1420 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1421 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1422 1423 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1424} 1425 1426SDValue MipsTargetLowering:: 1427LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1428{ 1429 // The first operand is the chain, the second is the condition, the third is 1430 // the block to branch to if the condition is true. 1431 SDValue Chain = Op.getOperand(0); 1432 SDValue Dest = Op.getOperand(2); 1433 DebugLoc dl = Op.getDebugLoc(); 1434 1435 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1436 1437 // Return if flag is not set by a floating point comparison. 1438 if (CondRes.getOpcode() != MipsISD::FPCmp) 1439 return Op; 1440 1441 SDValue CCNode = CondRes.getOperand(2); 1442 Mips::CondCode CC = 1443 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1444 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1445 1446 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1447 Dest, CondRes); 1448} 1449 1450SDValue MipsTargetLowering:: 1451LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1452{ 1453 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1454 1455 // Return if flag is not set by a floating point comparison. 1456 if (Cond.getOpcode() != MipsISD::FPCmp) 1457 return Op; 1458 1459 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1460 Op.getDebugLoc()); 1461} 1462 1463SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1464 SelectionDAG &DAG) const { 1465 // FIXME there isn't actually debug info here 1466 DebugLoc dl = Op.getDebugLoc(); 1467 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1468 1469 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1470 SDVTList VTs = DAG.getVTList(MVT::i32); 1471 1472 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1473 1474 // %gp_rel relocation 1475 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1476 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1477 MipsII::MO_GPREL); 1478 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1479 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1480 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1481 } 1482 // %hi/%lo relocation 1483 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1484 MipsII::MO_ABS_HI); 1485 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1486 MipsII::MO_ABS_LO); 1487 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1488 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1489 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1490 } 1491 1492 EVT ValTy = Op.getValueType(); 1493 bool HasGotOfst = (GV->hasInternalLinkage() || 1494 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1495 unsigned GotFlag = IsN64 ? 1496 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1497 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); 1498 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1499 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GA); 1500 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, 1501 MachinePointerInfo(), false, false, false, 0); 1502 // On functions and global targets not internal linked only 1503 // a load from got/GP is necessary for PIC to work. 1504 if (!HasGotOfst) 1505 return ResNode; 1506 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1507 IsN64 ? MipsII::MO_GOT_OFST : 1508 MipsII::MO_ABS_LO); 1509 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1510 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1511} 1512 1513SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1514 SelectionDAG &DAG) const { 1515 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1516 // FIXME there isn't actually debug info here 1517 DebugLoc dl = Op.getDebugLoc(); 1518 1519 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1520 // %hi/%lo relocation 1521 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI); 1522 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO); 1523 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1524 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1525 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1526 } 1527 1528 EVT ValTy = Op.getValueType(); 1529 unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1530 unsigned OFSTFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1531 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag); 1532 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, BAGOTOffset); 1533 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag); 1534 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset, 1535 MachinePointerInfo(), false, false, false, 0); 1536 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); 1537 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1538} 1539 1540SDValue MipsTargetLowering:: 1541LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1542{ 1543 // If the relocation model is PIC, use the General Dynamic TLS Model or 1544 // Local Dynamic TLS model, otherwise use the Initial Exec or 1545 // Local Exec TLS Model. 1546 1547 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1548 DebugLoc dl = GA->getDebugLoc(); 1549 const GlobalValue *GV = GA->getGlobal(); 1550 EVT PtrVT = getPointerTy(); 1551 1552 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1553 // General Dynamic TLS Model 1554 bool LocalDynamic = GV->hasInternalLinkage(); 1555 unsigned Flag = LocalDynamic ? MipsII::MO_TLSLDM :MipsII::MO_TLSGD; 1556 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1557 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, TGA); 1558 unsigned PtrSize = PtrVT.getSizeInBits(); 1559 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1560 1561 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1562 1563 ArgListTy Args; 1564 ArgListEntry Entry; 1565 Entry.Node = Argument; 1566 Entry.Ty = PtrTy; 1567 Args.push_back(Entry); 1568 1569 std::pair<SDValue, SDValue> CallResult = 1570 LowerCallTo(DAG.getEntryNode(), PtrTy, 1571 false, false, false, false, 0, CallingConv::C, false, true, 1572 TlsGetAddr, Args, DAG, dl); 1573 1574 SDValue Ret = CallResult.first; 1575 1576 if (!LocalDynamic) 1577 return Ret; 1578 1579 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1580 MipsII::MO_DTPREL_HI); 1581 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1582 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1583 MipsII::MO_DTPREL_LO); 1584 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1585 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1586 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1587 } 1588 1589 SDValue Offset; 1590 if (GV->isDeclaration()) { 1591 // Initial Exec TLS Model 1592 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1593 MipsII::MO_GOTTPREL); 1594 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, TGA); 1595 Offset = DAG.getLoad(PtrVT, dl, 1596 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1597 false, false, false, 0); 1598 } else { 1599 // Local Exec TLS Model 1600 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1601 MipsII::MO_TPREL_HI); 1602 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1603 MipsII::MO_TPREL_LO); 1604 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1605 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1606 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1607 } 1608 1609 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1610 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1611} 1612 1613SDValue MipsTargetLowering:: 1614LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1615{ 1616 SDValue HiPart, JTI, JTILo; 1617 // FIXME there isn't actually debug info here 1618 DebugLoc dl = Op.getDebugLoc(); 1619 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1620 EVT PtrVT = Op.getValueType(); 1621 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1622 1623 if (!IsPIC && !IsN64) { 1624 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); 1625 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); 1626 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); 1627 } else {// Emit Load from Global Pointer 1628 unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1629 unsigned OfstFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1630 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); 1631 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, JTI); 1632 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, 1633 MachinePointerInfo(), false, false, false, 0); 1634 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); 1635 } 1636 1637 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); 1638 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); 1639} 1640 1641SDValue MipsTargetLowering:: 1642LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1643{ 1644 SDValue ResNode; 1645 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1646 const Constant *C = N->getConstVal(); 1647 // FIXME there isn't actually debug info here 1648 DebugLoc dl = Op.getDebugLoc(); 1649 1650 // gp_rel relocation 1651 // FIXME: we should reference the constant pool using small data sections, 1652 // but the asm printer currently doesn't support this feature without 1653 // hacking it. This feature should come soon so we can uncomment the 1654 // stuff below. 1655 //if (IsInSmallSection(C->getType())) { 1656 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1657 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1658 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1659 1660 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1661 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1662 N->getOffset(), MipsII::MO_ABS_HI); 1663 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1664 N->getOffset(), MipsII::MO_ABS_LO); 1665 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1666 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1667 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1668 } else { 1669 EVT ValTy = Op.getValueType(); 1670 unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1671 unsigned OFSTFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1672 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1673 N->getOffset(), GOTFlag); 1674 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, CP); 1675 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP, 1676 MachinePointerInfo::getConstantPool(), false, 1677 false, false, 0); 1678 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1679 N->getOffset(), OFSTFlag); 1680 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); 1681 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1682 } 1683 1684 return ResNode; 1685} 1686 1687SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1688 MachineFunction &MF = DAG.getMachineFunction(); 1689 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1690 1691 DebugLoc dl = Op.getDebugLoc(); 1692 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1693 getPointerTy()); 1694 1695 // vastart just stores the address of the VarArgsFrameIndex slot into the 1696 // memory location argument. 1697 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1698 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1699 MachinePointerInfo(SV), false, false, 0); 1700} 1701 1702// Called if the size of integer registers is large enough to hold the whole 1703// floating point number. 1704static SDValue LowerFCOPYSIGNLargeIntReg(SDValue Op, SelectionDAG &DAG) { 1705 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1706 EVT ValTy = Op.getValueType(); 1707 EVT IntValTy = MVT::getIntegerVT(ValTy.getSizeInBits()); 1708 uint64_t Mask = (uint64_t)1 << (ValTy.getSizeInBits() - 1); 1709 DebugLoc dl = Op.getDebugLoc(); 1710 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(0)); 1711 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(1)); 1712 SDValue And0 = DAG.getNode(ISD::AND, dl, IntValTy, Op0, 1713 DAG.getConstant(Mask - 1, IntValTy)); 1714 SDValue And1 = DAG.getNode(ISD::AND, dl, IntValTy, Op1, 1715 DAG.getConstant(Mask, IntValTy)); 1716 SDValue Result = DAG.getNode(ISD::OR, dl, IntValTy, And0, And1); 1717 return DAG.getNode(ISD::BITCAST, dl, ValTy, Result); 1718} 1719 1720// Called if the size of integer registers is not large enough to hold the whole 1721// floating point number (e.g. f64 & 32-bit integer register). 1722static SDValue 1723LowerFCOPYSIGNSmallIntReg(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1724 // FIXME: 1725 // Use ext/ins instructions if target architecture is Mips32r2. 1726 // Eliminate redundant mfc1 and mtc1 instructions. 1727 unsigned LoIdx = 0, HiIdx = 1; 1728 1729 if (!isLittle) 1730 std::swap(LoIdx, HiIdx); 1731 1732 DebugLoc dl = Op.getDebugLoc(); 1733 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1734 Op.getOperand(0), 1735 DAG.getConstant(LoIdx, MVT::i32)); 1736 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1737 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1738 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1739 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1740 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1741 DAG.getConstant(0x7fffffff, MVT::i32)); 1742 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1743 DAG.getConstant(0x80000000, MVT::i32)); 1744 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1745 1746 if (!isLittle) 1747 std::swap(Word0, Word1); 1748 1749 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1750} 1751 1752SDValue 1753MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1754 EVT Ty = Op.getValueType(); 1755 1756 assert(Ty == MVT::f32 || Ty == MVT::f64); 1757 1758 if (Ty == MVT::f32 || HasMips64) 1759 return LowerFCOPYSIGNLargeIntReg(Op, DAG); 1760 1761 return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle()); 1762} 1763 1764SDValue MipsTargetLowering:: 1765LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1766 // check the depth 1767 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1768 "Frame address can only be determined for current frame."); 1769 1770 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1771 MFI->setFrameAddressIsTaken(true); 1772 EVT VT = Op.getValueType(); 1773 DebugLoc dl = Op.getDebugLoc(); 1774 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1775 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1776 return FrameAddr; 1777} 1778 1779// TODO: set SType according to the desired memory barrier behavior. 1780SDValue 1781MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const { 1782 unsigned SType = 0; 1783 DebugLoc dl = Op.getDebugLoc(); 1784 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1785 DAG.getConstant(SType, MVT::i32)); 1786} 1787 1788SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1789 SelectionDAG& DAG) const { 1790 // FIXME: Need pseudo-fence for 'singlethread' fences 1791 // FIXME: Set SType for weaker fences where supported/appropriate. 1792 unsigned SType = 0; 1793 DebugLoc dl = Op.getDebugLoc(); 1794 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1795 DAG.getConstant(SType, MVT::i32)); 1796} 1797 1798//===----------------------------------------------------------------------===// 1799// Calling Convention Implementation 1800//===----------------------------------------------------------------------===// 1801 1802//===----------------------------------------------------------------------===// 1803// TODO: Implement a generic logic using tblgen that can support this. 1804// Mips O32 ABI rules: 1805// --- 1806// i32 - Passed in A0, A1, A2, A3 and stack 1807// f32 - Only passed in f32 registers if no int reg has been used yet to hold 1808// an argument. Otherwise, passed in A1, A2, A3 and stack. 1809// f64 - Only passed in two aliased f32 registers if no int reg has been used 1810// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1811// not used, it must be shadowed. If only A3 is avaiable, shadow it and 1812// go to stack. 1813// 1814// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1815//===----------------------------------------------------------------------===// 1816 1817static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1818 MVT LocVT, CCValAssign::LocInfo LocInfo, 1819 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1820 1821 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1822 1823 static const unsigned IntRegs[] = { 1824 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1825 }; 1826 static const unsigned F32Regs[] = { 1827 Mips::F12, Mips::F14 1828 }; 1829 static const unsigned F64Regs[] = { 1830 Mips::D6, Mips::D7 1831 }; 1832 1833 // ByVal Args 1834 if (ArgFlags.isByVal()) { 1835 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1836 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1837 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1838 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1839 r < std::min(IntRegsSize, NextReg); ++r) 1840 State.AllocateReg(IntRegs[r]); 1841 return false; 1842 } 1843 1844 // Promote i8 and i16 1845 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1846 LocVT = MVT::i32; 1847 if (ArgFlags.isSExt()) 1848 LocInfo = CCValAssign::SExt; 1849 else if (ArgFlags.isZExt()) 1850 LocInfo = CCValAssign::ZExt; 1851 else 1852 LocInfo = CCValAssign::AExt; 1853 } 1854 1855 unsigned Reg; 1856 1857 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1858 // is true: function is vararg, argument is 3rd or higher, there is previous 1859 // argument which is not f32 or f64. 1860 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1861 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1862 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1863 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1864 1865 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1866 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1867 // If this is the first part of an i64 arg, 1868 // the allocated register must be either A0 or A2. 1869 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1870 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1871 LocVT = MVT::i32; 1872 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1873 // Allocate int register and shadow next int register. If first 1874 // available register is Mips::A1 or Mips::A3, shadow it too. 1875 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1876 if (Reg == Mips::A1 || Reg == Mips::A3) 1877 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1878 State.AllocateReg(IntRegs, IntRegsSize); 1879 LocVT = MVT::i32; 1880 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1881 // we are guaranteed to find an available float register 1882 if (ValVT == MVT::f32) { 1883 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1884 // Shadow int register 1885 State.AllocateReg(IntRegs, IntRegsSize); 1886 } else { 1887 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1888 // Shadow int registers 1889 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1890 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1891 State.AllocateReg(IntRegs, IntRegsSize); 1892 State.AllocateReg(IntRegs, IntRegsSize); 1893 } 1894 } else 1895 llvm_unreachable("Cannot handle this ValVT."); 1896 1897 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1898 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1899 1900 if (!Reg) 1901 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1902 else 1903 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1904 1905 return false; // CC must always match 1906} 1907 1908static const unsigned Mips64IntRegs[8] = 1909 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 1910 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; 1911static const unsigned Mips64DPRegs[8] = 1912 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 1913 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64}; 1914 1915static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT, 1916 CCValAssign::LocInfo LocInfo, 1917 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1918 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8); 1919 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8; 1920 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8); 1921 1922 assert(Align <= 16 && "Cannot handle alignments larger than 16."); 1923 1924 // If byval is 16-byte aligned, the first arg register must be even. 1925 if ((Align == 16) && (FirstIdx % 2)) { 1926 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]); 1927 ++FirstIdx; 1928 } 1929 1930 // Mark the registers allocated. 1931 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I) 1932 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]); 1933 1934 // Allocate space on caller's stack. 1935 unsigned Offset = State.AllocateStack(Size, Align); 1936 1937 if (FirstIdx < 8) 1938 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx], 1939 LocVT, LocInfo)); 1940 else 1941 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1942 1943 return true; 1944} 1945 1946#include "MipsGenCallingConv.inc" 1947 1948static void 1949AnalyzeMips64CallOperands(CCState &CCInfo, 1950 const SmallVectorImpl<ISD::OutputArg> &Outs) { 1951 unsigned NumOps = Outs.size(); 1952 for (unsigned i = 0; i != NumOps; ++i) { 1953 MVT ArgVT = Outs[i].VT; 1954 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 1955 bool R; 1956 1957 if (Outs[i].IsFixed) 1958 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 1959 else 1960 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 1961 1962 if (R) { 1963#ifndef NDEBUG 1964 dbgs() << "Call operand #" << i << " has unhandled type " 1965 << EVT(ArgVT).getEVTString(); 1966#endif 1967 llvm_unreachable(0); 1968 } 1969 } 1970} 1971 1972//===----------------------------------------------------------------------===// 1973// Call Calling Convention Implementation 1974//===----------------------------------------------------------------------===// 1975 1976static const unsigned O32IntRegsSize = 4; 1977 1978static const unsigned O32IntRegs[] = { 1979 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1980}; 1981 1982// Return next O32 integer argument register. 1983static unsigned getNextIntArgReg(unsigned Reg) { 1984 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 1985 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 1986} 1987 1988// Write ByVal Arg to arg registers and stack. 1989static void 1990WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 1991 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1992 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1993 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1994 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1995 MVT PtrType, bool isLittle) { 1996 unsigned LocMemOffset = VA.getLocMemOffset(); 1997 unsigned Offset = 0; 1998 uint32_t RemainingSize = Flags.getByValSize(); 1999 unsigned ByValAlign = Flags.getByValAlign(); 2000 2001 // Copy the first 4 words of byval arg to registers A0 - A3. 2002 // FIXME: Use a stricter alignment if it enables better optimization in passes 2003 // run later. 2004 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 2005 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 2006 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2007 DAG.getConstant(Offset, MVT::i32)); 2008 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 2009 MachinePointerInfo(), false, false, false, 2010 std::min(ByValAlign, (unsigned )4)); 2011 MemOpChains.push_back(LoadVal.getValue(1)); 2012 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2013 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2014 } 2015 2016 if (RemainingSize == 0) 2017 return; 2018 2019 // If there still is a register available for argument passing, write the 2020 // remaining part of the structure to it using subword loads and shifts. 2021 if (LocMemOffset < 4 * 4) { 2022 assert(RemainingSize <= 3 && RemainingSize >= 1 && 2023 "There must be one to three bytes remaining."); 2024 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 2025 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2026 DAG.getConstant(Offset, MVT::i32)); 2027 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 2028 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2029 LoadPtr, MachinePointerInfo(), 2030 MVT::getIntegerVT(LoadSize * 8), false, 2031 false, Alignment); 2032 MemOpChains.push_back(LoadVal.getValue(1)); 2033 2034 // If target is big endian, shift it to the most significant half-word or 2035 // byte. 2036 if (!isLittle) 2037 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 2038 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 2039 2040 Offset += LoadSize; 2041 RemainingSize -= LoadSize; 2042 2043 // Read second subword if necessary. 2044 if (RemainingSize != 0) { 2045 assert(RemainingSize == 1 && "There must be one byte remaining."); 2046 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2047 DAG.getConstant(Offset, MVT::i32)); 2048 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 2049 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2050 LoadPtr, MachinePointerInfo(), 2051 MVT::i8, false, false, Alignment); 2052 MemOpChains.push_back(Subword.getValue(1)); 2053 // Insert the loaded byte to LoadVal. 2054 // FIXME: Use INS if supported by target. 2055 unsigned ShiftAmt = isLittle ? 16 : 8; 2056 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 2057 DAG.getConstant(ShiftAmt, MVT::i32)); 2058 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 2059 } 2060 2061 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2062 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2063 return; 2064 } 2065 2066 // Create a fixed object on stack at offset LocMemOffset and copy 2067 // remaining part of byval arg to it using memcpy. 2068 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2069 DAG.getConstant(Offset, MVT::i32)); 2070 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 2071 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 2072 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 2073 DAG.getConstant(RemainingSize, MVT::i32), 2074 std::min(ByValAlign, (unsigned)4), 2075 /*isVolatile=*/false, /*AlwaysInline=*/false, 2076 MachinePointerInfo(0), MachinePointerInfo(0)); 2077} 2078 2079// Copy Mips64 byVal arg to registers and stack. 2080void static 2081PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 2082 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 2083 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 2084 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2085 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2086 EVT PtrTy, bool isLittle) { 2087 unsigned ByValSize = Flags.getByValSize(); 2088 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8); 2089 bool IsRegLoc = VA.isRegLoc(); 2090 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 2091 unsigned LocMemOffset = 0; 2092 unsigned MemCpySize = ByValSize; 2093 2094 if (!IsRegLoc) 2095 LocMemOffset = VA.getLocMemOffset(); 2096 else { 2097 const unsigned *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, 2098 VA.getLocReg()); 2099 const unsigned *RegEnd = Mips64IntRegs + 8; 2100 2101 // Copy double words to registers. 2102 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) { 2103 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2104 DAG.getConstant(Offset, PtrTy)); 2105 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr, 2106 MachinePointerInfo(), false, false, false, 2107 Alignment); 2108 MemOpChains.push_back(LoadVal.getValue(1)); 2109 RegsToPass.push_back(std::make_pair(*Reg, LoadVal)); 2110 } 2111 2112 // Return if the struct has been fully copied. 2113 if (!(MemCpySize = ByValSize - Offset)) 2114 return; 2115 2116 // If there is an argument register available, copy the remainder of the 2117 // byval argument with sub-doubleword loads and shifts. 2118 if (Reg != RegEnd) { 2119 assert((ByValSize < Offset + 8) && 2120 "Size of the remainder should be smaller than 8-byte."); 2121 SDValue Val; 2122 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) { 2123 unsigned RemSize = ByValSize - Offset; 2124 2125 if (RemSize < LoadSize) 2126 continue; 2127 2128 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2129 DAG.getConstant(Offset, PtrTy)); 2130 SDValue LoadVal = 2131 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr, 2132 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 2133 false, false, Alignment); 2134 MemOpChains.push_back(LoadVal.getValue(1)); 2135 2136 // Offset in number of bits from double word boundary. 2137 unsigned OffsetDW = (Offset % 8) * 8; 2138 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8); 2139 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal, 2140 DAG.getConstant(Shamt, MVT::i32)); 2141 2142 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) : 2143 Shift; 2144 Offset += LoadSize; 2145 Alignment = std::min(Alignment, LoadSize); 2146 } 2147 2148 RegsToPass.push_back(std::make_pair(*Reg, Val)); 2149 return; 2150 } 2151 } 2152 2153 assert(MemCpySize && "MemCpySize must not be zero."); 2154 2155 // Create a fixed object on stack at offset LocMemOffset and copy 2156 // remainder of byval arg to it with memcpy. 2157 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2158 DAG.getConstant(Offset, PtrTy)); 2159 LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true); 2160 SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy); 2161 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 2162 DAG.getConstant(MemCpySize, PtrTy), Alignment, 2163 /*isVolatile=*/false, /*AlwaysInline=*/false, 2164 MachinePointerInfo(0), MachinePointerInfo(0)); 2165} 2166 2167/// LowerCall - functions arguments are copied from virtual regs to 2168/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2169/// TODO: isTailCall. 2170SDValue 2171MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee, 2172 CallingConv::ID CallConv, bool isVarArg, 2173 bool &isTailCall, 2174 const SmallVectorImpl<ISD::OutputArg> &Outs, 2175 const SmallVectorImpl<SDValue> &OutVals, 2176 const SmallVectorImpl<ISD::InputArg> &Ins, 2177 DebugLoc dl, SelectionDAG &DAG, 2178 SmallVectorImpl<SDValue> &InVals) const { 2179 // MIPs target does not yet support tail call optimization. 2180 isTailCall = false; 2181 2182 MachineFunction &MF = DAG.getMachineFunction(); 2183 MachineFrameInfo *MFI = MF.getFrameInfo(); 2184 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2185 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2186 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2187 2188 // Analyze operands of the call, assigning locations to each operand. 2189 SmallVector<CCValAssign, 16> ArgLocs; 2190 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2191 getTargetMachine(), ArgLocs, *DAG.getContext()); 2192 2193 if (IsO32) 2194 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 2195 else if (HasMips64) 2196 AnalyzeMips64CallOperands(CCInfo, Outs); 2197 else 2198 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 2199 2200 // Get a count of how many bytes are to be pushed on the stack. 2201 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2202 2203 // Chain is the output chain of the last Load/Store or CopyToReg node. 2204 // ByValChain is the output chain of the last Memcpy node created for copying 2205 // byval arguments to the stack. 2206 SDValue Chain, CallSeqStart, ByValChain; 2207 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2208 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal); 2209 ByValChain = InChain; 2210 2211 // If this is the first call, create a stack frame object that points to 2212 // a location to which .cprestore saves $gp. 2213 if (IsO32 && IsPIC && !MipsFI->getGPFI()) 2214 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 2215 2216 // Get the frame index of the stack frame object that points to the location 2217 // of dynamically allocated area on the stack. 2218 int DynAllocFI = MipsFI->getDynAllocFI(); 2219 2220 // Update size of the maximum argument space. 2221 // For O32, a minimum of four words (16 bytes) of argument space is 2222 // allocated. 2223 if (IsO32) 2224 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 2225 2226 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 2227 2228 if (MaxCallFrameSize < NextStackOffset) { 2229 MipsFI->setMaxCallFrameSize(NextStackOffset); 2230 2231 // Set the offsets relative to $sp of the $gp restore slot and dynamically 2232 // allocated stack space. These offsets must be aligned to a boundary 2233 // determined by the stack alignment of the ABI. 2234 unsigned StackAlignment = TFL->getStackAlignment(); 2235 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 2236 StackAlignment * StackAlignment; 2237 2238 if (MipsFI->needGPSaveRestore()) 2239 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 2240 2241 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 2242 } 2243 2244 // With EABI is it possible to have 16 args on registers. 2245 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2246 SmallVector<SDValue, 8> MemOpChains; 2247 2248 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 2249 2250 // Walk the register/memloc assignments, inserting copies/loads. 2251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2252 SDValue Arg = OutVals[i]; 2253 CCValAssign &VA = ArgLocs[i]; 2254 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2255 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2256 2257 // ByVal Arg. 2258 if (Flags.isByVal()) { 2259 assert(Flags.getByValSize() && 2260 "ByVal args of size 0 should have been ignored by front-end."); 2261 if (IsO32) 2262 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, 2263 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2264 Subtarget->isLittle()); 2265 else 2266 PassByValArg64(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, 2267 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2268 Subtarget->isLittle()); 2269 continue; 2270 } 2271 2272 // Promote the value if needed. 2273 switch (VA.getLocInfo()) { 2274 default: llvm_unreachable("Unknown loc info!"); 2275 case CCValAssign::Full: 2276 if (VA.isRegLoc()) { 2277 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2278 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2279 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2280 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2281 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2282 Arg, DAG.getConstant(0, MVT::i32)); 2283 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2284 Arg, DAG.getConstant(1, MVT::i32)); 2285 if (!Subtarget->isLittle()) 2286 std::swap(Lo, Hi); 2287 unsigned LocRegLo = VA.getLocReg(); 2288 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2289 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2290 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2291 continue; 2292 } 2293 } 2294 break; 2295 case CCValAssign::SExt: 2296 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2297 break; 2298 case CCValAssign::ZExt: 2299 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2300 break; 2301 case CCValAssign::AExt: 2302 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2303 break; 2304 } 2305 2306 // Arguments that can be passed on register must be kept at 2307 // RegsToPass vector 2308 if (VA.isRegLoc()) { 2309 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2310 continue; 2311 } 2312 2313 // Register can't get to this point... 2314 assert(VA.isMemLoc()); 2315 2316 // Create the frame index object for this incoming parameter 2317 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2318 VA.getLocMemOffset(), true); 2319 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2320 2321 // emit ISD::STORE whichs stores the 2322 // parameter value to a stack Location 2323 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2324 MachinePointerInfo(), false, false, 0)); 2325 } 2326 2327 // Extend range of indices of frame objects for outgoing arguments that were 2328 // created during this function call. Skip this step if no such objects were 2329 // created. 2330 if (LastFI) 2331 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2332 2333 // If a memcpy has been created to copy a byval arg to a stack, replace the 2334 // chain input of CallSeqStart with ByValChain. 2335 if (InChain != ByValChain) 2336 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain, 2337 NextStackOffsetVal); 2338 2339 // Transform all store nodes into one single node because all store 2340 // nodes are independent of each other. 2341 if (!MemOpChains.empty()) 2342 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2343 &MemOpChains[0], MemOpChains.size()); 2344 2345 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2346 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2347 // node so that legalize doesn't hack it. 2348 unsigned char OpFlag; 2349 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2350 bool GlobalOrExternal = false; 2351 SDValue CalleeLo; 2352 2353 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2354 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2355 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2356 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2357 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2358 OpFlag); 2359 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2360 0, LoFlag); 2361 } else { 2362 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2363 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2364 getPointerTy(), 0, OpFlag); 2365 } 2366 2367 GlobalOrExternal = true; 2368 } 2369 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2370 if (IsN64 || (!IsO32 && IsPIC)) 2371 OpFlag = MipsII::MO_GOT_DISP; 2372 else if (!IsPIC) // !N64 && static 2373 OpFlag = MipsII::MO_NO_FLAG; 2374 else // O32 & PIC 2375 OpFlag = MipsII::MO_GOT_CALL; 2376 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2377 OpFlag); 2378 GlobalOrExternal = true; 2379 } 2380 2381 SDValue InFlag; 2382 2383 // Create nodes that load address of callee and copy it to T9 2384 if (IsPICCall) { 2385 if (GlobalOrExternal) { 2386 // Load callee address 2387 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(), Callee); 2388 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2389 Callee, MachinePointerInfo::getGOT(), 2390 false, false, false, 0); 2391 2392 // Use GOT+LO if callee has internal linkage. 2393 if (CalleeLo.getNode()) { 2394 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2395 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2396 } else 2397 Callee = LoadValue; 2398 } 2399 } 2400 2401 // T9 should contain the address of the callee function if 2402 // -reloction-model=pic or it is an indirect call. 2403 if (IsPICCall || !GlobalOrExternal) { 2404 // copy to T9 2405 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2406 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2407 InFlag = Chain.getValue(1); 2408 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2409 } 2410 2411 // Build a sequence of copy-to-reg nodes chained together with token 2412 // chain and flag operands which copy the outgoing args into registers. 2413 // The InFlag in necessary since all emitted instructions must be 2414 // stuck together. 2415 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2416 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2417 RegsToPass[i].second, InFlag); 2418 InFlag = Chain.getValue(1); 2419 } 2420 2421 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2422 // = Chain, Callee, Reg#1, Reg#2, ... 2423 // 2424 // Returns a chain & a flag for retval copy to use. 2425 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2426 SmallVector<SDValue, 8> Ops; 2427 Ops.push_back(Chain); 2428 Ops.push_back(Callee); 2429 2430 // Add argument registers to the end of the list so that they are 2431 // known live into the call. 2432 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2433 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2434 RegsToPass[i].second.getValueType())); 2435 2436 if (InFlag.getNode()) 2437 Ops.push_back(InFlag); 2438 2439 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2440 InFlag = Chain.getValue(1); 2441 2442 // Create the CALLSEQ_END node. 2443 Chain = DAG.getCALLSEQ_END(Chain, 2444 DAG.getIntPtrConstant(NextStackOffset, true), 2445 DAG.getIntPtrConstant(0, true), InFlag); 2446 InFlag = Chain.getValue(1); 2447 2448 // Handle result values, copying them out of physregs into vregs that we 2449 // return. 2450 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2451 Ins, dl, DAG, InVals); 2452} 2453 2454/// LowerCallResult - Lower the result values of a call into the 2455/// appropriate copies out of appropriate physical registers. 2456SDValue 2457MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2458 CallingConv::ID CallConv, bool isVarArg, 2459 const SmallVectorImpl<ISD::InputArg> &Ins, 2460 DebugLoc dl, SelectionDAG &DAG, 2461 SmallVectorImpl<SDValue> &InVals) const { 2462 // Assign locations to each value returned by this call. 2463 SmallVector<CCValAssign, 16> RVLocs; 2464 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2465 getTargetMachine(), RVLocs, *DAG.getContext()); 2466 2467 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2468 2469 // Copy all of the result registers out of their specified physreg. 2470 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2471 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2472 RVLocs[i].getValVT(), InFlag).getValue(1); 2473 InFlag = Chain.getValue(2); 2474 InVals.push_back(Chain.getValue(0)); 2475 } 2476 2477 return Chain; 2478} 2479 2480//===----------------------------------------------------------------------===// 2481// Formal Arguments Calling Convention Implementation 2482//===----------------------------------------------------------------------===// 2483static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2484 std::vector<SDValue>& OutChains, 2485 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2486 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 2487 unsigned LocMem = VA.getLocMemOffset(); 2488 unsigned FirstWord = LocMem / 4; 2489 2490 // copy register A0 - A3 to frame object 2491 for (unsigned i = 0; i < NumWords; ++i) { 2492 unsigned CurWord = FirstWord + i; 2493 if (CurWord >= O32IntRegsSize) 2494 break; 2495 2496 unsigned SrcReg = O32IntRegs[CurWord]; 2497 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2498 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2499 DAG.getConstant(i * 4, MVT::i32)); 2500 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2501 StorePtr, MachinePointerInfo(), false, 2502 false, 0); 2503 OutChains.push_back(Store); 2504 } 2505} 2506 2507// Create frame object on stack and copy registers used for byval passing to it. 2508static unsigned 2509CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2510 std::vector<SDValue>& OutChains, SelectionDAG &DAG, 2511 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2512 MachineFrameInfo *MFI, bool IsRegLoc, 2513 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, 2514 EVT PtrTy) { 2515 const unsigned *Reg = Mips64IntRegs + 8; 2516 int FOOffset; // Frame object offset from virtual frame pointer. 2517 2518 if (IsRegLoc) { 2519 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg()); 2520 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8; 2521 } 2522 else 2523 FOOffset = VA.getLocMemOffset(); 2524 2525 // Create frame object. 2526 unsigned NumRegs = (Flags.getByValSize() + 7) / 8; 2527 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true); 2528 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy); 2529 InVals.push_back(FIN); 2530 2531 // Copy arg registers. 2532 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs); 2533 ++Reg, ++I) { 2534 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass); 2535 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN, 2536 DAG.getConstant(I * 8, PtrTy)); 2537 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64), 2538 StorePtr, MachinePointerInfo(), false, 2539 false, 0); 2540 OutChains.push_back(Store); 2541 } 2542 2543 return LastFI; 2544} 2545 2546/// LowerFormalArguments - transform physical registers into virtual registers 2547/// and generate load operations for arguments places on the stack. 2548SDValue 2549MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2550 CallingConv::ID CallConv, 2551 bool isVarArg, 2552 const SmallVectorImpl<ISD::InputArg> &Ins, 2553 DebugLoc dl, SelectionDAG &DAG, 2554 SmallVectorImpl<SDValue> &InVals) 2555 const { 2556 MachineFunction &MF = DAG.getMachineFunction(); 2557 MachineFrameInfo *MFI = MF.getFrameInfo(); 2558 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2559 2560 MipsFI->setVarArgsFrameIndex(0); 2561 2562 // Used with vargs to acumulate store chains. 2563 std::vector<SDValue> OutChains; 2564 2565 // Assign locations to all of the incoming arguments. 2566 SmallVector<CCValAssign, 16> ArgLocs; 2567 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2568 getTargetMachine(), ArgLocs, *DAG.getContext()); 2569 2570 if (IsO32) 2571 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2572 else 2573 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2574 2575 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2576 2577 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2578 CCValAssign &VA = ArgLocs[i]; 2579 EVT ValVT = VA.getValVT(); 2580 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2581 bool IsRegLoc = VA.isRegLoc(); 2582 2583 if (Flags.isByVal()) { 2584 assert(Flags.getByValSize() && 2585 "ByVal args of size 0 should have been ignored by front-end."); 2586 if (IsO32) { 2587 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2588 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2589 true); 2590 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2591 InVals.push_back(FIN); 2592 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2593 } else // N32/64 2594 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags, 2595 MFI, IsRegLoc, InVals, MipsFI, 2596 getPointerTy()); 2597 continue; 2598 } 2599 2600 // Arguments stored on registers 2601 if (IsRegLoc) { 2602 EVT RegVT = VA.getLocVT(); 2603 unsigned ArgReg = VA.getLocReg(); 2604 const TargetRegisterClass *RC; 2605 2606 if (RegVT == MVT::i32) 2607 RC = Mips::CPURegsRegisterClass; 2608 else if (RegVT == MVT::i64) 2609 RC = Mips::CPU64RegsRegisterClass; 2610 else if (RegVT == MVT::f32) 2611 RC = Mips::FGR32RegisterClass; 2612 else if (RegVT == MVT::f64) 2613 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; 2614 else 2615 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2616 2617 // Transform the arguments stored on 2618 // physical registers into virtual ones 2619 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2620 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2621 2622 // If this is an 8 or 16-bit value, it has been passed promoted 2623 // to 32 bits. Insert an assert[sz]ext to capture this, then 2624 // truncate to the right size. 2625 if (VA.getLocInfo() != CCValAssign::Full) { 2626 unsigned Opcode = 0; 2627 if (VA.getLocInfo() == CCValAssign::SExt) 2628 Opcode = ISD::AssertSext; 2629 else if (VA.getLocInfo() == CCValAssign::ZExt) 2630 Opcode = ISD::AssertZext; 2631 if (Opcode) 2632 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2633 DAG.getValueType(ValVT)); 2634 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 2635 } 2636 2637 // Handle floating point arguments passed in integer registers. 2638 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2639 (RegVT == MVT::i64 && ValVT == MVT::f64)) 2640 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 2641 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2642 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2643 getNextIntArgReg(ArgReg), RC); 2644 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2645 if (!Subtarget->isLittle()) 2646 std::swap(ArgValue, ArgValue2); 2647 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2648 ArgValue, ArgValue2); 2649 } 2650 2651 InVals.push_back(ArgValue); 2652 } else { // VA.isRegLoc() 2653 2654 // sanity check 2655 assert(VA.isMemLoc()); 2656 2657 // The stack pointer offset is relative to the caller stack frame. 2658 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2659 VA.getLocMemOffset(), true); 2660 2661 // Create load nodes to retrieve arguments from the stack 2662 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2663 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 2664 MachinePointerInfo::getFixedStack(LastFI), 2665 false, false, false, 0)); 2666 } 2667 } 2668 2669 // The mips ABIs for returning structs by value requires that we copy 2670 // the sret argument into $v0 for the return. Save the argument into 2671 // a virtual register so that we can access it from the return points. 2672 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2673 unsigned Reg = MipsFI->getSRetReturnReg(); 2674 if (!Reg) { 2675 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2676 MipsFI->setSRetReturnReg(Reg); 2677 } 2678 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2679 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2680 } 2681 2682 if (isVarArg) { 2683 unsigned NumOfRegs = IsO32 ? 4 : 8; 2684 const unsigned *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs; 2685 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs); 2686 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot. 2687 const TargetRegisterClass *RC 2688 = IsO32 ? Mips::CPURegsRegisterClass : Mips::CPU64RegsRegisterClass; 2689 unsigned RegSize = RC->getSize(); 2690 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize; 2691 2692 // Offset of the first variable argument from stack pointer. 2693 int FirstVaArgOffset; 2694 2695 if (IsO32 || (Idx == NumOfRegs)) { 2696 FirstVaArgOffset = 2697 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize; 2698 } else 2699 FirstVaArgOffset = RegSlotOffset; 2700 2701 // Record the frame index of the first variable argument 2702 // which is a value necessary to VASTART. 2703 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true); 2704 MipsFI->setVarArgsFrameIndex(LastFI); 2705 2706 // Copy the integer registers that have not been used for argument passing 2707 // to the argument register save area. For O32, the save area is allocated 2708 // in the caller's stack frame, while for N32/64, it is allocated in the 2709 // callee's stack frame. 2710 for (int StackOffset = RegSlotOffset; 2711 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) { 2712 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC); 2713 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, 2714 MVT::getIntegerVT(RegSize * 8)); 2715 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true); 2716 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2717 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2718 MachinePointerInfo(), false, false, 0)); 2719 } 2720 } 2721 2722 MipsFI->setLastInArgFI(LastFI); 2723 2724 // All stores are grouped in one node to allow the matching between 2725 // the size of Ins and InVals. This only happens when on varg functions 2726 if (!OutChains.empty()) { 2727 OutChains.push_back(Chain); 2728 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2729 &OutChains[0], OutChains.size()); 2730 } 2731 2732 return Chain; 2733} 2734 2735//===----------------------------------------------------------------------===// 2736// Return Value Calling Convention Implementation 2737//===----------------------------------------------------------------------===// 2738 2739SDValue 2740MipsTargetLowering::LowerReturn(SDValue Chain, 2741 CallingConv::ID CallConv, bool isVarArg, 2742 const SmallVectorImpl<ISD::OutputArg> &Outs, 2743 const SmallVectorImpl<SDValue> &OutVals, 2744 DebugLoc dl, SelectionDAG &DAG) const { 2745 2746 // CCValAssign - represent the assignment of 2747 // the return value to a location 2748 SmallVector<CCValAssign, 16> RVLocs; 2749 2750 // CCState - Info about the registers and stack slot. 2751 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2752 getTargetMachine(), RVLocs, *DAG.getContext()); 2753 2754 // Analize return values. 2755 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2756 2757 // If this is the first return lowered for this function, add 2758 // the regs to the liveout set for the function. 2759 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2760 for (unsigned i = 0; i != RVLocs.size(); ++i) 2761 if (RVLocs[i].isRegLoc()) 2762 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2763 } 2764 2765 SDValue Flag; 2766 2767 // Copy the result values into the output registers. 2768 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2769 CCValAssign &VA = RVLocs[i]; 2770 assert(VA.isRegLoc() && "Can only return in registers!"); 2771 2772 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 2773 2774 // guarantee that all emitted copies are 2775 // stuck together, avoiding something bad 2776 Flag = Chain.getValue(1); 2777 } 2778 2779 // The mips ABIs for returning structs by value requires that we copy 2780 // the sret argument into $v0 for the return. We saved the argument into 2781 // a virtual register in the entry block, so now we copy the value out 2782 // and into $v0. 2783 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2784 MachineFunction &MF = DAG.getMachineFunction(); 2785 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2786 unsigned Reg = MipsFI->getSRetReturnReg(); 2787 2788 if (!Reg) 2789 llvm_unreachable("sret virtual register not created in the entry block"); 2790 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2791 2792 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2793 Flag = Chain.getValue(1); 2794 } 2795 2796 // Return on Mips is always a "jr $ra" 2797 if (Flag.getNode()) 2798 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2799 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2800 else // Return Void 2801 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2802 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2803} 2804 2805//===----------------------------------------------------------------------===// 2806// Mips Inline Assembly Support 2807//===----------------------------------------------------------------------===// 2808 2809/// getConstraintType - Given a constraint letter, return the type of 2810/// constraint it is for this target. 2811MipsTargetLowering::ConstraintType MipsTargetLowering:: 2812getConstraintType(const std::string &Constraint) const 2813{ 2814 // Mips specific constrainy 2815 // GCC config/mips/constraints.md 2816 // 2817 // 'd' : An address register. Equivalent to r 2818 // unless generating MIPS16 code. 2819 // 'y' : Equivalent to r; retained for 2820 // backwards compatibility. 2821 // 'f' : Floating Point registers. 2822 if (Constraint.size() == 1) { 2823 switch (Constraint[0]) { 2824 default : break; 2825 case 'd': 2826 case 'y': 2827 case 'f': 2828 return C_RegisterClass; 2829 } 2830 } 2831 return TargetLowering::getConstraintType(Constraint); 2832} 2833 2834/// Examine constraint type and operand type and determine a weight value. 2835/// This object must already have been set up with the operand type 2836/// and the current alternative constraint selected. 2837TargetLowering::ConstraintWeight 2838MipsTargetLowering::getSingleConstraintMatchWeight( 2839 AsmOperandInfo &info, const char *constraint) const { 2840 ConstraintWeight weight = CW_Invalid; 2841 Value *CallOperandVal = info.CallOperandVal; 2842 // If we don't have a value, we can't do a match, 2843 // but allow it at the lowest weight. 2844 if (CallOperandVal == NULL) 2845 return CW_Default; 2846 Type *type = CallOperandVal->getType(); 2847 // Look at the constraint type. 2848 switch (*constraint) { 2849 default: 2850 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2851 break; 2852 case 'd': 2853 case 'y': 2854 if (type->isIntegerTy()) 2855 weight = CW_Register; 2856 break; 2857 case 'f': 2858 if (type->isFloatTy()) 2859 weight = CW_Register; 2860 break; 2861 } 2862 return weight; 2863} 2864 2865/// Given a register class constraint, like 'r', if this corresponds directly 2866/// to an LLVM register class, return a register of 0 and the register class 2867/// pointer. 2868std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2869getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2870{ 2871 if (Constraint.size() == 1) { 2872 switch (Constraint[0]) { 2873 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2874 case 'y': // Same as 'r'. Exists for compatibility. 2875 case 'r': 2876 if (VT == MVT::i32) 2877 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2878 assert(VT == MVT::i64 && "Unexpected type."); 2879 return std::make_pair(0U, Mips::CPU64RegsRegisterClass); 2880 case 'f': 2881 if (VT == MVT::f32) 2882 return std::make_pair(0U, Mips::FGR32RegisterClass); 2883 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2884 if (Subtarget->isFP64bit()) 2885 return std::make_pair(0U, Mips::FGR64RegisterClass); 2886 else 2887 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2888 } 2889 } 2890 } 2891 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2892} 2893 2894bool 2895MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2896 // The Mips target isn't yet aware of offsets. 2897 return false; 2898} 2899 2900bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2901 if (VT != MVT::f32 && VT != MVT::f64) 2902 return false; 2903 if (Imm.isNegZero()) 2904 return false; 2905 return Imm.isZero(); 2906} 2907 2908unsigned MipsTargetLowering::getJumpTableEncoding() const { 2909 if (IsN64) 2910 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 2911 2912 return TargetLowering::getJumpTableEncoding(); 2913} 2914