MipsISelLowering.cpp revision 46ac4399b13d46baa9e6280d540c468d8feba8ad
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/CallingConv.h" 26#include "InstPrinter/MipsInstPrinter.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/ValueTypes.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36using namespace llvm; 37 38// If I is a shifted mask, set the size (Size) and the first bit of the 39// mask (Pos), and return true. 40// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 41static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 42 if (!isUInt<32>(I) || !isShiftedMask_32(I)) 43 return false; 44 45 Size = CountPopulation_32(I); 46 Pos = CountTrailingZeros_32(I); 47 return true; 48} 49 50const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 51 switch (Opcode) { 52 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 53 case MipsISD::Hi: return "MipsISD::Hi"; 54 case MipsISD::Lo: return "MipsISD::Lo"; 55 case MipsISD::GPRel: return "MipsISD::GPRel"; 56 case MipsISD::TlsGd: return "MipsISD::TlsGd"; 57 case MipsISD::TprelHi: return "MipsISD::TprelHi"; 58 case MipsISD::TprelLo: return "MipsISD::TprelLo"; 59 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 60 case MipsISD::Ret: return "MipsISD::Ret"; 61 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 62 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 63 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 64 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 65 case MipsISD::FPRound: return "MipsISD::FPRound"; 66 case MipsISD::MAdd: return "MipsISD::MAdd"; 67 case MipsISD::MAddu: return "MipsISD::MAddu"; 68 case MipsISD::MSub: return "MipsISD::MSub"; 69 case MipsISD::MSubu: return "MipsISD::MSubu"; 70 case MipsISD::DivRem: return "MipsISD::DivRem"; 71 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 72 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 73 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 74 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; 75 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 76 case MipsISD::Sync: return "MipsISD::Sync"; 77 case MipsISD::Ext: return "MipsISD::Ext"; 78 case MipsISD::Ins: return "MipsISD::Ins"; 79 default: return NULL; 80 } 81} 82 83MipsTargetLowering:: 84MipsTargetLowering(MipsTargetMachine &TM) 85 : TargetLowering(TM, new MipsTargetObjectFile()), 86 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 87 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 88 IsO32(Subtarget->isABI_O32()) { 89 90 // Mips does not have i1 type, so use i32 for 91 // setcc operations results (slt, sgt, ...). 92 setBooleanContents(ZeroOrOneBooleanContent); 93 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 94 95 // Set up the register classes 96 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 97 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 98 99 if (HasMips64) 100 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); 101 102 // When dealing with single precision only, use libcalls 103 if (!Subtarget->isSingleFloat()) { 104 if (HasMips64) 105 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); 106 else 107 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 108 } 109 110 // Load extented operations for i1 types must be promoted 111 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 112 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 113 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 114 115 // MIPS doesn't have extending float->double load/store 116 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 117 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 118 119 // Used by legalize types to correctly generate the setcc result. 120 // Without this, every float setcc comes with a AND/OR with the result, 121 // we don't want this, since the fpcmp result goes to a flag register, 122 // which is used implicitly by brcond and select operations. 123 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 124 125 // Mips Custom Operations 126 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 127 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 128 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 129 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 130 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 131 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 132 setOperationAction(ISD::SELECT, MVT::f32, Custom); 133 setOperationAction(ISD::SELECT, MVT::f64, Custom); 134 setOperationAction(ISD::SELECT, MVT::i32, Custom); 135 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 136 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 137 setOperationAction(ISD::VASTART, MVT::Other, Custom); 138 139 setOperationAction(ISD::SDIV, MVT::i32, Expand); 140 setOperationAction(ISD::SREM, MVT::i32, Expand); 141 setOperationAction(ISD::UDIV, MVT::i32, Expand); 142 setOperationAction(ISD::UREM, MVT::i32, Expand); 143 setOperationAction(ISD::SDIV, MVT::i64, Expand); 144 setOperationAction(ISD::SREM, MVT::i64, Expand); 145 setOperationAction(ISD::UDIV, MVT::i64, Expand); 146 setOperationAction(ISD::UREM, MVT::i64, Expand); 147 148 // Operations not directly supported by Mips. 149 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 150 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 151 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 153 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 155 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 156 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 157 setOperationAction(ISD::ROTL, MVT::i32, Expand); 158 setOperationAction(ISD::ROTL, MVT::i64, Expand); 159 160 if (!Subtarget->hasMips32r2()) 161 setOperationAction(ISD::ROTR, MVT::i32, Expand); 162 163 if (!Subtarget->hasMips64r2()) 164 setOperationAction(ISD::ROTR, MVT::i64, Expand); 165 166 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 167 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 168 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 169 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 170 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 171 setOperationAction(ISD::FSIN, MVT::f32, Expand); 172 setOperationAction(ISD::FSIN, MVT::f64, Expand); 173 setOperationAction(ISD::FCOS, MVT::f32, Expand); 174 setOperationAction(ISD::FCOS, MVT::f64, Expand); 175 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 176 setOperationAction(ISD::FPOW, MVT::f32, Expand); 177 setOperationAction(ISD::FPOW, MVT::f64, Expand); 178 setOperationAction(ISD::FLOG, MVT::f32, Expand); 179 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 180 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 181 setOperationAction(ISD::FEXP, MVT::f32, Expand); 182 setOperationAction(ISD::FMA, MVT::f32, Expand); 183 setOperationAction(ISD::FMA, MVT::f64, Expand); 184 185 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 186 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 187 188 setOperationAction(ISD::VAARG, MVT::Other, Expand); 189 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 190 setOperationAction(ISD::VAEND, MVT::Other, Expand); 191 192 // Use the default for now 193 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 194 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 195 196 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 197 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 198 199 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 200 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 201 202 setInsertFencesForAtomic(true); 203 204 if (Subtarget->isSingleFloat()) 205 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 206 207 if (!Subtarget->hasSEInReg()) { 208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 210 } 211 212 if (!Subtarget->hasBitCount()) 213 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 214 215 if (!Subtarget->hasSwap()) 216 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 217 218 setTargetDAGCombine(ISD::ADDE); 219 setTargetDAGCombine(ISD::SUBE); 220 setTargetDAGCombine(ISD::SDIVREM); 221 setTargetDAGCombine(ISD::UDIVREM); 222 setTargetDAGCombine(ISD::SETCC); 223 setTargetDAGCombine(ISD::AND); 224 setTargetDAGCombine(ISD::OR); 225 226 setMinFunctionAlignment(2); 227 228 setStackPointerRegisterToSaveRestore(Mips::SP); 229 computeRegisterProperties(); 230 231 setExceptionPointerRegister(Mips::A0); 232 setExceptionSelectorRegister(Mips::A1); 233} 234 235bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 236 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 237 return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16; 238} 239 240EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 241 return MVT::i32; 242} 243 244// SelectMadd - 245// Transforms a subgraph in CurDAG if the following pattern is found: 246// (addc multLo, Lo0), (adde multHi, Hi0), 247// where, 248// multHi/Lo: product of multiplication 249// Lo0: initial value of Lo register 250// Hi0: initial value of Hi register 251// Return true if pattern matching was successful. 252static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 253 // ADDENode's second operand must be a flag output of an ADDC node in order 254 // for the matching to be successful. 255 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 256 257 if (ADDCNode->getOpcode() != ISD::ADDC) 258 return false; 259 260 SDValue MultHi = ADDENode->getOperand(0); 261 SDValue MultLo = ADDCNode->getOperand(0); 262 SDNode* MultNode = MultHi.getNode(); 263 unsigned MultOpc = MultHi.getOpcode(); 264 265 // MultHi and MultLo must be generated by the same node, 266 if (MultLo.getNode() != MultNode) 267 return false; 268 269 // and it must be a multiplication. 270 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 271 return false; 272 273 // MultLo amd MultHi must be the first and second output of MultNode 274 // respectively. 275 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 276 return false; 277 278 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 279 // of the values of MultNode, in which case MultNode will be removed in later 280 // phases. 281 // If there exist users other than ADDENode or ADDCNode, this function returns 282 // here, which will result in MultNode being mapped to a single MULT 283 // instruction node rather than a pair of MULT and MADD instructions being 284 // produced. 285 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 286 return false; 287 288 SDValue Chain = CurDAG->getEntryNode(); 289 DebugLoc dl = ADDENode->getDebugLoc(); 290 291 // create MipsMAdd(u) node 292 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 293 294 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 295 MVT::Glue, 296 MultNode->getOperand(0),// Factor 0 297 MultNode->getOperand(1),// Factor 1 298 ADDCNode->getOperand(1),// Lo0 299 ADDENode->getOperand(1));// Hi0 300 301 // create CopyFromReg nodes 302 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 303 MAdd); 304 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 305 Mips::HI, MVT::i32, 306 CopyFromLo.getValue(2)); 307 308 // replace uses of adde and addc here 309 if (!SDValue(ADDCNode, 0).use_empty()) 310 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 311 312 if (!SDValue(ADDENode, 0).use_empty()) 313 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 314 315 return true; 316} 317 318// SelectMsub - 319// Transforms a subgraph in CurDAG if the following pattern is found: 320// (addc Lo0, multLo), (sube Hi0, multHi), 321// where, 322// multHi/Lo: product of multiplication 323// Lo0: initial value of Lo register 324// Hi0: initial value of Hi register 325// Return true if pattern matching was successful. 326static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 327 // SUBENode's second operand must be a flag output of an SUBC node in order 328 // for the matching to be successful. 329 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 330 331 if (SUBCNode->getOpcode() != ISD::SUBC) 332 return false; 333 334 SDValue MultHi = SUBENode->getOperand(1); 335 SDValue MultLo = SUBCNode->getOperand(1); 336 SDNode* MultNode = MultHi.getNode(); 337 unsigned MultOpc = MultHi.getOpcode(); 338 339 // MultHi and MultLo must be generated by the same node, 340 if (MultLo.getNode() != MultNode) 341 return false; 342 343 // and it must be a multiplication. 344 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 345 return false; 346 347 // MultLo amd MultHi must be the first and second output of MultNode 348 // respectively. 349 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 350 return false; 351 352 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 353 // of the values of MultNode, in which case MultNode will be removed in later 354 // phases. 355 // If there exist users other than SUBENode or SUBCNode, this function returns 356 // here, which will result in MultNode being mapped to a single MULT 357 // instruction node rather than a pair of MULT and MSUB instructions being 358 // produced. 359 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 360 return false; 361 362 SDValue Chain = CurDAG->getEntryNode(); 363 DebugLoc dl = SUBENode->getDebugLoc(); 364 365 // create MipsSub(u) node 366 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 367 368 SDValue MSub = CurDAG->getNode(MultOpc, dl, 369 MVT::Glue, 370 MultNode->getOperand(0),// Factor 0 371 MultNode->getOperand(1),// Factor 1 372 SUBCNode->getOperand(0),// Lo0 373 SUBENode->getOperand(0));// Hi0 374 375 // create CopyFromReg nodes 376 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 377 MSub); 378 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 379 Mips::HI, MVT::i32, 380 CopyFromLo.getValue(2)); 381 382 // replace uses of sube and subc here 383 if (!SDValue(SUBCNode, 0).use_empty()) 384 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 385 386 if (!SDValue(SUBENode, 0).use_empty()) 387 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 388 389 return true; 390} 391 392static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 393 TargetLowering::DAGCombinerInfo &DCI, 394 const MipsSubtarget* Subtarget) { 395 if (DCI.isBeforeLegalize()) 396 return SDValue(); 397 398 if (Subtarget->hasMips32() && SelectMadd(N, &DAG)) 399 return SDValue(N, 0); 400 401 return SDValue(); 402} 403 404static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 405 TargetLowering::DAGCombinerInfo &DCI, 406 const MipsSubtarget* Subtarget) { 407 if (DCI.isBeforeLegalize()) 408 return SDValue(); 409 410 if (Subtarget->hasMips32() && SelectMsub(N, &DAG)) 411 return SDValue(N, 0); 412 413 return SDValue(); 414} 415 416static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 417 TargetLowering::DAGCombinerInfo &DCI, 418 const MipsSubtarget* Subtarget) { 419 if (DCI.isBeforeLegalizeOps()) 420 return SDValue(); 421 422 EVT Ty = N->getValueType(0); 423 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 424 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 425 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 426 MipsISD::DivRemU; 427 DebugLoc dl = N->getDebugLoc(); 428 429 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 430 N->getOperand(0), N->getOperand(1)); 431 SDValue InChain = DAG.getEntryNode(); 432 SDValue InGlue = DivRem; 433 434 // insert MFLO 435 if (N->hasAnyUseOfValue(0)) { 436 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 437 InGlue); 438 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 439 InChain = CopyFromLo.getValue(1); 440 InGlue = CopyFromLo.getValue(2); 441 } 442 443 // insert MFHI 444 if (N->hasAnyUseOfValue(1)) { 445 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 446 HI, Ty, InGlue); 447 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 448 } 449 450 return SDValue(); 451} 452 453static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 454 switch (CC) { 455 default: llvm_unreachable("Unknown fp condition code!"); 456 case ISD::SETEQ: 457 case ISD::SETOEQ: return Mips::FCOND_OEQ; 458 case ISD::SETUNE: return Mips::FCOND_UNE; 459 case ISD::SETLT: 460 case ISD::SETOLT: return Mips::FCOND_OLT; 461 case ISD::SETGT: 462 case ISD::SETOGT: return Mips::FCOND_OGT; 463 case ISD::SETLE: 464 case ISD::SETOLE: return Mips::FCOND_OLE; 465 case ISD::SETGE: 466 case ISD::SETOGE: return Mips::FCOND_OGE; 467 case ISD::SETULT: return Mips::FCOND_ULT; 468 case ISD::SETULE: return Mips::FCOND_ULE; 469 case ISD::SETUGT: return Mips::FCOND_UGT; 470 case ISD::SETUGE: return Mips::FCOND_UGE; 471 case ISD::SETUO: return Mips::FCOND_UN; 472 case ISD::SETO: return Mips::FCOND_OR; 473 case ISD::SETNE: 474 case ISD::SETONE: return Mips::FCOND_ONE; 475 case ISD::SETUEQ: return Mips::FCOND_UEQ; 476 } 477} 478 479 480// Returns true if condition code has to be inverted. 481static bool InvertFPCondCode(Mips::CondCode CC) { 482 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 483 return false; 484 485 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 486 return true; 487 488 assert(false && "Illegal Condition Code"); 489 return false; 490} 491 492// Creates and returns an FPCmp node from a setcc node. 493// Returns Op if setcc is not a floating point comparison. 494static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 495 // must be a SETCC node 496 if (Op.getOpcode() != ISD::SETCC) 497 return Op; 498 499 SDValue LHS = Op.getOperand(0); 500 501 if (!LHS.getValueType().isFloatingPoint()) 502 return Op; 503 504 SDValue RHS = Op.getOperand(1); 505 DebugLoc dl = Op.getDebugLoc(); 506 507 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 508 // node if necessary. 509 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 510 511 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 512 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 513} 514 515// Creates and returns a CMovFPT/F node. 516static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 517 SDValue False, DebugLoc DL) { 518 bool invert = InvertFPCondCode((Mips::CondCode) 519 cast<ConstantSDNode>(Cond.getOperand(2)) 520 ->getSExtValue()); 521 522 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 523 True.getValueType(), True, False, Cond); 524} 525 526static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 527 TargetLowering::DAGCombinerInfo &DCI, 528 const MipsSubtarget* Subtarget) { 529 if (DCI.isBeforeLegalizeOps()) 530 return SDValue(); 531 532 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 533 534 if (Cond.getOpcode() != MipsISD::FPCmp) 535 return SDValue(); 536 537 SDValue True = DAG.getConstant(1, MVT::i32); 538 SDValue False = DAG.getConstant(0, MVT::i32); 539 540 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 541} 542 543static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 544 TargetLowering::DAGCombinerInfo &DCI, 545 const MipsSubtarget* Subtarget) { 546 // Pattern match EXT. 547 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 548 // => ext $dst, $src, size, pos 549 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 550 return SDValue(); 551 552 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 553 554 // Op's first operand must be a shift right. 555 if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL) 556 return SDValue(); 557 558 // The second operand of the shift must be an immediate. 559 uint64_t Pos; 560 ConstantSDNode *CN; 561 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 562 return SDValue(); 563 564 Pos = CN->getZExtValue(); 565 566 uint64_t SMPos, SMSize; 567 // Op's second operand must be a shifted mask. 568 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 569 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 570 return SDValue(); 571 572 // Return if the shifted mask does not start at bit 0 or the sum of its size 573 // and Pos exceeds the word's size. 574 if (SMPos != 0 || Pos + SMSize > 32) 575 return SDValue(); 576 577 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32, 578 ShiftRight.getOperand(0), 579 DAG.getConstant(Pos, MVT::i32), 580 DAG.getConstant(SMSize, MVT::i32)); 581} 582 583static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 584 TargetLowering::DAGCombinerInfo &DCI, 585 const MipsSubtarget* Subtarget) { 586 // Pattern match INS. 587 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 588 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 589 // => ins $dst, $src, size, pos, $src1 590 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 591 return SDValue(); 592 593 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 594 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 595 ConstantSDNode *CN; 596 597 // See if Op's first operand matches (and $src1 , mask0). 598 if (And0.getOpcode() != ISD::AND) 599 return SDValue(); 600 601 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 602 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 603 return SDValue(); 604 605 // See if Op's second operand matches (and (shl $src, pos), mask1). 606 if (And1.getOpcode() != ISD::AND) 607 return SDValue(); 608 609 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 610 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 611 return SDValue(); 612 613 // The shift masks must have the same position and size. 614 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 615 return SDValue(); 616 617 SDValue Shl = And1.getOperand(0); 618 if (Shl.getOpcode() != ISD::SHL) 619 return SDValue(); 620 621 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 622 return SDValue(); 623 624 unsigned Shamt = CN->getZExtValue(); 625 626 // Return if the shift amount and the first bit position of mask are not the 627 // same. 628 if (Shamt != SMPos0) 629 return SDValue(); 630 631 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32, 632 Shl.getOperand(0), 633 DAG.getConstant(SMPos0, MVT::i32), 634 DAG.getConstant(SMSize0, MVT::i32), 635 And0.getOperand(0)); 636} 637 638SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 639 const { 640 SelectionDAG &DAG = DCI.DAG; 641 unsigned opc = N->getOpcode(); 642 643 switch (opc) { 644 default: break; 645 case ISD::ADDE: 646 return PerformADDECombine(N, DAG, DCI, Subtarget); 647 case ISD::SUBE: 648 return PerformSUBECombine(N, DAG, DCI, Subtarget); 649 case ISD::SDIVREM: 650 case ISD::UDIVREM: 651 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 652 case ISD::SETCC: 653 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 654 case ISD::AND: 655 return PerformANDCombine(N, DAG, DCI, Subtarget); 656 case ISD::OR: 657 return PerformORCombine(N, DAG, DCI, Subtarget); 658 } 659 660 return SDValue(); 661} 662 663SDValue MipsTargetLowering:: 664LowerOperation(SDValue Op, SelectionDAG &DAG) const 665{ 666 switch (Op.getOpcode()) 667 { 668 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 669 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 670 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 671 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 672 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 673 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 674 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 675 case ISD::SELECT: return LowerSELECT(Op, DAG); 676 case ISD::VASTART: return LowerVASTART(Op, DAG); 677 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 678 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 679 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 680 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 681 } 682 return SDValue(); 683} 684 685//===----------------------------------------------------------------------===// 686// Lower helper functions 687//===----------------------------------------------------------------------===// 688 689// AddLiveIn - This helper function adds the specified physical register to the 690// MachineFunction as a live in value. It also creates a corresponding 691// virtual register for it. 692static unsigned 693AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 694{ 695 assert(RC->contains(PReg) && "Not the correct regclass!"); 696 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 697 MF.getRegInfo().addLiveIn(PReg, VReg); 698 return VReg; 699} 700 701// Get fp branch code (not opcode) from condition code. 702static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 703 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 704 return Mips::BRANCH_T; 705 706 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 707 return Mips::BRANCH_F; 708 709 return Mips::BRANCH_INVALID; 710} 711 712/* 713static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 714 DebugLoc dl, 715 const MipsSubtarget* Subtarget, 716 const TargetInstrInfo *TII, 717 bool isFPCmp, unsigned Opc) { 718 // There is no need to expand CMov instructions if target has 719 // conditional moves. 720 if (Subtarget->hasCondMov()) 721 return BB; 722 723 // To "insert" a SELECT_CC instruction, we actually have to insert the 724 // diamond control-flow pattern. The incoming instruction knows the 725 // destination vreg to set, the condition code register to branch on, the 726 // true/false values to select between, and a branch opcode to use. 727 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 728 MachineFunction::iterator It = BB; 729 ++It; 730 731 // thisMBB: 732 // ... 733 // TrueVal = ... 734 // setcc r1, r2, r3 735 // bNE r1, r0, copy1MBB 736 // fallthrough --> copy0MBB 737 MachineBasicBlock *thisMBB = BB; 738 MachineFunction *F = BB->getParent(); 739 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 740 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 741 F->insert(It, copy0MBB); 742 F->insert(It, sinkMBB); 743 744 // Transfer the remainder of BB and its successor edges to sinkMBB. 745 sinkMBB->splice(sinkMBB->begin(), BB, 746 llvm::next(MachineBasicBlock::iterator(MI)), 747 BB->end()); 748 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 749 750 // Next, add the true and fallthrough blocks as its successors. 751 BB->addSuccessor(copy0MBB); 752 BB->addSuccessor(sinkMBB); 753 754 // Emit the right instruction according to the type of the operands compared 755 if (isFPCmp) 756 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 757 else 758 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 759 .addReg(Mips::ZERO).addMBB(sinkMBB); 760 761 // copy0MBB: 762 // %FalseValue = ... 763 // # fallthrough to sinkMBB 764 BB = copy0MBB; 765 766 // Update machine-CFG edges 767 BB->addSuccessor(sinkMBB); 768 769 // sinkMBB: 770 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 771 // ... 772 BB = sinkMBB; 773 774 if (isFPCmp) 775 BuildMI(*BB, BB->begin(), dl, 776 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 777 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 778 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 779 else 780 BuildMI(*BB, BB->begin(), dl, 781 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 782 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 783 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 784 785 MI->eraseFromParent(); // The pseudo instruction is gone now. 786 return BB; 787} 788*/ 789MachineBasicBlock * 790MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 791 MachineBasicBlock *BB) const { 792 switch (MI->getOpcode()) { 793 default: 794 assert(false && "Unexpected instr type to insert"); 795 return NULL; 796 case Mips::ATOMIC_LOAD_ADD_I8: 797 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 798 case Mips::ATOMIC_LOAD_ADD_I16: 799 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 800 case Mips::ATOMIC_LOAD_ADD_I32: 801 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 802 803 case Mips::ATOMIC_LOAD_AND_I8: 804 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 805 case Mips::ATOMIC_LOAD_AND_I16: 806 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 807 case Mips::ATOMIC_LOAD_AND_I32: 808 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 809 810 case Mips::ATOMIC_LOAD_OR_I8: 811 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 812 case Mips::ATOMIC_LOAD_OR_I16: 813 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 814 case Mips::ATOMIC_LOAD_OR_I32: 815 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 816 817 case Mips::ATOMIC_LOAD_XOR_I8: 818 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 819 case Mips::ATOMIC_LOAD_XOR_I16: 820 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 821 case Mips::ATOMIC_LOAD_XOR_I32: 822 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 823 824 case Mips::ATOMIC_LOAD_NAND_I8: 825 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 826 case Mips::ATOMIC_LOAD_NAND_I16: 827 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 828 case Mips::ATOMIC_LOAD_NAND_I32: 829 return EmitAtomicBinary(MI, BB, 4, 0, true); 830 831 case Mips::ATOMIC_LOAD_SUB_I8: 832 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 833 case Mips::ATOMIC_LOAD_SUB_I16: 834 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 835 case Mips::ATOMIC_LOAD_SUB_I32: 836 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 837 838 case Mips::ATOMIC_SWAP_I8: 839 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 840 case Mips::ATOMIC_SWAP_I16: 841 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 842 case Mips::ATOMIC_SWAP_I32: 843 return EmitAtomicBinary(MI, BB, 4, 0); 844 845 case Mips::ATOMIC_CMP_SWAP_I8: 846 return EmitAtomicCmpSwapPartword(MI, BB, 1); 847 case Mips::ATOMIC_CMP_SWAP_I16: 848 return EmitAtomicCmpSwapPartword(MI, BB, 2); 849 case Mips::ATOMIC_CMP_SWAP_I32: 850 return EmitAtomicCmpSwap(MI, BB, 4); 851 } 852} 853 854// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 855// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 856MachineBasicBlock * 857MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 858 unsigned Size, unsigned BinOpcode, 859 bool Nand) const { 860 assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); 861 862 MachineFunction *MF = BB->getParent(); 863 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 864 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 865 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 866 DebugLoc dl = MI->getDebugLoc(); 867 868 unsigned OldVal = MI->getOperand(0).getReg(); 869 unsigned Ptr = MI->getOperand(1).getReg(); 870 unsigned Incr = MI->getOperand(2).getReg(); 871 872 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 873 unsigned AndRes = RegInfo.createVirtualRegister(RC); 874 unsigned Success = RegInfo.createVirtualRegister(RC); 875 876 // insert new blocks after the current block 877 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 878 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 879 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 880 MachineFunction::iterator It = BB; 881 ++It; 882 MF->insert(It, loopMBB); 883 MF->insert(It, exitMBB); 884 885 // Transfer the remainder of BB and its successor edges to exitMBB. 886 exitMBB->splice(exitMBB->begin(), BB, 887 llvm::next(MachineBasicBlock::iterator(MI)), 888 BB->end()); 889 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 890 891 // thisMBB: 892 // ... 893 // fallthrough --> loopMBB 894 BB->addSuccessor(loopMBB); 895 loopMBB->addSuccessor(loopMBB); 896 loopMBB->addSuccessor(exitMBB); 897 898 // loopMBB: 899 // ll oldval, 0(ptr) 900 // <binop> storeval, oldval, incr 901 // sc success, storeval, 0(ptr) 902 // beq success, $0, loopMBB 903 BB = loopMBB; 904 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0); 905 if (Nand) { 906 // and andres, oldval, incr 907 // nor storeval, $0, andres 908 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr); 909 BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal) 910 .addReg(Mips::ZERO).addReg(AndRes); 911 } else if (BinOpcode) { 912 // <binop> storeval, oldval, incr 913 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 914 } else { 915 StoreVal = Incr; 916 } 917 BuildMI(BB, dl, TII->get(Mips::SC), Success) 918 .addReg(StoreVal).addReg(Ptr).addImm(0); 919 BuildMI(BB, dl, TII->get(Mips::BEQ)) 920 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 921 922 MI->eraseFromParent(); // The instruction is gone now. 923 924 return exitMBB; 925} 926 927MachineBasicBlock * 928MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 929 MachineBasicBlock *BB, 930 unsigned Size, unsigned BinOpcode, 931 bool Nand) const { 932 assert((Size == 1 || Size == 2) && 933 "Unsupported size for EmitAtomicBinaryPartial."); 934 935 MachineFunction *MF = BB->getParent(); 936 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 937 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 938 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 939 DebugLoc dl = MI->getDebugLoc(); 940 941 unsigned Dest = MI->getOperand(0).getReg(); 942 unsigned Ptr = MI->getOperand(1).getReg(); 943 unsigned Incr = MI->getOperand(2).getReg(); 944 945 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 946 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 947 unsigned Mask = RegInfo.createVirtualRegister(RC); 948 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 949 unsigned NewVal = RegInfo.createVirtualRegister(RC); 950 unsigned OldVal = RegInfo.createVirtualRegister(RC); 951 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 952 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 953 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 954 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 955 unsigned AndRes = RegInfo.createVirtualRegister(RC); 956 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 957 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 958 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 959 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 960 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 961 unsigned SllRes = RegInfo.createVirtualRegister(RC); 962 unsigned Success = RegInfo.createVirtualRegister(RC); 963 964 // insert new blocks after the current block 965 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 966 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 967 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 968 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 969 MachineFunction::iterator It = BB; 970 ++It; 971 MF->insert(It, loopMBB); 972 MF->insert(It, sinkMBB); 973 MF->insert(It, exitMBB); 974 975 // Transfer the remainder of BB and its successor edges to exitMBB. 976 exitMBB->splice(exitMBB->begin(), BB, 977 llvm::next(MachineBasicBlock::iterator(MI)), 978 BB->end()); 979 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 980 981 BB->addSuccessor(loopMBB); 982 loopMBB->addSuccessor(loopMBB); 983 loopMBB->addSuccessor(sinkMBB); 984 sinkMBB->addSuccessor(exitMBB); 985 986 // thisMBB: 987 // addiu masklsb2,$0,-4 # 0xfffffffc 988 // and alignedaddr,ptr,masklsb2 989 // andi ptrlsb2,ptr,3 990 // sll shiftamt,ptrlsb2,3 991 // ori maskupper,$0,255 # 0xff 992 // sll mask,maskupper,shiftamt 993 // nor mask2,$0,mask 994 // sll incr2,incr,shiftamt 995 996 int64_t MaskImm = (Size == 1) ? 255 : 65535; 997 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 998 .addReg(Mips::ZERO).addImm(-4); 999 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1000 .addReg(Ptr).addReg(MaskLSB2); 1001 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1002 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1003 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1004 .addReg(Mips::ZERO).addImm(MaskImm); 1005 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1006 .addReg(ShiftAmt).addReg(MaskUpper); 1007 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1008 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1009 1010 1011 // atomic.load.binop 1012 // loopMBB: 1013 // ll oldval,0(alignedaddr) 1014 // binop binopres,oldval,incr2 1015 // and newval,binopres,mask 1016 // and maskedoldval0,oldval,mask2 1017 // or storeval,maskedoldval0,newval 1018 // sc success,storeval,0(alignedaddr) 1019 // beq success,$0,loopMBB 1020 1021 // atomic.swap 1022 // loopMBB: 1023 // ll oldval,0(alignedaddr) 1024 // and newval,incr2,mask 1025 // and maskedoldval0,oldval,mask2 1026 // or storeval,maskedoldval0,newval 1027 // sc success,storeval,0(alignedaddr) 1028 // beq success,$0,loopMBB 1029 1030 BB = loopMBB; 1031 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1032 if (Nand) { 1033 // and andres, oldval, incr2 1034 // nor binopres, $0, andres 1035 // and newval, binopres, mask 1036 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1037 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1038 .addReg(Mips::ZERO).addReg(AndRes); 1039 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1040 } else if (BinOpcode) { 1041 // <binop> binopres, oldval, incr2 1042 // and newval, binopres, mask 1043 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1044 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1045 } else {// atomic.swap 1046 // and newval, incr2, mask 1047 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1048 } 1049 1050 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1051 .addReg(OldVal).addReg(Mask2); 1052 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1053 .addReg(MaskedOldVal0).addReg(NewVal); 1054 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1055 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1056 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1057 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1058 1059 // sinkMBB: 1060 // and maskedoldval1,oldval,mask 1061 // srl srlres,maskedoldval1,shiftamt 1062 // sll sllres,srlres,24 1063 // sra dest,sllres,24 1064 BB = sinkMBB; 1065 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1066 1067 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1068 .addReg(OldVal).addReg(Mask); 1069 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1070 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1071 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1072 .addReg(SrlRes).addImm(ShiftImm); 1073 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1074 .addReg(SllRes).addImm(ShiftImm); 1075 1076 MI->eraseFromParent(); // The instruction is gone now. 1077 1078 return exitMBB; 1079} 1080 1081MachineBasicBlock * 1082MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1083 MachineBasicBlock *BB, 1084 unsigned Size) const { 1085 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); 1086 1087 MachineFunction *MF = BB->getParent(); 1088 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1089 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1090 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1091 DebugLoc dl = MI->getDebugLoc(); 1092 1093 unsigned Dest = MI->getOperand(0).getReg(); 1094 unsigned Ptr = MI->getOperand(1).getReg(); 1095 unsigned OldVal = MI->getOperand(2).getReg(); 1096 unsigned NewVal = MI->getOperand(3).getReg(); 1097 1098 unsigned Success = RegInfo.createVirtualRegister(RC); 1099 1100 // insert new blocks after the current block 1101 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1102 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1103 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1104 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1105 MachineFunction::iterator It = BB; 1106 ++It; 1107 MF->insert(It, loop1MBB); 1108 MF->insert(It, loop2MBB); 1109 MF->insert(It, exitMBB); 1110 1111 // Transfer the remainder of BB and its successor edges to exitMBB. 1112 exitMBB->splice(exitMBB->begin(), BB, 1113 llvm::next(MachineBasicBlock::iterator(MI)), 1114 BB->end()); 1115 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1116 1117 // thisMBB: 1118 // ... 1119 // fallthrough --> loop1MBB 1120 BB->addSuccessor(loop1MBB); 1121 loop1MBB->addSuccessor(exitMBB); 1122 loop1MBB->addSuccessor(loop2MBB); 1123 loop2MBB->addSuccessor(loop1MBB); 1124 loop2MBB->addSuccessor(exitMBB); 1125 1126 // loop1MBB: 1127 // ll dest, 0(ptr) 1128 // bne dest, oldval, exitMBB 1129 BB = loop1MBB; 1130 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); 1131 BuildMI(BB, dl, TII->get(Mips::BNE)) 1132 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1133 1134 // loop2MBB: 1135 // sc success, newval, 0(ptr) 1136 // beq success, $0, loop1MBB 1137 BB = loop2MBB; 1138 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1139 .addReg(NewVal).addReg(Ptr).addImm(0); 1140 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1141 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1142 1143 MI->eraseFromParent(); // The instruction is gone now. 1144 1145 return exitMBB; 1146} 1147 1148MachineBasicBlock * 1149MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1150 MachineBasicBlock *BB, 1151 unsigned Size) const { 1152 assert((Size == 1 || Size == 2) && 1153 "Unsupported size for EmitAtomicCmpSwapPartial."); 1154 1155 MachineFunction *MF = BB->getParent(); 1156 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1157 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1158 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1159 DebugLoc dl = MI->getDebugLoc(); 1160 1161 unsigned Dest = MI->getOperand(0).getReg(); 1162 unsigned Ptr = MI->getOperand(1).getReg(); 1163 unsigned CmpVal = MI->getOperand(2).getReg(); 1164 unsigned NewVal = MI->getOperand(3).getReg(); 1165 1166 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1167 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1168 unsigned Mask = RegInfo.createVirtualRegister(RC); 1169 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1170 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1171 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1172 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1173 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1174 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1175 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1176 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1177 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1178 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1179 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1180 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1181 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1182 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1183 unsigned Success = RegInfo.createVirtualRegister(RC); 1184 1185 // insert new blocks after the current block 1186 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1187 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1188 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1189 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1190 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1191 MachineFunction::iterator It = BB; 1192 ++It; 1193 MF->insert(It, loop1MBB); 1194 MF->insert(It, loop2MBB); 1195 MF->insert(It, sinkMBB); 1196 MF->insert(It, exitMBB); 1197 1198 // Transfer the remainder of BB and its successor edges to exitMBB. 1199 exitMBB->splice(exitMBB->begin(), BB, 1200 llvm::next(MachineBasicBlock::iterator(MI)), 1201 BB->end()); 1202 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1203 1204 BB->addSuccessor(loop1MBB); 1205 loop1MBB->addSuccessor(sinkMBB); 1206 loop1MBB->addSuccessor(loop2MBB); 1207 loop2MBB->addSuccessor(loop1MBB); 1208 loop2MBB->addSuccessor(sinkMBB); 1209 sinkMBB->addSuccessor(exitMBB); 1210 1211 // FIXME: computation of newval2 can be moved to loop2MBB. 1212 // thisMBB: 1213 // addiu masklsb2,$0,-4 # 0xfffffffc 1214 // and alignedaddr,ptr,masklsb2 1215 // andi ptrlsb2,ptr,3 1216 // sll shiftamt,ptrlsb2,3 1217 // ori maskupper,$0,255 # 0xff 1218 // sll mask,maskupper,shiftamt 1219 // nor mask2,$0,mask 1220 // andi maskedcmpval,cmpval,255 1221 // sll shiftedcmpval,maskedcmpval,shiftamt 1222 // andi maskednewval,newval,255 1223 // sll shiftednewval,maskednewval,shiftamt 1224 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1225 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1226 .addReg(Mips::ZERO).addImm(-4); 1227 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1228 .addReg(Ptr).addReg(MaskLSB2); 1229 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1230 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1231 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1232 .addReg(Mips::ZERO).addImm(MaskImm); 1233 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1234 .addReg(ShiftAmt).addReg(MaskUpper); 1235 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1236 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1237 .addReg(CmpVal).addImm(MaskImm); 1238 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1239 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1240 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1241 .addReg(NewVal).addImm(MaskImm); 1242 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1243 .addReg(ShiftAmt).addReg(MaskedNewVal); 1244 1245 // loop1MBB: 1246 // ll oldval,0(alginedaddr) 1247 // and maskedoldval0,oldval,mask 1248 // bne maskedoldval0,shiftedcmpval,sinkMBB 1249 BB = loop1MBB; 1250 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1251 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1252 .addReg(OldVal).addReg(Mask); 1253 BuildMI(BB, dl, TII->get(Mips::BNE)) 1254 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1255 1256 // loop2MBB: 1257 // and maskedoldval1,oldval,mask2 1258 // or storeval,maskedoldval1,shiftednewval 1259 // sc success,storeval,0(alignedaddr) 1260 // beq success,$0,loop1MBB 1261 BB = loop2MBB; 1262 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1263 .addReg(OldVal).addReg(Mask2); 1264 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1265 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1266 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1267 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1268 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1269 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1270 1271 // sinkMBB: 1272 // srl srlres,maskedoldval0,shiftamt 1273 // sll sllres,srlres,24 1274 // sra dest,sllres,24 1275 BB = sinkMBB; 1276 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1277 1278 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1279 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1280 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1281 .addReg(SrlRes).addImm(ShiftImm); 1282 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1283 .addReg(SllRes).addImm(ShiftImm); 1284 1285 MI->eraseFromParent(); // The instruction is gone now. 1286 1287 return exitMBB; 1288} 1289 1290//===----------------------------------------------------------------------===// 1291// Misc Lower Operation implementation 1292//===----------------------------------------------------------------------===// 1293SDValue MipsTargetLowering:: 1294LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1295{ 1296 MachineFunction &MF = DAG.getMachineFunction(); 1297 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1298 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP; 1299 1300 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1301 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1302 "Cannot lower if the alignment of the allocated space is larger than \ 1303 that of the stack."); 1304 1305 SDValue Chain = Op.getOperand(0); 1306 SDValue Size = Op.getOperand(1); 1307 DebugLoc dl = Op.getDebugLoc(); 1308 1309 // Get a reference from Mips stack pointer 1310 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy()); 1311 1312 // Subtract the dynamic size from the actual stack size to 1313 // obtain the new stack size. 1314 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size); 1315 1316 // The Sub result contains the new stack start address, so it 1317 // must be placed in the stack pointer register. 1318 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue()); 1319 1320 // This node always has two return values: a new stack pointer 1321 // value and a chain 1322 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other); 1323 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1324 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1325 1326 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1327} 1328 1329SDValue MipsTargetLowering:: 1330LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1331{ 1332 // The first operand is the chain, the second is the condition, the third is 1333 // the block to branch to if the condition is true. 1334 SDValue Chain = Op.getOperand(0); 1335 SDValue Dest = Op.getOperand(2); 1336 DebugLoc dl = Op.getDebugLoc(); 1337 1338 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1339 1340 // Return if flag is not set by a floating point comparison. 1341 if (CondRes.getOpcode() != MipsISD::FPCmp) 1342 return Op; 1343 1344 SDValue CCNode = CondRes.getOperand(2); 1345 Mips::CondCode CC = 1346 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1347 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1348 1349 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1350 Dest, CondRes); 1351} 1352 1353SDValue MipsTargetLowering:: 1354LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1355{ 1356 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1357 1358 // Return if flag is not set by a floating point comparison. 1359 if (Cond.getOpcode() != MipsISD::FPCmp) 1360 return Op; 1361 1362 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1363 Op.getDebugLoc()); 1364} 1365 1366SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1367 SelectionDAG &DAG) const { 1368 // FIXME there isn't actually debug info here 1369 DebugLoc dl = Op.getDebugLoc(); 1370 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1371 1372 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1373 SDVTList VTs = DAG.getVTList(MVT::i32); 1374 1375 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1376 1377 // %gp_rel relocation 1378 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1379 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1380 MipsII::MO_GPREL); 1381 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1382 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1383 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1384 } 1385 // %hi/%lo relocation 1386 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1387 MipsII::MO_ABS_HI); 1388 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1389 MipsII::MO_ABS_LO); 1390 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1391 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1392 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1393 } 1394 1395 EVT ValTy = Op.getValueType(); 1396 bool HasGotOfst = (GV->hasInternalLinkage() || 1397 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1398 unsigned GotFlag = IsN64 ? 1399 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1400 MipsII::MO_GOT; 1401 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1402 GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA); 1403 SDValue ResNode = DAG.getLoad(ValTy, dl, 1404 DAG.getEntryNode(), GA, MachinePointerInfo(), 1405 false, false, false, 0); 1406 // On functions and global targets not internal linked only 1407 // a load from got/GP is necessary for PIC to work. 1408 if (!HasGotOfst) 1409 return ResNode; 1410 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1411 IsN64 ? MipsII::MO_GOT_OFST : 1412 MipsII::MO_ABS_LO); 1413 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1414 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1415} 1416 1417SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1418 SelectionDAG &DAG) const { 1419 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1420 // FIXME there isn't actually debug info here 1421 DebugLoc dl = Op.getDebugLoc(); 1422 1423 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1424 // %hi/%lo relocation 1425 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 1426 MipsII::MO_ABS_HI); 1427 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 1428 MipsII::MO_ABS_LO); 1429 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1430 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1431 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1432 } 1433 1434 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1435 MipsII::MO_GOT); 1436 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset); 1437 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1438 MipsII::MO_ABS_LO); 1439 SDValue Load = DAG.getLoad(MVT::i32, dl, 1440 DAG.getEntryNode(), BAGOTOffset, 1441 MachinePointerInfo(), false, false, false, 0); 1442 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 1443 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1444} 1445 1446SDValue MipsTargetLowering:: 1447LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1448{ 1449 // If the relocation model is PIC, use the General Dynamic TLS Model, 1450 // otherwise use the Initial Exec or Local Exec TLS Model. 1451 // TODO: implement Local Dynamic TLS model 1452 1453 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1454 DebugLoc dl = GA->getDebugLoc(); 1455 const GlobalValue *GV = GA->getGlobal(); 1456 EVT PtrVT = getPointerTy(); 1457 1458 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1459 // General Dynamic TLS Model 1460 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 1461 0, MipsII::MO_TLSGD); 1462 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); 1463 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); 1464 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); 1465 1466 ArgListTy Args; 1467 ArgListEntry Entry; 1468 Entry.Node = Argument; 1469 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1470 Args.push_back(Entry); 1471 std::pair<SDValue, SDValue> CallResult = 1472 LowerCallTo(DAG.getEntryNode(), 1473 (Type *) Type::getInt32Ty(*DAG.getContext()), 1474 false, false, false, false, 0, CallingConv::C, false, true, 1475 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, 1476 dl); 1477 1478 return CallResult.first; 1479 } 1480 1481 SDValue Offset; 1482 if (GV->isDeclaration()) { 1483 // Initial Exec TLS Model 1484 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1485 MipsII::MO_GOTTPREL); 1486 Offset = DAG.getLoad(MVT::i32, dl, 1487 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1488 false, false, false, 0); 1489 } else { 1490 // Local Exec TLS Model 1491 SDVTList VTs = DAG.getVTList(MVT::i32); 1492 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1493 MipsII::MO_TPREL_HI); 1494 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1495 MipsII::MO_TPREL_LO); 1496 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); 1497 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); 1498 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1499 } 1500 1501 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1502 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1503} 1504 1505SDValue MipsTargetLowering:: 1506LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1507{ 1508 SDValue ResNode; 1509 SDValue HiPart; 1510 // FIXME there isn't actually debug info here 1511 DebugLoc dl = Op.getDebugLoc(); 1512 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1513 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 1514 1515 EVT PtrVT = Op.getValueType(); 1516 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1517 1518 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 1519 1520 if (!IsPIC) { 1521 SDValue Ops[] = { JTI }; 1522 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 1523 } else {// Emit Load from Global Pointer 1524 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); 1525 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 1526 MachinePointerInfo(), 1527 false, false, false, 0); 1528 } 1529 1530 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 1531 MipsII::MO_ABS_LO); 1532 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 1533 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1534 1535 return ResNode; 1536} 1537 1538SDValue MipsTargetLowering:: 1539LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1540{ 1541 SDValue ResNode; 1542 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1543 const Constant *C = N->getConstVal(); 1544 // FIXME there isn't actually debug info here 1545 DebugLoc dl = Op.getDebugLoc(); 1546 1547 // gp_rel relocation 1548 // FIXME: we should reference the constant pool using small data sections, 1549 // but the asm printer currently doesn't support this feature without 1550 // hacking it. This feature should come soon so we can uncomment the 1551 // stuff below. 1552 //if (IsInSmallSection(C->getType())) { 1553 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1554 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1555 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1556 1557 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1558 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1559 N->getOffset(), MipsII::MO_ABS_HI); 1560 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1561 N->getOffset(), MipsII::MO_ABS_LO); 1562 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1563 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1564 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1565 } else { 1566 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1567 N->getOffset(), MipsII::MO_GOT); 1568 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); 1569 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 1570 CP, MachinePointerInfo::getConstantPool(), 1571 false, false, false, 0); 1572 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1573 N->getOffset(), MipsII::MO_ABS_LO); 1574 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1575 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1576 } 1577 1578 return ResNode; 1579} 1580 1581SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1582 MachineFunction &MF = DAG.getMachineFunction(); 1583 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1584 1585 DebugLoc dl = Op.getDebugLoc(); 1586 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1587 getPointerTy()); 1588 1589 // vastart just stores the address of the VarArgsFrameIndex slot into the 1590 // memory location argument. 1591 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1592 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1593 MachinePointerInfo(SV), 1594 false, false, 0); 1595} 1596 1597static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 1598 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1599 DebugLoc dl = Op.getDebugLoc(); 1600 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 1601 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 1602 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 1603 DAG.getConstant(0x7fffffff, MVT::i32)); 1604 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 1605 DAG.getConstant(0x80000000, MVT::i32)); 1606 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1607 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 1608} 1609 1610static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1611 // FIXME: 1612 // Use ext/ins instructions if target architecture is Mips32r2. 1613 // Eliminate redundant mfc1 and mtc1 instructions. 1614 unsigned LoIdx = 0, HiIdx = 1; 1615 1616 if (!isLittle) 1617 std::swap(LoIdx, HiIdx); 1618 1619 DebugLoc dl = Op.getDebugLoc(); 1620 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1621 Op.getOperand(0), 1622 DAG.getConstant(LoIdx, MVT::i32)); 1623 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1624 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1625 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1626 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1627 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1628 DAG.getConstant(0x7fffffff, MVT::i32)); 1629 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1630 DAG.getConstant(0x80000000, MVT::i32)); 1631 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1632 1633 if (!isLittle) 1634 std::swap(Word0, Word1); 1635 1636 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1637} 1638 1639SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 1640 const { 1641 EVT Ty = Op.getValueType(); 1642 1643 assert(Ty == MVT::f32 || Ty == MVT::f64); 1644 1645 if (Ty == MVT::f32) 1646 return LowerFCOPYSIGN32(Op, DAG); 1647 else 1648 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 1649} 1650 1651SDValue MipsTargetLowering:: 1652LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1653 // check the depth 1654 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1655 "Frame address can only be determined for current frame."); 1656 1657 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1658 MFI->setFrameAddressIsTaken(true); 1659 EVT VT = Op.getValueType(); 1660 DebugLoc dl = Op.getDebugLoc(); 1661 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1662 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1663 return FrameAddr; 1664} 1665 1666// TODO: set SType according to the desired memory barrier behavior. 1667SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, 1668 SelectionDAG& DAG) const { 1669 unsigned SType = 0; 1670 DebugLoc dl = Op.getDebugLoc(); 1671 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1672 DAG.getConstant(SType, MVT::i32)); 1673} 1674 1675SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1676 SelectionDAG& DAG) const { 1677 // FIXME: Need pseudo-fence for 'singlethread' fences 1678 // FIXME: Set SType for weaker fences where supported/appropriate. 1679 unsigned SType = 0; 1680 DebugLoc dl = Op.getDebugLoc(); 1681 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1682 DAG.getConstant(SType, MVT::i32)); 1683} 1684 1685//===----------------------------------------------------------------------===// 1686// Calling Convention Implementation 1687//===----------------------------------------------------------------------===// 1688 1689#include "MipsGenCallingConv.inc" 1690 1691//===----------------------------------------------------------------------===// 1692// TODO: Implement a generic logic using tblgen that can support this. 1693// Mips O32 ABI rules: 1694// --- 1695// i32 - Passed in A0, A1, A2, A3 and stack 1696// f32 - Only passed in f32 registers if no int reg has been used yet to hold 1697// an argument. Otherwise, passed in A1, A2, A3 and stack. 1698// f64 - Only passed in two aliased f32 registers if no int reg has been used 1699// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1700// not used, it must be shadowed. If only A3 is avaiable, shadow it and 1701// go to stack. 1702// 1703// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1704//===----------------------------------------------------------------------===// 1705 1706static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1707 MVT LocVT, CCValAssign::LocInfo LocInfo, 1708 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1709 1710 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1711 1712 static const unsigned IntRegs[] = { 1713 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1714 }; 1715 static const unsigned F32Regs[] = { 1716 Mips::F12, Mips::F14 1717 }; 1718 static const unsigned F64Regs[] = { 1719 Mips::D6, Mips::D7 1720 }; 1721 1722 // ByVal Args 1723 if (ArgFlags.isByVal()) { 1724 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1725 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1726 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1727 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1728 r < std::min(IntRegsSize, NextReg); ++r) 1729 State.AllocateReg(IntRegs[r]); 1730 return false; 1731 } 1732 1733 // Promote i8 and i16 1734 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1735 LocVT = MVT::i32; 1736 if (ArgFlags.isSExt()) 1737 LocInfo = CCValAssign::SExt; 1738 else if (ArgFlags.isZExt()) 1739 LocInfo = CCValAssign::ZExt; 1740 else 1741 LocInfo = CCValAssign::AExt; 1742 } 1743 1744 unsigned Reg; 1745 1746 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1747 // is true: function is vararg, argument is 3rd or higher, there is previous 1748 // argument which is not f32 or f64. 1749 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1750 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1751 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1752 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1753 1754 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1755 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1756 // If this is the first part of an i64 arg, 1757 // the allocated register must be either A0 or A2. 1758 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1759 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1760 LocVT = MVT::i32; 1761 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1762 // Allocate int register and shadow next int register. If first 1763 // available register is Mips::A1 or Mips::A3, shadow it too. 1764 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1765 if (Reg == Mips::A1 || Reg == Mips::A3) 1766 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1767 State.AllocateReg(IntRegs, IntRegsSize); 1768 LocVT = MVT::i32; 1769 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1770 // we are guaranteed to find an available float register 1771 if (ValVT == MVT::f32) { 1772 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1773 // Shadow int register 1774 State.AllocateReg(IntRegs, IntRegsSize); 1775 } else { 1776 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1777 // Shadow int registers 1778 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1779 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1780 State.AllocateReg(IntRegs, IntRegsSize); 1781 State.AllocateReg(IntRegs, IntRegsSize); 1782 } 1783 } else 1784 llvm_unreachable("Cannot handle this ValVT."); 1785 1786 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1787 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1788 1789 if (!Reg) 1790 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1791 else 1792 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1793 1794 return false; // CC must always match 1795} 1796 1797//===----------------------------------------------------------------------===// 1798// Call Calling Convention Implementation 1799//===----------------------------------------------------------------------===// 1800 1801static const unsigned O32IntRegsSize = 4; 1802 1803static const unsigned O32IntRegs[] = { 1804 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1805}; 1806 1807// Return next O32 integer argument register. 1808static unsigned getNextIntArgReg(unsigned Reg) { 1809 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 1810 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 1811} 1812 1813// Write ByVal Arg to arg registers and stack. 1814static void 1815WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 1816 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1817 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1818 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1819 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1820 MVT PtrType, bool isLittle) { 1821 unsigned LocMemOffset = VA.getLocMemOffset(); 1822 unsigned Offset = 0; 1823 uint32_t RemainingSize = Flags.getByValSize(); 1824 unsigned ByValAlign = Flags.getByValAlign(); 1825 1826 // Copy the first 4 words of byval arg to registers A0 - A3. 1827 // FIXME: Use a stricter alignment if it enables better optimization in passes 1828 // run later. 1829 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 1830 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 1831 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1832 DAG.getConstant(Offset, MVT::i32)); 1833 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1834 MachinePointerInfo(), 1835 false, false, false, std::min(ByValAlign, 1836 (unsigned )4)); 1837 MemOpChains.push_back(LoadVal.getValue(1)); 1838 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1839 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1840 } 1841 1842 if (RemainingSize == 0) 1843 return; 1844 1845 // If there still is a register available for argument passing, write the 1846 // remaining part of the structure to it using subword loads and shifts. 1847 if (LocMemOffset < 4 * 4) { 1848 assert(RemainingSize <= 3 && RemainingSize >= 1 && 1849 "There must be one to three bytes remaining."); 1850 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 1851 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1852 DAG.getConstant(Offset, MVT::i32)); 1853 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 1854 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1855 LoadPtr, MachinePointerInfo(), 1856 MVT::getIntegerVT(LoadSize * 8), false, 1857 false, Alignment); 1858 MemOpChains.push_back(LoadVal.getValue(1)); 1859 1860 // If target is big endian, shift it to the most significant half-word or 1861 // byte. 1862 if (!isLittle) 1863 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 1864 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 1865 1866 Offset += LoadSize; 1867 RemainingSize -= LoadSize; 1868 1869 // Read second subword if necessary. 1870 if (RemainingSize != 0) { 1871 assert(RemainingSize == 1 && "There must be one byte remaining."); 1872 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1873 DAG.getConstant(Offset, MVT::i32)); 1874 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 1875 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1876 LoadPtr, MachinePointerInfo(), 1877 MVT::i8, false, false, Alignment); 1878 MemOpChains.push_back(Subword.getValue(1)); 1879 // Insert the loaded byte to LoadVal. 1880 // FIXME: Use INS if supported by target. 1881 unsigned ShiftAmt = isLittle ? 16 : 8; 1882 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 1883 DAG.getConstant(ShiftAmt, MVT::i32)); 1884 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 1885 } 1886 1887 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1888 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1889 return; 1890 } 1891 1892 // Create a fixed object on stack at offset LocMemOffset and copy 1893 // remaining part of byval arg to it using memcpy. 1894 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1895 DAG.getConstant(Offset, MVT::i32)); 1896 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 1897 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1898 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 1899 DAG.getConstant(RemainingSize, MVT::i32), 1900 std::min(ByValAlign, (unsigned)4), 1901 /*isVolatile=*/false, /*AlwaysInline=*/false, 1902 MachinePointerInfo(0), MachinePointerInfo(0)); 1903} 1904 1905/// LowerCall - functions arguments are copied from virtual regs to 1906/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1907/// TODO: isTailCall. 1908SDValue 1909MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee, 1910 CallingConv::ID CallConv, bool isVarArg, 1911 bool &isTailCall, 1912 const SmallVectorImpl<ISD::OutputArg> &Outs, 1913 const SmallVectorImpl<SDValue> &OutVals, 1914 const SmallVectorImpl<ISD::InputArg> &Ins, 1915 DebugLoc dl, SelectionDAG &DAG, 1916 SmallVectorImpl<SDValue> &InVals) const { 1917 // MIPs target does not yet support tail call optimization. 1918 isTailCall = false; 1919 1920 MachineFunction &MF = DAG.getMachineFunction(); 1921 MachineFrameInfo *MFI = MF.getFrameInfo(); 1922 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1923 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1924 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1925 1926 // Analyze operands of the call, assigning locations to each operand. 1927 SmallVector<CCValAssign, 16> ArgLocs; 1928 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1929 getTargetMachine(), ArgLocs, *DAG.getContext()); 1930 1931 if (IsO32) 1932 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1933 else 1934 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1935 1936 // Get a count of how many bytes are to be pushed on the stack. 1937 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1938 1939 // Chain is the output chain of the last Load/Store or CopyToReg node. 1940 // ByValChain is the output chain of the last Memcpy node created for copying 1941 // byval arguments to the stack. 1942 SDValue Chain, CallSeqStart, ByValChain; 1943 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 1944 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal); 1945 ByValChain = InChain; 1946 1947 // If this is the first call, create a stack frame object that points to 1948 // a location to which .cprestore saves $gp. 1949 if (IsO32 && IsPIC && !MipsFI->getGPFI()) 1950 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1951 1952 // Get the frame index of the stack frame object that points to the location 1953 // of dynamically allocated area on the stack. 1954 int DynAllocFI = MipsFI->getDynAllocFI(); 1955 1956 // Update size of the maximum argument space. 1957 // For O32, a minimum of four words (16 bytes) of argument space is 1958 // allocated. 1959 if (IsO32) 1960 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1961 1962 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1963 1964 if (MaxCallFrameSize < NextStackOffset) { 1965 MipsFI->setMaxCallFrameSize(NextStackOffset); 1966 1967 // Set the offsets relative to $sp of the $gp restore slot and dynamically 1968 // allocated stack space. These offsets must be aligned to a boundary 1969 // determined by the stack alignment of the ABI. 1970 unsigned StackAlignment = TFL->getStackAlignment(); 1971 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1972 StackAlignment * StackAlignment; 1973 1974 if (MipsFI->needGPSaveRestore()) 1975 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 1976 1977 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 1978 } 1979 1980 // With EABI is it possible to have 16 args on registers. 1981 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1982 SmallVector<SDValue, 8> MemOpChains; 1983 1984 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1985 1986 // Walk the register/memloc assignments, inserting copies/loads. 1987 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1988 SDValue Arg = OutVals[i]; 1989 CCValAssign &VA = ArgLocs[i]; 1990 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 1991 1992 // Promote the value if needed. 1993 switch (VA.getLocInfo()) { 1994 default: llvm_unreachable("Unknown loc info!"); 1995 case CCValAssign::Full: 1996 if (VA.isRegLoc()) { 1997 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 1998 (ValVT == MVT::f64 && LocVT == MVT::i64)) 1999 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2000 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2001 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2002 Arg, DAG.getConstant(0, MVT::i32)); 2003 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2004 Arg, DAG.getConstant(1, MVT::i32)); 2005 if (!Subtarget->isLittle()) 2006 std::swap(Lo, Hi); 2007 unsigned LocRegLo = VA.getLocReg(); 2008 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2009 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2010 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2011 continue; 2012 } 2013 } 2014 break; 2015 case CCValAssign::SExt: 2016 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2017 break; 2018 case CCValAssign::ZExt: 2019 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2020 break; 2021 case CCValAssign::AExt: 2022 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2023 break; 2024 } 2025 2026 // Arguments that can be passed on register must be kept at 2027 // RegsToPass vector 2028 if (VA.isRegLoc()) { 2029 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2030 continue; 2031 } 2032 2033 // Register can't get to this point... 2034 assert(VA.isMemLoc()); 2035 2036 // ByVal Arg. 2037 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2038 if (Flags.isByVal()) { 2039 assert(IsO32 && 2040 "No support for ByVal args by ABIs other than O32 yet."); 2041 assert(Flags.getByValSize() && 2042 "ByVal args of size 0 should have been ignored by front-end."); 2043 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, 2044 DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle()); 2045 continue; 2046 } 2047 2048 // Create the frame index object for this incoming parameter 2049 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2050 VA.getLocMemOffset(), true); 2051 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2052 2053 // emit ISD::STORE whichs stores the 2054 // parameter value to a stack Location 2055 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2056 MachinePointerInfo(), 2057 false, false, 0)); 2058 } 2059 2060 // Extend range of indices of frame objects for outgoing arguments that were 2061 // created during this function call. Skip this step if no such objects were 2062 // created. 2063 if (LastFI) 2064 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2065 2066 // If a memcpy has been created to copy a byval arg to a stack, replace the 2067 // chain input of CallSeqStart with ByValChain. 2068 if (InChain != ByValChain) 2069 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain, 2070 NextStackOffsetVal); 2071 2072 // Transform all store nodes into one single node because all store 2073 // nodes are independent of each other. 2074 if (!MemOpChains.empty()) 2075 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2076 &MemOpChains[0], MemOpChains.size()); 2077 2078 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2079 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2080 // node so that legalize doesn't hack it. 2081 unsigned char OpFlag; 2082 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2083 bool LoadSymAddr = false; 2084 SDValue CalleeLo; 2085 2086 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2087 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2088 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2089 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2090 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2091 OpFlag); 2092 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2093 0, LoFlag); 2094 } else { 2095 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2096 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2097 getPointerTy(), 0, OpFlag); 2098 } 2099 2100 LoadSymAddr = true; 2101 } 2102 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2103 if (IsN64 || (!IsO32 && IsPIC)) 2104 OpFlag = MipsII::MO_GOT_DISP; 2105 else if (!IsPIC) // !N64 && static 2106 OpFlag = MipsII::MO_NO_FLAG; 2107 else // O32 & PIC 2108 OpFlag = MipsII::MO_GOT_CALL; 2109 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 2110 getPointerTy(), OpFlag); 2111 LoadSymAddr = true; 2112 } 2113 2114 SDValue InFlag; 2115 2116 // Create nodes that load address of callee and copy it to T9 2117 if (IsPICCall) { 2118 if (LoadSymAddr) { 2119 // Load callee address 2120 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, getPointerTy(), Callee); 2121 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2122 Callee, MachinePointerInfo::getGOT(), 2123 false, false, false, 0); 2124 2125 // Use GOT+LO if callee has internal linkage. 2126 if (CalleeLo.getNode()) { 2127 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2128 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2129 } else 2130 Callee = LoadValue; 2131 } 2132 2133 // copy to T9 2134 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2135 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2136 InFlag = Chain.getValue(1); 2137 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2138 } 2139 2140 // Build a sequence of copy-to-reg nodes chained together with token 2141 // chain and flag operands which copy the outgoing args into registers. 2142 // The InFlag in necessary since all emitted instructions must be 2143 // stuck together. 2144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2145 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2146 RegsToPass[i].second, InFlag); 2147 InFlag = Chain.getValue(1); 2148 } 2149 2150 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2151 // = Chain, Callee, Reg#1, Reg#2, ... 2152 // 2153 // Returns a chain & a flag for retval copy to use. 2154 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2155 SmallVector<SDValue, 8> Ops; 2156 Ops.push_back(Chain); 2157 Ops.push_back(Callee); 2158 2159 // Add argument registers to the end of the list so that they are 2160 // known live into the call. 2161 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2162 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2163 RegsToPass[i].second.getValueType())); 2164 2165 if (InFlag.getNode()) 2166 Ops.push_back(InFlag); 2167 2168 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2169 InFlag = Chain.getValue(1); 2170 2171 // Create the CALLSEQ_END node. 2172 Chain = DAG.getCALLSEQ_END(Chain, 2173 DAG.getIntPtrConstant(NextStackOffset, true), 2174 DAG.getIntPtrConstant(0, true), InFlag); 2175 InFlag = Chain.getValue(1); 2176 2177 // Handle result values, copying them out of physregs into vregs that we 2178 // return. 2179 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2180 Ins, dl, DAG, InVals); 2181} 2182 2183/// LowerCallResult - Lower the result values of a call into the 2184/// appropriate copies out of appropriate physical registers. 2185SDValue 2186MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2187 CallingConv::ID CallConv, bool isVarArg, 2188 const SmallVectorImpl<ISD::InputArg> &Ins, 2189 DebugLoc dl, SelectionDAG &DAG, 2190 SmallVectorImpl<SDValue> &InVals) const { 2191 // Assign locations to each value returned by this call. 2192 SmallVector<CCValAssign, 16> RVLocs; 2193 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2194 getTargetMachine(), RVLocs, *DAG.getContext()); 2195 2196 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2197 2198 // Copy all of the result registers out of their specified physreg. 2199 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2200 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2201 RVLocs[i].getValVT(), InFlag).getValue(1); 2202 InFlag = Chain.getValue(2); 2203 InVals.push_back(Chain.getValue(0)); 2204 } 2205 2206 return Chain; 2207} 2208 2209//===----------------------------------------------------------------------===// 2210// Formal Arguments Calling Convention Implementation 2211//===----------------------------------------------------------------------===// 2212static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2213 std::vector<SDValue>& OutChains, 2214 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2215 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 2216 unsigned LocMem = VA.getLocMemOffset(); 2217 unsigned FirstWord = LocMem / 4; 2218 2219 // copy register A0 - A3 to frame object 2220 for (unsigned i = 0; i < NumWords; ++i) { 2221 unsigned CurWord = FirstWord + i; 2222 if (CurWord >= O32IntRegsSize) 2223 break; 2224 2225 unsigned SrcReg = O32IntRegs[CurWord]; 2226 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2227 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2228 DAG.getConstant(i * 4, MVT::i32)); 2229 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2230 StorePtr, MachinePointerInfo(), false, 2231 false, 0); 2232 OutChains.push_back(Store); 2233 } 2234} 2235 2236/// LowerFormalArguments - transform physical registers into virtual registers 2237/// and generate load operations for arguments places on the stack. 2238SDValue 2239MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2240 CallingConv::ID CallConv, 2241 bool isVarArg, 2242 const SmallVectorImpl<ISD::InputArg> 2243 &Ins, 2244 DebugLoc dl, SelectionDAG &DAG, 2245 SmallVectorImpl<SDValue> &InVals) 2246 const { 2247 MachineFunction &MF = DAG.getMachineFunction(); 2248 MachineFrameInfo *MFI = MF.getFrameInfo(); 2249 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2250 2251 MipsFI->setVarArgsFrameIndex(0); 2252 2253 // Used with vargs to acumulate store chains. 2254 std::vector<SDValue> OutChains; 2255 2256 // Assign locations to all of the incoming arguments. 2257 SmallVector<CCValAssign, 16> ArgLocs; 2258 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2259 getTargetMachine(), ArgLocs, *DAG.getContext()); 2260 2261 if (IsO32) 2262 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2263 else 2264 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2265 2266 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2267 2268 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2269 CCValAssign &VA = ArgLocs[i]; 2270 EVT ValVT = VA.getValVT(); 2271 2272 // Arguments stored on registers 2273 if (VA.isRegLoc()) { 2274 EVT RegVT = VA.getLocVT(); 2275 unsigned ArgReg = VA.getLocReg(); 2276 TargetRegisterClass *RC = 0; 2277 2278 if (RegVT == MVT::i32) 2279 RC = Mips::CPURegsRegisterClass; 2280 else if (RegVT == MVT::i64) 2281 RC = Mips::CPU64RegsRegisterClass; 2282 else if (RegVT == MVT::f32) 2283 RC = Mips::FGR32RegisterClass; 2284 else if (RegVT == MVT::f64) 2285 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; 2286 else 2287 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2288 2289 // Transform the arguments stored on 2290 // physical registers into virtual ones 2291 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2292 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2293 2294 // If this is an 8 or 16-bit value, it has been passed promoted 2295 // to 32 bits. Insert an assert[sz]ext to capture this, then 2296 // truncate to the right size. 2297 if (VA.getLocInfo() != CCValAssign::Full) { 2298 unsigned Opcode = 0; 2299 if (VA.getLocInfo() == CCValAssign::SExt) 2300 Opcode = ISD::AssertSext; 2301 else if (VA.getLocInfo() == CCValAssign::ZExt) 2302 Opcode = ISD::AssertZext; 2303 if (Opcode) 2304 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2305 DAG.getValueType(ValVT)); 2306 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 2307 } 2308 2309 // Handle floating point arguments passed in integer registers. 2310 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2311 (RegVT == MVT::i64 && ValVT == MVT::f64)) 2312 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 2313 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2314 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2315 getNextIntArgReg(ArgReg), RC); 2316 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2317 if (!Subtarget->isLittle()) 2318 std::swap(ArgValue, ArgValue2); 2319 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2320 ArgValue, ArgValue2); 2321 } 2322 2323 InVals.push_back(ArgValue); 2324 } else { // VA.isRegLoc() 2325 2326 // sanity check 2327 assert(VA.isMemLoc()); 2328 2329 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2330 2331 if (Flags.isByVal()) { 2332 assert(IsO32 && 2333 "No support for ByVal args by ABIs other than O32 yet."); 2334 assert(Flags.getByValSize() && 2335 "ByVal args of size 0 should have been ignored by front-end."); 2336 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2337 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2338 true); 2339 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2340 InVals.push_back(FIN); 2341 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2342 2343 continue; 2344 } 2345 2346 // The stack pointer offset is relative to the caller stack frame. 2347 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2348 VA.getLocMemOffset(), true); 2349 2350 // Create load nodes to retrieve arguments from the stack 2351 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2352 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 2353 MachinePointerInfo::getFixedStack(LastFI), 2354 false, false, false, 0)); 2355 } 2356 } 2357 2358 // The mips ABIs for returning structs by value requires that we copy 2359 // the sret argument into $v0 for the return. Save the argument into 2360 // a virtual register so that we can access it from the return points. 2361 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2362 unsigned Reg = MipsFI->getSRetReturnReg(); 2363 if (!Reg) { 2364 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2365 MipsFI->setSRetReturnReg(Reg); 2366 } 2367 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2368 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2369 } 2370 2371 if (isVarArg && IsO32) { 2372 // Record the frame index of the first variable argument 2373 // which is a value necessary to VASTART. 2374 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2375 assert(NextStackOffset % 4 == 0 && 2376 "NextStackOffset must be aligned to 4-byte boundaries."); 2377 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2378 MipsFI->setVarArgsFrameIndex(LastFI); 2379 2380 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 2381 // copy the integer registers that have not been used for argument passing 2382 // to the caller's stack frame. 2383 for (; NextStackOffset < 16; NextStackOffset += 4) { 2384 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 2385 unsigned Idx = NextStackOffset / 4; 2386 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 2387 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 2388 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2389 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2390 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2391 MachinePointerInfo(), 2392 false, false, 0)); 2393 } 2394 } 2395 2396 MipsFI->setLastInArgFI(LastFI); 2397 2398 // All stores are grouped in one node to allow the matching between 2399 // the size of Ins and InVals. This only happens when on varg functions 2400 if (!OutChains.empty()) { 2401 OutChains.push_back(Chain); 2402 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2403 &OutChains[0], OutChains.size()); 2404 } 2405 2406 return Chain; 2407} 2408 2409//===----------------------------------------------------------------------===// 2410// Return Value Calling Convention Implementation 2411//===----------------------------------------------------------------------===// 2412 2413SDValue 2414MipsTargetLowering::LowerReturn(SDValue Chain, 2415 CallingConv::ID CallConv, bool isVarArg, 2416 const SmallVectorImpl<ISD::OutputArg> &Outs, 2417 const SmallVectorImpl<SDValue> &OutVals, 2418 DebugLoc dl, SelectionDAG &DAG) const { 2419 2420 // CCValAssign - represent the assignment of 2421 // the return value to a location 2422 SmallVector<CCValAssign, 16> RVLocs; 2423 2424 // CCState - Info about the registers and stack slot. 2425 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2426 getTargetMachine(), RVLocs, *DAG.getContext()); 2427 2428 // Analize return values. 2429 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2430 2431 // If this is the first return lowered for this function, add 2432 // the regs to the liveout set for the function. 2433 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2434 for (unsigned i = 0; i != RVLocs.size(); ++i) 2435 if (RVLocs[i].isRegLoc()) 2436 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2437 } 2438 2439 SDValue Flag; 2440 2441 // Copy the result values into the output registers. 2442 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2443 CCValAssign &VA = RVLocs[i]; 2444 assert(VA.isRegLoc() && "Can only return in registers!"); 2445 2446 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2447 OutVals[i], Flag); 2448 2449 // guarantee that all emitted copies are 2450 // stuck together, avoiding something bad 2451 Flag = Chain.getValue(1); 2452 } 2453 2454 // The mips ABIs for returning structs by value requires that we copy 2455 // the sret argument into $v0 for the return. We saved the argument into 2456 // a virtual register in the entry block, so now we copy the value out 2457 // and into $v0. 2458 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2459 MachineFunction &MF = DAG.getMachineFunction(); 2460 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2461 unsigned Reg = MipsFI->getSRetReturnReg(); 2462 2463 if (!Reg) 2464 llvm_unreachable("sret virtual register not created in the entry block"); 2465 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2466 2467 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2468 Flag = Chain.getValue(1); 2469 } 2470 2471 // Return on Mips is always a "jr $ra" 2472 if (Flag.getNode()) 2473 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2474 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2475 else // Return Void 2476 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2477 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2478} 2479 2480//===----------------------------------------------------------------------===// 2481// Mips Inline Assembly Support 2482//===----------------------------------------------------------------------===// 2483 2484/// getConstraintType - Given a constraint letter, return the type of 2485/// constraint it is for this target. 2486MipsTargetLowering::ConstraintType MipsTargetLowering:: 2487getConstraintType(const std::string &Constraint) const 2488{ 2489 // Mips specific constrainy 2490 // GCC config/mips/constraints.md 2491 // 2492 // 'd' : An address register. Equivalent to r 2493 // unless generating MIPS16 code. 2494 // 'y' : Equivalent to r; retained for 2495 // backwards compatibility. 2496 // 'f' : Floating Point registers. 2497 if (Constraint.size() == 1) { 2498 switch (Constraint[0]) { 2499 default : break; 2500 case 'd': 2501 case 'y': 2502 case 'f': 2503 return C_RegisterClass; 2504 break; 2505 } 2506 } 2507 return TargetLowering::getConstraintType(Constraint); 2508} 2509 2510/// Examine constraint type and operand type and determine a weight value. 2511/// This object must already have been set up with the operand type 2512/// and the current alternative constraint selected. 2513TargetLowering::ConstraintWeight 2514MipsTargetLowering::getSingleConstraintMatchWeight( 2515 AsmOperandInfo &info, const char *constraint) const { 2516 ConstraintWeight weight = CW_Invalid; 2517 Value *CallOperandVal = info.CallOperandVal; 2518 // If we don't have a value, we can't do a match, 2519 // but allow it at the lowest weight. 2520 if (CallOperandVal == NULL) 2521 return CW_Default; 2522 Type *type = CallOperandVal->getType(); 2523 // Look at the constraint type. 2524 switch (*constraint) { 2525 default: 2526 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2527 break; 2528 case 'd': 2529 case 'y': 2530 if (type->isIntegerTy()) 2531 weight = CW_Register; 2532 break; 2533 case 'f': 2534 if (type->isFloatTy()) 2535 weight = CW_Register; 2536 break; 2537 } 2538 return weight; 2539} 2540 2541/// Given a register class constraint, like 'r', if this corresponds directly 2542/// to an LLVM register class, return a register of 0 and the register class 2543/// pointer. 2544std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2545getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2546{ 2547 if (Constraint.size() == 1) { 2548 switch (Constraint[0]) { 2549 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2550 case 'y': // Same as 'r'. Exists for compatibility. 2551 case 'r': 2552 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2553 case 'f': 2554 if (VT == MVT::f32) 2555 return std::make_pair(0U, Mips::FGR32RegisterClass); 2556 if (VT == MVT::f64) 2557 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 2558 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2559 break; 2560 } 2561 } 2562 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2563} 2564 2565bool 2566MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2567 // The Mips target isn't yet aware of offsets. 2568 return false; 2569} 2570 2571bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2572 if (VT != MVT::f32 && VT != MVT::f64) 2573 return false; 2574 if (Imm.isNegZero()) 2575 return false; 2576 return Imm.isZero(); 2577} 2578