MipsISelLowering.cpp revision 648f00c2f0eb29c0ae2a333fa0bfa55970059f08
1//=== --MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16#include "MipsISelLowering.h" 17#include "MipsMachineFunction.h" 18#include "MipsTargetMachine.h" 19#include "MipsTargetObjectFile.h" 20#include "MipsSubtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/CallingConv.h" 26#include "InstPrinter/MipsInstPrinter.h" 27#include "MCTargetDesc/MipsBaseInfo.h" 28#include "llvm/CodeGen/CallingConvLower.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAGISel.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37using namespace llvm; 38 39// If I is a shifted mask, set the size (Size) and the first bit of the 40// mask (Pos), and return true. 41// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 42static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 43 if (!isShiftedMask_64(I)) 44 return false; 45 46 Size = CountPopulation_64(I); 47 Pos = CountTrailingZeros_64(I); 48 return true; 49} 50 51static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { 52 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 53 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 54} 55 56const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 57 switch (Opcode) { 58 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 59 case MipsISD::Hi: return "MipsISD::Hi"; 60 case MipsISD::Lo: return "MipsISD::Lo"; 61 case MipsISD::GPRel: return "MipsISD::GPRel"; 62 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 63 case MipsISD::Ret: return "MipsISD::Ret"; 64 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 65 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 66 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 67 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 68 case MipsISD::FPRound: return "MipsISD::FPRound"; 69 case MipsISD::MAdd: return "MipsISD::MAdd"; 70 case MipsISD::MAddu: return "MipsISD::MAddu"; 71 case MipsISD::MSub: return "MipsISD::MSub"; 72 case MipsISD::MSubu: return "MipsISD::MSubu"; 73 case MipsISD::DivRem: return "MipsISD::DivRem"; 74 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 75 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 76 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 77 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 78 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 79 case MipsISD::Sync: return "MipsISD::Sync"; 80 case MipsISD::Ext: return "MipsISD::Ext"; 81 case MipsISD::Ins: return "MipsISD::Ins"; 82 default: return NULL; 83 } 84} 85 86MipsTargetLowering:: 87MipsTargetLowering(MipsTargetMachine &TM) 88 : TargetLowering(TM, new MipsTargetObjectFile()), 89 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 90 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 91 IsO32(Subtarget->isABI_O32()) { 92 93 // Mips does not have i1 type, so use i32 for 94 // setcc operations results (slt, sgt, ...). 95 setBooleanContents(ZeroOrOneBooleanContent); 96 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 97 98 // Set up the register classes 99 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 100 101 if (HasMips64) 102 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); 103 104 if (!TM.Options.UseSoftFloat) { 105 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 106 107 // When dealing with single precision only, use libcalls 108 if (!Subtarget->isSingleFloat()) { 109 if (HasMips64) 110 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); 111 else 112 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 113 } 114 } 115 116 // Load extented operations for i1 types must be promoted 117 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 120 121 // MIPS doesn't have extending float->double load/store 122 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 123 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 124 125 // Used by legalize types to correctly generate the setcc result. 126 // Without this, every float setcc comes with a AND/OR with the result, 127 // we don't want this, since the fpcmp result goes to a flag register, 128 // which is used implicitly by brcond and select operations. 129 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 130 131 // Mips Custom Operations 132 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 133 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 134 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 135 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 136 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 137 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 138 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 139 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 140 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 141 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 142 setOperationAction(ISD::SELECT, MVT::f32, Custom); 143 setOperationAction(ISD::SELECT, MVT::f64, Custom); 144 setOperationAction(ISD::SELECT, MVT::i32, Custom); 145 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 146 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 147 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 148 setOperationAction(ISD::VASTART, MVT::Other, Custom); 149 150 setOperationAction(ISD::SDIV, MVT::i32, Expand); 151 setOperationAction(ISD::SREM, MVT::i32, Expand); 152 setOperationAction(ISD::UDIV, MVT::i32, Expand); 153 setOperationAction(ISD::UREM, MVT::i32, Expand); 154 setOperationAction(ISD::SDIV, MVT::i64, Expand); 155 setOperationAction(ISD::SREM, MVT::i64, Expand); 156 setOperationAction(ISD::UDIV, MVT::i64, Expand); 157 setOperationAction(ISD::UREM, MVT::i64, Expand); 158 159 // Operations not directly supported by Mips. 160 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 161 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 162 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 163 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 164 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 165 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 166 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 167 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 168 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 169 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 170 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 171 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 172 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 173 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 174 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 175 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 176 setOperationAction(ISD::ROTL, MVT::i32, Expand); 177 setOperationAction(ISD::ROTL, MVT::i64, Expand); 178 179 if (!Subtarget->hasMips32r2()) 180 setOperationAction(ISD::ROTR, MVT::i32, Expand); 181 182 if (!Subtarget->hasMips64r2()) 183 setOperationAction(ISD::ROTR, MVT::i64, Expand); 184 185 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 186 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 187 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 188 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 190 setOperationAction(ISD::FSIN, MVT::f32, Expand); 191 setOperationAction(ISD::FSIN, MVT::f64, Expand); 192 setOperationAction(ISD::FCOS, MVT::f32, Expand); 193 setOperationAction(ISD::FCOS, MVT::f64, Expand); 194 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 195 setOperationAction(ISD::FPOW, MVT::f32, Expand); 196 setOperationAction(ISD::FPOW, MVT::f64, Expand); 197 setOperationAction(ISD::FLOG, MVT::f32, Expand); 198 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 199 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 200 setOperationAction(ISD::FEXP, MVT::f32, Expand); 201 setOperationAction(ISD::FMA, MVT::f32, Expand); 202 setOperationAction(ISD::FMA, MVT::f64, Expand); 203 204 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 205 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 206 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 207 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 208 209 setOperationAction(ISD::VAARG, MVT::Other, Expand); 210 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 211 setOperationAction(ISD::VAEND, MVT::Other, Expand); 212 213 // Use the default for now 214 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 215 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 216 217 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 218 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 219 220 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 221 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 222 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 223 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 224 225 setInsertFencesForAtomic(true); 226 227 if (Subtarget->isSingleFloat()) 228 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 229 230 if (!Subtarget->hasSEInReg()) { 231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 233 } 234 235 if (!Subtarget->hasBitCount()) { 236 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 237 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 238 } 239 240 if (!Subtarget->hasSwap()) { 241 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 242 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 243 } 244 245 setTargetDAGCombine(ISD::ADDE); 246 setTargetDAGCombine(ISD::SUBE); 247 setTargetDAGCombine(ISD::SDIVREM); 248 setTargetDAGCombine(ISD::UDIVREM); 249 setTargetDAGCombine(ISD::SETCC); 250 setTargetDAGCombine(ISD::AND); 251 setTargetDAGCombine(ISD::OR); 252 253 setMinFunctionAlignment(2); 254 255 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 256 computeRegisterProperties(); 257 258 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 259 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 260} 261 262bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 263 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 264 return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16; 265} 266 267EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 268 return MVT::i32; 269} 270 271// SelectMadd - 272// Transforms a subgraph in CurDAG if the following pattern is found: 273// (addc multLo, Lo0), (adde multHi, Hi0), 274// where, 275// multHi/Lo: product of multiplication 276// Lo0: initial value of Lo register 277// Hi0: initial value of Hi register 278// Return true if pattern matching was successful. 279static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 280 // ADDENode's second operand must be a flag output of an ADDC node in order 281 // for the matching to be successful. 282 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 283 284 if (ADDCNode->getOpcode() != ISD::ADDC) 285 return false; 286 287 SDValue MultHi = ADDENode->getOperand(0); 288 SDValue MultLo = ADDCNode->getOperand(0); 289 SDNode* MultNode = MultHi.getNode(); 290 unsigned MultOpc = MultHi.getOpcode(); 291 292 // MultHi and MultLo must be generated by the same node, 293 if (MultLo.getNode() != MultNode) 294 return false; 295 296 // and it must be a multiplication. 297 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 298 return false; 299 300 // MultLo amd MultHi must be the first and second output of MultNode 301 // respectively. 302 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 303 return false; 304 305 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 306 // of the values of MultNode, in which case MultNode will be removed in later 307 // phases. 308 // If there exist users other than ADDENode or ADDCNode, this function returns 309 // here, which will result in MultNode being mapped to a single MULT 310 // instruction node rather than a pair of MULT and MADD instructions being 311 // produced. 312 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 313 return false; 314 315 SDValue Chain = CurDAG->getEntryNode(); 316 DebugLoc dl = ADDENode->getDebugLoc(); 317 318 // create MipsMAdd(u) node 319 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 320 321 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue, 322 MultNode->getOperand(0),// Factor 0 323 MultNode->getOperand(1),// Factor 1 324 ADDCNode->getOperand(1),// Lo0 325 ADDENode->getOperand(1));// Hi0 326 327 // create CopyFromReg nodes 328 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 329 MAdd); 330 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 331 Mips::HI, MVT::i32, 332 CopyFromLo.getValue(2)); 333 334 // replace uses of adde and addc here 335 if (!SDValue(ADDCNode, 0).use_empty()) 336 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 337 338 if (!SDValue(ADDENode, 0).use_empty()) 339 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 340 341 return true; 342} 343 344// SelectMsub - 345// Transforms a subgraph in CurDAG if the following pattern is found: 346// (addc Lo0, multLo), (sube Hi0, multHi), 347// where, 348// multHi/Lo: product of multiplication 349// Lo0: initial value of Lo register 350// Hi0: initial value of Hi register 351// Return true if pattern matching was successful. 352static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 353 // SUBENode's second operand must be a flag output of an SUBC node in order 354 // for the matching to be successful. 355 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 356 357 if (SUBCNode->getOpcode() != ISD::SUBC) 358 return false; 359 360 SDValue MultHi = SUBENode->getOperand(1); 361 SDValue MultLo = SUBCNode->getOperand(1); 362 SDNode* MultNode = MultHi.getNode(); 363 unsigned MultOpc = MultHi.getOpcode(); 364 365 // MultHi and MultLo must be generated by the same node, 366 if (MultLo.getNode() != MultNode) 367 return false; 368 369 // and it must be a multiplication. 370 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 371 return false; 372 373 // MultLo amd MultHi must be the first and second output of MultNode 374 // respectively. 375 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 376 return false; 377 378 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 379 // of the values of MultNode, in which case MultNode will be removed in later 380 // phases. 381 // If there exist users other than SUBENode or SUBCNode, this function returns 382 // here, which will result in MultNode being mapped to a single MULT 383 // instruction node rather than a pair of MULT and MSUB instructions being 384 // produced. 385 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 386 return false; 387 388 SDValue Chain = CurDAG->getEntryNode(); 389 DebugLoc dl = SUBENode->getDebugLoc(); 390 391 // create MipsSub(u) node 392 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 393 394 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue, 395 MultNode->getOperand(0),// Factor 0 396 MultNode->getOperand(1),// Factor 1 397 SUBCNode->getOperand(0),// Lo0 398 SUBENode->getOperand(0));// Hi0 399 400 // create CopyFromReg nodes 401 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 402 MSub); 403 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 404 Mips::HI, MVT::i32, 405 CopyFromLo.getValue(2)); 406 407 // replace uses of sube and subc here 408 if (!SDValue(SUBCNode, 0).use_empty()) 409 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 410 411 if (!SDValue(SUBENode, 0).use_empty()) 412 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 413 414 return true; 415} 416 417static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 418 TargetLowering::DAGCombinerInfo &DCI, 419 const MipsSubtarget* Subtarget) { 420 if (DCI.isBeforeLegalize()) 421 return SDValue(); 422 423 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 424 SelectMadd(N, &DAG)) 425 return SDValue(N, 0); 426 427 return SDValue(); 428} 429 430static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 431 TargetLowering::DAGCombinerInfo &DCI, 432 const MipsSubtarget* Subtarget) { 433 if (DCI.isBeforeLegalize()) 434 return SDValue(); 435 436 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 437 SelectMsub(N, &DAG)) 438 return SDValue(N, 0); 439 440 return SDValue(); 441} 442 443static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 444 TargetLowering::DAGCombinerInfo &DCI, 445 const MipsSubtarget* Subtarget) { 446 if (DCI.isBeforeLegalizeOps()) 447 return SDValue(); 448 449 EVT Ty = N->getValueType(0); 450 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 451 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 452 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 453 MipsISD::DivRemU; 454 DebugLoc dl = N->getDebugLoc(); 455 456 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 457 N->getOperand(0), N->getOperand(1)); 458 SDValue InChain = DAG.getEntryNode(); 459 SDValue InGlue = DivRem; 460 461 // insert MFLO 462 if (N->hasAnyUseOfValue(0)) { 463 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 464 InGlue); 465 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 466 InChain = CopyFromLo.getValue(1); 467 InGlue = CopyFromLo.getValue(2); 468 } 469 470 // insert MFHI 471 if (N->hasAnyUseOfValue(1)) { 472 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 473 HI, Ty, InGlue); 474 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 475 } 476 477 return SDValue(); 478} 479 480static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 481 switch (CC) { 482 default: llvm_unreachable("Unknown fp condition code!"); 483 case ISD::SETEQ: 484 case ISD::SETOEQ: return Mips::FCOND_OEQ; 485 case ISD::SETUNE: return Mips::FCOND_UNE; 486 case ISD::SETLT: 487 case ISD::SETOLT: return Mips::FCOND_OLT; 488 case ISD::SETGT: 489 case ISD::SETOGT: return Mips::FCOND_OGT; 490 case ISD::SETLE: 491 case ISD::SETOLE: return Mips::FCOND_OLE; 492 case ISD::SETGE: 493 case ISD::SETOGE: return Mips::FCOND_OGE; 494 case ISD::SETULT: return Mips::FCOND_ULT; 495 case ISD::SETULE: return Mips::FCOND_ULE; 496 case ISD::SETUGT: return Mips::FCOND_UGT; 497 case ISD::SETUGE: return Mips::FCOND_UGE; 498 case ISD::SETUO: return Mips::FCOND_UN; 499 case ISD::SETO: return Mips::FCOND_OR; 500 case ISD::SETNE: 501 case ISD::SETONE: return Mips::FCOND_ONE; 502 case ISD::SETUEQ: return Mips::FCOND_UEQ; 503 } 504} 505 506 507// Returns true if condition code has to be inverted. 508static bool InvertFPCondCode(Mips::CondCode CC) { 509 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 510 return false; 511 512 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 513 "Illegal Condition Code"); 514 515 return true; 516} 517 518// Creates and returns an FPCmp node from a setcc node. 519// Returns Op if setcc is not a floating point comparison. 520static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 521 // must be a SETCC node 522 if (Op.getOpcode() != ISD::SETCC) 523 return Op; 524 525 SDValue LHS = Op.getOperand(0); 526 527 if (!LHS.getValueType().isFloatingPoint()) 528 return Op; 529 530 SDValue RHS = Op.getOperand(1); 531 DebugLoc dl = Op.getDebugLoc(); 532 533 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 534 // node if necessary. 535 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 536 537 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 538 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 539} 540 541// Creates and returns a CMovFPT/F node. 542static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 543 SDValue False, DebugLoc DL) { 544 bool invert = InvertFPCondCode((Mips::CondCode) 545 cast<ConstantSDNode>(Cond.getOperand(2)) 546 ->getSExtValue()); 547 548 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 549 True.getValueType(), True, False, Cond); 550} 551 552static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 553 TargetLowering::DAGCombinerInfo &DCI, 554 const MipsSubtarget* Subtarget) { 555 if (DCI.isBeforeLegalizeOps()) 556 return SDValue(); 557 558 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 559 560 if (Cond.getOpcode() != MipsISD::FPCmp) 561 return SDValue(); 562 563 SDValue True = DAG.getConstant(1, MVT::i32); 564 SDValue False = DAG.getConstant(0, MVT::i32); 565 566 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 567} 568 569static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 570 TargetLowering::DAGCombinerInfo &DCI, 571 const MipsSubtarget* Subtarget) { 572 // Pattern match EXT. 573 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 574 // => ext $dst, $src, size, pos 575 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 576 return SDValue(); 577 578 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 579 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 580 581 // Op's first operand must be a shift right. 582 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 583 return SDValue(); 584 585 // The second operand of the shift must be an immediate. 586 ConstantSDNode *CN; 587 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 588 return SDValue(); 589 590 uint64_t Pos = CN->getZExtValue(); 591 uint64_t SMPos, SMSize; 592 593 // Op's second operand must be a shifted mask. 594 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 595 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 596 return SDValue(); 597 598 // Return if the shifted mask does not start at bit 0 or the sum of its size 599 // and Pos exceeds the word's size. 600 EVT ValTy = N->getValueType(0); 601 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 602 return SDValue(); 603 604 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy, 605 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 606 DAG.getConstant(SMSize, MVT::i32)); 607} 608 609static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 610 TargetLowering::DAGCombinerInfo &DCI, 611 const MipsSubtarget* Subtarget) { 612 // Pattern match INS. 613 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 614 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 615 // => ins $dst, $src, size, pos, $src1 616 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 617 return SDValue(); 618 619 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 620 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 621 ConstantSDNode *CN; 622 623 // See if Op's first operand matches (and $src1 , mask0). 624 if (And0.getOpcode() != ISD::AND) 625 return SDValue(); 626 627 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 628 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 629 return SDValue(); 630 631 // See if Op's second operand matches (and (shl $src, pos), mask1). 632 if (And1.getOpcode() != ISD::AND) 633 return SDValue(); 634 635 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 636 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 637 return SDValue(); 638 639 // The shift masks must have the same position and size. 640 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 641 return SDValue(); 642 643 SDValue Shl = And1.getOperand(0); 644 if (Shl.getOpcode() != ISD::SHL) 645 return SDValue(); 646 647 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 648 return SDValue(); 649 650 unsigned Shamt = CN->getZExtValue(); 651 652 // Return if the shift amount and the first bit position of mask are not the 653 // same. 654 EVT ValTy = N->getValueType(0); 655 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 656 return SDValue(); 657 658 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0), 659 DAG.getConstant(SMPos0, MVT::i32), 660 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 661} 662 663SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 664 const { 665 SelectionDAG &DAG = DCI.DAG; 666 unsigned opc = N->getOpcode(); 667 668 switch (opc) { 669 default: break; 670 case ISD::ADDE: 671 return PerformADDECombine(N, DAG, DCI, Subtarget); 672 case ISD::SUBE: 673 return PerformSUBECombine(N, DAG, DCI, Subtarget); 674 case ISD::SDIVREM: 675 case ISD::UDIVREM: 676 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 677 case ISD::SETCC: 678 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 679 case ISD::AND: 680 return PerformANDCombine(N, DAG, DCI, Subtarget); 681 case ISD::OR: 682 return PerformORCombine(N, DAG, DCI, Subtarget); 683 } 684 685 return SDValue(); 686} 687 688SDValue MipsTargetLowering:: 689LowerOperation(SDValue Op, SelectionDAG &DAG) const 690{ 691 switch (Op.getOpcode()) 692 { 693 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 694 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 695 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 696 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 697 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 698 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 699 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 700 case ISD::SELECT: return LowerSELECT(Op, DAG); 701 case ISD::VASTART: return LowerVASTART(Op, DAG); 702 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 703 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 704 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 705 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 706 } 707 return SDValue(); 708} 709 710//===----------------------------------------------------------------------===// 711// Lower helper functions 712//===----------------------------------------------------------------------===// 713 714// AddLiveIn - This helper function adds the specified physical register to the 715// MachineFunction as a live in value. It also creates a corresponding 716// virtual register for it. 717static unsigned 718AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 719{ 720 assert(RC->contains(PReg) && "Not the correct regclass!"); 721 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 722 MF.getRegInfo().addLiveIn(PReg, VReg); 723 return VReg; 724} 725 726// Get fp branch code (not opcode) from condition code. 727static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 728 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 729 return Mips::BRANCH_T; 730 731 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 732 "Invalid CondCode."); 733 734 return Mips::BRANCH_F; 735} 736 737/* 738static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 739 DebugLoc dl, 740 const MipsSubtarget* Subtarget, 741 const TargetInstrInfo *TII, 742 bool isFPCmp, unsigned Opc) { 743 // There is no need to expand CMov instructions if target has 744 // conditional moves. 745 if (Subtarget->hasCondMov()) 746 return BB; 747 748 // To "insert" a SELECT_CC instruction, we actually have to insert the 749 // diamond control-flow pattern. The incoming instruction knows the 750 // destination vreg to set, the condition code register to branch on, the 751 // true/false values to select between, and a branch opcode to use. 752 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 753 MachineFunction::iterator It = BB; 754 ++It; 755 756 // thisMBB: 757 // ... 758 // TrueVal = ... 759 // setcc r1, r2, r3 760 // bNE r1, r0, copy1MBB 761 // fallthrough --> copy0MBB 762 MachineBasicBlock *thisMBB = BB; 763 MachineFunction *F = BB->getParent(); 764 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 765 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 766 F->insert(It, copy0MBB); 767 F->insert(It, sinkMBB); 768 769 // Transfer the remainder of BB and its successor edges to sinkMBB. 770 sinkMBB->splice(sinkMBB->begin(), BB, 771 llvm::next(MachineBasicBlock::iterator(MI)), 772 BB->end()); 773 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 774 775 // Next, add the true and fallthrough blocks as its successors. 776 BB->addSuccessor(copy0MBB); 777 BB->addSuccessor(sinkMBB); 778 779 // Emit the right instruction according to the type of the operands compared 780 if (isFPCmp) 781 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 782 else 783 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 784 .addReg(Mips::ZERO).addMBB(sinkMBB); 785 786 // copy0MBB: 787 // %FalseValue = ... 788 // # fallthrough to sinkMBB 789 BB = copy0MBB; 790 791 // Update machine-CFG edges 792 BB->addSuccessor(sinkMBB); 793 794 // sinkMBB: 795 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 796 // ... 797 BB = sinkMBB; 798 799 if (isFPCmp) 800 BuildMI(*BB, BB->begin(), dl, 801 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 802 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 803 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 804 else 805 BuildMI(*BB, BB->begin(), dl, 806 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 807 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 808 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 809 810 MI->eraseFromParent(); // The pseudo instruction is gone now. 811 return BB; 812} 813*/ 814MachineBasicBlock * 815MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 816 MachineBasicBlock *BB) const { 817 switch (MI->getOpcode()) { 818 default: llvm_unreachable("Unexpected instr type to insert"); 819 case Mips::ATOMIC_LOAD_ADD_I8: 820 case Mips::ATOMIC_LOAD_ADD_I8_P8: 821 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 822 case Mips::ATOMIC_LOAD_ADD_I16: 823 case Mips::ATOMIC_LOAD_ADD_I16_P8: 824 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 825 case Mips::ATOMIC_LOAD_ADD_I32: 826 case Mips::ATOMIC_LOAD_ADD_I32_P8: 827 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 828 case Mips::ATOMIC_LOAD_ADD_I64: 829 case Mips::ATOMIC_LOAD_ADD_I64_P8: 830 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu); 831 832 case Mips::ATOMIC_LOAD_AND_I8: 833 case Mips::ATOMIC_LOAD_AND_I8_P8: 834 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 835 case Mips::ATOMIC_LOAD_AND_I16: 836 case Mips::ATOMIC_LOAD_AND_I16_P8: 837 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 838 case Mips::ATOMIC_LOAD_AND_I32: 839 case Mips::ATOMIC_LOAD_AND_I32_P8: 840 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 841 case Mips::ATOMIC_LOAD_AND_I64: 842 case Mips::ATOMIC_LOAD_AND_I64_P8: 843 return EmitAtomicBinary(MI, BB, 8, Mips::AND64); 844 845 case Mips::ATOMIC_LOAD_OR_I8: 846 case Mips::ATOMIC_LOAD_OR_I8_P8: 847 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 848 case Mips::ATOMIC_LOAD_OR_I16: 849 case Mips::ATOMIC_LOAD_OR_I16_P8: 850 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 851 case Mips::ATOMIC_LOAD_OR_I32: 852 case Mips::ATOMIC_LOAD_OR_I32_P8: 853 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 854 case Mips::ATOMIC_LOAD_OR_I64: 855 case Mips::ATOMIC_LOAD_OR_I64_P8: 856 return EmitAtomicBinary(MI, BB, 8, Mips::OR64); 857 858 case Mips::ATOMIC_LOAD_XOR_I8: 859 case Mips::ATOMIC_LOAD_XOR_I8_P8: 860 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 861 case Mips::ATOMIC_LOAD_XOR_I16: 862 case Mips::ATOMIC_LOAD_XOR_I16_P8: 863 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 864 case Mips::ATOMIC_LOAD_XOR_I32: 865 case Mips::ATOMIC_LOAD_XOR_I32_P8: 866 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 867 case Mips::ATOMIC_LOAD_XOR_I64: 868 case Mips::ATOMIC_LOAD_XOR_I64_P8: 869 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64); 870 871 case Mips::ATOMIC_LOAD_NAND_I8: 872 case Mips::ATOMIC_LOAD_NAND_I8_P8: 873 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 874 case Mips::ATOMIC_LOAD_NAND_I16: 875 case Mips::ATOMIC_LOAD_NAND_I16_P8: 876 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 877 case Mips::ATOMIC_LOAD_NAND_I32: 878 case Mips::ATOMIC_LOAD_NAND_I32_P8: 879 return EmitAtomicBinary(MI, BB, 4, 0, true); 880 case Mips::ATOMIC_LOAD_NAND_I64: 881 case Mips::ATOMIC_LOAD_NAND_I64_P8: 882 return EmitAtomicBinary(MI, BB, 8, 0, true); 883 884 case Mips::ATOMIC_LOAD_SUB_I8: 885 case Mips::ATOMIC_LOAD_SUB_I8_P8: 886 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 887 case Mips::ATOMIC_LOAD_SUB_I16: 888 case Mips::ATOMIC_LOAD_SUB_I16_P8: 889 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 890 case Mips::ATOMIC_LOAD_SUB_I32: 891 case Mips::ATOMIC_LOAD_SUB_I32_P8: 892 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 893 case Mips::ATOMIC_LOAD_SUB_I64: 894 case Mips::ATOMIC_LOAD_SUB_I64_P8: 895 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu); 896 897 case Mips::ATOMIC_SWAP_I8: 898 case Mips::ATOMIC_SWAP_I8_P8: 899 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 900 case Mips::ATOMIC_SWAP_I16: 901 case Mips::ATOMIC_SWAP_I16_P8: 902 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 903 case Mips::ATOMIC_SWAP_I32: 904 case Mips::ATOMIC_SWAP_I32_P8: 905 return EmitAtomicBinary(MI, BB, 4, 0); 906 case Mips::ATOMIC_SWAP_I64: 907 case Mips::ATOMIC_SWAP_I64_P8: 908 return EmitAtomicBinary(MI, BB, 8, 0); 909 910 case Mips::ATOMIC_CMP_SWAP_I8: 911 case Mips::ATOMIC_CMP_SWAP_I8_P8: 912 return EmitAtomicCmpSwapPartword(MI, BB, 1); 913 case Mips::ATOMIC_CMP_SWAP_I16: 914 case Mips::ATOMIC_CMP_SWAP_I16_P8: 915 return EmitAtomicCmpSwapPartword(MI, BB, 2); 916 case Mips::ATOMIC_CMP_SWAP_I32: 917 case Mips::ATOMIC_CMP_SWAP_I32_P8: 918 return EmitAtomicCmpSwap(MI, BB, 4); 919 case Mips::ATOMIC_CMP_SWAP_I64: 920 case Mips::ATOMIC_CMP_SWAP_I64_P8: 921 return EmitAtomicCmpSwap(MI, BB, 8); 922 } 923} 924 925// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 926// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 927MachineBasicBlock * 928MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 929 unsigned Size, unsigned BinOpcode, 930 bool Nand) const { 931 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 932 933 MachineFunction *MF = BB->getParent(); 934 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 935 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 936 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 937 DebugLoc dl = MI->getDebugLoc(); 938 unsigned LL, SC, AND, NOR, ZERO, BEQ; 939 940 if (Size == 4) { 941 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 942 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 943 AND = Mips::AND; 944 NOR = Mips::NOR; 945 ZERO = Mips::ZERO; 946 BEQ = Mips::BEQ; 947 } 948 else { 949 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 950 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 951 AND = Mips::AND64; 952 NOR = Mips::NOR64; 953 ZERO = Mips::ZERO_64; 954 BEQ = Mips::BEQ64; 955 } 956 957 unsigned OldVal = MI->getOperand(0).getReg(); 958 unsigned Ptr = MI->getOperand(1).getReg(); 959 unsigned Incr = MI->getOperand(2).getReg(); 960 961 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 962 unsigned AndRes = RegInfo.createVirtualRegister(RC); 963 unsigned Success = RegInfo.createVirtualRegister(RC); 964 965 // insert new blocks after the current block 966 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 967 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 968 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 969 MachineFunction::iterator It = BB; 970 ++It; 971 MF->insert(It, loopMBB); 972 MF->insert(It, exitMBB); 973 974 // Transfer the remainder of BB and its successor edges to exitMBB. 975 exitMBB->splice(exitMBB->begin(), BB, 976 llvm::next(MachineBasicBlock::iterator(MI)), 977 BB->end()); 978 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 979 980 // thisMBB: 981 // ... 982 // fallthrough --> loopMBB 983 BB->addSuccessor(loopMBB); 984 loopMBB->addSuccessor(loopMBB); 985 loopMBB->addSuccessor(exitMBB); 986 987 // loopMBB: 988 // ll oldval, 0(ptr) 989 // <binop> storeval, oldval, incr 990 // sc success, storeval, 0(ptr) 991 // beq success, $0, loopMBB 992 BB = loopMBB; 993 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 994 if (Nand) { 995 // and andres, oldval, incr 996 // nor storeval, $0, andres 997 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 998 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 999 } else if (BinOpcode) { 1000 // <binop> storeval, oldval, incr 1001 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1002 } else { 1003 StoreVal = Incr; 1004 } 1005 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1006 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1007 1008 MI->eraseFromParent(); // The instruction is gone now. 1009 1010 return exitMBB; 1011} 1012 1013MachineBasicBlock * 1014MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 1015 MachineBasicBlock *BB, 1016 unsigned Size, unsigned BinOpcode, 1017 bool Nand) const { 1018 assert((Size == 1 || Size == 2) && 1019 "Unsupported size for EmitAtomicBinaryPartial."); 1020 1021 MachineFunction *MF = BB->getParent(); 1022 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1023 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1024 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1025 DebugLoc dl = MI->getDebugLoc(); 1026 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1027 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1028 1029 unsigned Dest = MI->getOperand(0).getReg(); 1030 unsigned Ptr = MI->getOperand(1).getReg(); 1031 unsigned Incr = MI->getOperand(2).getReg(); 1032 1033 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1034 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1035 unsigned Mask = RegInfo.createVirtualRegister(RC); 1036 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1037 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1038 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1039 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1040 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1041 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1042 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1043 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1044 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1045 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1046 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1047 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1048 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1049 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1050 unsigned Success = RegInfo.createVirtualRegister(RC); 1051 1052 // insert new blocks after the current block 1053 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1054 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1055 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1056 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1057 MachineFunction::iterator It = BB; 1058 ++It; 1059 MF->insert(It, loopMBB); 1060 MF->insert(It, sinkMBB); 1061 MF->insert(It, exitMBB); 1062 1063 // Transfer the remainder of BB and its successor edges to exitMBB. 1064 exitMBB->splice(exitMBB->begin(), BB, 1065 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1066 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1067 1068 BB->addSuccessor(loopMBB); 1069 loopMBB->addSuccessor(loopMBB); 1070 loopMBB->addSuccessor(sinkMBB); 1071 sinkMBB->addSuccessor(exitMBB); 1072 1073 // thisMBB: 1074 // addiu masklsb2,$0,-4 # 0xfffffffc 1075 // and alignedaddr,ptr,masklsb2 1076 // andi ptrlsb2,ptr,3 1077 // sll shiftamt,ptrlsb2,3 1078 // ori maskupper,$0,255 # 0xff 1079 // sll mask,maskupper,shiftamt 1080 // nor mask2,$0,mask 1081 // sll incr2,incr,shiftamt 1082 1083 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1084 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1085 .addReg(Mips::ZERO).addImm(-4); 1086 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1087 .addReg(Ptr).addReg(MaskLSB2); 1088 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1089 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1090 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1091 .addReg(Mips::ZERO).addImm(MaskImm); 1092 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1093 .addReg(ShiftAmt).addReg(MaskUpper); 1094 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1095 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1096 1097 // atomic.load.binop 1098 // loopMBB: 1099 // ll oldval,0(alignedaddr) 1100 // binop binopres,oldval,incr2 1101 // and newval,binopres,mask 1102 // and maskedoldval0,oldval,mask2 1103 // or storeval,maskedoldval0,newval 1104 // sc success,storeval,0(alignedaddr) 1105 // beq success,$0,loopMBB 1106 1107 // atomic.swap 1108 // loopMBB: 1109 // ll oldval,0(alignedaddr) 1110 // and newval,incr2,mask 1111 // and maskedoldval0,oldval,mask2 1112 // or storeval,maskedoldval0,newval 1113 // sc success,storeval,0(alignedaddr) 1114 // beq success,$0,loopMBB 1115 1116 BB = loopMBB; 1117 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1118 if (Nand) { 1119 // and andres, oldval, incr2 1120 // nor binopres, $0, andres 1121 // and newval, binopres, mask 1122 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1123 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1124 .addReg(Mips::ZERO).addReg(AndRes); 1125 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1126 } else if (BinOpcode) { 1127 // <binop> binopres, oldval, incr2 1128 // and newval, binopres, mask 1129 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1130 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1131 } else {// atomic.swap 1132 // and newval, incr2, mask 1133 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1134 } 1135 1136 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1137 .addReg(OldVal).addReg(Mask2); 1138 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1139 .addReg(MaskedOldVal0).addReg(NewVal); 1140 BuildMI(BB, dl, TII->get(SC), Success) 1141 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1142 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1143 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1144 1145 // sinkMBB: 1146 // and maskedoldval1,oldval,mask 1147 // srl srlres,maskedoldval1,shiftamt 1148 // sll sllres,srlres,24 1149 // sra dest,sllres,24 1150 BB = sinkMBB; 1151 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1152 1153 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1154 .addReg(OldVal).addReg(Mask); 1155 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1156 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1157 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1158 .addReg(SrlRes).addImm(ShiftImm); 1159 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1160 .addReg(SllRes).addImm(ShiftImm); 1161 1162 MI->eraseFromParent(); // The instruction is gone now. 1163 1164 return exitMBB; 1165} 1166 1167MachineBasicBlock * 1168MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1169 MachineBasicBlock *BB, 1170 unsigned Size) const { 1171 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1172 1173 MachineFunction *MF = BB->getParent(); 1174 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1175 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1176 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1177 DebugLoc dl = MI->getDebugLoc(); 1178 unsigned LL, SC, ZERO, BNE, BEQ; 1179 1180 if (Size == 4) { 1181 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1182 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1183 ZERO = Mips::ZERO; 1184 BNE = Mips::BNE; 1185 BEQ = Mips::BEQ; 1186 } 1187 else { 1188 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1189 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1190 ZERO = Mips::ZERO_64; 1191 BNE = Mips::BNE64; 1192 BEQ = Mips::BEQ64; 1193 } 1194 1195 unsigned Dest = MI->getOperand(0).getReg(); 1196 unsigned Ptr = MI->getOperand(1).getReg(); 1197 unsigned OldVal = MI->getOperand(2).getReg(); 1198 unsigned NewVal = MI->getOperand(3).getReg(); 1199 1200 unsigned Success = RegInfo.createVirtualRegister(RC); 1201 1202 // insert new blocks after the current block 1203 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1204 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1205 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1206 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1207 MachineFunction::iterator It = BB; 1208 ++It; 1209 MF->insert(It, loop1MBB); 1210 MF->insert(It, loop2MBB); 1211 MF->insert(It, exitMBB); 1212 1213 // Transfer the remainder of BB and its successor edges to exitMBB. 1214 exitMBB->splice(exitMBB->begin(), BB, 1215 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1216 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1217 1218 // thisMBB: 1219 // ... 1220 // fallthrough --> loop1MBB 1221 BB->addSuccessor(loop1MBB); 1222 loop1MBB->addSuccessor(exitMBB); 1223 loop1MBB->addSuccessor(loop2MBB); 1224 loop2MBB->addSuccessor(loop1MBB); 1225 loop2MBB->addSuccessor(exitMBB); 1226 1227 // loop1MBB: 1228 // ll dest, 0(ptr) 1229 // bne dest, oldval, exitMBB 1230 BB = loop1MBB; 1231 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1232 BuildMI(BB, dl, TII->get(BNE)) 1233 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1234 1235 // loop2MBB: 1236 // sc success, newval, 0(ptr) 1237 // beq success, $0, loop1MBB 1238 BB = loop2MBB; 1239 BuildMI(BB, dl, TII->get(SC), Success) 1240 .addReg(NewVal).addReg(Ptr).addImm(0); 1241 BuildMI(BB, dl, TII->get(BEQ)) 1242 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1243 1244 MI->eraseFromParent(); // The instruction is gone now. 1245 1246 return exitMBB; 1247} 1248 1249MachineBasicBlock * 1250MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1251 MachineBasicBlock *BB, 1252 unsigned Size) const { 1253 assert((Size == 1 || Size == 2) && 1254 "Unsupported size for EmitAtomicCmpSwapPartial."); 1255 1256 MachineFunction *MF = BB->getParent(); 1257 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1258 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1259 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1260 DebugLoc dl = MI->getDebugLoc(); 1261 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1262 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1263 1264 unsigned Dest = MI->getOperand(0).getReg(); 1265 unsigned Ptr = MI->getOperand(1).getReg(); 1266 unsigned CmpVal = MI->getOperand(2).getReg(); 1267 unsigned NewVal = MI->getOperand(3).getReg(); 1268 1269 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1270 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1271 unsigned Mask = RegInfo.createVirtualRegister(RC); 1272 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1273 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1274 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1275 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1276 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1277 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1278 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1279 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1280 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1281 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1282 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1283 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1284 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1285 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1286 unsigned Success = RegInfo.createVirtualRegister(RC); 1287 1288 // insert new blocks after the current block 1289 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1290 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1291 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1292 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1293 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1294 MachineFunction::iterator It = BB; 1295 ++It; 1296 MF->insert(It, loop1MBB); 1297 MF->insert(It, loop2MBB); 1298 MF->insert(It, sinkMBB); 1299 MF->insert(It, exitMBB); 1300 1301 // Transfer the remainder of BB and its successor edges to exitMBB. 1302 exitMBB->splice(exitMBB->begin(), BB, 1303 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1304 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1305 1306 BB->addSuccessor(loop1MBB); 1307 loop1MBB->addSuccessor(sinkMBB); 1308 loop1MBB->addSuccessor(loop2MBB); 1309 loop2MBB->addSuccessor(loop1MBB); 1310 loop2MBB->addSuccessor(sinkMBB); 1311 sinkMBB->addSuccessor(exitMBB); 1312 1313 // FIXME: computation of newval2 can be moved to loop2MBB. 1314 // thisMBB: 1315 // addiu masklsb2,$0,-4 # 0xfffffffc 1316 // and alignedaddr,ptr,masklsb2 1317 // andi ptrlsb2,ptr,3 1318 // sll shiftamt,ptrlsb2,3 1319 // ori maskupper,$0,255 # 0xff 1320 // sll mask,maskupper,shiftamt 1321 // nor mask2,$0,mask 1322 // andi maskedcmpval,cmpval,255 1323 // sll shiftedcmpval,maskedcmpval,shiftamt 1324 // andi maskednewval,newval,255 1325 // sll shiftednewval,maskednewval,shiftamt 1326 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1327 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1328 .addReg(Mips::ZERO).addImm(-4); 1329 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1330 .addReg(Ptr).addReg(MaskLSB2); 1331 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1332 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1333 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1334 .addReg(Mips::ZERO).addImm(MaskImm); 1335 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1336 .addReg(ShiftAmt).addReg(MaskUpper); 1337 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1338 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1339 .addReg(CmpVal).addImm(MaskImm); 1340 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1341 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1342 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1343 .addReg(NewVal).addImm(MaskImm); 1344 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1345 .addReg(ShiftAmt).addReg(MaskedNewVal); 1346 1347 // loop1MBB: 1348 // ll oldval,0(alginedaddr) 1349 // and maskedoldval0,oldval,mask 1350 // bne maskedoldval0,shiftedcmpval,sinkMBB 1351 BB = loop1MBB; 1352 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1353 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1354 .addReg(OldVal).addReg(Mask); 1355 BuildMI(BB, dl, TII->get(Mips::BNE)) 1356 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1357 1358 // loop2MBB: 1359 // and maskedoldval1,oldval,mask2 1360 // or storeval,maskedoldval1,shiftednewval 1361 // sc success,storeval,0(alignedaddr) 1362 // beq success,$0,loop1MBB 1363 BB = loop2MBB; 1364 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1365 .addReg(OldVal).addReg(Mask2); 1366 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1367 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1368 BuildMI(BB, dl, TII->get(SC), Success) 1369 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1370 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1371 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1372 1373 // sinkMBB: 1374 // srl srlres,maskedoldval0,shiftamt 1375 // sll sllres,srlres,24 1376 // sra dest,sllres,24 1377 BB = sinkMBB; 1378 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1379 1380 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1381 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1382 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1383 .addReg(SrlRes).addImm(ShiftImm); 1384 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1385 .addReg(SllRes).addImm(ShiftImm); 1386 1387 MI->eraseFromParent(); // The instruction is gone now. 1388 1389 return exitMBB; 1390} 1391 1392//===----------------------------------------------------------------------===// 1393// Misc Lower Operation implementation 1394//===----------------------------------------------------------------------===// 1395SDValue MipsTargetLowering:: 1396LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1397{ 1398 MachineFunction &MF = DAG.getMachineFunction(); 1399 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1400 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP; 1401 1402 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1403 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1404 "Cannot lower if the alignment of the allocated space is larger than \ 1405 that of the stack."); 1406 1407 SDValue Chain = Op.getOperand(0); 1408 SDValue Size = Op.getOperand(1); 1409 DebugLoc dl = Op.getDebugLoc(); 1410 1411 // Get a reference from Mips stack pointer 1412 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy()); 1413 1414 // Subtract the dynamic size from the actual stack size to 1415 // obtain the new stack size. 1416 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size); 1417 1418 // The Sub result contains the new stack start address, so it 1419 // must be placed in the stack pointer register. 1420 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue()); 1421 1422 // This node always has two return values: a new stack pointer 1423 // value and a chain 1424 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other); 1425 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1426 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1427 1428 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1429} 1430 1431SDValue MipsTargetLowering:: 1432LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1433{ 1434 // The first operand is the chain, the second is the condition, the third is 1435 // the block to branch to if the condition is true. 1436 SDValue Chain = Op.getOperand(0); 1437 SDValue Dest = Op.getOperand(2); 1438 DebugLoc dl = Op.getDebugLoc(); 1439 1440 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1441 1442 // Return if flag is not set by a floating point comparison. 1443 if (CondRes.getOpcode() != MipsISD::FPCmp) 1444 return Op; 1445 1446 SDValue CCNode = CondRes.getOperand(2); 1447 Mips::CondCode CC = 1448 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1449 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1450 1451 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1452 Dest, CondRes); 1453} 1454 1455SDValue MipsTargetLowering:: 1456LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1457{ 1458 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1459 1460 // Return if flag is not set by a floating point comparison. 1461 if (Cond.getOpcode() != MipsISD::FPCmp) 1462 return Op; 1463 1464 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1465 Op.getDebugLoc()); 1466} 1467 1468SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1469 SelectionDAG &DAG) const { 1470 // FIXME there isn't actually debug info here 1471 DebugLoc dl = Op.getDebugLoc(); 1472 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1473 1474 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1475 SDVTList VTs = DAG.getVTList(MVT::i32); 1476 1477 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1478 1479 // %gp_rel relocation 1480 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1481 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1482 MipsII::MO_GPREL); 1483 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1484 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1485 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1486 } 1487 // %hi/%lo relocation 1488 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1489 MipsII::MO_ABS_HI); 1490 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1491 MipsII::MO_ABS_LO); 1492 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1493 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1494 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1495 } 1496 1497 EVT ValTy = Op.getValueType(); 1498 bool HasGotOfst = (GV->hasInternalLinkage() || 1499 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1500 unsigned GotFlag = IsN64 ? 1501 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1502 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16); 1503 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1504 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA); 1505 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA, 1506 MachinePointerInfo(), false, false, false, 0); 1507 // On functions and global targets not internal linked only 1508 // a load from got/GP is necessary for PIC to work. 1509 if (!HasGotOfst) 1510 return ResNode; 1511 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1512 IsN64 ? MipsII::MO_GOT_OFST : 1513 MipsII::MO_ABS_LO); 1514 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1515 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1516} 1517 1518SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1519 SelectionDAG &DAG) const { 1520 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1521 // FIXME there isn't actually debug info here 1522 DebugLoc dl = Op.getDebugLoc(); 1523 1524 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1525 // %hi/%lo relocation 1526 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI); 1527 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO); 1528 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1529 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1530 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1531 } 1532 1533 EVT ValTy = Op.getValueType(); 1534 unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1535 unsigned OFSTFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1536 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag); 1537 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy, 1538 GetGlobalReg(DAG, ValTy), BAGOTOffset); 1539 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag); 1540 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset, 1541 MachinePointerInfo(), false, false, false, 0); 1542 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset); 1543 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1544} 1545 1546SDValue MipsTargetLowering:: 1547LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1548{ 1549 // If the relocation model is PIC, use the General Dynamic TLS Model or 1550 // Local Dynamic TLS model, otherwise use the Initial Exec or 1551 // Local Exec TLS Model. 1552 1553 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1554 DebugLoc dl = GA->getDebugLoc(); 1555 const GlobalValue *GV = GA->getGlobal(); 1556 EVT PtrVT = getPointerTy(); 1557 1558 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1559 // General Dynamic TLS Model 1560 bool LocalDynamic = GV->hasInternalLinkage(); 1561 unsigned Flag = LocalDynamic ? MipsII::MO_TLSLDM :MipsII::MO_TLSGD; 1562 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag); 1563 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, 1564 GetGlobalReg(DAG, PtrVT), TGA); 1565 unsigned PtrSize = PtrVT.getSizeInBits(); 1566 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1567 1568 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1569 1570 ArgListTy Args; 1571 ArgListEntry Entry; 1572 Entry.Node = Argument; 1573 Entry.Ty = PtrTy; 1574 Args.push_back(Entry); 1575 1576 std::pair<SDValue, SDValue> CallResult = 1577 LowerCallTo(DAG.getEntryNode(), PtrTy, 1578 false, false, false, false, 0, CallingConv::C, false, true, 1579 TlsGetAddr, Args, DAG, dl); 1580 1581 SDValue Ret = CallResult.first; 1582 1583 if (!LocalDynamic) 1584 return Ret; 1585 1586 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1587 MipsII::MO_DTPREL_HI); 1588 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1589 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1590 MipsII::MO_DTPREL_LO); 1591 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1592 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret); 1593 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo); 1594 } 1595 1596 SDValue Offset; 1597 if (GV->isDeclaration()) { 1598 // Initial Exec TLS Model 1599 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1600 MipsII::MO_GOTTPREL); 1601 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1602 TGA); 1603 Offset = DAG.getLoad(PtrVT, dl, 1604 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1605 false, false, false, 0); 1606 } else { 1607 // Local Exec TLS Model 1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1609 MipsII::MO_TPREL_HI); 1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1611 MipsII::MO_TPREL_LO); 1612 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi); 1613 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo); 1614 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1615 } 1616 1617 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1618 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1619} 1620 1621SDValue MipsTargetLowering:: 1622LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1623{ 1624 SDValue HiPart, JTI, JTILo; 1625 // FIXME there isn't actually debug info here 1626 DebugLoc dl = Op.getDebugLoc(); 1627 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1628 EVT PtrVT = Op.getValueType(); 1629 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1630 1631 if (!IsPIC && !IsN64) { 1632 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI); 1633 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI); 1634 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); 1635 } else {// Emit Load from Global Pointer 1636 unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1637 unsigned OfstFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1638 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag); 1639 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT), 1640 JTI); 1641 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI, 1642 MachinePointerInfo(), false, false, false, 0); 1643 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag); 1644 } 1645 1646 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo); 1647 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo); 1648} 1649 1650SDValue MipsTargetLowering:: 1651LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1652{ 1653 SDValue ResNode; 1654 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1655 const Constant *C = N->getConstVal(); 1656 // FIXME there isn't actually debug info here 1657 DebugLoc dl = Op.getDebugLoc(); 1658 1659 // gp_rel relocation 1660 // FIXME: we should reference the constant pool using small data sections, 1661 // but the asm printer currently doesn't support this feature without 1662 // hacking it. This feature should come soon so we can uncomment the 1663 // stuff below. 1664 //if (IsInSmallSection(C->getType())) { 1665 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1666 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1667 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1668 1669 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1670 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1671 N->getOffset(), MipsII::MO_ABS_HI); 1672 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1673 N->getOffset(), MipsII::MO_ABS_LO); 1674 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1675 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1676 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1677 } else { 1678 EVT ValTy = Op.getValueType(); 1679 unsigned GOTFlag = IsN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 1680 unsigned OFSTFlag = IsN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 1681 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1682 N->getOffset(), GOTFlag); 1683 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP); 1684 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP, 1685 MachinePointerInfo::getConstantPool(), false, 1686 false, false, 0); 1687 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(), 1688 N->getOffset(), OFSTFlag); 1689 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo); 1690 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo); 1691 } 1692 1693 return ResNode; 1694} 1695 1696SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1697 MachineFunction &MF = DAG.getMachineFunction(); 1698 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1699 1700 DebugLoc dl = Op.getDebugLoc(); 1701 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1702 getPointerTy()); 1703 1704 // vastart just stores the address of the VarArgsFrameIndex slot into the 1705 // memory location argument. 1706 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1707 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1708 MachinePointerInfo(SV), false, false, 0); 1709} 1710 1711// Called if the size of integer registers is large enough to hold the whole 1712// floating point number. 1713static SDValue LowerFCOPYSIGNLargeIntReg(SDValue Op, SelectionDAG &DAG) { 1714 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1715 EVT ValTy = Op.getValueType(); 1716 EVT IntValTy = MVT::getIntegerVT(ValTy.getSizeInBits()); 1717 uint64_t Mask = (uint64_t)1 << (ValTy.getSizeInBits() - 1); 1718 DebugLoc dl = Op.getDebugLoc(); 1719 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(0)); 1720 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(1)); 1721 SDValue And0 = DAG.getNode(ISD::AND, dl, IntValTy, Op0, 1722 DAG.getConstant(Mask - 1, IntValTy)); 1723 SDValue And1 = DAG.getNode(ISD::AND, dl, IntValTy, Op1, 1724 DAG.getConstant(Mask, IntValTy)); 1725 SDValue Result = DAG.getNode(ISD::OR, dl, IntValTy, And0, And1); 1726 return DAG.getNode(ISD::BITCAST, dl, ValTy, Result); 1727} 1728 1729// Called if the size of integer registers is not large enough to hold the whole 1730// floating point number (e.g. f64 & 32-bit integer register). 1731static SDValue 1732LowerFCOPYSIGNSmallIntReg(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1733 // FIXME: 1734 // Use ext/ins instructions if target architecture is Mips32r2. 1735 // Eliminate redundant mfc1 and mtc1 instructions. 1736 unsigned LoIdx = 0, HiIdx = 1; 1737 1738 if (!isLittle) 1739 std::swap(LoIdx, HiIdx); 1740 1741 DebugLoc dl = Op.getDebugLoc(); 1742 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1743 Op.getOperand(0), 1744 DAG.getConstant(LoIdx, MVT::i32)); 1745 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1746 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1747 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1748 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1749 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1750 DAG.getConstant(0x7fffffff, MVT::i32)); 1751 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1752 DAG.getConstant(0x80000000, MVT::i32)); 1753 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1754 1755 if (!isLittle) 1756 std::swap(Word0, Word1); 1757 1758 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1759} 1760 1761SDValue 1762MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1763 EVT Ty = Op.getValueType(); 1764 1765 assert(Ty == MVT::f32 || Ty == MVT::f64); 1766 1767 if (Ty == MVT::f32 || HasMips64) 1768 return LowerFCOPYSIGNLargeIntReg(Op, DAG); 1769 1770 return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle()); 1771} 1772 1773SDValue MipsTargetLowering:: 1774LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1775 // check the depth 1776 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1777 "Frame address can only be determined for current frame."); 1778 1779 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1780 MFI->setFrameAddressIsTaken(true); 1781 EVT VT = Op.getValueType(); 1782 DebugLoc dl = Op.getDebugLoc(); 1783 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1784 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1785 return FrameAddr; 1786} 1787 1788// TODO: set SType according to the desired memory barrier behavior. 1789SDValue 1790MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const { 1791 unsigned SType = 0; 1792 DebugLoc dl = Op.getDebugLoc(); 1793 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1794 DAG.getConstant(SType, MVT::i32)); 1795} 1796 1797SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1798 SelectionDAG& DAG) const { 1799 // FIXME: Need pseudo-fence for 'singlethread' fences 1800 // FIXME: Set SType for weaker fences where supported/appropriate. 1801 unsigned SType = 0; 1802 DebugLoc dl = Op.getDebugLoc(); 1803 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1804 DAG.getConstant(SType, MVT::i32)); 1805} 1806 1807//===----------------------------------------------------------------------===// 1808// Calling Convention Implementation 1809//===----------------------------------------------------------------------===// 1810 1811//===----------------------------------------------------------------------===// 1812// TODO: Implement a generic logic using tblgen that can support this. 1813// Mips O32 ABI rules: 1814// --- 1815// i32 - Passed in A0, A1, A2, A3 and stack 1816// f32 - Only passed in f32 registers if no int reg has been used yet to hold 1817// an argument. Otherwise, passed in A1, A2, A3 and stack. 1818// f64 - Only passed in two aliased f32 registers if no int reg has been used 1819// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1820// not used, it must be shadowed. If only A3 is avaiable, shadow it and 1821// go to stack. 1822// 1823// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1824//===----------------------------------------------------------------------===// 1825 1826static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1827 MVT LocVT, CCValAssign::LocInfo LocInfo, 1828 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1829 1830 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1831 1832 static const unsigned IntRegs[] = { 1833 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1834 }; 1835 static const unsigned F32Regs[] = { 1836 Mips::F12, Mips::F14 1837 }; 1838 static const unsigned F64Regs[] = { 1839 Mips::D6, Mips::D7 1840 }; 1841 1842 // ByVal Args 1843 if (ArgFlags.isByVal()) { 1844 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1845 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1846 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1847 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1848 r < std::min(IntRegsSize, NextReg); ++r) 1849 State.AllocateReg(IntRegs[r]); 1850 return false; 1851 } 1852 1853 // Promote i8 and i16 1854 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1855 LocVT = MVT::i32; 1856 if (ArgFlags.isSExt()) 1857 LocInfo = CCValAssign::SExt; 1858 else if (ArgFlags.isZExt()) 1859 LocInfo = CCValAssign::ZExt; 1860 else 1861 LocInfo = CCValAssign::AExt; 1862 } 1863 1864 unsigned Reg; 1865 1866 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1867 // is true: function is vararg, argument is 3rd or higher, there is previous 1868 // argument which is not f32 or f64. 1869 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1870 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1871 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1872 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1873 1874 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1875 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1876 // If this is the first part of an i64 arg, 1877 // the allocated register must be either A0 or A2. 1878 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1879 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1880 LocVT = MVT::i32; 1881 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1882 // Allocate int register and shadow next int register. If first 1883 // available register is Mips::A1 or Mips::A3, shadow it too. 1884 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1885 if (Reg == Mips::A1 || Reg == Mips::A3) 1886 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1887 State.AllocateReg(IntRegs, IntRegsSize); 1888 LocVT = MVT::i32; 1889 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1890 // we are guaranteed to find an available float register 1891 if (ValVT == MVT::f32) { 1892 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1893 // Shadow int register 1894 State.AllocateReg(IntRegs, IntRegsSize); 1895 } else { 1896 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1897 // Shadow int registers 1898 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1899 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1900 State.AllocateReg(IntRegs, IntRegsSize); 1901 State.AllocateReg(IntRegs, IntRegsSize); 1902 } 1903 } else 1904 llvm_unreachable("Cannot handle this ValVT."); 1905 1906 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1907 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1908 1909 if (!Reg) 1910 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1911 else 1912 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1913 1914 return false; // CC must always match 1915} 1916 1917static const unsigned Mips64IntRegs[8] = 1918 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 1919 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; 1920static const unsigned Mips64DPRegs[8] = 1921 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 1922 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64}; 1923 1924static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT, 1925 CCValAssign::LocInfo LocInfo, 1926 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1927 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8); 1928 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8; 1929 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8); 1930 1931 assert(Align <= 16 && "Cannot handle alignments larger than 16."); 1932 1933 // If byval is 16-byte aligned, the first arg register must be even. 1934 if ((Align == 16) && (FirstIdx % 2)) { 1935 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]); 1936 ++FirstIdx; 1937 } 1938 1939 // Mark the registers allocated. 1940 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I) 1941 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]); 1942 1943 // Allocate space on caller's stack. 1944 unsigned Offset = State.AllocateStack(Size, Align); 1945 1946 if (FirstIdx < 8) 1947 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx], 1948 LocVT, LocInfo)); 1949 else 1950 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1951 1952 return true; 1953} 1954 1955#include "MipsGenCallingConv.inc" 1956 1957static void 1958AnalyzeMips64CallOperands(CCState &CCInfo, 1959 const SmallVectorImpl<ISD::OutputArg> &Outs) { 1960 unsigned NumOps = Outs.size(); 1961 for (unsigned i = 0; i != NumOps; ++i) { 1962 MVT ArgVT = Outs[i].VT; 1963 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 1964 bool R; 1965 1966 if (Outs[i].IsFixed) 1967 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 1968 else 1969 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 1970 1971 if (R) { 1972#ifndef NDEBUG 1973 dbgs() << "Call operand #" << i << " has unhandled type " 1974 << EVT(ArgVT).getEVTString(); 1975#endif 1976 llvm_unreachable(0); 1977 } 1978 } 1979} 1980 1981//===----------------------------------------------------------------------===// 1982// Call Calling Convention Implementation 1983//===----------------------------------------------------------------------===// 1984 1985static const unsigned O32IntRegsSize = 4; 1986 1987static const unsigned O32IntRegs[] = { 1988 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1989}; 1990 1991// Return next O32 integer argument register. 1992static unsigned getNextIntArgReg(unsigned Reg) { 1993 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 1994 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 1995} 1996 1997// Write ByVal Arg to arg registers and stack. 1998static void 1999WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 2000 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 2001 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 2002 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2003 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2004 MVT PtrType, bool isLittle) { 2005 unsigned LocMemOffset = VA.getLocMemOffset(); 2006 unsigned Offset = 0; 2007 uint32_t RemainingSize = Flags.getByValSize(); 2008 unsigned ByValAlign = Flags.getByValAlign(); 2009 2010 // Copy the first 4 words of byval arg to registers A0 - A3. 2011 // FIXME: Use a stricter alignment if it enables better optimization in passes 2012 // run later. 2013 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 2014 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 2015 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2016 DAG.getConstant(Offset, MVT::i32)); 2017 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 2018 MachinePointerInfo(), false, false, false, 2019 std::min(ByValAlign, (unsigned )4)); 2020 MemOpChains.push_back(LoadVal.getValue(1)); 2021 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2022 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2023 } 2024 2025 if (RemainingSize == 0) 2026 return; 2027 2028 // If there still is a register available for argument passing, write the 2029 // remaining part of the structure to it using subword loads and shifts. 2030 if (LocMemOffset < 4 * 4) { 2031 assert(RemainingSize <= 3 && RemainingSize >= 1 && 2032 "There must be one to three bytes remaining."); 2033 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 2034 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2035 DAG.getConstant(Offset, MVT::i32)); 2036 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 2037 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2038 LoadPtr, MachinePointerInfo(), 2039 MVT::getIntegerVT(LoadSize * 8), false, 2040 false, Alignment); 2041 MemOpChains.push_back(LoadVal.getValue(1)); 2042 2043 // If target is big endian, shift it to the most significant half-word or 2044 // byte. 2045 if (!isLittle) 2046 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 2047 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 2048 2049 Offset += LoadSize; 2050 RemainingSize -= LoadSize; 2051 2052 // Read second subword if necessary. 2053 if (RemainingSize != 0) { 2054 assert(RemainingSize == 1 && "There must be one byte remaining."); 2055 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2056 DAG.getConstant(Offset, MVT::i32)); 2057 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 2058 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 2059 LoadPtr, MachinePointerInfo(), 2060 MVT::i8, false, false, Alignment); 2061 MemOpChains.push_back(Subword.getValue(1)); 2062 // Insert the loaded byte to LoadVal. 2063 // FIXME: Use INS if supported by target. 2064 unsigned ShiftAmt = isLittle ? 16 : 8; 2065 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 2066 DAG.getConstant(ShiftAmt, MVT::i32)); 2067 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 2068 } 2069 2070 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 2071 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 2072 return; 2073 } 2074 2075 // Create a fixed object on stack at offset LocMemOffset and copy 2076 // remaining part of byval arg to it using memcpy. 2077 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 2078 DAG.getConstant(Offset, MVT::i32)); 2079 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 2080 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 2081 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 2082 DAG.getConstant(RemainingSize, MVT::i32), 2083 std::min(ByValAlign, (unsigned)4), 2084 /*isVolatile=*/false, /*AlwaysInline=*/false, 2085 MachinePointerInfo(0), MachinePointerInfo(0)); 2086} 2087 2088// Copy Mips64 byVal arg to registers and stack. 2089void static 2090PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 2091 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 2092 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 2093 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 2094 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2095 EVT PtrTy, bool isLittle) { 2096 unsigned ByValSize = Flags.getByValSize(); 2097 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8); 2098 bool IsRegLoc = VA.isRegLoc(); 2099 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 2100 unsigned LocMemOffset = 0; 2101 unsigned MemCpySize = ByValSize; 2102 2103 if (!IsRegLoc) 2104 LocMemOffset = VA.getLocMemOffset(); 2105 else { 2106 const unsigned *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, 2107 VA.getLocReg()); 2108 const unsigned *RegEnd = Mips64IntRegs + 8; 2109 2110 // Copy double words to registers. 2111 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) { 2112 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2113 DAG.getConstant(Offset, PtrTy)); 2114 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr, 2115 MachinePointerInfo(), false, false, false, 2116 Alignment); 2117 MemOpChains.push_back(LoadVal.getValue(1)); 2118 RegsToPass.push_back(std::make_pair(*Reg, LoadVal)); 2119 } 2120 2121 // Return if the struct has been fully copied. 2122 if (!(MemCpySize = ByValSize - Offset)) 2123 return; 2124 2125 // If there is an argument register available, copy the remainder of the 2126 // byval argument with sub-doubleword loads and shifts. 2127 if (Reg != RegEnd) { 2128 assert((ByValSize < Offset + 8) && 2129 "Size of the remainder should be smaller than 8-byte."); 2130 SDValue Val; 2131 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) { 2132 unsigned RemSize = ByValSize - Offset; 2133 2134 if (RemSize < LoadSize) 2135 continue; 2136 2137 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2138 DAG.getConstant(Offset, PtrTy)); 2139 SDValue LoadVal = 2140 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr, 2141 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 2142 false, false, Alignment); 2143 MemOpChains.push_back(LoadVal.getValue(1)); 2144 2145 // Offset in number of bits from double word boundary. 2146 unsigned OffsetDW = (Offset % 8) * 8; 2147 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8); 2148 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal, 2149 DAG.getConstant(Shamt, MVT::i32)); 2150 2151 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) : 2152 Shift; 2153 Offset += LoadSize; 2154 Alignment = std::min(Alignment, LoadSize); 2155 } 2156 2157 RegsToPass.push_back(std::make_pair(*Reg, Val)); 2158 return; 2159 } 2160 } 2161 2162 assert(MemCpySize && "MemCpySize must not be zero."); 2163 2164 // Create a fixed object on stack at offset LocMemOffset and copy 2165 // remainder of byval arg to it with memcpy. 2166 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg, 2167 DAG.getConstant(Offset, PtrTy)); 2168 LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true); 2169 SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy); 2170 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 2171 DAG.getConstant(MemCpySize, PtrTy), Alignment, 2172 /*isVolatile=*/false, /*AlwaysInline=*/false, 2173 MachinePointerInfo(0), MachinePointerInfo(0)); 2174} 2175 2176/// LowerCall - functions arguments are copied from virtual regs to 2177/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2178/// TODO: isTailCall. 2179SDValue 2180MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee, 2181 CallingConv::ID CallConv, bool isVarArg, 2182 bool &isTailCall, 2183 const SmallVectorImpl<ISD::OutputArg> &Outs, 2184 const SmallVectorImpl<SDValue> &OutVals, 2185 const SmallVectorImpl<ISD::InputArg> &Ins, 2186 DebugLoc dl, SelectionDAG &DAG, 2187 SmallVectorImpl<SDValue> &InVals) const { 2188 // MIPs target does not yet support tail call optimization. 2189 isTailCall = false; 2190 2191 MachineFunction &MF = DAG.getMachineFunction(); 2192 MachineFrameInfo *MFI = MF.getFrameInfo(); 2193 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2194 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2195 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2196 2197 // Analyze operands of the call, assigning locations to each operand. 2198 SmallVector<CCValAssign, 16> ArgLocs; 2199 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2200 getTargetMachine(), ArgLocs, *DAG.getContext()); 2201 2202 if (IsO32) 2203 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 2204 else if (HasMips64) 2205 AnalyzeMips64CallOperands(CCInfo, Outs); 2206 else 2207 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 2208 2209 // Get a count of how many bytes are to be pushed on the stack. 2210 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2211 2212 // Chain is the output chain of the last Load/Store or CopyToReg node. 2213 // ByValChain is the output chain of the last Memcpy node created for copying 2214 // byval arguments to the stack. 2215 SDValue Chain, CallSeqStart, ByValChain; 2216 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2217 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal); 2218 ByValChain = InChain; 2219 2220 // If this is the first call, create a stack frame object that points to 2221 // a location to which .cprestore saves $gp. 2222 if (IsO32 && IsPIC && MipsFI->globalBaseRegFixed() && !MipsFI->getGPFI()) 2223 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 2224 2225 // Get the frame index of the stack frame object that points to the location 2226 // of dynamically allocated area on the stack. 2227 int DynAllocFI = MipsFI->getDynAllocFI(); 2228 2229 // Update size of the maximum argument space. 2230 // For O32, a minimum of four words (16 bytes) of argument space is 2231 // allocated. 2232 if (IsO32) 2233 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 2234 2235 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 2236 2237 if (MaxCallFrameSize < NextStackOffset) { 2238 MipsFI->setMaxCallFrameSize(NextStackOffset); 2239 2240 // Set the offsets relative to $sp of the $gp restore slot and dynamically 2241 // allocated stack space. These offsets must be aligned to a boundary 2242 // determined by the stack alignment of the ABI. 2243 unsigned StackAlignment = TFL->getStackAlignment(); 2244 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 2245 StackAlignment * StackAlignment; 2246 2247 if (MipsFI->needGPSaveRestore()) 2248 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 2249 2250 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 2251 } 2252 2253 // With EABI is it possible to have 16 args on registers. 2254 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 2255 SmallVector<SDValue, 8> MemOpChains; 2256 2257 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 2258 2259 // Walk the register/memloc assignments, inserting copies/loads. 2260 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2261 SDValue Arg = OutVals[i]; 2262 CCValAssign &VA = ArgLocs[i]; 2263 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2264 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2265 2266 // ByVal Arg. 2267 if (Flags.isByVal()) { 2268 assert(Flags.getByValSize() && 2269 "ByVal args of size 0 should have been ignored by front-end."); 2270 if (IsO32) 2271 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, 2272 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2273 Subtarget->isLittle()); 2274 else 2275 PassByValArg64(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, 2276 MFI, DAG, Arg, VA, Flags, getPointerTy(), 2277 Subtarget->isLittle()); 2278 continue; 2279 } 2280 2281 // Promote the value if needed. 2282 switch (VA.getLocInfo()) { 2283 default: llvm_unreachable("Unknown loc info!"); 2284 case CCValAssign::Full: 2285 if (VA.isRegLoc()) { 2286 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2287 (ValVT == MVT::f64 && LocVT == MVT::i64)) 2288 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg); 2289 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2290 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2291 Arg, DAG.getConstant(0, MVT::i32)); 2292 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2293 Arg, DAG.getConstant(1, MVT::i32)); 2294 if (!Subtarget->isLittle()) 2295 std::swap(Lo, Hi); 2296 unsigned LocRegLo = VA.getLocReg(); 2297 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2298 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2299 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2300 continue; 2301 } 2302 } 2303 break; 2304 case CCValAssign::SExt: 2305 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg); 2306 break; 2307 case CCValAssign::ZExt: 2308 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); 2309 break; 2310 case CCValAssign::AExt: 2311 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg); 2312 break; 2313 } 2314 2315 // Arguments that can be passed on register must be kept at 2316 // RegsToPass vector 2317 if (VA.isRegLoc()) { 2318 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2319 continue; 2320 } 2321 2322 // Register can't get to this point... 2323 assert(VA.isMemLoc()); 2324 2325 // Create the frame index object for this incoming parameter 2326 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2327 VA.getLocMemOffset(), true); 2328 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2329 2330 // emit ISD::STORE whichs stores the 2331 // parameter value to a stack Location 2332 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2333 MachinePointerInfo(), false, false, 0)); 2334 } 2335 2336 // Extend range of indices of frame objects for outgoing arguments that were 2337 // created during this function call. Skip this step if no such objects were 2338 // created. 2339 if (LastFI) 2340 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2341 2342 // If a memcpy has been created to copy a byval arg to a stack, replace the 2343 // chain input of CallSeqStart with ByValChain. 2344 if (InChain != ByValChain) 2345 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain, 2346 NextStackOffsetVal); 2347 2348 // Transform all store nodes into one single node because all store 2349 // nodes are independent of each other. 2350 if (!MemOpChains.empty()) 2351 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2352 &MemOpChains[0], MemOpChains.size()); 2353 2354 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2355 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2356 // node so that legalize doesn't hack it. 2357 unsigned char OpFlag; 2358 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2359 bool GlobalOrExternal = false; 2360 SDValue CalleeLo; 2361 2362 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2363 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) { 2364 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE; 2365 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST; 2366 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0, 2367 OpFlag); 2368 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2369 0, LoFlag); 2370 } else { 2371 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2372 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2373 getPointerTy(), 0, OpFlag); 2374 } 2375 2376 GlobalOrExternal = true; 2377 } 2378 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2379 if (IsN64 || (!IsO32 && IsPIC)) 2380 OpFlag = MipsII::MO_GOT_DISP; 2381 else if (!IsPIC) // !N64 && static 2382 OpFlag = MipsII::MO_NO_FLAG; 2383 else // O32 & PIC 2384 OpFlag = MipsII::MO_GOT_CALL; 2385 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2386 OpFlag); 2387 GlobalOrExternal = true; 2388 } 2389 2390 SDValue InFlag; 2391 2392 // Create nodes that load address of callee and copy it to T9 2393 if (IsPICCall) { 2394 if (GlobalOrExternal) { 2395 // Load callee address 2396 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(), 2397 GetGlobalReg(DAG, getPointerTy()), Callee); 2398 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 2399 Callee, MachinePointerInfo::getGOT(), 2400 false, false, false, 0); 2401 2402 // Use GOT+LO if callee has internal linkage. 2403 if (CalleeLo.getNode()) { 2404 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo); 2405 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo); 2406 } else 2407 Callee = LoadValue; 2408 } 2409 } 2410 2411 // T9 should contain the address of the callee function if 2412 // -reloction-model=pic or it is an indirect call. 2413 if (IsPICCall || !GlobalOrExternal) { 2414 // copy to T9 2415 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 2416 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0)); 2417 InFlag = Chain.getValue(1); 2418 Callee = DAG.getRegister(T9Reg, getPointerTy()); 2419 } 2420 2421 // Build a sequence of copy-to-reg nodes chained together with token 2422 // chain and flag operands which copy the outgoing args into registers. 2423 // The InFlag in necessary since all emitted instructions must be 2424 // stuck together. 2425 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2426 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2427 RegsToPass[i].second, InFlag); 2428 InFlag = Chain.getValue(1); 2429 } 2430 2431 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2432 // = Chain, Callee, Reg#1, Reg#2, ... 2433 // 2434 // Returns a chain & a flag for retval copy to use. 2435 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2436 SmallVector<SDValue, 8> Ops; 2437 Ops.push_back(Chain); 2438 Ops.push_back(Callee); 2439 2440 // Add argument registers to the end of the list so that they are 2441 // known live into the call. 2442 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2443 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2444 RegsToPass[i].second.getValueType())); 2445 2446 if (InFlag.getNode()) 2447 Ops.push_back(InFlag); 2448 2449 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2450 InFlag = Chain.getValue(1); 2451 2452 // Create the CALLSEQ_END node. 2453 Chain = DAG.getCALLSEQ_END(Chain, 2454 DAG.getIntPtrConstant(NextStackOffset, true), 2455 DAG.getIntPtrConstant(0, true), InFlag); 2456 InFlag = Chain.getValue(1); 2457 2458 // Handle result values, copying them out of physregs into vregs that we 2459 // return. 2460 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2461 Ins, dl, DAG, InVals); 2462} 2463 2464/// LowerCallResult - Lower the result values of a call into the 2465/// appropriate copies out of appropriate physical registers. 2466SDValue 2467MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2468 CallingConv::ID CallConv, bool isVarArg, 2469 const SmallVectorImpl<ISD::InputArg> &Ins, 2470 DebugLoc dl, SelectionDAG &DAG, 2471 SmallVectorImpl<SDValue> &InVals) const { 2472 // Assign locations to each value returned by this call. 2473 SmallVector<CCValAssign, 16> RVLocs; 2474 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2475 getTargetMachine(), RVLocs, *DAG.getContext()); 2476 2477 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2478 2479 // Copy all of the result registers out of their specified physreg. 2480 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2481 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2482 RVLocs[i].getValVT(), InFlag).getValue(1); 2483 InFlag = Chain.getValue(2); 2484 InVals.push_back(Chain.getValue(0)); 2485 } 2486 2487 return Chain; 2488} 2489 2490//===----------------------------------------------------------------------===// 2491// Formal Arguments Calling Convention Implementation 2492//===----------------------------------------------------------------------===// 2493static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2494 std::vector<SDValue>& OutChains, 2495 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2496 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 2497 unsigned LocMem = VA.getLocMemOffset(); 2498 unsigned FirstWord = LocMem / 4; 2499 2500 // copy register A0 - A3 to frame object 2501 for (unsigned i = 0; i < NumWords; ++i) { 2502 unsigned CurWord = FirstWord + i; 2503 if (CurWord >= O32IntRegsSize) 2504 break; 2505 2506 unsigned SrcReg = O32IntRegs[CurWord]; 2507 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2508 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2509 DAG.getConstant(i * 4, MVT::i32)); 2510 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2511 StorePtr, MachinePointerInfo(), false, 2512 false, 0); 2513 OutChains.push_back(Store); 2514 } 2515} 2516 2517// Create frame object on stack and copy registers used for byval passing to it. 2518static unsigned 2519CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2520 std::vector<SDValue>& OutChains, SelectionDAG &DAG, 2521 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 2522 MachineFrameInfo *MFI, bool IsRegLoc, 2523 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, 2524 EVT PtrTy) { 2525 const unsigned *Reg = Mips64IntRegs + 8; 2526 int FOOffset; // Frame object offset from virtual frame pointer. 2527 2528 if (IsRegLoc) { 2529 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg()); 2530 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8; 2531 } 2532 else 2533 FOOffset = VA.getLocMemOffset(); 2534 2535 // Create frame object. 2536 unsigned NumRegs = (Flags.getByValSize() + 7) / 8; 2537 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true); 2538 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy); 2539 InVals.push_back(FIN); 2540 2541 // Copy arg registers. 2542 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs); 2543 ++Reg, ++I) { 2544 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass); 2545 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN, 2546 DAG.getConstant(I * 8, PtrTy)); 2547 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64), 2548 StorePtr, MachinePointerInfo(), false, 2549 false, 0); 2550 OutChains.push_back(Store); 2551 } 2552 2553 return LastFI; 2554} 2555 2556/// LowerFormalArguments - transform physical registers into virtual registers 2557/// and generate load operations for arguments places on the stack. 2558SDValue 2559MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2560 CallingConv::ID CallConv, 2561 bool isVarArg, 2562 const SmallVectorImpl<ISD::InputArg> &Ins, 2563 DebugLoc dl, SelectionDAG &DAG, 2564 SmallVectorImpl<SDValue> &InVals) 2565 const { 2566 MachineFunction &MF = DAG.getMachineFunction(); 2567 MachineFrameInfo *MFI = MF.getFrameInfo(); 2568 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2569 2570 MipsFI->setVarArgsFrameIndex(0); 2571 2572 // Used with vargs to acumulate store chains. 2573 std::vector<SDValue> OutChains; 2574 2575 // Assign locations to all of the incoming arguments. 2576 SmallVector<CCValAssign, 16> ArgLocs; 2577 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2578 getTargetMachine(), ArgLocs, *DAG.getContext()); 2579 2580 if (IsO32) 2581 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2582 else 2583 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2584 2585 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2586 2587 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2588 CCValAssign &VA = ArgLocs[i]; 2589 EVT ValVT = VA.getValVT(); 2590 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2591 bool IsRegLoc = VA.isRegLoc(); 2592 2593 if (Flags.isByVal()) { 2594 assert(Flags.getByValSize() && 2595 "ByVal args of size 0 should have been ignored by front-end."); 2596 if (IsO32) { 2597 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2598 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2599 true); 2600 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2601 InVals.push_back(FIN); 2602 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2603 } else // N32/64 2604 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags, 2605 MFI, IsRegLoc, InVals, MipsFI, 2606 getPointerTy()); 2607 continue; 2608 } 2609 2610 // Arguments stored on registers 2611 if (IsRegLoc) { 2612 EVT RegVT = VA.getLocVT(); 2613 unsigned ArgReg = VA.getLocReg(); 2614 const TargetRegisterClass *RC; 2615 2616 if (RegVT == MVT::i32) 2617 RC = Mips::CPURegsRegisterClass; 2618 else if (RegVT == MVT::i64) 2619 RC = Mips::CPU64RegsRegisterClass; 2620 else if (RegVT == MVT::f32) 2621 RC = Mips::FGR32RegisterClass; 2622 else if (RegVT == MVT::f64) 2623 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; 2624 else 2625 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2626 2627 // Transform the arguments stored on 2628 // physical registers into virtual ones 2629 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2630 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2631 2632 // If this is an 8 or 16-bit value, it has been passed promoted 2633 // to 32 bits. Insert an assert[sz]ext to capture this, then 2634 // truncate to the right size. 2635 if (VA.getLocInfo() != CCValAssign::Full) { 2636 unsigned Opcode = 0; 2637 if (VA.getLocInfo() == CCValAssign::SExt) 2638 Opcode = ISD::AssertSext; 2639 else if (VA.getLocInfo() == CCValAssign::ZExt) 2640 Opcode = ISD::AssertZext; 2641 if (Opcode) 2642 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2643 DAG.getValueType(ValVT)); 2644 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue); 2645 } 2646 2647 // Handle floating point arguments passed in integer registers. 2648 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2649 (RegVT == MVT::i64 && ValVT == MVT::f64)) 2650 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue); 2651 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2652 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2653 getNextIntArgReg(ArgReg), RC); 2654 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2655 if (!Subtarget->isLittle()) 2656 std::swap(ArgValue, ArgValue2); 2657 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2658 ArgValue, ArgValue2); 2659 } 2660 2661 InVals.push_back(ArgValue); 2662 } else { // VA.isRegLoc() 2663 2664 // sanity check 2665 assert(VA.isMemLoc()); 2666 2667 // The stack pointer offset is relative to the caller stack frame. 2668 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2669 VA.getLocMemOffset(), true); 2670 2671 // Create load nodes to retrieve arguments from the stack 2672 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2673 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN, 2674 MachinePointerInfo::getFixedStack(LastFI), 2675 false, false, false, 0)); 2676 } 2677 } 2678 2679 // The mips ABIs for returning structs by value requires that we copy 2680 // the sret argument into $v0 for the return. Save the argument into 2681 // a virtual register so that we can access it from the return points. 2682 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2683 unsigned Reg = MipsFI->getSRetReturnReg(); 2684 if (!Reg) { 2685 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2686 MipsFI->setSRetReturnReg(Reg); 2687 } 2688 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2689 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2690 } 2691 2692 if (isVarArg) { 2693 unsigned NumOfRegs = IsO32 ? 4 : 8; 2694 const unsigned *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs; 2695 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs); 2696 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot. 2697 const TargetRegisterClass *RC 2698 = IsO32 ? Mips::CPURegsRegisterClass : Mips::CPU64RegsRegisterClass; 2699 unsigned RegSize = RC->getSize(); 2700 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize; 2701 2702 // Offset of the first variable argument from stack pointer. 2703 int FirstVaArgOffset; 2704 2705 if (IsO32 || (Idx == NumOfRegs)) { 2706 FirstVaArgOffset = 2707 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize; 2708 } else 2709 FirstVaArgOffset = RegSlotOffset; 2710 2711 // Record the frame index of the first variable argument 2712 // which is a value necessary to VASTART. 2713 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true); 2714 MipsFI->setVarArgsFrameIndex(LastFI); 2715 2716 // Copy the integer registers that have not been used for argument passing 2717 // to the argument register save area. For O32, the save area is allocated 2718 // in the caller's stack frame, while for N32/64, it is allocated in the 2719 // callee's stack frame. 2720 for (int StackOffset = RegSlotOffset; 2721 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) { 2722 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC); 2723 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, 2724 MVT::getIntegerVT(RegSize * 8)); 2725 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true); 2726 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2727 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2728 MachinePointerInfo(), false, false, 0)); 2729 } 2730 } 2731 2732 MipsFI->setLastInArgFI(LastFI); 2733 2734 // All stores are grouped in one node to allow the matching between 2735 // the size of Ins and InVals. This only happens when on varg functions 2736 if (!OutChains.empty()) { 2737 OutChains.push_back(Chain); 2738 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2739 &OutChains[0], OutChains.size()); 2740 } 2741 2742 return Chain; 2743} 2744 2745//===----------------------------------------------------------------------===// 2746// Return Value Calling Convention Implementation 2747//===----------------------------------------------------------------------===// 2748 2749SDValue 2750MipsTargetLowering::LowerReturn(SDValue Chain, 2751 CallingConv::ID CallConv, bool isVarArg, 2752 const SmallVectorImpl<ISD::OutputArg> &Outs, 2753 const SmallVectorImpl<SDValue> &OutVals, 2754 DebugLoc dl, SelectionDAG &DAG) const { 2755 2756 // CCValAssign - represent the assignment of 2757 // the return value to a location 2758 SmallVector<CCValAssign, 16> RVLocs; 2759 2760 // CCState - Info about the registers and stack slot. 2761 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2762 getTargetMachine(), RVLocs, *DAG.getContext()); 2763 2764 // Analize return values. 2765 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2766 2767 // If this is the first return lowered for this function, add 2768 // the regs to the liveout set for the function. 2769 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2770 for (unsigned i = 0; i != RVLocs.size(); ++i) 2771 if (RVLocs[i].isRegLoc()) 2772 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2773 } 2774 2775 SDValue Flag; 2776 2777 // Copy the result values into the output registers. 2778 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2779 CCValAssign &VA = RVLocs[i]; 2780 assert(VA.isRegLoc() && "Can only return in registers!"); 2781 2782 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 2783 2784 // guarantee that all emitted copies are 2785 // stuck together, avoiding something bad 2786 Flag = Chain.getValue(1); 2787 } 2788 2789 // The mips ABIs for returning structs by value requires that we copy 2790 // the sret argument into $v0 for the return. We saved the argument into 2791 // a virtual register in the entry block, so now we copy the value out 2792 // and into $v0. 2793 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2794 MachineFunction &MF = DAG.getMachineFunction(); 2795 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2796 unsigned Reg = MipsFI->getSRetReturnReg(); 2797 2798 if (!Reg) 2799 llvm_unreachable("sret virtual register not created in the entry block"); 2800 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2801 2802 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2803 Flag = Chain.getValue(1); 2804 } 2805 2806 // Return on Mips is always a "jr $ra" 2807 if (Flag.getNode()) 2808 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2809 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2810 else // Return Void 2811 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2812 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2813} 2814 2815//===----------------------------------------------------------------------===// 2816// Mips Inline Assembly Support 2817//===----------------------------------------------------------------------===// 2818 2819/// getConstraintType - Given a constraint letter, return the type of 2820/// constraint it is for this target. 2821MipsTargetLowering::ConstraintType MipsTargetLowering:: 2822getConstraintType(const std::string &Constraint) const 2823{ 2824 // Mips specific constrainy 2825 // GCC config/mips/constraints.md 2826 // 2827 // 'd' : An address register. Equivalent to r 2828 // unless generating MIPS16 code. 2829 // 'y' : Equivalent to r; retained for 2830 // backwards compatibility. 2831 // 'f' : Floating Point registers. 2832 if (Constraint.size() == 1) { 2833 switch (Constraint[0]) { 2834 default : break; 2835 case 'd': 2836 case 'y': 2837 case 'f': 2838 return C_RegisterClass; 2839 } 2840 } 2841 return TargetLowering::getConstraintType(Constraint); 2842} 2843 2844/// Examine constraint type and operand type and determine a weight value. 2845/// This object must already have been set up with the operand type 2846/// and the current alternative constraint selected. 2847TargetLowering::ConstraintWeight 2848MipsTargetLowering::getSingleConstraintMatchWeight( 2849 AsmOperandInfo &info, const char *constraint) const { 2850 ConstraintWeight weight = CW_Invalid; 2851 Value *CallOperandVal = info.CallOperandVal; 2852 // If we don't have a value, we can't do a match, 2853 // but allow it at the lowest weight. 2854 if (CallOperandVal == NULL) 2855 return CW_Default; 2856 Type *type = CallOperandVal->getType(); 2857 // Look at the constraint type. 2858 switch (*constraint) { 2859 default: 2860 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2861 break; 2862 case 'd': 2863 case 'y': 2864 if (type->isIntegerTy()) 2865 weight = CW_Register; 2866 break; 2867 case 'f': 2868 if (type->isFloatTy()) 2869 weight = CW_Register; 2870 break; 2871 } 2872 return weight; 2873} 2874 2875/// Given a register class constraint, like 'r', if this corresponds directly 2876/// to an LLVM register class, return a register of 0 and the register class 2877/// pointer. 2878std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2879getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2880{ 2881 if (Constraint.size() == 1) { 2882 switch (Constraint[0]) { 2883 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2884 case 'y': // Same as 'r'. Exists for compatibility. 2885 case 'r': 2886 if (VT == MVT::i32) 2887 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2888 assert(VT == MVT::i64 && "Unexpected type."); 2889 return std::make_pair(0U, Mips::CPU64RegsRegisterClass); 2890 case 'f': 2891 if (VT == MVT::f32) 2892 return std::make_pair(0U, Mips::FGR32RegisterClass); 2893 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2894 if (Subtarget->isFP64bit()) 2895 return std::make_pair(0U, Mips::FGR64RegisterClass); 2896 else 2897 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2898 } 2899 } 2900 } 2901 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2902} 2903 2904bool 2905MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2906 // The Mips target isn't yet aware of offsets. 2907 return false; 2908} 2909 2910bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2911 if (VT != MVT::f32 && VT != MVT::f64) 2912 return false; 2913 if (Imm.isNegZero()) 2914 return false; 2915 return Imm.isZero(); 2916} 2917 2918unsigned MipsTargetLowering::getJumpTableEncoding() const { 2919 if (IsN64) 2920 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 2921 2922 return TargetLowering::getJumpTableEncoding(); 2923} 2924