MipsISelLowering.cpp revision a2b1bb5296624d32a200f9c53d6f26c0c9c3bddc
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Bruno Cardoso Lopes and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16 17#include "MipsISelLowering.h" 18#include "MipsMachineFunction.h" 19#include "MipsTargetMachine.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/Intrinsics.h" 23#include "llvm/CallingConv.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/CodeGen/SSARegMap.h" 30#include "llvm/CodeGen/ValueTypes.h" 31#include "llvm/Support/Debug.h" 32#include <queue> 33#include <set> 34 35using namespace llvm; 36 37const char *MipsTargetLowering:: 38getTargetNodeName(unsigned Opcode) const 39{ 40 switch (Opcode) 41 { 42 case MipsISD::JmpLink : return "MipsISD::JmpLink"; 43 case MipsISD::Hi : return "MipsISD::Hi"; 44 case MipsISD::Lo : return "MipsISD::Lo"; 45 case MipsISD::Ret : return "MipsISD::Ret"; 46 case MipsISD::Add : return "MipsISD::Add"; 47 default : return NULL; 48 } 49} 50 51MipsTargetLowering:: 52MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) 53{ 54 // Mips does not have i1 type, so use i32 for 55 // setcc operations results (slt, sgt, ...). 56 setSetCCResultType(MVT::i32); 57 setSetCCResultContents(ZeroOrOneSetCCResult); 58 59 // Set up the register classes 60 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 61 62 // Custom 63 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 64 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 65 setOperationAction(ISD::RET, MVT::Other, Custom); 66 67 // Load extented operations for i1 types must be promoted 68 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); 69 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); 70 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 71 72 // Store operations for i1 types must be promoted 73 setStoreXAction(MVT::i1, Promote); 74 75 // Mips does not have these NodeTypes below. 76 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 77 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 78 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 79 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 80 setOperationAction(ISD::SELECT, MVT::i32, Expand); 81 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 82 83 // Mips not supported intrinsics. 84 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 85 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 86 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 87 88 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 89 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 90 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 91 setOperationAction(ISD::ROTL , MVT::i32, Expand); 92 setOperationAction(ISD::ROTR , MVT::i32, Expand); 93 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 94 95 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 96 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 97 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 98 99 // We don't have line number support yet. 100 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 101 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 102 setOperationAction(ISD::LABEL, MVT::Other, Expand); 103 104 // Use the default for now 105 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 106 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 107 108 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand); 109 110 setStackPointerRegisterToSaveRestore(Mips::SP); 111 computeRegisterProperties(); 112} 113 114 115SDOperand MipsTargetLowering:: 116LowerOperation(SDOperand Op, SelectionDAG &DAG) 117{ 118 switch (Op.getOpcode()) 119 { 120 case ISD::CALL: return LowerCALL(Op, DAG); 121 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 122 case ISD::RET: return LowerRET(Op, DAG); 123 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 124 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 125 } 126 return SDOperand(); 127} 128 129//===----------------------------------------------------------------------===// 130// Lower helper functions 131//===----------------------------------------------------------------------===// 132 133// AddLiveIn - This helper function adds the specified physical register to the 134// MachineFunction as a live in value. It also creates a corresponding 135// virtual register for it. 136static unsigned 137AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 138{ 139 assert(RC->contains(PReg) && "Not the correct regclass!"); 140 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 141 MF.addLiveIn(PReg, VReg); 142 return VReg; 143} 144 145//===----------------------------------------------------------------------===// 146// Misc Lower Operation implementation 147//===----------------------------------------------------------------------===// 148SDOperand MipsTargetLowering:: 149LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) 150{ 151 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 152 153 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 154 155 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag); 156 SDOperand Ops[] = { GA }; 157 158 SDOperand Hi = DAG.getNode(MipsISD::Hi, VTs, 2, Ops, 1); 159 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); 160 161 SDOperand InFlag = Hi.getValue(1); 162 return DAG.getNode(MipsISD::Add, MVT::i32, Lo, Hi, InFlag); 163} 164 165SDOperand MipsTargetLowering:: 166LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) 167{ 168 assert(0 && "TLS not implemented for MIPS."); 169} 170 171//===----------------------------------------------------------------------===// 172// Calling Convention Implementation 173// 174// The lower operations present on calling convention works on this order: 175// LowerCALL (virt regs --> phys regs, virt regs --> stack) 176// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs) 177// LowerRET (virt regs --> phys regs) 178// LowerCALL (phys regs --> virt regs) 179// 180//===----------------------------------------------------------------------===// 181 182#include "MipsGenCallingConv.inc" 183 184//===----------------------------------------------------------------------===// 185// CALL Calling Convention Implementation 186//===----------------------------------------------------------------------===// 187 188/// Mips custom CALL implementation 189SDOperand MipsTargetLowering:: 190LowerCALL(SDOperand Op, SelectionDAG &DAG) 191{ 192 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 193 194 // By now, only CallingConv::C implemented 195 switch (CallingConv) 196 { 197 default: 198 assert(0 && "Unsupported calling convention"); 199 case CallingConv::Fast: 200 case CallingConv::C: 201 return LowerCCCCallTo(Op, DAG, CallingConv); 202 } 203} 204 205/// LowerCCCCallTo - functions arguments are copied from virtual 206/// regs to (physical regs)/(stack frame), CALLSEQ_START and 207/// CALLSEQ_END are emitted. 208/// TODO: isVarArg, isTailCall, sret, GOT, linkage types. 209SDOperand MipsTargetLowering:: 210LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) 211{ 212 MachineFunction &MF = DAG.getMachineFunction(); 213 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 214 215 SDOperand Chain = Op.getOperand(0); 216 SDOperand Callee = Op.getOperand(4); 217 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 218 219 MachineFrameInfo *MFI = MF.getFrameInfo(); 220 221 // Analyze operands of the call, assigning locations to each operand. 222 SmallVector<CCValAssign, 16> ArgLocs; 223 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 224 225 // To meet ABI, Mips must always allocate 16 bytes on 226 // the stack (even if less than 4 are used as arguments) 227 int VTsize = MVT::getSizeInBits(MVT::i32)/8; 228 MFI->CreateFixedObject(VTsize, (VTsize*3)); 229 230 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips); 231 232 // Get a count of how many bytes are to be pushed on the stack. 233 unsigned NumBytes = CCInfo.getNextStackOffset(); 234 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 235 getPointerTy())); 236 237 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; 238 SmallVector<SDOperand, 8> MemOpChains; 239 240 SDOperand StackPtr; 241 242 // Walk the register/memloc assignments, inserting copies/loads. 243 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 244 CCValAssign &VA = ArgLocs[i]; 245 246 // Arguments start after the 5 first operands of ISD::CALL 247 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 248 249 // Promote the value if needed. 250 switch (VA.getLocInfo()) { 251 default: assert(0 && "Unknown loc info!"); 252 case CCValAssign::Full: break; 253 case CCValAssign::SExt: 254 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 255 break; 256 case CCValAssign::ZExt: 257 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 258 break; 259 case CCValAssign::AExt: 260 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 261 break; 262 } 263 264 // Arguments that can be passed on register, 265 // must be kept at RegsToPass vector 266 if (VA.isRegLoc()) { 267 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 268 } else { 269 270 assert(VA.isMemLoc()); 271 272 if (StackPtr.Val == 0) 273 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 274 275 // Create the frame index object for this incoming parameter 276 // This guarantees that when allocating Local Area the firsts 277 // 16 bytes which are alwayes reserved won't be overwritten. 278 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, 279 (16 + VA.getLocMemOffset())); 280 281 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy()); 282 283 // emit ISD::STORE whichs stores the 284 // parameter value to a stack Location 285 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 286 } 287 } 288 289 // Transform all store nodes into one single node because 290 // all store nodes are independent of each other. 291 if (!MemOpChains.empty()) 292 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 293 &MemOpChains[0], MemOpChains.size()); 294 295 // Build a sequence of copy-to-reg nodes chained together with token 296 // chain and flag operands which copy the outgoing args into registers. 297 // The InFlag in necessary since all emited instructions must be 298 // stuck together. 299 SDOperand InFlag; 300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 301 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, 302 RegsToPass[i].second, InFlag); 303 InFlag = Chain.getValue(1); 304 } 305 306 // If the callee is a GlobalAddress node (quite common, every direct 307 // call is) turn it into a TargetGlobalAddress node so that legalize 308 // doesn't hack it. 309 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 310 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 311 } else 312 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 313 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 314 315 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 316 // = Chain, Callee, Reg#1, Reg#2, ... 317 // 318 // Returns a chain & a flag for retval copy to use. 319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 320 SmallVector<SDOperand, 8> Ops; 321 Ops.push_back(Chain); 322 Ops.push_back(Callee); 323 324 // Add argument registers to the end of the list so that they are 325 // known live into the call. 326 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 327 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 328 RegsToPass[i].second.getValueType())); 329 330 if (InFlag.Val) 331 Ops.push_back(InFlag); 332 333 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); 334 InFlag = Chain.getValue(1); 335 336 // Create the CALLSEQ_END node. 337 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 338 Ops.clear(); 339 Ops.push_back(Chain); 340 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 341 Ops.push_back(InFlag); 342 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 343 InFlag = Chain.getValue(1); 344 345 // Handle result values, copying them out of physregs into vregs that we 346 // return. 347 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 348} 349 350/// LowerCallResult - Lower the result values of an ISD::CALL into the 351/// appropriate copies out of appropriate physical registers. This assumes that 352/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 353/// being lowered. Returns a SDNode with the same number of values as the 354/// ISD::CALL. 355SDNode *MipsTargetLowering:: 356LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, 357 unsigned CallingConv, SelectionDAG &DAG) { 358 359 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; 360 361 // Assign locations to each value returned by this call. 362 SmallVector<CCValAssign, 16> RVLocs; 363 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 364 365 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips); 366 SmallVector<SDOperand, 8> ResultVals; 367 368 // Copy all of the result registers out of their specified physreg. 369 for (unsigned i = 0; i != RVLocs.size(); ++i) { 370 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 371 RVLocs[i].getValVT(), InFlag).getValue(1); 372 InFlag = Chain.getValue(2); 373 ResultVals.push_back(Chain.getValue(0)); 374 } 375 376 // Merge everything together with a MERGE_VALUES node. 377 ResultVals.push_back(Chain); 378 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), 379 &ResultVals[0], ResultVals.size()).Val; 380} 381 382//===----------------------------------------------------------------------===// 383// FORMAL_ARGUMENTS Calling Convention Implementation 384//===----------------------------------------------------------------------===// 385 386/// Mips custom FORMAL_ARGUMENTS implementation 387SDOperand MipsTargetLowering:: 388LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) 389{ 390 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 391 switch(CC) 392 { 393 default: 394 assert(0 && "Unsupported calling convention"); 395 case CallingConv::C: 396 return LowerCCCArguments(Op, DAG); 397 } 398} 399 400/// LowerCCCArguments - transform physical registers into 401/// virtual registers and generate load operations for 402/// arguments places on the stack. 403/// TODO: isVarArg, sret 404SDOperand MipsTargetLowering:: 405LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) 406{ 407 SDOperand Root = Op.getOperand(0); 408 MachineFunction &MF = DAG.getMachineFunction(); 409 MachineFrameInfo *MFI = MF.getFrameInfo(); 410 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 411 412 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 413 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 414 415 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 416 417 // Assign locations to all of the incoming arguments. 418 SmallVector<CCValAssign, 16> ArgLocs; 419 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 420 421 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips); 422 SmallVector<SDOperand, 8> ArgValues; 423 SDOperand StackPtr; 424 425 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 426 427 CCValAssign &VA = ArgLocs[i]; 428 429 // Arguments stored on registers 430 if (VA.isRegLoc()) { 431 MVT::ValueType RegVT = VA.getLocVT(); 432 TargetRegisterClass *RC; 433 434 if (RegVT == MVT::i32) 435 RC = Mips::CPURegsRegisterClass; 436 else 437 assert(0 && "support only Mips::CPURegsRegisterClass"); 438 439 // Transform the arguments stored on 440 // physical registers into virtual ones 441 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 442 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 443 444 // If this is an 8 or 16-bit value, it is really passed promoted 445 // to 32 bits. Insert an assert[sz]ext to capture this, then 446 // truncate to the right size. 447 if (VA.getLocInfo() == CCValAssign::SExt) 448 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 449 DAG.getValueType(VA.getValVT())); 450 else if (VA.getLocInfo() == CCValAssign::ZExt) 451 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 452 DAG.getValueType(VA.getValVT())); 453 454 if (VA.getLocInfo() != CCValAssign::Full) 455 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 456 457 ArgValues.push_back(ArgValue); 458 459 // To meet ABI, when VARARGS are passed on registers, the registers 460 // must have their values written to the caller stack frame. 461 if (isVarArg) { 462 463 if (StackPtr.Val == 0) 464 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 465 466 // The stack pointer offset is relative to the caller stack frame. 467 // Since the real stack size is unknown here, a negative SPOffset 468 // is used so there's a way to adjust these offsets when the stack 469 // size get known (on EliminateFrameIndex). A dummy SPOffset is 470 // used instead of a direct negative address (which is recorded to 471 // be used on emitPrologue) to avoid mis-calc of the first stack 472 // offset on PEI::calculateFrameObjectOffsets. 473 // Arguments are always 32-bit. 474 int FI = MFI->CreateFixedObject(4, 0); 475 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4))); 476 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 477 478 // emit ISD::STORE whichs stores the 479 // parameter value to a stack Location 480 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0)); 481 } 482 483 } else { 484 // sanity check 485 assert(VA.isMemLoc()); 486 487 // The stack pointer offset is relative to the caller stack frame. 488 // Since the real stack size is unknown here, a negative SPOffset 489 // is used so there's a way to adjust these offsets when the stack 490 // size get known (on EliminateFrameIndex). A dummy SPOffset is 491 // used instead of a direct negative address (which is recorded to 492 // be used on emitPrologue) to avoid mis-calc of the first stack 493 // offset on PEI::calculateFrameObjectOffsets. 494 // Arguments are always 32-bit. 495 int FI = MFI->CreateFixedObject(4, 0); 496 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset()))); 497 498 // Create load nodes to retrieve arguments from the stack 499 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 500 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); 501 } 502 } 503 ArgValues.push_back(Root); 504 505 // Return the new list of results. 506 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 507 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); 508} 509 510//===----------------------------------------------------------------------===// 511// Return Value Calling Convention Implementation 512//===----------------------------------------------------------------------===// 513 514SDOperand MipsTargetLowering:: 515LowerRET(SDOperand Op, SelectionDAG &DAG) 516{ 517 // CCValAssign - represent the assignment of 518 // the return value to a location 519 SmallVector<CCValAssign, 16> RVLocs; 520 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 521 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 522 523 // CCState - Info about the registers and stack slot. 524 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 525 526 // Analize return values of ISD::RET 527 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips); 528 529 // If this is the first return lowered for this function, add 530 // the regs to the liveout set for the function. 531 if (DAG.getMachineFunction().liveout_empty()) { 532 for (unsigned i = 0; i != RVLocs.size(); ++i) 533 if (RVLocs[i].isRegLoc()) 534 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 535 } 536 537 // The chain is always operand #0 538 SDOperand Chain = Op.getOperand(0); 539 SDOperand Flag; 540 541 // Copy the result values into the output registers. 542 for (unsigned i = 0; i != RVLocs.size(); ++i) { 543 CCValAssign &VA = RVLocs[i]; 544 assert(VA.isRegLoc() && "Can only return in registers!"); 545 546 // ISD::RET => ret chain, (regnum1,val1), ... 547 // So i*2+1 index only the regnums 548 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), 549 Op.getOperand(i*2+1), Flag); 550 551 // guarantee that all emitted copies are 552 // stuck together, avoiding something bad 553 Flag = Chain.getValue(1); 554 } 555 556 // Return on Mips is always a "jr $ra" 557 if (Flag.Val) 558 return DAG.getNode(MipsISD::Ret, MVT::Other, 559 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 560 else // Return Void 561 return DAG.getNode(MipsISD::Ret, MVT::Other, 562 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 563} 564 565//===----------------------------------------------------------------------===// 566// Mips Inline Assembly Support 567//===----------------------------------------------------------------------===// 568 569/// getConstraintType - Given a constraint letter, return the type of 570/// constraint it is for this target. 571MipsTargetLowering::ConstraintType MipsTargetLowering:: 572getConstraintType(const std::string &Constraint) const 573{ 574 if (Constraint.size() == 1) { 575 // Mips specific constrainy 576 // GCC config/mips/constraints.md 577 // 578 // 'd' : An address register. Equivalent to r 579 // unless generating MIPS16 code. 580 // 'y' : Equivalent to r; retained for 581 // backwards compatibility. 582 // 583 switch (Constraint[0]) { 584 default : break; 585 case 'd': 586 case 'y': 587 return C_RegisterClass; 588 break; 589 } 590 } 591 return TargetLowering::getConstraintType(Constraint); 592} 593 594std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 595getRegForInlineAsmConstraint(const std::string &Constraint, 596 MVT::ValueType VT) const 597{ 598 if (Constraint.size() == 1) { 599 switch (Constraint[0]) { 600 case 'r': 601 return std::make_pair(0U, Mips::CPURegsRegisterClass); 602 break; 603 } 604 } 605 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 606} 607 608std::vector<unsigned> MipsTargetLowering:: 609getRegClassForInlineAsmConstraint(const std::string &Constraint, 610 MVT::ValueType VT) const 611{ 612 if (Constraint.size() != 1) 613 return std::vector<unsigned>(); 614 615 switch (Constraint[0]) { 616 default : break; 617 case 'r': 618 // GCC Mips Constraint Letters 619 case 'd': 620 case 'y': 621 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0, 622 Mips::A1, Mips::A2, Mips::A3, 623 Mips::T0, Mips::T1, Mips::T2, 624 Mips::T3, Mips::T4, Mips::T5, 625 Mips::T6, Mips::T7, Mips::S0, 626 Mips::S1, Mips::S2, Mips::S3, 627 Mips::S4, Mips::S5, Mips::S6, 628 Mips::S7, Mips::T8, Mips::T9, 0); 629 break; 630 } 631 return std::vector<unsigned>(); 632} 633