MipsISelLowering.cpp revision b37a742333b9d624f2c42b737352a30fd02fbd98 
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "mips-lower"
16#include "MipsISelLowering.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "MipsTargetObjectFile.h"
20#include "MipsSubtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalVariable.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/CallingConv.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/SelectionDAGISel.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35using namespace llvm;
36
37const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
38  switch (Opcode) {
39    case MipsISD::JmpLink    : return "MipsISD::JmpLink";
40    case MipsISD::Hi         : return "MipsISD::Hi";
41    case MipsISD::Lo         : return "MipsISD::Lo";
42    case MipsISD::GPRel      : return "MipsISD::GPRel";
43    case MipsISD::Ret        : return "MipsISD::Ret";
44    case MipsISD::CMov       : return "MipsISD::CMov";
45    case MipsISD::SelectCC   : return "MipsISD::SelectCC";
46    case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
47    case MipsISD::FPBrcond   : return "MipsISD::FPBrcond";
48    case MipsISD::FPCmp      : return "MipsISD::FPCmp";
49    case MipsISD::FPRound    : return "MipsISD::FPRound";
50    default                  : return NULL;
51  }
52}
53
54MipsTargetLowering::
55MipsTargetLowering(MipsTargetMachine &TM)
56  : TargetLowering(TM, new MipsTargetObjectFile()) {
57  Subtarget = &TM.getSubtarget<MipsSubtarget>();
58
59  // Mips does not have i1 type, so use i32 for
60  // setcc operations results (slt, sgt, ...).
61  setBooleanContents(ZeroOrOneBooleanContent);
62
63  // Set up the register classes
64  addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
65  addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
66
67  // When dealing with single precision only, use libcalls
68  if (!Subtarget->isSingleFloat())
69    if (!Subtarget->isFP64bit())
70      addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
71
72  // Load extented operations for i1 types must be promoted
73  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
74  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
75  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
76
77  // MIPS doesn't have extending float->double load/store
78  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
79  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
80
81  // Used by legalize types to correctly generate the setcc result.
82  // Without this, every float setcc comes with a AND/OR with the result,
83  // we don't want this, since the fpcmp result goes to a flag register,
84  // which is used implicitly by brcond and select operations.
85  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
86
87  // Mips Custom Operations
88  setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
89  setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
90  setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
91  setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
92  setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
93  setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
94  setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
95  setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
96  setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
97  setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
98  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Custom);
99  setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
100
101  // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
102  // with operands comming from setcc fp comparions. This is necessary since
103  // the result from these setcc are in a flag registers (FCR31).
104  setOperationAction(ISD::AND,              MVT::i32,   Custom);
105  setOperationAction(ISD::OR,               MVT::i32,   Custom);
106
107  // Operations not directly supported by Mips.
108  setOperationAction(ISD::BR_JT,             MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,             MVT::Other, Expand);
110  setOperationAction(ISD::SELECT_CC,         MVT::Other, Expand);
111  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
112  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
113  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
114  setOperationAction(ISD::CTPOP,             MVT::i32,   Expand);
115  setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
116  setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
117  setOperationAction(ISD::ROTR,              MVT::i32,   Expand);
118  setOperationAction(ISD::SHL_PARTS,         MVT::i32,   Expand);
119  setOperationAction(ISD::SRA_PARTS,         MVT::i32,   Expand);
120  setOperationAction(ISD::SRL_PARTS,         MVT::i32,   Expand);
121  setOperationAction(ISD::FCOPYSIGN,         MVT::f32,   Expand);
122  setOperationAction(ISD::FCOPYSIGN,         MVT::f64,   Expand);
123  setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
124  setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
125  setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
126  setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
127  setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
128  setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
129  setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
130  setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
131
132  setOperationAction(ISD::EH_LABEL,          MVT::Other, Expand);
133
134  // Use the default for now
135  setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
136  setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
137  setOperationAction(ISD::MEMBARRIER,        MVT::Other, Expand);
138
139  if (Subtarget->isSingleFloat())
140    setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
141
142  if (!Subtarget->hasSEInReg()) {
143    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
144    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
145  }
146
147  if (!Subtarget->hasBitCount())
148    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
149
150  if (!Subtarget->hasSwap())
151    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
152
153  setStackPointerRegisterToSaveRestore(Mips::SP);
154  computeRegisterProperties();
155}
156
157MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
158  return MVT::i32;
159}
160
161/// getFunctionAlignment - Return the Log2 alignment of this function.
162unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
163  return 2;
164}
165
166SDValue MipsTargetLowering::
167LowerOperation(SDValue Op, SelectionDAG &DAG)
168{
169  switch (Op.getOpcode())
170  {
171    case ISD::AND:                return LowerANDOR(Op, DAG);
172    case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
173    case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
174    case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
175    case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
176    case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
177    case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
178    case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
179    case ISD::OR:                 return LowerANDOR(Op, DAG);
180    case ISD::SELECT:             return LowerSELECT(Op, DAG);
181    case ISD::SETCC:              return LowerSETCC(Op, DAG);
182  }
183  return SDValue();
184}
185
186//===----------------------------------------------------------------------===//
187//  Lower helper functions
188//===----------------------------------------------------------------------===//
189
190// AddLiveIn - This helper function adds the specified physical register to the
191// MachineFunction as a live in value.  It also creates a corresponding
192// virtual register for it.
193static unsigned
194AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
195{
196  assert(RC->contains(PReg) && "Not the correct regclass!");
197  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
198  MF.getRegInfo().addLiveIn(PReg, VReg);
199  return VReg;
200}
201
202// Get fp branch code (not opcode) from condition code.
203static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
204  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
205    return Mips::BRANCH_T;
206
207  if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
208    return Mips::BRANCH_F;
209
210  return Mips::BRANCH_INVALID;
211}
212
213static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
214  switch(BC) {
215    default:
216      llvm_unreachable("Unknown branch code");
217    case Mips::BRANCH_T  : return Mips::BC1T;
218    case Mips::BRANCH_F  : return Mips::BC1F;
219    case Mips::BRANCH_TL : return Mips::BC1TL;
220    case Mips::BRANCH_FL : return Mips::BC1FL;
221  }
222}
223
224static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
225  switch (CC) {
226  default: llvm_unreachable("Unknown fp condition code!");
227  case ISD::SETEQ:
228  case ISD::SETOEQ: return Mips::FCOND_EQ;
229  case ISD::SETUNE: return Mips::FCOND_OGL;
230  case ISD::SETLT:
231  case ISD::SETOLT: return Mips::FCOND_OLT;
232  case ISD::SETGT:
233  case ISD::SETOGT: return Mips::FCOND_OGT;
234  case ISD::SETLE:
235  case ISD::SETOLE: return Mips::FCOND_OLE;
236  case ISD::SETGE:
237  case ISD::SETOGE: return Mips::FCOND_OGE;
238  case ISD::SETULT: return Mips::FCOND_ULT;
239  case ISD::SETULE: return Mips::FCOND_ULE;
240  case ISD::SETUGT: return Mips::FCOND_UGT;
241  case ISD::SETUGE: return Mips::FCOND_UGE;
242  case ISD::SETUO:  return Mips::FCOND_UN;
243  case ISD::SETO:   return Mips::FCOND_OR;
244  case ISD::SETNE:
245  case ISD::SETONE: return Mips::FCOND_NEQ;
246  case ISD::SETUEQ: return Mips::FCOND_UEQ;
247  }
248}
249
250MachineBasicBlock *
251MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
252                                                MachineBasicBlock *BB,
253                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
254  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
255  bool isFPCmp = false;
256  DebugLoc dl = MI->getDebugLoc();
257
258  switch (MI->getOpcode()) {
259  default: assert(false && "Unexpected instr type to insert");
260  case Mips::Select_FCC:
261  case Mips::Select_FCC_S32:
262  case Mips::Select_FCC_D32:
263    isFPCmp = true; // FALL THROUGH
264  case Mips::Select_CC:
265  case Mips::Select_CC_S32:
266  case Mips::Select_CC_D32: {
267    // To "insert" a SELECT_CC instruction, we actually have to insert the
268    // diamond control-flow pattern.  The incoming instruction knows the
269    // destination vreg to set, the condition code register to branch on, the
270    // true/false values to select between, and a branch opcode to use.
271    const BasicBlock *LLVM_BB = BB->getBasicBlock();
272    MachineFunction::iterator It = BB;
273    ++It;
274
275    //  thisMBB:
276    //  ...
277    //   TrueVal = ...
278    //   setcc r1, r2, r3
279    //   bNE   r1, r0, copy1MBB
280    //   fallthrough --> copy0MBB
281    MachineBasicBlock *thisMBB  = BB;
282    MachineFunction *F = BB->getParent();
283    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
284    MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
285
286    // Emit the right instruction according to the type of the operands compared
287    if (isFPCmp) {
288      // Find the condiction code present in the setcc operation.
289      Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
290      // Get the branch opcode from the branch code.
291      unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
292      BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
293    } else
294      BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
295        .addReg(Mips::ZERO).addMBB(sinkMBB);
296
297    F->insert(It, copy0MBB);
298    F->insert(It, sinkMBB);
299    // Update machine-CFG edges by first adding all successors of the current
300    // block to the new block which will contain the Phi node for the select.
301    // Also inform sdisel of the edge changes.
302    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
303          e = BB->succ_end(); i != e; ++i) {
304      EM->insert(std::make_pair(*i, sinkMBB));
305      sinkMBB->addSuccessor(*i);
306    }
307    // Next, remove all successors of the current block, and add the true
308    // and fallthrough blocks as its successors.
309    while(!BB->succ_empty())
310      BB->removeSuccessor(BB->succ_begin());
311    BB->addSuccessor(copy0MBB);
312    BB->addSuccessor(sinkMBB);
313
314    //  copy0MBB:
315    //   %FalseValue = ...
316    //   # fallthrough to sinkMBB
317    BB = copy0MBB;
318
319    // Update machine-CFG edges
320    BB->addSuccessor(sinkMBB);
321
322    //  sinkMBB:
323    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
324    //  ...
325    BB = sinkMBB;
326    BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
327      .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
328      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
329
330    F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
331    return BB;
332  }
333  }
334}
335
336//===----------------------------------------------------------------------===//
337//  Misc Lower Operation implementation
338//===----------------------------------------------------------------------===//
339
340SDValue MipsTargetLowering::
341LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
342{
343  if (!Subtarget->isMips1())
344    return Op;
345
346  MachineFunction &MF = DAG.getMachineFunction();
347  unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
348
349  SDValue Chain = DAG.getEntryNode();
350  DebugLoc dl = Op.getDebugLoc();
351  SDValue Src = Op.getOperand(0);
352
353  // Set the condition register
354  SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
355  CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
356  CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
357
358  SDValue Cst = DAG.getConstant(3, MVT::i32);
359  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
360  Cst = DAG.getConstant(2, MVT::i32);
361  SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
362
363  SDValue InFlag(0, 0);
364  CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
365
366  // Emit the round instruction and bit convert to integer
367  SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
368                              Src, CondReg.getValue(1));
369  SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
370  return BitCvt;
371}
372
373SDValue MipsTargetLowering::
374LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
375{
376  SDValue Chain = Op.getOperand(0);
377  SDValue Size = Op.getOperand(1);
378  DebugLoc dl = Op.getDebugLoc();
379
380  // Get a reference from Mips stack pointer
381  SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
382
383  // Subtract the dynamic size from the actual stack size to
384  // obtain the new stack size.
385  SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
386
387  // The Sub result contains the new stack start address, so it
388  // must be placed in the stack pointer register.
389  Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
390
391  // This node always has two return values: a new stack pointer
392  // value and a chain
393  SDValue Ops[2] = { Sub, Chain };
394  return DAG.getMergeValues(Ops, 2, dl);
395}
396
397SDValue MipsTargetLowering::
398LowerANDOR(SDValue Op, SelectionDAG &DAG)
399{
400  SDValue LHS   = Op.getOperand(0);
401  SDValue RHS   = Op.getOperand(1);
402  DebugLoc dl   = Op.getDebugLoc();
403
404  if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
405    return Op;
406
407  SDValue True  = DAG.getConstant(1, MVT::i32);
408  SDValue False = DAG.getConstant(0, MVT::i32);
409
410  SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
411                             LHS, True, False, LHS.getOperand(2));
412  SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
413                             RHS, True, False, RHS.getOperand(2));
414
415  return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
416}
417
418SDValue MipsTargetLowering::
419LowerBRCOND(SDValue Op, SelectionDAG &DAG)
420{
421  // The first operand is the chain, the second is the condition, the third is
422  // the block to branch to if the condition is true.
423  SDValue Chain = Op.getOperand(0);
424  SDValue Dest = Op.getOperand(2);
425  DebugLoc dl = Op.getDebugLoc();
426
427  if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
428    return Op;
429
430  SDValue CondRes = Op.getOperand(1);
431  SDValue CCNode  = CondRes.getOperand(2);
432  Mips::CondCode CC =
433    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
434  SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
435
436  return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
437             Dest, CondRes);
438}
439
440SDValue MipsTargetLowering::
441LowerSETCC(SDValue Op, SelectionDAG &DAG)
442{
443  // The operands to this are the left and right operands to compare (ops #0,
444  // and #1) and the condition code to compare them with (op #2) as a
445  // CondCodeSDNode.
446  SDValue LHS = Op.getOperand(0);
447  SDValue RHS = Op.getOperand(1);
448  DebugLoc dl = Op.getDebugLoc();
449
450  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
451
452  return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
453                 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
454}
455
456SDValue MipsTargetLowering::
457LowerSELECT(SDValue Op, SelectionDAG &DAG)
458{
459  SDValue Cond  = Op.getOperand(0);
460  SDValue True  = Op.getOperand(1);
461  SDValue False = Op.getOperand(2);
462  DebugLoc dl = Op.getDebugLoc();
463
464  // if the incomming condition comes from a integer compare, the select
465  // operation must be SelectCC or a conditional move if the subtarget
466  // supports it.
467  if (Cond.getOpcode() != MipsISD::FPCmp) {
468    if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
469      return Op;
470    return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
471                       Cond, True, False);
472  }
473
474  // if the incomming condition comes from fpcmp, the select
475  // operation must use FPSelectCC.
476  SDValue CCNode = Cond.getOperand(2);
477  return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
478                     Cond, True, False, CCNode);
479}
480
481SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
482  // FIXME there isn't actually debug info here
483  DebugLoc dl = Op.getDebugLoc();
484  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
485
486  if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
487    SDVTList VTs = DAG.getVTList(MVT::i32);
488
489    MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
490
491    // %gp_rel relocation
492    if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
493      SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
494                                              MipsII::MO_GPREL);
495      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
496      SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
497      return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
498    }
499    // %hi/%lo relocation
500    SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
501                                            MipsII::MO_ABS_HILO);
502    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
503    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
504    return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
505
506  } else {
507    SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
508                                            MipsII::MO_GOT);
509    SDValue ResNode = DAG.getLoad(MVT::i32, dl,
510                                  DAG.getEntryNode(), GA, NULL, 0);
511    // On functions and global targets not internal linked only
512    // a load from got/GP is necessary for PIC to work.
513    if (!GV->hasLocalLinkage() || isa<Function>(GV))
514      return ResNode;
515    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
516    return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
517  }
518
519  llvm_unreachable("Dont know how to handle GlobalAddress");
520  return SDValue(0,0);
521}
522
523SDValue MipsTargetLowering::
524LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
525{
526  llvm_unreachable("TLS not implemented for MIPS.");
527  return SDValue(); // Not reached
528}
529
530SDValue MipsTargetLowering::
531LowerJumpTable(SDValue Op, SelectionDAG &DAG)
532{
533  SDValue ResNode;
534  SDValue HiPart;
535  // FIXME there isn't actually debug info here
536  DebugLoc dl = Op.getDebugLoc();
537  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
538  unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
539
540  EVT PtrVT = Op.getValueType();
541  JumpTableSDNode *JT  = cast<JumpTableSDNode>(Op);
542
543  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
544
545  if (IsPIC) {
546    SDValue Ops[] = { JTI };
547    HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
548  } else // Emit Load from Global Pointer
549    HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
550
551  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
552  ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
553
554  return ResNode;
555}
556
557SDValue MipsTargetLowering::
558LowerConstantPool(SDValue Op, SelectionDAG &DAG)
559{
560  SDValue ResNode;
561  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
562  Constant *C = N->getConstVal();
563  // FIXME there isn't actually debug info here
564  DebugLoc dl = Op.getDebugLoc();
565
566  // gp_rel relocation
567  // FIXME: we should reference the constant pool using small data sections,
568  // but the asm printer currently doens't support this feature without
569  // hacking it. This feature should come soon so we can uncomment the
570  // stuff below.
571  //if (IsInSmallSection(C->getType())) {
572  //  SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
573  //  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
574  //  ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
575
576  if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
577    SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
578                                      N->getOffset(), MipsII::MO_ABS_HILO);
579    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
580    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
581    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
582  } else {
583    SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
584                                      N->getOffset(), MipsII::MO_GOT);
585    SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
586                                 CP, NULL, 0);
587    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
588    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
589  }
590
591  return ResNode;
592}
593
594//===----------------------------------------------------------------------===//
595//                      Calling Convention Implementation
596//===----------------------------------------------------------------------===//
597
598#include "MipsGenCallingConv.inc"
599
600//===----------------------------------------------------------------------===//
601// TODO: Implement a generic logic using tblgen that can support this.
602// Mips O32 ABI rules:
603// ---
604// i32 - Passed in A0, A1, A2, A3 and stack
605// f32 - Only passed in f32 registers if no int reg has been used yet to hold
606//       an argument. Otherwise, passed in A1, A2, A3 and stack.
607// f64 - Only passed in two aliased f32 registers if no int reg has been used
608//       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
609//       not used, it must be shadowed. If only A3 is avaiable, shadow it and
610//       go to stack.
611//===----------------------------------------------------------------------===//
612
613static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
614                       EVT LocVT, CCValAssign::LocInfo LocInfo,
615                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
616
617  static const unsigned IntRegsSize=4, FloatRegsSize=2;
618
619  static const unsigned IntRegs[] = {
620      Mips::A0, Mips::A1, Mips::A2, Mips::A3
621  };
622  static const unsigned F32Regs[] = {
623      Mips::F12, Mips::F14
624  };
625  static const unsigned F64Regs[] = {
626      Mips::D6, Mips::D7
627  };
628
629  unsigned Reg=0;
630  unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
631  bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
632
633  // Promote i8 and i16
634  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
635    LocVT = MVT::i32;
636    if (ArgFlags.isSExt())
637      LocInfo = CCValAssign::SExt;
638    else if (ArgFlags.isZExt())
639      LocInfo = CCValAssign::ZExt;
640    else
641      LocInfo = CCValAssign::AExt;
642  }
643
644  if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
645    Reg = State.AllocateReg(IntRegs, IntRegsSize);
646    IntRegUsed = true;
647    LocVT = MVT::i32;
648  }
649
650  if (ValVT.isFloatingPoint() && !IntRegUsed) {
651    if (ValVT == MVT::f32)
652      Reg = State.AllocateReg(F32Regs, FloatRegsSize);
653    else
654      Reg = State.AllocateReg(F64Regs, FloatRegsSize);
655  }
656
657  if (ValVT == MVT::f64 && IntRegUsed) {
658    if (UnallocIntReg != IntRegsSize) {
659      // If we hit register A3 as the first not allocated, we must
660      // mark it as allocated (shadow) and use the stack instead.
661      if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
662        Reg = Mips::A2;
663      for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
664        State.AllocateReg(UnallocIntReg);
665    }
666    LocVT = MVT::i32;
667  }
668
669  if (!Reg) {
670    unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
671    unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
672    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
673  } else
674    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
675
676  return false; // CC must always match
677}
678
679static bool CC_MipsO32_VarArgs(unsigned ValNo, EVT ValVT,
680                       EVT LocVT, CCValAssign::LocInfo LocInfo,
681                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
682
683  static const unsigned IntRegsSize=4;
684
685  static const unsigned IntRegs[] = {
686      Mips::A0, Mips::A1, Mips::A2, Mips::A3
687  };
688
689  // Promote i8 and i16
690  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
691    LocVT = MVT::i32;
692    if (ArgFlags.isSExt())
693      LocInfo = CCValAssign::SExt;
694    else if (ArgFlags.isZExt())
695      LocInfo = CCValAssign::ZExt;
696    else
697      LocInfo = CCValAssign::AExt;
698  }
699
700  if (ValVT == MVT::i32 || ValVT == MVT::f32) {
701    if (unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize)) {
702      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
703      return false;
704    }
705    unsigned Off = State.AllocateStack(4, 4);
706    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
707    return false;
708  }
709
710  unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
711  if (ValVT == MVT::f64) {
712    if (IntRegs[UnallocIntReg] == (unsigned (Mips::A1))) {
713      // A1 can't be used anymore, because 64 bit arguments
714      // must be aligned when copied back to the caller stack
715      State.AllocateReg(IntRegs, IntRegsSize);
716      UnallocIntReg++;
717    }
718
719    if (IntRegs[UnallocIntReg] == (unsigned (Mips::A0)) ||
720        IntRegs[UnallocIntReg] == (unsigned (Mips::A2))) {
721      unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize);
722      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
723      // Shadow the next register so it can be used
724      // later to get the other 32bit part.
725      State.AllocateReg(IntRegs, IntRegsSize);
726      return false;
727    }
728
729    // Register is shadowed to preserve alignment, and the
730    // argument goes to a stack location.
731    if (UnallocIntReg != IntRegsSize)
732      State.AllocateReg(IntRegs, IntRegsSize);
733
734    unsigned Off = State.AllocateStack(8, 8);
735    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
736    return false;
737  }
738
739  return true; // CC didn't match
740}
741
742//===----------------------------------------------------------------------===//
743//                  Call Calling Convention Implementation
744//===----------------------------------------------------------------------===//
745
746/// LowerCall - functions arguments are copied from virtual regs to
747/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
748/// TODO: isTailCall.
749SDValue
750MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
751                              CallingConv::ID CallConv, bool isVarArg,
752                              bool &isTailCall,
753                              const SmallVectorImpl<ISD::OutputArg> &Outs,
754                              const SmallVectorImpl<ISD::InputArg> &Ins,
755                              DebugLoc dl, SelectionDAG &DAG,
756                              SmallVectorImpl<SDValue> &InVals) {
757  // MIPs target does not yet support tail call optimization.
758  isTailCall = false;
759
760  MachineFunction &MF = DAG.getMachineFunction();
761  MachineFrameInfo *MFI = MF.getFrameInfo();
762  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
763
764  // Analyze operands of the call, assigning locations to each operand.
765  SmallVector<CCValAssign, 16> ArgLocs;
766  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
767                 *DAG.getContext());
768
769  // To meet O32 ABI, Mips must always allocate 16 bytes on
770  // the stack (even if less than 4 are used as arguments)
771  if (Subtarget->isABI_O32()) {
772    int VTsize = EVT(MVT::i32).getSizeInBits()/8;
773    MFI->CreateFixedObject(VTsize, (VTsize*3), true, false);
774    CCInfo.AnalyzeCallOperands(Outs,
775                     isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
776  } else
777    CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
778
779  // Get a count of how many bytes are to be pushed on the stack.
780  unsigned NumBytes = CCInfo.getNextStackOffset();
781  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
782
783  // With EABI is it possible to have 16 args on registers.
784  SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
785  SmallVector<SDValue, 8> MemOpChains;
786
787  // First/LastArgStackLoc contains the first/last
788  // "at stack" argument location.
789  int LastArgStackLoc = 0;
790  unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
791
792  // Walk the register/memloc assignments, inserting copies/loads.
793  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
794    SDValue Arg = Outs[i].Val;
795    CCValAssign &VA = ArgLocs[i];
796
797    // Promote the value if needed.
798    switch (VA.getLocInfo()) {
799    default: llvm_unreachable("Unknown loc info!");
800    case CCValAssign::Full:
801      if (Subtarget->isABI_O32() && VA.isRegLoc()) {
802        if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
803          Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
804        if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
805          Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
806          SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
807                                   DAG.getConstant(0, getPointerTy()));
808          SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
809                                   DAG.getConstant(1, getPointerTy()));
810          RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
811          RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
812          continue;
813        }
814      }
815      break;
816    case CCValAssign::SExt:
817      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
818      break;
819    case CCValAssign::ZExt:
820      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
821      break;
822    case CCValAssign::AExt:
823      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
824      break;
825    }
826
827    // Arguments that can be passed on register must be kept at
828    // RegsToPass vector
829    if (VA.isRegLoc()) {
830      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
831      continue;
832    }
833
834    // Register can't get to this point...
835    assert(VA.isMemLoc());
836
837    // Create the frame index object for this incoming parameter
838    // This guarantees that when allocating Local Area the firsts
839    // 16 bytes which are alwayes reserved won't be overwritten
840    // if O32 ABI is used. For EABI the first address is zero.
841    LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
842    int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
843                                    LastArgStackLoc, true, false);
844
845    SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
846
847    // emit ISD::STORE whichs stores the
848    // parameter value to a stack Location
849    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
850  }
851
852  // Transform all store nodes into one single node because all store
853  // nodes are independent of each other.
854  if (!MemOpChains.empty())
855    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
856                        &MemOpChains[0], MemOpChains.size());
857
858  // Build a sequence of copy-to-reg nodes chained together with token
859  // chain and flag operands which copy the outgoing args into registers.
860  // The InFlag in necessary since all emited instructions must be
861  // stuck together.
862  SDValue InFlag;
863  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
864    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
865                             RegsToPass[i].second, InFlag);
866    InFlag = Chain.getValue(1);
867  }
868
869  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
870  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
871  // node so that legalize doesn't hack it.
872  unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
873  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
874    Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
875                                getPointerTy(), 0, OpFlag);
876  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
877    Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
878                                getPointerTy(), OpFlag);
879
880  // MipsJmpLink = #chain, #target_address, #opt_in_flags...
881  //             = Chain, Callee, Reg#1, Reg#2, ...
882  //
883  // Returns a chain & a flag for retval copy to use.
884  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
885  SmallVector<SDValue, 8> Ops;
886  Ops.push_back(Chain);
887  Ops.push_back(Callee);
888
889  // Add argument registers to the end of the list so that they are
890  // known live into the call.
891  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
892    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
893                                  RegsToPass[i].second.getValueType()));
894
895  if (InFlag.getNode())
896    Ops.push_back(InFlag);
897
898  Chain  = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
899  InFlag = Chain.getValue(1);
900
901  // Create a stack location to hold GP when PIC is used. This stack
902  // location is used on function prologue to save GP and also after all
903  // emited CALL's to restore GP.
904  if (IsPIC) {
905      // Function can have an arbitrary number of calls, so
906      // hold the LastArgStackLoc with the biggest offset.
907      int FI;
908      MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
909      if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
910        LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
911        // Create the frame index only once. SPOffset here can be anything
912        // (this will be fixed on processFunctionBeforeFrameFinalized)
913        if (MipsFI->getGPStackOffset() == -1) {
914          FI = MFI->CreateFixedObject(4, 0, true, false);
915          MipsFI->setGPFI(FI);
916        }
917        MipsFI->setGPStackOffset(LastArgStackLoc);
918      }
919
920      // Reload GP value.
921      FI = MipsFI->getGPFI();
922      SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
923      SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
924      Chain = GPLoad.getValue(1);
925      Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
926                               GPLoad, SDValue(0,0));
927      InFlag = Chain.getValue(1);
928  }
929
930  // Create the CALLSEQ_END node.
931  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
932                             DAG.getIntPtrConstant(0, true), InFlag);
933  InFlag = Chain.getValue(1);
934
935  // Handle result values, copying them out of physregs into vregs that we
936  // return.
937  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
938                         Ins, dl, DAG, InVals);
939}
940
941/// LowerCallResult - Lower the result values of a call into the
942/// appropriate copies out of appropriate physical registers.
943SDValue
944MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
945                                    CallingConv::ID CallConv, bool isVarArg,
946                                    const SmallVectorImpl<ISD::InputArg> &Ins,
947                                    DebugLoc dl, SelectionDAG &DAG,
948                                    SmallVectorImpl<SDValue> &InVals) {
949
950  // Assign locations to each value returned by this call.
951  SmallVector<CCValAssign, 16> RVLocs;
952  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
953                 RVLocs, *DAG.getContext());
954
955  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
956
957  // Copy all of the result registers out of their specified physreg.
958  for (unsigned i = 0; i != RVLocs.size(); ++i) {
959    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
960                               RVLocs[i].getValVT(), InFlag).getValue(1);
961    InFlag = Chain.getValue(2);
962    InVals.push_back(Chain.getValue(0));
963  }
964
965  return Chain;
966}
967
968//===----------------------------------------------------------------------===//
969//             Formal Arguments Calling Convention Implementation
970//===----------------------------------------------------------------------===//
971
972/// LowerFormalArguments - transform physical registers into virtual registers
973/// and generate load operations for arguments places on the stack.
974SDValue
975MipsTargetLowering::LowerFormalArguments(SDValue Chain,
976                                        CallingConv::ID CallConv, bool isVarArg,
977                                        const SmallVectorImpl<ISD::InputArg>
978                                        &Ins,
979                                        DebugLoc dl, SelectionDAG &DAG,
980                                        SmallVectorImpl<SDValue> &InVals) {
981
982  MachineFunction &MF = DAG.getMachineFunction();
983  MachineFrameInfo *MFI = MF.getFrameInfo();
984  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
985
986  unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
987
988  // Used with vargs to acumulate store chains.
989  std::vector<SDValue> OutChains;
990
991  // Keep track of the last register used for arguments
992  unsigned ArgRegEnd = 0;
993
994  // Assign locations to all of the incoming arguments.
995  SmallVector<CCValAssign, 16> ArgLocs;
996  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
997                 ArgLocs, *DAG.getContext());
998
999  if (Subtarget->isABI_O32())
1000    CCInfo.AnalyzeFormalArguments(Ins,
1001                        isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1002  else
1003    CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1004
1005  SDValue StackPtr;
1006
1007  unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1008
1009  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1010    CCValAssign &VA = ArgLocs[i];
1011
1012    // Arguments stored on registers
1013    if (VA.isRegLoc()) {
1014      EVT RegVT = VA.getLocVT();
1015      ArgRegEnd = VA.getLocReg();
1016      TargetRegisterClass *RC = 0;
1017
1018      if (RegVT == MVT::i32)
1019        RC = Mips::CPURegsRegisterClass;
1020      else if (RegVT == MVT::f32)
1021        RC = Mips::FGR32RegisterClass;
1022      else if (RegVT == MVT::f64) {
1023        if (!Subtarget->isSingleFloat())
1024          RC = Mips::AFGR64RegisterClass;
1025      } else
1026        llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1027
1028      // Transform the arguments stored on
1029      // physical registers into virtual ones
1030      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1031      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1032
1033      // If this is an 8 or 16-bit value, it has been passed promoted
1034      // to 32 bits.  Insert an assert[sz]ext to capture this, then
1035      // truncate to the right size.
1036      if (VA.getLocInfo() != CCValAssign::Full) {
1037        unsigned Opcode = 0;
1038        if (VA.getLocInfo() == CCValAssign::SExt)
1039          Opcode = ISD::AssertSext;
1040        else if (VA.getLocInfo() == CCValAssign::ZExt)
1041          Opcode = ISD::AssertZext;
1042        if (Opcode)
1043          ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1044                                 DAG.getValueType(VA.getValVT()));
1045        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1046      }
1047
1048      // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1049      if (Subtarget->isABI_O32()) {
1050        if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1051          ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1052        if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1053          unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1054                                    VA.getLocReg()+1, RC);
1055          SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1056          SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
1057          SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
1058          ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1059        }
1060      }
1061
1062      InVals.push_back(ArgValue);
1063    } else { // VA.isRegLoc()
1064
1065      // sanity check
1066      assert(VA.isMemLoc());
1067
1068      // The last argument is not a register anymore
1069      ArgRegEnd = 0;
1070
1071      // The stack pointer offset is relative to the caller stack frame.
1072      // Since the real stack size is unknown here, a negative SPOffset
1073      // is used so there's a way to adjust these offsets when the stack
1074      // size get known (on EliminateFrameIndex). A dummy SPOffset is
1075      // used instead of a direct negative address (which is recorded to
1076      // be used on emitPrologue) to avoid mis-calc of the first stack
1077      // offset on PEI::calculateFrameObjectOffsets.
1078      // Arguments are always 32-bit.
1079      unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1080      int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
1081      MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1082        (FirstStackArgLoc + VA.getLocMemOffset())));
1083
1084      // Create load nodes to retrieve arguments from the stack
1085      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1086      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1087    }
1088  }
1089
1090  // The mips ABIs for returning structs by value requires that we copy
1091  // the sret argument into $v0 for the return. Save the argument into
1092  // a virtual register so that we can access it from the return points.
1093  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1094    unsigned Reg = MipsFI->getSRetReturnReg();
1095    if (!Reg) {
1096      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1097      MipsFI->setSRetReturnReg(Reg);
1098    }
1099    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1100    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1101  }
1102
1103  // To meet ABI, when VARARGS are passed on registers, the registers
1104  // must have their values written to the caller stack frame. If the last
1105  // argument was placed in the stack, there's no need to save any register.
1106  if ((isVarArg) && (Subtarget->isABI_O32() && ArgRegEnd)) {
1107    if (StackPtr.getNode() == 0)
1108      StackPtr = DAG.getRegister(StackReg, getPointerTy());
1109
1110    // The last register argument that must be saved is Mips::A3
1111    TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1112    unsigned StackLoc = ArgLocs.size()-1;
1113
1114    for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd, ++StackLoc) {
1115      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1116      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1117
1118      int FI = MFI->CreateFixedObject(4, 0, true, false);
1119      MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
1120      SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1121      OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0));
1122    }
1123  }
1124
1125  // All stores are grouped in one node to allow the matching between
1126  // the size of Ins and InVals. This only happens when on varg functions
1127  if (!OutChains.empty()) {
1128    OutChains.push_back(Chain);
1129    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1130                        &OutChains[0], OutChains.size());
1131  }
1132
1133  return Chain;
1134}
1135
1136//===----------------------------------------------------------------------===//
1137//               Return Value Calling Convention Implementation
1138//===----------------------------------------------------------------------===//
1139
1140SDValue
1141MipsTargetLowering::LowerReturn(SDValue Chain,
1142                                CallingConv::ID CallConv, bool isVarArg,
1143                                const SmallVectorImpl<ISD::OutputArg> &Outs,
1144                                DebugLoc dl, SelectionDAG &DAG) {
1145
1146  // CCValAssign - represent the assignment of
1147  // the return value to a location
1148  SmallVector<CCValAssign, 16> RVLocs;
1149
1150  // CCState - Info about the registers and stack slot.
1151  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1152                 RVLocs, *DAG.getContext());
1153
1154  // Analize return values.
1155  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1156
1157  // If this is the first return lowered for this function, add
1158  // the regs to the liveout set for the function.
1159  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1160    for (unsigned i = 0; i != RVLocs.size(); ++i)
1161      if (RVLocs[i].isRegLoc())
1162        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1163  }
1164
1165  SDValue Flag;
1166
1167  // Copy the result values into the output registers.
1168  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1169    CCValAssign &VA = RVLocs[i];
1170    assert(VA.isRegLoc() && "Can only return in registers!");
1171
1172    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1173                             Outs[i].Val, Flag);
1174
1175    // guarantee that all emitted copies are
1176    // stuck together, avoiding something bad
1177    Flag = Chain.getValue(1);
1178  }
1179
1180  // The mips ABIs for returning structs by value requires that we copy
1181  // the sret argument into $v0 for the return. We saved the argument into
1182  // a virtual register in the entry block, so now we copy the value out
1183  // and into $v0.
1184  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1185    MachineFunction &MF      = DAG.getMachineFunction();
1186    MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1187    unsigned Reg = MipsFI->getSRetReturnReg();
1188
1189    if (!Reg)
1190      llvm_unreachable("sret virtual register not created in the entry block");
1191    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1192
1193    Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1194    Flag = Chain.getValue(1);
1195  }
1196
1197  // Return on Mips is always a "jr $ra"
1198  if (Flag.getNode())
1199    return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1200                       Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1201  else // Return Void
1202    return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1203                       Chain, DAG.getRegister(Mips::RA, MVT::i32));
1204}
1205
1206//===----------------------------------------------------------------------===//
1207//                           Mips Inline Assembly Support
1208//===----------------------------------------------------------------------===//
1209
1210/// getConstraintType - Given a constraint letter, return the type of
1211/// constraint it is for this target.
1212MipsTargetLowering::ConstraintType MipsTargetLowering::
1213getConstraintType(const std::string &Constraint) const
1214{
1215  // Mips specific constrainy
1216  // GCC config/mips/constraints.md
1217  //
1218  // 'd' : An address register. Equivalent to r
1219  //       unless generating MIPS16 code.
1220  // 'y' : Equivalent to r; retained for
1221  //       backwards compatibility.
1222  // 'f' : Floating Point registers.
1223  if (Constraint.size() == 1) {
1224    switch (Constraint[0]) {
1225      default : break;
1226      case 'd':
1227      case 'y':
1228      case 'f':
1229        return C_RegisterClass;
1230        break;
1231    }
1232  }
1233  return TargetLowering::getConstraintType(Constraint);
1234}
1235
1236/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1237/// return a list of registers that can be used to satisfy the constraint.
1238/// This should only be used for C_RegisterClass constraints.
1239std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1240getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1241{
1242  if (Constraint.size() == 1) {
1243    switch (Constraint[0]) {
1244    case 'r':
1245      return std::make_pair(0U, Mips::CPURegsRegisterClass);
1246    case 'f':
1247      if (VT == MVT::f32)
1248        return std::make_pair(0U, Mips::FGR32RegisterClass);
1249      if (VT == MVT::f64)
1250        if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1251          return std::make_pair(0U, Mips::AFGR64RegisterClass);
1252    }
1253  }
1254  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1255}
1256
1257/// Given a register class constraint, like 'r', if this corresponds directly
1258/// to an LLVM register class, return a register of 0 and the register class
1259/// pointer.
1260std::vector<unsigned> MipsTargetLowering::
1261getRegClassForInlineAsmConstraint(const std::string &Constraint,
1262                                  EVT VT) const
1263{
1264  if (Constraint.size() != 1)
1265    return std::vector<unsigned>();
1266
1267  switch (Constraint[0]) {
1268    default : break;
1269    case 'r':
1270    // GCC Mips Constraint Letters
1271    case 'd':
1272    case 'y':
1273      return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1274             Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1275             Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1276             Mips::T8, 0);
1277
1278    case 'f':
1279      if (VT == MVT::f32) {
1280        if (Subtarget->isSingleFloat())
1281          return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1282                 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1283                 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1284                 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1285                 Mips::F30, Mips::F31, 0);
1286        else
1287          return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1288                 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1289                 Mips::F28, Mips::F30, 0);
1290      }
1291
1292      if (VT == MVT::f64)
1293        if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1294          return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1295                 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1296                 Mips::D14, Mips::D15, 0);
1297  }
1298  return std::vector<unsigned>();
1299}
1300
1301bool
1302MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1303  // The Mips target isn't yet aware of offsets.
1304  return false;
1305}
1306
1307bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1308  if (VT != MVT::f32 && VT != MVT::f64)
1309    return false;
1310  return Imm.isZero();
1311}
1312