MipsISelLowering.cpp revision b4d8d31e59b11e7a4d560c01377ce02f1245f056
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16//#include <algorithm> 17#include "MipsISelLowering.h" 18#include "MipsMachineFunction.h" 19#include "MipsTargetMachine.h" 20#include "MipsTargetObjectFile.h" 21#include "MipsSubtarget.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/CallingConv.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/SelectionDAGISel.h" 33#include "llvm/CodeGen/ValueTypes.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36using namespace llvm; 37 38const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 39 switch (Opcode) { 40 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 41 case MipsISD::Hi: return "MipsISD::Hi"; 42 case MipsISD::Lo: return "MipsISD::Lo"; 43 case MipsISD::GPRel: return "MipsISD::GPRel"; 44 case MipsISD::Ret: return "MipsISD::Ret"; 45 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 46 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 47 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 48 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 49 case MipsISD::FPRound: return "MipsISD::FPRound"; 50 case MipsISD::MAdd: return "MipsISD::MAdd"; 51 case MipsISD::MAddu: return "MipsISD::MAddu"; 52 case MipsISD::MSub: return "MipsISD::MSub"; 53 case MipsISD::MSubu: return "MipsISD::MSubu"; 54 case MipsISD::DivRem: return "MipsISD::DivRem"; 55 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 56 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 57 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 58 default: return NULL; 59 } 60} 61 62MipsTargetLowering:: 63MipsTargetLowering(MipsTargetMachine &TM) 64 : TargetLowering(TM, new MipsTargetObjectFile()) { 65 Subtarget = &TM.getSubtarget<MipsSubtarget>(); 66 67 // Mips does not have i1 type, so use i32 for 68 // setcc operations results (slt, sgt, ...). 69 setBooleanContents(ZeroOrOneBooleanContent); 70 71 // Set up the register classes 72 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 73 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 74 75 // When dealing with single precision only, use libcalls 76 if (!Subtarget->isSingleFloat()) 77 if (!Subtarget->isFP64bit()) 78 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 79 80 // Load extented operations for i1 types must be promoted 81 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 82 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 84 85 // MIPS doesn't have extending float->double load/store 86 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 87 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 88 89 // Used by legalize types to correctly generate the setcc result. 90 // Without this, every float setcc comes with a AND/OR with the result, 91 // we don't want this, since the fpcmp result goes to a flag register, 92 // which is used implicitly by brcond and select operations. 93 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 94 95 // Mips Custom Operations 96 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 97 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 98 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 99 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 100 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 101 setOperationAction(ISD::SELECT, MVT::f32, Custom); 102 setOperationAction(ISD::SELECT, MVT::f64, Custom); 103 setOperationAction(ISD::SELECT, MVT::i32, Custom); 104 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 105 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 107 setOperationAction(ISD::VASTART, MVT::Other, Custom); 108 109 setOperationAction(ISD::SDIV, MVT::i32, Expand); 110 setOperationAction(ISD::SREM, MVT::i32, Expand); 111 setOperationAction(ISD::UDIV, MVT::i32, Expand); 112 setOperationAction(ISD::UREM, MVT::i32, Expand); 113 114 // Operations not directly supported by Mips. 115 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 116 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 117 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 118 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 119 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 121 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 122 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 123 setOperationAction(ISD::ROTL, MVT::i32, Expand); 124 125 if (!Subtarget->isMips32r2()) 126 setOperationAction(ISD::ROTR, MVT::i32, Expand); 127 128 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 129 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 130 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 131 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 132 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 133 setOperationAction(ISD::FSIN, MVT::f32, Expand); 134 setOperationAction(ISD::FSIN, MVT::f64, Expand); 135 setOperationAction(ISD::FCOS, MVT::f32, Expand); 136 setOperationAction(ISD::FCOS, MVT::f64, Expand); 137 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 138 setOperationAction(ISD::FPOW, MVT::f32, Expand); 139 setOperationAction(ISD::FPOW, MVT::f64, Expand); 140 setOperationAction(ISD::FLOG, MVT::f32, Expand); 141 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 142 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 143 setOperationAction(ISD::FEXP, MVT::f32, Expand); 144 145 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 146 147 setOperationAction(ISD::VAARG, MVT::Other, Expand); 148 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 149 setOperationAction(ISD::VAEND, MVT::Other, Expand); 150 151 // Use the default for now 152 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 153 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 154 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 155 156 if (Subtarget->isSingleFloat()) 157 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 158 159 if (!Subtarget->hasSEInReg()) { 160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 162 } 163 164 if (!Subtarget->hasBitCount()) 165 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 166 167 if (!Subtarget->hasSwap()) 168 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 169 170 setTargetDAGCombine(ISD::ADDE); 171 setTargetDAGCombine(ISD::SUBE); 172 setTargetDAGCombine(ISD::SDIVREM); 173 setTargetDAGCombine(ISD::UDIVREM); 174 setTargetDAGCombine(ISD::SETCC); 175 176 setMinFunctionAlignment(2); 177 178 setStackPointerRegisterToSaveRestore(Mips::SP); 179 computeRegisterProperties(); 180} 181 182MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const { 183 return MVT::i32; 184} 185 186// SelectMadd - 187// Transforms a subgraph in CurDAG if the following pattern is found: 188// (addc multLo, Lo0), (adde multHi, Hi0), 189// where, 190// multHi/Lo: product of multiplication 191// Lo0: initial value of Lo register 192// Hi0: initial value of Hi register 193// Return true if pattern matching was successful. 194static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 195 // ADDENode's second operand must be a flag output of an ADDC node in order 196 // for the matching to be successful. 197 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 198 199 if (ADDCNode->getOpcode() != ISD::ADDC) 200 return false; 201 202 SDValue MultHi = ADDENode->getOperand(0); 203 SDValue MultLo = ADDCNode->getOperand(0); 204 SDNode* MultNode = MultHi.getNode(); 205 unsigned MultOpc = MultHi.getOpcode(); 206 207 // MultHi and MultLo must be generated by the same node, 208 if (MultLo.getNode() != MultNode) 209 return false; 210 211 // and it must be a multiplication. 212 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 213 return false; 214 215 // MultLo amd MultHi must be the first and second output of MultNode 216 // respectively. 217 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 218 return false; 219 220 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 221 // of the values of MultNode, in which case MultNode will be removed in later 222 // phases. 223 // If there exist users other than ADDENode or ADDCNode, this function returns 224 // here, which will result in MultNode being mapped to a single MULT 225 // instruction node rather than a pair of MULT and MADD instructions being 226 // produced. 227 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 228 return false; 229 230 SDValue Chain = CurDAG->getEntryNode(); 231 DebugLoc dl = ADDENode->getDebugLoc(); 232 233 // create MipsMAdd(u) node 234 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 235 236 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 237 MVT::Glue, 238 MultNode->getOperand(0),// Factor 0 239 MultNode->getOperand(1),// Factor 1 240 ADDCNode->getOperand(1),// Lo0 241 ADDENode->getOperand(1));// Hi0 242 243 // create CopyFromReg nodes 244 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 245 MAdd); 246 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 247 Mips::HI, MVT::i32, 248 CopyFromLo.getValue(2)); 249 250 // replace uses of adde and addc here 251 if (!SDValue(ADDCNode, 0).use_empty()) 252 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 253 254 if (!SDValue(ADDENode, 0).use_empty()) 255 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 256 257 return true; 258} 259 260// SelectMsub - 261// Transforms a subgraph in CurDAG if the following pattern is found: 262// (addc Lo0, multLo), (sube Hi0, multHi), 263// where, 264// multHi/Lo: product of multiplication 265// Lo0: initial value of Lo register 266// Hi0: initial value of Hi register 267// Return true if pattern matching was successful. 268static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 269 // SUBENode's second operand must be a flag output of an SUBC node in order 270 // for the matching to be successful. 271 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 272 273 if (SUBCNode->getOpcode() != ISD::SUBC) 274 return false; 275 276 SDValue MultHi = SUBENode->getOperand(1); 277 SDValue MultLo = SUBCNode->getOperand(1); 278 SDNode* MultNode = MultHi.getNode(); 279 unsigned MultOpc = MultHi.getOpcode(); 280 281 // MultHi and MultLo must be generated by the same node, 282 if (MultLo.getNode() != MultNode) 283 return false; 284 285 // and it must be a multiplication. 286 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 287 return false; 288 289 // MultLo amd MultHi must be the first and second output of MultNode 290 // respectively. 291 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 292 return false; 293 294 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 295 // of the values of MultNode, in which case MultNode will be removed in later 296 // phases. 297 // If there exist users other than SUBENode or SUBCNode, this function returns 298 // here, which will result in MultNode being mapped to a single MULT 299 // instruction node rather than a pair of MULT and MSUB instructions being 300 // produced. 301 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 302 return false; 303 304 SDValue Chain = CurDAG->getEntryNode(); 305 DebugLoc dl = SUBENode->getDebugLoc(); 306 307 // create MipsSub(u) node 308 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 309 310 SDValue MSub = CurDAG->getNode(MultOpc, dl, 311 MVT::Glue, 312 MultNode->getOperand(0),// Factor 0 313 MultNode->getOperand(1),// Factor 1 314 SUBCNode->getOperand(0),// Lo0 315 SUBENode->getOperand(0));// Hi0 316 317 // create CopyFromReg nodes 318 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 319 MSub); 320 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 321 Mips::HI, MVT::i32, 322 CopyFromLo.getValue(2)); 323 324 // replace uses of sube and subc here 325 if (!SDValue(SUBCNode, 0).use_empty()) 326 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 327 328 if (!SDValue(SUBENode, 0).use_empty()) 329 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 330 331 return true; 332} 333 334static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 335 TargetLowering::DAGCombinerInfo &DCI, 336 const MipsSubtarget* Subtarget) { 337 if (DCI.isBeforeLegalize()) 338 return SDValue(); 339 340 if (Subtarget->isMips32() && SelectMadd(N, &DAG)) 341 return SDValue(N, 0); 342 343 return SDValue(); 344} 345 346static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 347 TargetLowering::DAGCombinerInfo &DCI, 348 const MipsSubtarget* Subtarget) { 349 if (DCI.isBeforeLegalize()) 350 return SDValue(); 351 352 if (Subtarget->isMips32() && SelectMsub(N, &DAG)) 353 return SDValue(N, 0); 354 355 return SDValue(); 356} 357 358static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 359 TargetLowering::DAGCombinerInfo &DCI, 360 const MipsSubtarget* Subtarget) { 361 if (DCI.isBeforeLegalizeOps()) 362 return SDValue(); 363 364 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 365 MipsISD::DivRemU; 366 DebugLoc dl = N->getDebugLoc(); 367 368 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 369 N->getOperand(0), N->getOperand(1)); 370 SDValue InChain = DAG.getEntryNode(); 371 SDValue InGlue = DivRem; 372 373 // insert MFLO 374 if (N->hasAnyUseOfValue(0)) { 375 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32, 376 InGlue); 377 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 378 InChain = CopyFromLo.getValue(1); 379 InGlue = CopyFromLo.getValue(2); 380 } 381 382 // insert MFHI 383 if (N->hasAnyUseOfValue(1)) { 384 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 385 Mips::HI, MVT::i32, InGlue); 386 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 387 } 388 389 return SDValue(); 390} 391 392static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 393 switch (CC) { 394 default: llvm_unreachable("Unknown fp condition code!"); 395 case ISD::SETEQ: 396 case ISD::SETOEQ: return Mips::FCOND_OEQ; 397 case ISD::SETUNE: return Mips::FCOND_UNE; 398 case ISD::SETLT: 399 case ISD::SETOLT: return Mips::FCOND_OLT; 400 case ISD::SETGT: 401 case ISD::SETOGT: return Mips::FCOND_OGT; 402 case ISD::SETLE: 403 case ISD::SETOLE: return Mips::FCOND_OLE; 404 case ISD::SETGE: 405 case ISD::SETOGE: return Mips::FCOND_OGE; 406 case ISD::SETULT: return Mips::FCOND_ULT; 407 case ISD::SETULE: return Mips::FCOND_ULE; 408 case ISD::SETUGT: return Mips::FCOND_UGT; 409 case ISD::SETUGE: return Mips::FCOND_UGE; 410 case ISD::SETUO: return Mips::FCOND_UN; 411 case ISD::SETO: return Mips::FCOND_OR; 412 case ISD::SETNE: 413 case ISD::SETONE: return Mips::FCOND_ONE; 414 case ISD::SETUEQ: return Mips::FCOND_UEQ; 415 } 416} 417 418 419// Returns true if condition code has to be inverted. 420static bool InvertFPCondCode(Mips::CondCode CC) { 421 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 422 return false; 423 424 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 425 return true; 426 427 assert(false && "Illegal Condition Code"); 428 return false; 429} 430 431// Creates and returns an FPCmp node from a setcc node. 432// Returns Op if setcc is not a floating point comparison. 433static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 434 // must be a SETCC node 435 if (Op.getOpcode() != ISD::SETCC) 436 return Op; 437 438 SDValue LHS = Op.getOperand(0); 439 440 if (!LHS.getValueType().isFloatingPoint()) 441 return Op; 442 443 SDValue RHS = Op.getOperand(1); 444 DebugLoc dl = Op.getDebugLoc(); 445 446 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 447 // node if necessary. 448 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 449 450 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 451 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 452} 453 454// Creates and returns a CMovFPT/F node. 455static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 456 SDValue False, DebugLoc DL) { 457 bool invert = InvertFPCondCode((Mips::CondCode) 458 cast<ConstantSDNode>(Cond.getOperand(2)) 459 ->getSExtValue()); 460 461 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 462 True.getValueType(), True, False, Cond); 463} 464 465static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 466 TargetLowering::DAGCombinerInfo &DCI, 467 const MipsSubtarget* Subtarget) { 468 if (DCI.isBeforeLegalizeOps()) 469 return SDValue(); 470 471 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 472 473 if (Cond.getOpcode() != MipsISD::FPCmp) 474 return SDValue(); 475 476 SDValue True = DAG.getConstant(1, MVT::i32); 477 SDValue False = DAG.getConstant(0, MVT::i32); 478 479 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 480} 481 482SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 483 const { 484 SelectionDAG &DAG = DCI.DAG; 485 unsigned opc = N->getOpcode(); 486 487 switch (opc) { 488 default: break; 489 case ISD::ADDE: 490 return PerformADDECombine(N, DAG, DCI, Subtarget); 491 case ISD::SUBE: 492 return PerformSUBECombine(N, DAG, DCI, Subtarget); 493 case ISD::SDIVREM: 494 case ISD::UDIVREM: 495 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 496 case ISD::SETCC: 497 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 498 } 499 500 return SDValue(); 501} 502 503SDValue MipsTargetLowering:: 504LowerOperation(SDValue Op, SelectionDAG &DAG) const 505{ 506 switch (Op.getOpcode()) 507 { 508 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 509 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 510 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 511 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 512 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 513 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 514 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 515 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 516 case ISD::SELECT: return LowerSELECT(Op, DAG); 517 case ISD::VASTART: return LowerVASTART(Op, DAG); 518 } 519 return SDValue(); 520} 521 522//===----------------------------------------------------------------------===// 523// Lower helper functions 524//===----------------------------------------------------------------------===// 525 526// AddLiveIn - This helper function adds the specified physical register to the 527// MachineFunction as a live in value. It also creates a corresponding 528// virtual register for it. 529static unsigned 530AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 531{ 532 assert(RC->contains(PReg) && "Not the correct regclass!"); 533 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 534 MF.getRegInfo().addLiveIn(PReg, VReg); 535 return VReg; 536} 537 538// Get fp branch code (not opcode) from condition code. 539static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 540 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 541 return Mips::BRANCH_T; 542 543 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 544 return Mips::BRANCH_F; 545 546 return Mips::BRANCH_INVALID; 547} 548 549MachineBasicBlock * 550MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 551 MachineBasicBlock *BB) const { 552 // There is no need to expand CMov instructions if target has 553 // conditional moves. 554 if (Subtarget->hasCondMov()) 555 return BB; 556 557 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 558 bool isFPCmp = false; 559 DebugLoc dl = MI->getDebugLoc(); 560 unsigned Opc; 561 562 switch (MI->getOpcode()) { 563 default: assert(false && "Unexpected instr type to insert"); 564 case Mips::MOVT: 565 case Mips::MOVT_S: 566 case Mips::MOVT_D: 567 isFPCmp = true; 568 Opc = Mips::BC1F; 569 break; 570 case Mips::MOVF: 571 case Mips::MOVF_S: 572 case Mips::MOVF_D: 573 isFPCmp = true; 574 Opc = Mips::BC1T; 575 break; 576 case Mips::MOVZ_I: 577 case Mips::MOVZ_S: 578 case Mips::MOVZ_D: 579 Opc = Mips::BNE; 580 break; 581 case Mips::MOVN_I: 582 case Mips::MOVN_S: 583 case Mips::MOVN_D: 584 Opc = Mips::BEQ; 585 break; 586 } 587 588 // To "insert" a SELECT_CC instruction, we actually have to insert the 589 // diamond control-flow pattern. The incoming instruction knows the 590 // destination vreg to set, the condition code register to branch on, the 591 // true/false values to select between, and a branch opcode to use. 592 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 593 MachineFunction::iterator It = BB; 594 ++It; 595 596 // thisMBB: 597 // ... 598 // TrueVal = ... 599 // setcc r1, r2, r3 600 // bNE r1, r0, copy1MBB 601 // fallthrough --> copy0MBB 602 MachineBasicBlock *thisMBB = BB; 603 MachineFunction *F = BB->getParent(); 604 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 605 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 606 F->insert(It, copy0MBB); 607 F->insert(It, sinkMBB); 608 609 // Transfer the remainder of BB and its successor edges to sinkMBB. 610 sinkMBB->splice(sinkMBB->begin(), BB, 611 llvm::next(MachineBasicBlock::iterator(MI)), 612 BB->end()); 613 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 614 615 // Next, add the true and fallthrough blocks as its successors. 616 BB->addSuccessor(copy0MBB); 617 BB->addSuccessor(sinkMBB); 618 619 // Emit the right instruction according to the type of the operands compared 620 if (isFPCmp) 621 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 622 else 623 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 624 .addReg(Mips::ZERO).addMBB(sinkMBB); 625 626 627 // copy0MBB: 628 // %FalseValue = ... 629 // # fallthrough to sinkMBB 630 BB = copy0MBB; 631 632 // Update machine-CFG edges 633 BB->addSuccessor(sinkMBB); 634 635 // sinkMBB: 636 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 637 // ... 638 BB = sinkMBB; 639 640 if (isFPCmp) 641 BuildMI(*BB, BB->begin(), dl, 642 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 643 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 644 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 645 else 646 BuildMI(*BB, BB->begin(), dl, 647 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 648 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 649 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 650 651 MI->eraseFromParent(); // The pseudo instruction is gone now. 652 return BB; 653} 654 655//===----------------------------------------------------------------------===// 656// Misc Lower Operation implementation 657//===----------------------------------------------------------------------===// 658 659SDValue MipsTargetLowering:: 660LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const 661{ 662 if (!Subtarget->isMips1()) 663 return Op; 664 665 MachineFunction &MF = DAG.getMachineFunction(); 666 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass); 667 668 SDValue Chain = DAG.getEntryNode(); 669 DebugLoc dl = Op.getDebugLoc(); 670 SDValue Src = Op.getOperand(0); 671 672 // Set the condition register 673 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32); 674 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg); 675 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32); 676 677 SDValue Cst = DAG.getConstant(3, MVT::i32); 678 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst); 679 Cst = DAG.getConstant(2, MVT::i32); 680 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst); 681 682 SDValue InFlag(0, 0); 683 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag); 684 685 // Emit the round instruction and bit convert to integer 686 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32, 687 Src, CondReg.getValue(1)); 688 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc); 689 return BitCvt; 690} 691 692SDValue MipsTargetLowering:: 693LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 694{ 695 SDValue Chain = Op.getOperand(0); 696 SDValue Size = Op.getOperand(1); 697 DebugLoc dl = Op.getDebugLoc(); 698 699 // Get a reference from Mips stack pointer 700 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 701 702 // Subtract the dynamic size from the actual stack size to 703 // obtain the new stack size. 704 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 705 706 // The Sub result contains the new stack start address, so it 707 // must be placed in the stack pointer register. 708 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub); 709 710 // This node always has two return values: a new stack pointer 711 // value and a chain 712 SDValue Ops[2] = { Sub, Chain }; 713 return DAG.getMergeValues(Ops, 2, dl); 714} 715 716SDValue MipsTargetLowering:: 717LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 718{ 719 // The first operand is the chain, the second is the condition, the third is 720 // the block to branch to if the condition is true. 721 SDValue Chain = Op.getOperand(0); 722 SDValue Dest = Op.getOperand(2); 723 DebugLoc dl = Op.getDebugLoc(); 724 725 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 726 727 // Return if flag is not set by a floating point comparison. 728 if (CondRes.getOpcode() != MipsISD::FPCmp) 729 return Op; 730 731 SDValue CCNode = CondRes.getOperand(2); 732 Mips::CondCode CC = 733 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 734 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 735 736 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 737 Dest, CondRes); 738} 739 740SDValue MipsTargetLowering:: 741LowerSELECT(SDValue Op, SelectionDAG &DAG) const 742{ 743 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 744 745 // Return if flag is not set by a floating point comparison. 746 if (Cond.getOpcode() != MipsISD::FPCmp) 747 return Op; 748 749 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 750 Op.getDebugLoc()); 751} 752 753SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 754 SelectionDAG &DAG) const { 755 // FIXME there isn't actually debug info here 756 DebugLoc dl = Op.getDebugLoc(); 757 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 758 759 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 760 SDVTList VTs = DAG.getVTList(MVT::i32); 761 762 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 763 764 // %gp_rel relocation 765 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 766 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 767 MipsII::MO_GPREL); 768 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 769 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 770 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 771 } 772 // %hi/%lo relocation 773 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 774 MipsII::MO_ABS_HI); 775 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 776 MipsII::MO_ABS_LO); 777 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 778 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 779 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 780 } else { 781 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 782 MipsII::MO_GOT); 783 SDValue ResNode = DAG.getLoad(MVT::i32, dl, 784 DAG.getEntryNode(), GA, MachinePointerInfo(), 785 false, false, 0); 786 // On functions and global targets not internal linked only 787 // a load from got/GP is necessary for PIC to work. 788 if (!GV->hasInternalLinkage() && 789 (!GV->hasLocalLinkage() || isa<Function>(GV))) 790 return ResNode; 791 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 792 MipsII::MO_ABS_LO); 793 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 794 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); 795 } 796 797 llvm_unreachable("Dont know how to handle GlobalAddress"); 798 return SDValue(0,0); 799} 800 801SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 802 SelectionDAG &DAG) const { 803 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 804 // FIXME there isn't actually debug info here 805 DebugLoc dl = Op.getDebugLoc(); 806 807 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 808 // %hi/%lo relocation 809 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 810 MipsII::MO_ABS_HI); 811 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 812 MipsII::MO_ABS_LO); 813 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 814 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 815 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 816 } 817 818 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 819 MipsII::MO_GOT); 820 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 821 MipsII::MO_ABS_LO); 822 SDValue Load = DAG.getLoad(MVT::i32, dl, 823 DAG.getEntryNode(), BAGOTOffset, 824 MachinePointerInfo(), false, false, 0); 825 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 826 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 827} 828 829SDValue MipsTargetLowering:: 830LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 831{ 832 llvm_unreachable("TLS not implemented for MIPS."); 833 return SDValue(); // Not reached 834} 835 836SDValue MipsTargetLowering:: 837LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 838{ 839 SDValue ResNode; 840 SDValue HiPart; 841 // FIXME there isn't actually debug info here 842 DebugLoc dl = Op.getDebugLoc(); 843 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 844 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 845 846 EVT PtrVT = Op.getValueType(); 847 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 848 849 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 850 851 if (!IsPIC) { 852 SDValue Ops[] = { JTI }; 853 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 854 } else // Emit Load from Global Pointer 855 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 856 MachinePointerInfo(), 857 false, false, 0); 858 859 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 860 MipsII::MO_ABS_LO); 861 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 862 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 863 864 return ResNode; 865} 866 867SDValue MipsTargetLowering:: 868LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 869{ 870 SDValue ResNode; 871 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 872 const Constant *C = N->getConstVal(); 873 // FIXME there isn't actually debug info here 874 DebugLoc dl = Op.getDebugLoc(); 875 876 // gp_rel relocation 877 // FIXME: we should reference the constant pool using small data sections, 878 // but the asm printer currently doesn't support this feature without 879 // hacking it. This feature should come soon so we can uncomment the 880 // stuff below. 881 //if (IsInSmallSection(C->getType())) { 882 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 883 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 884 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 885 886 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 887 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 888 N->getOffset(), MipsII::MO_ABS_HI); 889 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 890 N->getOffset(), MipsII::MO_ABS_LO); 891 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 892 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 893 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 894 } else { 895 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 896 N->getOffset(), MipsII::MO_GOT); 897 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 898 CP, MachinePointerInfo::getConstantPool(), 899 false, false, 0); 900 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 901 N->getOffset(), MipsII::MO_ABS_LO); 902 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 903 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 904 } 905 906 return ResNode; 907} 908 909SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 910 MachineFunction &MF = DAG.getMachineFunction(); 911 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 912 913 DebugLoc dl = Op.getDebugLoc(); 914 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 915 getPointerTy()); 916 917 // vastart just stores the address of the VarArgsFrameIndex slot into the 918 // memory location argument. 919 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 920 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 921 MachinePointerInfo(SV), 922 false, false, 0); 923} 924 925//===----------------------------------------------------------------------===// 926// Calling Convention Implementation 927//===----------------------------------------------------------------------===// 928 929#include "MipsGenCallingConv.inc" 930 931//===----------------------------------------------------------------------===// 932// TODO: Implement a generic logic using tblgen that can support this. 933// Mips O32 ABI rules: 934// --- 935// i32 - Passed in A0, A1, A2, A3 and stack 936// f32 - Only passed in f32 registers if no int reg has been used yet to hold 937// an argument. Otherwise, passed in A1, A2, A3 and stack. 938// f64 - Only passed in two aliased f32 registers if no int reg has been used 939// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 940// not used, it must be shadowed. If only A3 is avaiable, shadow it and 941// go to stack. 942// 943// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 944//===----------------------------------------------------------------------===// 945 946static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 947 MVT LocVT, CCValAssign::LocInfo LocInfo, 948 ISD::ArgFlagsTy ArgFlags, CCState &State) { 949 950 static const unsigned IntRegsSize=4, FloatRegsSize=2; 951 952 static const unsigned IntRegs[] = { 953 Mips::A0, Mips::A1, Mips::A2, Mips::A3 954 }; 955 static const unsigned F32Regs[] = { 956 Mips::F12, Mips::F14 957 }; 958 static const unsigned F64Regs[] = { 959 Mips::D6, Mips::D7 960 }; 961 962 // Promote i8 and i16 963 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 964 LocVT = MVT::i32; 965 if (ArgFlags.isSExt()) 966 LocInfo = CCValAssign::SExt; 967 else if (ArgFlags.isZExt()) 968 LocInfo = CCValAssign::ZExt; 969 else 970 LocInfo = CCValAssign::AExt; 971 } 972 973 unsigned Reg; 974 975 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 976 // is true: function is vararg, argument is 3rd or higher, there is previous 977 // argument which is not f32 or f64. 978 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 979 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 980 unsigned OrigAlign = ArgFlags.getOrigAlign(); 981 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 982 983 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 984 Reg = State.AllocateReg(IntRegs, IntRegsSize); 985 // If this is the first part of an i64 arg, 986 // the allocated register must be either A0 or A2. 987 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 988 Reg = State.AllocateReg(IntRegs, IntRegsSize); 989 LocVT = MVT::i32; 990 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 991 // Allocate int register and shadow next int register. If first 992 // available register is Mips::A1 or Mips::A3, shadow it too. 993 Reg = State.AllocateReg(IntRegs, IntRegsSize); 994 if (Reg == Mips::A1 || Reg == Mips::A3) 995 Reg = State.AllocateReg(IntRegs, IntRegsSize); 996 State.AllocateReg(IntRegs, IntRegsSize); 997 LocVT = MVT::i32; 998 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 999 // we are guaranteed to find an available float register 1000 if (ValVT == MVT::f32) { 1001 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1002 // Shadow int register 1003 State.AllocateReg(IntRegs, IntRegsSize); 1004 } else { 1005 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1006 // Shadow int registers 1007 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1008 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1009 State.AllocateReg(IntRegs, IntRegsSize); 1010 State.AllocateReg(IntRegs, IntRegsSize); 1011 } 1012 } else 1013 llvm_unreachable("Cannot handle this ValVT."); 1014 1015 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1016 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1017 1018 if (!Reg) 1019 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1020 else 1021 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1022 1023 return false; // CC must always match 1024} 1025 1026//===----------------------------------------------------------------------===// 1027// Call Calling Convention Implementation 1028//===----------------------------------------------------------------------===// 1029 1030/// LowerCall - functions arguments are copied from virtual regs to 1031/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1032/// TODO: isTailCall. 1033SDValue 1034MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1035 CallingConv::ID CallConv, bool isVarArg, 1036 bool &isTailCall, 1037 const SmallVectorImpl<ISD::OutputArg> &Outs, 1038 const SmallVectorImpl<SDValue> &OutVals, 1039 const SmallVectorImpl<ISD::InputArg> &Ins, 1040 DebugLoc dl, SelectionDAG &DAG, 1041 SmallVectorImpl<SDValue> &InVals) const { 1042 // MIPs target does not yet support tail call optimization. 1043 isTailCall = false; 1044 1045 MachineFunction &MF = DAG.getMachineFunction(); 1046 MachineFrameInfo *MFI = MF.getFrameInfo(); 1047 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1048 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1049 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1050 1051 // Analyze operands of the call, assigning locations to each operand. 1052 SmallVector<CCValAssign, 16> ArgLocs; 1053 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1054 *DAG.getContext()); 1055 1056 if (Subtarget->isABI_O32()) 1057 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1058 else 1059 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1060 1061 // Get a count of how many bytes are to be pushed on the stack. 1062 unsigned NumBytes = CCInfo.getNextStackOffset(); 1063 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1064 1065 // With EABI is it possible to have 16 args on registers. 1066 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1067 SmallVector<SDValue, 8> MemOpChains; 1068 1069 MipsFI->setHasCall(); 1070 1071 // Create GP frame object if this is the first call. 1072 // SPOffset will be updated after call frame size is known. 1073 if (IsPIC && !MipsFI->getGPFI()) 1074 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1075 1076 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1077 1078 // Walk the register/memloc assignments, inserting copies/loads. 1079 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1080 SDValue Arg = OutVals[i]; 1081 CCValAssign &VA = ArgLocs[i]; 1082 1083 // Promote the value if needed. 1084 switch (VA.getLocInfo()) { 1085 default: llvm_unreachable("Unknown loc info!"); 1086 case CCValAssign::Full: 1087 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 1088 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 1089 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 1090 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 1091 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1092 Arg, DAG.getConstant(0, MVT::i32)); 1093 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1094 Arg, DAG.getConstant(1, MVT::i32)); 1095 if (!Subtarget->isLittle()) 1096 std::swap(Lo, Hi); 1097 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); 1098 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi)); 1099 continue; 1100 } 1101 } 1102 break; 1103 case CCValAssign::SExt: 1104 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1105 break; 1106 case CCValAssign::ZExt: 1107 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1108 break; 1109 case CCValAssign::AExt: 1110 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1111 break; 1112 } 1113 1114 // Arguments that can be passed on register must be kept at 1115 // RegsToPass vector 1116 if (VA.isRegLoc()) { 1117 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1118 continue; 1119 } 1120 1121 // Register can't get to this point... 1122 assert(VA.isMemLoc()); 1123 1124 // Create the frame index object for this incoming parameter 1125 // This guarantees that when allocating Local Area the firsts 1126 // 16 bytes which are alwayes reserved won't be overwritten 1127 // if O32 ABI is used. For EABI the first address is zero. 1128 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1129 VA.getLocMemOffset(), true); 1130 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 1131 1132 // emit ISD::STORE whichs stores the 1133 // parameter value to a stack Location 1134 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 1135 MachinePointerInfo(), 1136 false, false, 0)); 1137 } 1138 1139 // Transform all store nodes into one single node because all store 1140 // nodes are independent of each other. 1141 if (!MemOpChains.empty()) 1142 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1143 &MemOpChains[0], MemOpChains.size()); 1144 1145 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1146 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1147 // node so that legalize doesn't hack it. 1148 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 1149 bool LoadSymAddr = false; 1150 SDValue CalleeLo; 1151 1152 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1153 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 1154 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1155 getPointerTy(), 0,MipsII:: MO_GOT); 1156 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 1157 0, MipsII::MO_ABS_LO); 1158 } else { 1159 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 1160 getPointerTy(), 0, OpFlag); 1161 } 1162 1163 LoadSymAddr = true; 1164 } 1165 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1166 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 1167 getPointerTy(), OpFlag); 1168 LoadSymAddr = true; 1169 } 1170 1171 SDValue InFlag; 1172 1173 // Create nodes that load address of callee and copy it to T9 1174 if (IsPIC) { 1175 if (LoadSymAddr) { 1176 // Load callee address 1177 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee, 1178 MachinePointerInfo::getGOT(), 1179 false, false, 0); 1180 1181 // Use GOT+LO if callee has internal linkage. 1182 if (CalleeLo.getNode()) { 1183 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 1184 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 1185 } else 1186 Callee = LoadValue; 1187 1188 // Use chain output from LoadValue 1189 Chain = LoadValue.getValue(1); 1190 } 1191 1192 // copy to T9 1193 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 1194 InFlag = Chain.getValue(1); 1195 Callee = DAG.getRegister(Mips::T9, MVT::i32); 1196 } 1197 1198 // Build a sequence of copy-to-reg nodes chained together with token 1199 // chain and flag operands which copy the outgoing args into registers. 1200 // The InFlag in necessary since all emitted instructions must be 1201 // stuck together. 1202 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1203 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1204 RegsToPass[i].second, InFlag); 1205 InFlag = Chain.getValue(1); 1206 } 1207 1208 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 1209 // = Chain, Callee, Reg#1, Reg#2, ... 1210 // 1211 // Returns a chain & a flag for retval copy to use. 1212 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1213 SmallVector<SDValue, 8> Ops; 1214 Ops.push_back(Chain); 1215 Ops.push_back(Callee); 1216 1217 // Add argument registers to the end of the list so that they are 1218 // known live into the call. 1219 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1220 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1221 RegsToPass[i].second.getValueType())); 1222 1223 if (InFlag.getNode()) 1224 Ops.push_back(InFlag); 1225 1226 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 1227 InFlag = Chain.getValue(1); 1228 1229 // Create a stack location to hold GP when PIC is used. This stack 1230 // location is used on function prologue to save GP and also after all 1231 // emitted CALL's to restore GP. 1232 if (IsPIC) { 1233 // Function can have an arbitrary number of calls, so 1234 // hold the LastArgStackLoc with the biggest offset. 1235 int MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1236 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1237 1238 // For O32, a minimum of four words (16 bytes) of argument space is 1239 // allocated. 1240 if (Subtarget->isABI_O32()) 1241 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1242 1243 if (MaxCallFrameSize < (int)NextStackOffset) { 1244 MipsFI->setMaxCallFrameSize(NextStackOffset); 1245 1246 // $gp restore slot must be aligned. 1247 unsigned StackAlignment = TFL->getStackAlignment(); 1248 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1249 StackAlignment * StackAlignment; 1250 int GPFI = MipsFI->getGPFI(); 1251 MFI->setObjectOffset(GPFI, NextStackOffset); 1252 } 1253 } 1254 1255 // Extend range of indices of frame objects for outgoing arguments that were 1256 // created during this function call. Skip this step if no such objects were 1257 // created. 1258 if (LastFI) 1259 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 1260 1261 // Create the CALLSEQ_END node. 1262 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1263 DAG.getIntPtrConstant(0, true), InFlag); 1264 InFlag = Chain.getValue(1); 1265 1266 // Handle result values, copying them out of physregs into vregs that we 1267 // return. 1268 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 1269 Ins, dl, DAG, InVals); 1270} 1271 1272/// LowerCallResult - Lower the result values of a call into the 1273/// appropriate copies out of appropriate physical registers. 1274SDValue 1275MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1276 CallingConv::ID CallConv, bool isVarArg, 1277 const SmallVectorImpl<ISD::InputArg> &Ins, 1278 DebugLoc dl, SelectionDAG &DAG, 1279 SmallVectorImpl<SDValue> &InVals) const { 1280 1281 // Assign locations to each value returned by this call. 1282 SmallVector<CCValAssign, 16> RVLocs; 1283 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1284 RVLocs, *DAG.getContext()); 1285 1286 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 1287 1288 // Copy all of the result registers out of their specified physreg. 1289 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1290 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 1291 RVLocs[i].getValVT(), InFlag).getValue(1); 1292 InFlag = Chain.getValue(2); 1293 InVals.push_back(Chain.getValue(0)); 1294 } 1295 1296 return Chain; 1297} 1298 1299//===----------------------------------------------------------------------===// 1300// Formal Arguments Calling Convention Implementation 1301//===----------------------------------------------------------------------===// 1302 1303/// LowerFormalArguments - transform physical registers into virtual registers 1304/// and generate load operations for arguments places on the stack. 1305SDValue 1306MipsTargetLowering::LowerFormalArguments(SDValue Chain, 1307 CallingConv::ID CallConv, 1308 bool isVarArg, 1309 const SmallVectorImpl<ISD::InputArg> 1310 &Ins, 1311 DebugLoc dl, SelectionDAG &DAG, 1312 SmallVectorImpl<SDValue> &InVals) 1313 const { 1314 1315 MachineFunction &MF = DAG.getMachineFunction(); 1316 MachineFrameInfo *MFI = MF.getFrameInfo(); 1317 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1318 1319 MipsFI->setVarArgsFrameIndex(0); 1320 1321 // Used with vargs to acumulate store chains. 1322 std::vector<SDValue> OutChains; 1323 1324 // Assign locations to all of the incoming arguments. 1325 SmallVector<CCValAssign, 16> ArgLocs; 1326 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1327 ArgLocs, *DAG.getContext()); 1328 1329 if (Subtarget->isABI_O32()) 1330 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 1331 else 1332 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 1333 1334 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 1335 1336 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1337 CCValAssign &VA = ArgLocs[i]; 1338 1339 // Arguments stored on registers 1340 if (VA.isRegLoc()) { 1341 EVT RegVT = VA.getLocVT(); 1342 unsigned ArgReg = VA.getLocReg(); 1343 TargetRegisterClass *RC = 0; 1344 1345 if (RegVT == MVT::i32) 1346 RC = Mips::CPURegsRegisterClass; 1347 else if (RegVT == MVT::f32) 1348 RC = Mips::FGR32RegisterClass; 1349 else if (RegVT == MVT::f64) { 1350 if (!Subtarget->isSingleFloat()) 1351 RC = Mips::AFGR64RegisterClass; 1352 } else 1353 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 1354 1355 // Transform the arguments stored on 1356 // physical registers into virtual ones 1357 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 1358 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1359 1360 // If this is an 8 or 16-bit value, it has been passed promoted 1361 // to 32 bits. Insert an assert[sz]ext to capture this, then 1362 // truncate to the right size. 1363 if (VA.getLocInfo() != CCValAssign::Full) { 1364 unsigned Opcode = 0; 1365 if (VA.getLocInfo() == CCValAssign::SExt) 1366 Opcode = ISD::AssertSext; 1367 else if (VA.getLocInfo() == CCValAssign::ZExt) 1368 Opcode = ISD::AssertZext; 1369 if (Opcode) 1370 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 1371 DAG.getValueType(VA.getValVT())); 1372 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1373 } 1374 1375 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 1376 if (Subtarget->isABI_O32()) { 1377 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 1378 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 1379 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 1380 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 1381 VA.getLocReg()+1, RC); 1382 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 1383 if (!Subtarget->isLittle()) 1384 std::swap(ArgValue, ArgValue2); 1385 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 1386 ArgValue, ArgValue2); 1387 } 1388 } 1389 1390 InVals.push_back(ArgValue); 1391 } else { // VA.isRegLoc() 1392 1393 // sanity check 1394 assert(VA.isMemLoc()); 1395 1396 // The stack pointer offset is relative to the caller stack frame. 1397 // Since the real stack size is unknown here, a negative SPOffset 1398 // is used so there's a way to adjust these offsets when the stack 1399 // size get known (on EliminateFrameIndex). A dummy SPOffset is 1400 // used instead of a direct negative address (which is recorded to 1401 // be used on emitPrologue) to avoid mis-calc of the first stack 1402 // offset on PEI::calculateFrameObjectOffsets. 1403 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1404 VA.getLocMemOffset(), true); 1405 1406 // Create load nodes to retrieve arguments from the stack 1407 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 1408 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1409 MachinePointerInfo::getFixedStack(LastFI), 1410 false, false, 0)); 1411 } 1412 } 1413 1414 // The mips ABIs for returning structs by value requires that we copy 1415 // the sret argument into $v0 for the return. Save the argument into 1416 // a virtual register so that we can access it from the return points. 1417 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1418 unsigned Reg = MipsFI->getSRetReturnReg(); 1419 if (!Reg) { 1420 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 1421 MipsFI->setSRetReturnReg(Reg); 1422 } 1423 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1424 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1425 } 1426 1427 // To meet ABI, when VARARGS are passed on registers, the registers 1428 // must have their values written to the caller stack frame. If the last 1429 // argument was placed in the stack, there's no need to save any register. 1430 if (isVarArg && Subtarget->isABI_O32()) { 1431 // Record the frame index of the first variable argument 1432 // which is a value necessary to VASTART. 1433 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1434 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 1435 MipsFI->setVarArgsFrameIndex(LastFI); 1436 1437 const unsigned O32IntRegs[] = { 1438 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1439 }; 1440 1441 // Copy variable arguments passed in registers to stack. 1442 for (; NextStackOffset < 16; NextStackOffset += 4) { 1443 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 1444 unsigned Idx = NextStackOffset / 4; 1445 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 1446 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 1447 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 1448 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 1449 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 1450 MachinePointerInfo(), 1451 false, false, 0)); 1452 } 1453 } 1454 1455 MipsFI->setLastInArgFI(LastFI); 1456 1457 // All stores are grouped in one node to allow the matching between 1458 // the size of Ins and InVals. This only happens when on varg functions 1459 if (!OutChains.empty()) { 1460 OutChains.push_back(Chain); 1461 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1462 &OutChains[0], OutChains.size()); 1463 } 1464 1465 return Chain; 1466} 1467 1468//===----------------------------------------------------------------------===// 1469// Return Value Calling Convention Implementation 1470//===----------------------------------------------------------------------===// 1471 1472SDValue 1473MipsTargetLowering::LowerReturn(SDValue Chain, 1474 CallingConv::ID CallConv, bool isVarArg, 1475 const SmallVectorImpl<ISD::OutputArg> &Outs, 1476 const SmallVectorImpl<SDValue> &OutVals, 1477 DebugLoc dl, SelectionDAG &DAG) const { 1478 1479 // CCValAssign - represent the assignment of 1480 // the return value to a location 1481 SmallVector<CCValAssign, 16> RVLocs; 1482 1483 // CCState - Info about the registers and stack slot. 1484 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1485 RVLocs, *DAG.getContext()); 1486 1487 // Analize return values. 1488 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 1489 1490 // If this is the first return lowered for this function, add 1491 // the regs to the liveout set for the function. 1492 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1493 for (unsigned i = 0; i != RVLocs.size(); ++i) 1494 if (RVLocs[i].isRegLoc()) 1495 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1496 } 1497 1498 SDValue Flag; 1499 1500 // Copy the result values into the output registers. 1501 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1502 CCValAssign &VA = RVLocs[i]; 1503 assert(VA.isRegLoc() && "Can only return in registers!"); 1504 1505 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1506 OutVals[i], Flag); 1507 1508 // guarantee that all emitted copies are 1509 // stuck together, avoiding something bad 1510 Flag = Chain.getValue(1); 1511 } 1512 1513 // The mips ABIs for returning structs by value requires that we copy 1514 // the sret argument into $v0 for the return. We saved the argument into 1515 // a virtual register in the entry block, so now we copy the value out 1516 // and into $v0. 1517 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1518 MachineFunction &MF = DAG.getMachineFunction(); 1519 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1520 unsigned Reg = MipsFI->getSRetReturnReg(); 1521 1522 if (!Reg) 1523 llvm_unreachable("sret virtual register not created in the entry block"); 1524 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1525 1526 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 1527 Flag = Chain.getValue(1); 1528 } 1529 1530 // Return on Mips is always a "jr $ra" 1531 if (Flag.getNode()) 1532 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 1533 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 1534 else // Return Void 1535 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 1536 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 1537} 1538 1539//===----------------------------------------------------------------------===// 1540// Mips Inline Assembly Support 1541//===----------------------------------------------------------------------===// 1542 1543/// getConstraintType - Given a constraint letter, return the type of 1544/// constraint it is for this target. 1545MipsTargetLowering::ConstraintType MipsTargetLowering:: 1546getConstraintType(const std::string &Constraint) const 1547{ 1548 // Mips specific constrainy 1549 // GCC config/mips/constraints.md 1550 // 1551 // 'd' : An address register. Equivalent to r 1552 // unless generating MIPS16 code. 1553 // 'y' : Equivalent to r; retained for 1554 // backwards compatibility. 1555 // 'f' : Floating Point registers. 1556 if (Constraint.size() == 1) { 1557 switch (Constraint[0]) { 1558 default : break; 1559 case 'd': 1560 case 'y': 1561 case 'f': 1562 return C_RegisterClass; 1563 break; 1564 } 1565 } 1566 return TargetLowering::getConstraintType(Constraint); 1567} 1568 1569/// Examine constraint type and operand type and determine a weight value. 1570/// This object must already have been set up with the operand type 1571/// and the current alternative constraint selected. 1572TargetLowering::ConstraintWeight 1573MipsTargetLowering::getSingleConstraintMatchWeight( 1574 AsmOperandInfo &info, const char *constraint) const { 1575 ConstraintWeight weight = CW_Invalid; 1576 Value *CallOperandVal = info.CallOperandVal; 1577 // If we don't have a value, we can't do a match, 1578 // but allow it at the lowest weight. 1579 if (CallOperandVal == NULL) 1580 return CW_Default; 1581 const Type *type = CallOperandVal->getType(); 1582 // Look at the constraint type. 1583 switch (*constraint) { 1584 default: 1585 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1586 break; 1587 case 'd': 1588 case 'y': 1589 if (type->isIntegerTy()) 1590 weight = CW_Register; 1591 break; 1592 case 'f': 1593 if (type->isFloatTy()) 1594 weight = CW_Register; 1595 break; 1596 } 1597 return weight; 1598} 1599 1600/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1601/// return a list of registers that can be used to satisfy the constraint. 1602/// This should only be used for C_RegisterClass constraints. 1603std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 1604getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 1605{ 1606 if (Constraint.size() == 1) { 1607 switch (Constraint[0]) { 1608 case 'r': 1609 return std::make_pair(0U, Mips::CPURegsRegisterClass); 1610 case 'f': 1611 if (VT == MVT::f32) 1612 return std::make_pair(0U, Mips::FGR32RegisterClass); 1613 if (VT == MVT::f64) 1614 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1615 return std::make_pair(0U, Mips::AFGR64RegisterClass); 1616 } 1617 } 1618 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1619} 1620 1621/// Given a register class constraint, like 'r', if this corresponds directly 1622/// to an LLVM register class, return a register of 0 and the register class 1623/// pointer. 1624std::vector<unsigned> MipsTargetLowering:: 1625getRegClassForInlineAsmConstraint(const std::string &Constraint, 1626 EVT VT) const 1627{ 1628 if (Constraint.size() != 1) 1629 return std::vector<unsigned>(); 1630 1631 switch (Constraint[0]) { 1632 default : break; 1633 case 'r': 1634 // GCC Mips Constraint Letters 1635 case 'd': 1636 case 'y': 1637 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3, 1638 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, 1639 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, 1640 Mips::T8, 0); 1641 1642 case 'f': 1643 if (VT == MVT::f32) { 1644 if (Subtarget->isSingleFloat()) 1645 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5, 1646 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, 1647 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, 1648 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, 1649 Mips::F30, Mips::F31, 0); 1650 else 1651 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8, 1652 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26, 1653 Mips::F28, Mips::F30, 0); 1654 } 1655 1656 if (VT == MVT::f64) 1657 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1658 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4, 1659 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13, 1660 Mips::D14, Mips::D15, 0); 1661 } 1662 return std::vector<unsigned>(); 1663} 1664 1665bool 1666MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1667 // The Mips target isn't yet aware of offsets. 1668 return false; 1669} 1670 1671bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 1672 if (VT != MVT::f32 && VT != MVT::f64) 1673 return false; 1674 if (Imm.isNegZero()) 1675 return false; 1676 return Imm.isZero(); 1677} 1678