MipsISelLowering.cpp revision c7db5618f9e5e708b87d9ae6595b3fd510a2a0c0
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Bruno Cardoso Lopes and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16 17#include "MipsISelLowering.h" 18#include "MipsMachineFunction.h" 19#include "MipsTargetMachine.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/Function.h" 22#include "llvm/Intrinsics.h" 23#include "llvm/CallingConv.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/SelectionDAGISel.h" 29#include "llvm/CodeGen/SSARegMap.h" 30#include "llvm/CodeGen/ValueTypes.h" 31#include "llvm/Support/Debug.h" 32#include <queue> 33#include <set> 34 35using namespace llvm; 36 37const char *MipsTargetLowering:: 38getTargetNodeName(unsigned Opcode) const 39{ 40 switch (Opcode) 41 { 42 case MipsISD::JmpLink : return "MipsISD::JmpLink"; 43 case MipsISD::Hi : return "MipsISD::Hi"; 44 case MipsISD::Lo : return "MipsISD::Lo"; 45 case MipsISD::Ret : return "MipsISD::Ret"; 46 default : return NULL; 47 } 48} 49 50MipsTargetLowering:: 51MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) 52{ 53 // Mips does not have i1 type, so use i32 for 54 // setcc operations results (slt, sgt, ...). 55 setSetCCResultType(MVT::i32); 56 setSetCCResultContents(ZeroOrOneSetCCResult); 57 58 // Set up the register classes 59 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 60 61 // Custom 62 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 63 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 64 setOperationAction(ISD::RET, MVT::Other, Custom); 65 66 // Load extented operations for i1 types must be promoted 67 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); 68 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); 69 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 70 71 // Store operations for i1 types must be promoted 72 setStoreXAction(MVT::i1, Promote); 73 74 // Mips does not have these NodeTypes below. 75 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 76 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 77 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 78 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 79 setOperationAction(ISD::SELECT, MVT::i32, Expand); 80 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 81 82 // Mips not supported intrinsics. 83 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 84 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 85 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 86 87 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 88 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 89 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 90 setOperationAction(ISD::ROTL , MVT::i32, Expand); 91 setOperationAction(ISD::ROTR , MVT::i32, Expand); 92 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 93 94 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 95 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 96 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 97 98 // We don't have line number support yet. 99 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 100 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 101 setOperationAction(ISD::LABEL, MVT::Other, Expand); 102 103 // Use the default for now 104 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 105 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 106 107 setStackPointerRegisterToSaveRestore(Mips::SP); 108 computeRegisterProperties(); 109} 110 111 112SDOperand MipsTargetLowering:: 113LowerOperation(SDOperand Op, SelectionDAG &DAG) 114{ 115 switch (Op.getOpcode()) 116 { 117 case ISD::CALL: return LowerCALL(Op, DAG); 118 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 119 case ISD::RET: return LowerRET(Op, DAG); 120 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 121 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 122 } 123 return SDOperand(); 124} 125 126//===----------------------------------------------------------------------===// 127// Lower helper functions 128//===----------------------------------------------------------------------===// 129 130// AddLiveIn - This helper function adds the specified physical register to the 131// MachineFunction as a live in value. It also creates a corresponding 132// virtual register for it. 133static unsigned 134AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 135{ 136 assert(RC->contains(PReg) && "Not the correct regclass!"); 137 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 138 MF.addLiveIn(PReg, VReg); 139 return VReg; 140} 141 142//===----------------------------------------------------------------------===// 143// Misc Lower Operation implementation 144//===----------------------------------------------------------------------===// 145SDOperand MipsTargetLowering:: 146LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) 147{ 148 SDOperand ResNode; 149 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 150 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 151 bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_); 152 153 SDOperand HiPart; 154 if (!isPIC) { 155 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32); 156 SDOperand Ops[] = { GA }; 157 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); 158 } else // Emit Load from Global Pointer 159 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); 160 161 // On functions and global targets not internal linked only 162 // a load from got/GP is necessary for PIC to work. 163 if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV)))) 164 return HiPart; 165 166 SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); 167 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); 168 169 return ResNode; 170} 171 172SDOperand MipsTargetLowering:: 173LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) 174{ 175 assert(0 && "TLS not implemented for MIPS."); 176} 177 178//===----------------------------------------------------------------------===// 179// Calling Convention Implementation 180// 181// The lower operations present on calling convention works on this order: 182// LowerCALL (virt regs --> phys regs, virt regs --> stack) 183// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs) 184// LowerRET (virt regs --> phys regs) 185// LowerCALL (phys regs --> virt regs) 186// 187//===----------------------------------------------------------------------===// 188 189#include "MipsGenCallingConv.inc" 190 191//===----------------------------------------------------------------------===// 192// CALL Calling Convention Implementation 193//===----------------------------------------------------------------------===// 194 195/// Mips custom CALL implementation 196SDOperand MipsTargetLowering:: 197LowerCALL(SDOperand Op, SelectionDAG &DAG) 198{ 199 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 200 201 // By now, only CallingConv::C implemented 202 switch (CallingConv) 203 { 204 default: 205 assert(0 && "Unsupported calling convention"); 206 case CallingConv::Fast: 207 case CallingConv::C: 208 return LowerCCCCallTo(Op, DAG, CallingConv); 209 } 210} 211 212/// LowerCCCCallTo - functions arguments are copied from virtual 213/// regs to (physical regs)/(stack frame), CALLSEQ_START and 214/// CALLSEQ_END are emitted. 215/// TODO: isVarArg, isTailCall, sret. 216SDOperand MipsTargetLowering:: 217LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC) 218{ 219 MachineFunction &MF = DAG.getMachineFunction(); 220 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 221 222 SDOperand Chain = Op.getOperand(0); 223 SDOperand Callee = Op.getOperand(4); 224 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 225 226 MachineFrameInfo *MFI = MF.getFrameInfo(); 227 228 // Analyze operands of the call, assigning locations to each operand. 229 SmallVector<CCValAssign, 16> ArgLocs; 230 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 231 232 // To meet ABI, Mips must always allocate 16 bytes on 233 // the stack (even if less than 4 are used as arguments) 234 int VTsize = MVT::getSizeInBits(MVT::i32)/8; 235 MFI->CreateFixedObject(VTsize, (VTsize*3)); 236 237 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips); 238 239 // Get a count of how many bytes are to be pushed on the stack. 240 unsigned NumBytes = CCInfo.getNextStackOffset(); 241 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 242 getPointerTy())); 243 244 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; 245 SmallVector<SDOperand, 8> MemOpChains; 246 247 SDOperand StackPtr; 248 int LastStackLoc=0; 249 250 // Walk the register/memloc assignments, inserting copies/loads. 251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 252 CCValAssign &VA = ArgLocs[i]; 253 254 // Arguments start after the 5 first operands of ISD::CALL 255 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 256 257 // Promote the value if needed. 258 switch (VA.getLocInfo()) { 259 default: assert(0 && "Unknown loc info!"); 260 case CCValAssign::Full: break; 261 case CCValAssign::SExt: 262 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 263 break; 264 case CCValAssign::ZExt: 265 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 266 break; 267 case CCValAssign::AExt: 268 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 269 break; 270 } 271 272 // Arguments that can be passed on register must be kept at 273 // RegsToPass vector 274 if (VA.isRegLoc()) { 275 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 276 } else { 277 278 assert(VA.isMemLoc()); 279 280 if (StackPtr.Val == 0) 281 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 282 283 // Create the frame index object for this incoming parameter 284 // This guarantees that when allocating Local Area the firsts 285 // 16 bytes which are alwayes reserved won't be overwritten. 286 LastStackLoc = (16 + VA.getLocMemOffset()); 287 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, 288 LastStackLoc); 289 290 SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy()); 291 292 // emit ISD::STORE whichs stores the 293 // parameter value to a stack Location 294 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 295 } 296 } 297 298 // Transform all store nodes into one single node because 299 // all store nodes are independent of each other. 300 if (!MemOpChains.empty()) 301 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 302 &MemOpChains[0], MemOpChains.size()); 303 304 // Build a sequence of copy-to-reg nodes chained together with token 305 // chain and flag operands which copy the outgoing args into registers. 306 // The InFlag in necessary since all emited instructions must be 307 // stuck together. 308 SDOperand InFlag; 309 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 310 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, 311 RegsToPass[i].second, InFlag); 312 InFlag = Chain.getValue(1); 313 } 314 315 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 316 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 317 // node so that legalize doesn't hack it. 318 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 319 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 320 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 321 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 322 323 324 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 325 // = Chain, Callee, Reg#1, Reg#2, ... 326 // 327 // Returns a chain & a flag for retval copy to use. 328 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 329 SmallVector<SDOperand, 8> Ops; 330 Ops.push_back(Chain); 331 Ops.push_back(Callee); 332 333 // Add argument registers to the end of the list so that they are 334 // known live into the call. 335 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 336 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 337 RegsToPass[i].second.getValueType())); 338 339 if (InFlag.Val) 340 Ops.push_back(InFlag); 341 342 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); 343 InFlag = Chain.getValue(1); 344 345 // Create a stack location to hold GP when PIC is used. This stack 346 // location is used on function prologue to save GP and also after all 347 // emited CALL's to restore GP. 348 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 349 350 // Function can have an arbitrary number of calls, so 351 // hold the LastStackLoc with the biggest offset. 352 int FI; 353 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 354 if (LastStackLoc >= MipsFI->getGPStackOffset()) { 355 356 LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4); 357 // Create the frame index only once. SPOffset here can be anything 358 // (this will be fixed on processFunctionBeforeFrameFinalized) 359 if (MipsFI->getGPStackOffset() == -1) { 360 FI = MFI->CreateFixedObject(4, 0); 361 MipsFI->setGPFI(FI); 362 } 363 MipsFI->setGPStackOffset(LastStackLoc); 364 } 365 366 367 // Reload GP value. 368 FI = MipsFI->getGPFI(); 369 SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy()); 370 SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); 371 Chain = GPLoad.getValue(1); 372 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32), 373 GPLoad, SDOperand(0,0)); 374 } 375 376 // Create the CALLSEQ_END node. 377 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 378 Ops.clear(); 379 Ops.push_back(Chain); 380 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 381 Ops.push_back(InFlag); 382 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 383 InFlag = Chain.getValue(1); 384 385 // Handle result values, copying them out of physregs into vregs that we 386 // return. 387 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 388} 389 390/// LowerCallResult - Lower the result values of an ISD::CALL into the 391/// appropriate copies out of appropriate physical registers. This assumes that 392/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 393/// being lowered. Returns a SDNode with the same number of values as the 394/// ISD::CALL. 395SDNode *MipsTargetLowering:: 396LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, 397 unsigned CallingConv, SelectionDAG &DAG) { 398 399 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; 400 401 // Assign locations to each value returned by this call. 402 SmallVector<CCValAssign, 16> RVLocs; 403 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 404 405 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips); 406 SmallVector<SDOperand, 8> ResultVals; 407 408 // Copy all of the result registers out of their specified physreg. 409 for (unsigned i = 0; i != RVLocs.size(); ++i) { 410 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 411 RVLocs[i].getValVT(), InFlag).getValue(1); 412 InFlag = Chain.getValue(2); 413 ResultVals.push_back(Chain.getValue(0)); 414 } 415 416 ResultVals.push_back(Chain); 417 418 // Merge everything together with a MERGE_VALUES node. 419 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), 420 &ResultVals[0], ResultVals.size()).Val; 421} 422 423//===----------------------------------------------------------------------===// 424// FORMAL_ARGUMENTS Calling Convention Implementation 425//===----------------------------------------------------------------------===// 426 427/// Mips custom FORMAL_ARGUMENTS implementation 428SDOperand MipsTargetLowering:: 429LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) 430{ 431 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 432 switch(CC) 433 { 434 default: 435 assert(0 && "Unsupported calling convention"); 436 case CallingConv::C: 437 return LowerCCCArguments(Op, DAG); 438 } 439} 440 441/// LowerCCCArguments - transform physical registers into 442/// virtual registers and generate load operations for 443/// arguments places on the stack. 444/// TODO: isVarArg, sret 445SDOperand MipsTargetLowering:: 446LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) 447{ 448 SDOperand Root = Op.getOperand(0); 449 MachineFunction &MF = DAG.getMachineFunction(); 450 MachineFrameInfo *MFI = MF.getFrameInfo(); 451 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 452 453 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 454 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 455 456 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 457 458 // Assign locations to all of the incoming arguments. 459 SmallVector<CCValAssign, 16> ArgLocs; 460 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 461 462 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips); 463 SmallVector<SDOperand, 8> ArgValues; 464 SDOperand StackPtr; 465 466 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 467 468 CCValAssign &VA = ArgLocs[i]; 469 470 // Arguments stored on registers 471 if (VA.isRegLoc()) { 472 MVT::ValueType RegVT = VA.getLocVT(); 473 TargetRegisterClass *RC; 474 475 if (RegVT == MVT::i32) 476 RC = Mips::CPURegsRegisterClass; 477 else 478 assert(0 && "support only Mips::CPURegsRegisterClass"); 479 480 // Transform the arguments stored on 481 // physical registers into virtual ones 482 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 483 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 484 485 // If this is an 8 or 16-bit value, it is really passed promoted 486 // to 32 bits. Insert an assert[sz]ext to capture this, then 487 // truncate to the right size. 488 if (VA.getLocInfo() == CCValAssign::SExt) 489 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 490 DAG.getValueType(VA.getValVT())); 491 else if (VA.getLocInfo() == CCValAssign::ZExt) 492 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 493 DAG.getValueType(VA.getValVT())); 494 495 if (VA.getLocInfo() != CCValAssign::Full) 496 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 497 498 ArgValues.push_back(ArgValue); 499 500 // To meet ABI, when VARARGS are passed on registers, the registers 501 // must have their values written to the caller stack frame. 502 if (isVarArg) { 503 504 if (StackPtr.Val == 0) 505 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 506 507 // The stack pointer offset is relative to the caller stack frame. 508 // Since the real stack size is unknown here, a negative SPOffset 509 // is used so there's a way to adjust these offsets when the stack 510 // size get known (on EliminateFrameIndex). A dummy SPOffset is 511 // used instead of a direct negative address (which is recorded to 512 // be used on emitPrologue) to avoid mis-calc of the first stack 513 // offset on PEI::calculateFrameObjectOffsets. 514 // Arguments are always 32-bit. 515 int FI = MFI->CreateFixedObject(4, 0); 516 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4))); 517 SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 518 519 // emit ISD::STORE whichs stores the 520 // parameter value to a stack Location 521 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0)); 522 } 523 524 } else { 525 // sanity check 526 assert(VA.isMemLoc()); 527 528 // The stack pointer offset is relative to the caller stack frame. 529 // Since the real stack size is unknown here, a negative SPOffset 530 // is used so there's a way to adjust these offsets when the stack 531 // size get known (on EliminateFrameIndex). A dummy SPOffset is 532 // used instead of a direct negative address (which is recorded to 533 // be used on emitPrologue) to avoid mis-calc of the first stack 534 // offset on PEI::calculateFrameObjectOffsets. 535 // Arguments are always 32-bit. 536 int FI = MFI->CreateFixedObject(4, 0); 537 MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset()))); 538 539 // Create load nodes to retrieve arguments from the stack 540 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 541 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); 542 } 543 } 544 ArgValues.push_back(Root); 545 546 // Return the new list of results. 547 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 548 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); 549} 550 551//===----------------------------------------------------------------------===// 552// Return Value Calling Convention Implementation 553//===----------------------------------------------------------------------===// 554 555SDOperand MipsTargetLowering:: 556LowerRET(SDOperand Op, SelectionDAG &DAG) 557{ 558 // CCValAssign - represent the assignment of 559 // the return value to a location 560 SmallVector<CCValAssign, 16> RVLocs; 561 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 562 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 563 564 // CCState - Info about the registers and stack slot. 565 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 566 567 // Analize return values of ISD::RET 568 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips); 569 570 // If this is the first return lowered for this function, add 571 // the regs to the liveout set for the function. 572 if (DAG.getMachineFunction().liveout_empty()) { 573 for (unsigned i = 0; i != RVLocs.size(); ++i) 574 if (RVLocs[i].isRegLoc()) 575 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); 576 } 577 578 // The chain is always operand #0 579 SDOperand Chain = Op.getOperand(0); 580 SDOperand Flag; 581 582 // Copy the result values into the output registers. 583 for (unsigned i = 0; i != RVLocs.size(); ++i) { 584 CCValAssign &VA = RVLocs[i]; 585 assert(VA.isRegLoc() && "Can only return in registers!"); 586 587 // ISD::RET => ret chain, (regnum1,val1), ... 588 // So i*2+1 index only the regnums 589 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 590 591 // guarantee that all emitted copies are 592 // stuck together, avoiding something bad 593 Flag = Chain.getValue(1); 594 } 595 596 // Return on Mips is always a "jr $ra" 597 if (Flag.Val) 598 return DAG.getNode(MipsISD::Ret, MVT::Other, 599 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 600 else // Return Void 601 return DAG.getNode(MipsISD::Ret, MVT::Other, 602 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 603} 604 605//===----------------------------------------------------------------------===// 606// Mips Inline Assembly Support 607//===----------------------------------------------------------------------===// 608 609/// getConstraintType - Given a constraint letter, return the type of 610/// constraint it is for this target. 611MipsTargetLowering::ConstraintType MipsTargetLowering:: 612getConstraintType(const std::string &Constraint) const 613{ 614 if (Constraint.size() == 1) { 615 // Mips specific constrainy 616 // GCC config/mips/constraints.md 617 // 618 // 'd' : An address register. Equivalent to r 619 // unless generating MIPS16 code. 620 // 'y' : Equivalent to r; retained for 621 // backwards compatibility. 622 // 623 switch (Constraint[0]) { 624 default : break; 625 case 'd': 626 case 'y': 627 return C_RegisterClass; 628 break; 629 } 630 } 631 return TargetLowering::getConstraintType(Constraint); 632} 633 634std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 635getRegForInlineAsmConstraint(const std::string &Constraint, 636 MVT::ValueType VT) const 637{ 638 if (Constraint.size() == 1) { 639 switch (Constraint[0]) { 640 case 'r': 641 return std::make_pair(0U, Mips::CPURegsRegisterClass); 642 break; 643 } 644 } 645 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 646} 647 648std::vector<unsigned> MipsTargetLowering:: 649getRegClassForInlineAsmConstraint(const std::string &Constraint, 650 MVT::ValueType VT) const 651{ 652 if (Constraint.size() != 1) 653 return std::vector<unsigned>(); 654 655 switch (Constraint[0]) { 656 default : break; 657 case 'r': 658 // GCC Mips Constraint Letters 659 case 'd': 660 case 'y': 661 return make_vector<unsigned>(Mips::V0, Mips::V1, Mips::A0, 662 Mips::A1, Mips::A2, Mips::A3, 663 Mips::T0, Mips::T1, Mips::T2, 664 Mips::T3, Mips::T4, Mips::T5, 665 Mips::T6, Mips::T7, Mips::S0, 666 Mips::S1, Mips::S2, Mips::S3, 667 Mips::S4, Mips::S5, Mips::S6, 668 Mips::S7, Mips::T8, Mips::T9, 0); 669 break; 670 } 671 return std::vector<unsigned>(); 672} 673