MipsISelLowering.cpp revision e184fec550ea249d00e058cfba34ec6913951895 
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "mips-lower"
16#include "MipsISelLowering.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "MipsTargetObjectFile.h"
20#include "MipsSubtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalVariable.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/CallingConv.h"
26#include "InstPrinter/MipsInstPrinter.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36using namespace llvm;
37
38// If I is a shifted mask, set the size (Size) and the first bit of the
39// mask (Pos), and return true.
40// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
41static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
42  if (!isUInt<32>(I) || !isShiftedMask_32(I))
43     return false;
44
45  Size = CountPopulation_32(I);
46  Pos = CountTrailingZeros_32(I);
47  return true;
48}
49
50const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
51  switch (Opcode) {
52  case MipsISD::JmpLink:           return "MipsISD::JmpLink";
53  case MipsISD::Hi:                return "MipsISD::Hi";
54  case MipsISD::Lo:                return "MipsISD::Lo";
55  case MipsISD::GPRel:             return "MipsISD::GPRel";
56  case MipsISD::TlsGd:             return "MipsISD::TlsGd";
57  case MipsISD::TprelHi:           return "MipsISD::TprelHi";
58  case MipsISD::TprelLo:           return "MipsISD::TprelLo";
59  case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
60  case MipsISD::Ret:               return "MipsISD::Ret";
61  case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
62  case MipsISD::FPCmp:             return "MipsISD::FPCmp";
63  case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
64  case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
65  case MipsISD::FPRound:           return "MipsISD::FPRound";
66  case MipsISD::MAdd:              return "MipsISD::MAdd";
67  case MipsISD::MAddu:             return "MipsISD::MAddu";
68  case MipsISD::MSub:              return "MipsISD::MSub";
69  case MipsISD::MSubu:             return "MipsISD::MSubu";
70  case MipsISD::DivRem:            return "MipsISD::DivRem";
71  case MipsISD::DivRemU:           return "MipsISD::DivRemU";
72  case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
73  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
74  case MipsISD::WrapperPIC:        return "MipsISD::WrapperPIC";
75  case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
76  case MipsISD::Sync:              return "MipsISD::Sync";
77  case MipsISD::Ext:               return "MipsISD::Ext";
78  case MipsISD::Ins:               return "MipsISD::Ins";
79  default:                         return NULL;
80  }
81}
82
83MipsTargetLowering::
84MipsTargetLowering(MipsTargetMachine &TM)
85  : TargetLowering(TM, new MipsTargetObjectFile()),
86    Subtarget(&TM.getSubtarget<MipsSubtarget>()),
87    HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
88    IsO32(Subtarget->isABI_O32()) {
89
90  // Mips does not have i1 type, so use i32 for
91  // setcc operations results (slt, sgt, ...).
92  setBooleanContents(ZeroOrOneBooleanContent);
93  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
94
95  // Set up the register classes
96  addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
97  addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
98
99  if (HasMips64)
100    addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
101
102  // When dealing with single precision only, use libcalls
103  if (!Subtarget->isSingleFloat()) {
104    if (HasMips64)
105      addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
106    else
107      addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
108  }
109
110  // Load extented operations for i1 types must be promoted
111  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
112  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
113  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
114
115  // MIPS doesn't have extending float->double load/store
116  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
117  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
118
119  // Used by legalize types to correctly generate the setcc result.
120  // Without this, every float setcc comes with a AND/OR with the result,
121  // we don't want this, since the fpcmp result goes to a flag register,
122  // which is used implicitly by brcond and select operations.
123  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
124
125  // Mips Custom Operations
126  setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
127  setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
128  setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
129  setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
130  setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
131  setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
132  setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
133  setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
134  setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
135  setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
136  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Custom);
137  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
138
139  setOperationAction(ISD::SDIV, MVT::i32, Expand);
140  setOperationAction(ISD::SREM, MVT::i32, Expand);
141  setOperationAction(ISD::UDIV, MVT::i32, Expand);
142  setOperationAction(ISD::UREM, MVT::i32, Expand);
143  setOperationAction(ISD::SDIV, MVT::i64, Expand);
144  setOperationAction(ISD::SREM, MVT::i64, Expand);
145  setOperationAction(ISD::UDIV, MVT::i64, Expand);
146  setOperationAction(ISD::UREM, MVT::i64, Expand);
147
148  // Operations not directly supported by Mips.
149  setOperationAction(ISD::BR_JT,             MVT::Other, Expand);
150  setOperationAction(ISD::BR_CC,             MVT::Other, Expand);
151  setOperationAction(ISD::SELECT_CC,         MVT::Other, Expand);
152  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
153  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
154  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
155  setOperationAction(ISD::CTPOP,             MVT::i32,   Expand);
156  setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
157  setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
158  setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
159
160  if (!Subtarget->hasMips32r2())
161    setOperationAction(ISD::ROTR, MVT::i32,   Expand);
162
163  if (!Subtarget->hasMips64r2())
164    setOperationAction(ISD::ROTR, MVT::i64,   Expand);
165
166  setOperationAction(ISD::SHL_PARTS,         MVT::i32,   Expand);
167  setOperationAction(ISD::SRA_PARTS,         MVT::i32,   Expand);
168  setOperationAction(ISD::SRL_PARTS,         MVT::i32,   Expand);
169  setOperationAction(ISD::FCOPYSIGN,         MVT::f32,   Custom);
170  setOperationAction(ISD::FCOPYSIGN,         MVT::f64,   Custom);
171  setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
172  setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
173  setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
174  setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
175  setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
176  setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
177  setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
178  setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
179  setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
180  setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
181  setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
182  setOperationAction(ISD::FMA,               MVT::f32,   Expand);
183  setOperationAction(ISD::FMA,               MVT::f64,   Expand);
184
185  setOperationAction(ISD::EXCEPTIONADDR,     MVT::i32, Expand);
186  setOperationAction(ISD::EHSELECTION,       MVT::i32, Expand);
187
188  setOperationAction(ISD::VAARG,             MVT::Other, Expand);
189  setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
190  setOperationAction(ISD::VAEND,             MVT::Other, Expand);
191
192  // Use the default for now
193  setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
194  setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
195
196  setOperationAction(ISD::MEMBARRIER,        MVT::Other, Custom);
197  setOperationAction(ISD::ATOMIC_FENCE,      MVT::Other, Custom);
198
199  setOperationAction(ISD::ATOMIC_LOAD,       MVT::i32,    Expand);
200  setOperationAction(ISD::ATOMIC_STORE,      MVT::i32,    Expand);
201
202  setInsertFencesForAtomic(true);
203
204  if (Subtarget->isSingleFloat())
205    setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
206
207  if (!Subtarget->hasSEInReg()) {
208    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
209    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
210  }
211
212  if (!Subtarget->hasBitCount())
213    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
214
215  if (!Subtarget->hasSwap())
216    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
217
218  setTargetDAGCombine(ISD::ADDE);
219  setTargetDAGCombine(ISD::SUBE);
220  setTargetDAGCombine(ISD::SDIVREM);
221  setTargetDAGCombine(ISD::UDIVREM);
222  setTargetDAGCombine(ISD::SETCC);
223  setTargetDAGCombine(ISD::AND);
224  setTargetDAGCombine(ISD::OR);
225
226  setMinFunctionAlignment(2);
227
228  setStackPointerRegisterToSaveRestore(Mips::SP);
229  computeRegisterProperties();
230
231  setExceptionPointerRegister(Mips::A0);
232  setExceptionSelectorRegister(Mips::A1);
233}
234
235bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
236  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
237  return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16;
238}
239
240EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
241  return MVT::i32;
242}
243
244// SelectMadd -
245// Transforms a subgraph in CurDAG if the following pattern is found:
246//  (addc multLo, Lo0), (adde multHi, Hi0),
247// where,
248//  multHi/Lo: product of multiplication
249//  Lo0: initial value of Lo register
250//  Hi0: initial value of Hi register
251// Return true if pattern matching was successful.
252static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
253  // ADDENode's second operand must be a flag output of an ADDC node in order
254  // for the matching to be successful.
255  SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
256
257  if (ADDCNode->getOpcode() != ISD::ADDC)
258    return false;
259
260  SDValue MultHi = ADDENode->getOperand(0);
261  SDValue MultLo = ADDCNode->getOperand(0);
262  SDNode* MultNode = MultHi.getNode();
263  unsigned MultOpc = MultHi.getOpcode();
264
265  // MultHi and MultLo must be generated by the same node,
266  if (MultLo.getNode() != MultNode)
267    return false;
268
269  // and it must be a multiplication.
270  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
271    return false;
272
273  // MultLo amd MultHi must be the first and second output of MultNode
274  // respectively.
275  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
276    return false;
277
278  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
279  // of the values of MultNode, in which case MultNode will be removed in later
280  // phases.
281  // If there exist users other than ADDENode or ADDCNode, this function returns
282  // here, which will result in MultNode being mapped to a single MULT
283  // instruction node rather than a pair of MULT and MADD instructions being
284  // produced.
285  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
286    return false;
287
288  SDValue Chain = CurDAG->getEntryNode();
289  DebugLoc dl = ADDENode->getDebugLoc();
290
291  // create MipsMAdd(u) node
292  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
293
294  SDValue MAdd = CurDAG->getNode(MultOpc, dl,
295                                 MVT::Glue,
296                                 MultNode->getOperand(0),// Factor 0
297                                 MultNode->getOperand(1),// Factor 1
298                                 ADDCNode->getOperand(1),// Lo0
299                                 ADDENode->getOperand(1));// Hi0
300
301  // create CopyFromReg nodes
302  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
303                                              MAdd);
304  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
305                                              Mips::HI, MVT::i32,
306                                              CopyFromLo.getValue(2));
307
308  // replace uses of adde and addc here
309  if (!SDValue(ADDCNode, 0).use_empty())
310    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
311
312  if (!SDValue(ADDENode, 0).use_empty())
313    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
314
315  return true;
316}
317
318// SelectMsub -
319// Transforms a subgraph in CurDAG if the following pattern is found:
320//  (addc Lo0, multLo), (sube Hi0, multHi),
321// where,
322//  multHi/Lo: product of multiplication
323//  Lo0: initial value of Lo register
324//  Hi0: initial value of Hi register
325// Return true if pattern matching was successful.
326static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
327  // SUBENode's second operand must be a flag output of an SUBC node in order
328  // for the matching to be successful.
329  SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
330
331  if (SUBCNode->getOpcode() != ISD::SUBC)
332    return false;
333
334  SDValue MultHi = SUBENode->getOperand(1);
335  SDValue MultLo = SUBCNode->getOperand(1);
336  SDNode* MultNode = MultHi.getNode();
337  unsigned MultOpc = MultHi.getOpcode();
338
339  // MultHi and MultLo must be generated by the same node,
340  if (MultLo.getNode() != MultNode)
341    return false;
342
343  // and it must be a multiplication.
344  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
345    return false;
346
347  // MultLo amd MultHi must be the first and second output of MultNode
348  // respectively.
349  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
350    return false;
351
352  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
353  // of the values of MultNode, in which case MultNode will be removed in later
354  // phases.
355  // If there exist users other than SUBENode or SUBCNode, this function returns
356  // here, which will result in MultNode being mapped to a single MULT
357  // instruction node rather than a pair of MULT and MSUB instructions being
358  // produced.
359  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
360    return false;
361
362  SDValue Chain = CurDAG->getEntryNode();
363  DebugLoc dl = SUBENode->getDebugLoc();
364
365  // create MipsSub(u) node
366  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
367
368  SDValue MSub = CurDAG->getNode(MultOpc, dl,
369                                 MVT::Glue,
370                                 MultNode->getOperand(0),// Factor 0
371                                 MultNode->getOperand(1),// Factor 1
372                                 SUBCNode->getOperand(0),// Lo0
373                                 SUBENode->getOperand(0));// Hi0
374
375  // create CopyFromReg nodes
376  SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
377                                              MSub);
378  SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
379                                              Mips::HI, MVT::i32,
380                                              CopyFromLo.getValue(2));
381
382  // replace uses of sube and subc here
383  if (!SDValue(SUBCNode, 0).use_empty())
384    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
385
386  if (!SDValue(SUBENode, 0).use_empty())
387    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
388
389  return true;
390}
391
392static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
393                                  TargetLowering::DAGCombinerInfo &DCI,
394                                  const MipsSubtarget* Subtarget) {
395  if (DCI.isBeforeLegalize())
396    return SDValue();
397
398  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
399      SelectMadd(N, &DAG))
400    return SDValue(N, 0);
401
402  return SDValue();
403}
404
405static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
406                                  TargetLowering::DAGCombinerInfo &DCI,
407                                  const MipsSubtarget* Subtarget) {
408  if (DCI.isBeforeLegalize())
409    return SDValue();
410
411  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
412      SelectMsub(N, &DAG))
413    return SDValue(N, 0);
414
415  return SDValue();
416}
417
418static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
419                                    TargetLowering::DAGCombinerInfo &DCI,
420                                    const MipsSubtarget* Subtarget) {
421  if (DCI.isBeforeLegalizeOps())
422    return SDValue();
423
424  EVT Ty = N->getValueType(0);
425  unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
426  unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
427  unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
428                                                  MipsISD::DivRemU;
429  DebugLoc dl = N->getDebugLoc();
430
431  SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
432                               N->getOperand(0), N->getOperand(1));
433  SDValue InChain = DAG.getEntryNode();
434  SDValue InGlue = DivRem;
435
436  // insert MFLO
437  if (N->hasAnyUseOfValue(0)) {
438    SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
439                                            InGlue);
440    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
441    InChain = CopyFromLo.getValue(1);
442    InGlue = CopyFromLo.getValue(2);
443  }
444
445  // insert MFHI
446  if (N->hasAnyUseOfValue(1)) {
447    SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
448                                            HI, Ty, InGlue);
449    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
450  }
451
452  return SDValue();
453}
454
455static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
456  switch (CC) {
457  default: llvm_unreachable("Unknown fp condition code!");
458  case ISD::SETEQ:
459  case ISD::SETOEQ: return Mips::FCOND_OEQ;
460  case ISD::SETUNE: return Mips::FCOND_UNE;
461  case ISD::SETLT:
462  case ISD::SETOLT: return Mips::FCOND_OLT;
463  case ISD::SETGT:
464  case ISD::SETOGT: return Mips::FCOND_OGT;
465  case ISD::SETLE:
466  case ISD::SETOLE: return Mips::FCOND_OLE;
467  case ISD::SETGE:
468  case ISD::SETOGE: return Mips::FCOND_OGE;
469  case ISD::SETULT: return Mips::FCOND_ULT;
470  case ISD::SETULE: return Mips::FCOND_ULE;
471  case ISD::SETUGT: return Mips::FCOND_UGT;
472  case ISD::SETUGE: return Mips::FCOND_UGE;
473  case ISD::SETUO:  return Mips::FCOND_UN;
474  case ISD::SETO:   return Mips::FCOND_OR;
475  case ISD::SETNE:
476  case ISD::SETONE: return Mips::FCOND_ONE;
477  case ISD::SETUEQ: return Mips::FCOND_UEQ;
478  }
479}
480
481
482// Returns true if condition code has to be inverted.
483static bool InvertFPCondCode(Mips::CondCode CC) {
484  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
485    return false;
486
487  if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
488    return true;
489
490  assert(false && "Illegal Condition Code");
491  return false;
492}
493
494// Creates and returns an FPCmp node from a setcc node.
495// Returns Op if setcc is not a floating point comparison.
496static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
497  // must be a SETCC node
498  if (Op.getOpcode() != ISD::SETCC)
499    return Op;
500
501  SDValue LHS = Op.getOperand(0);
502
503  if (!LHS.getValueType().isFloatingPoint())
504    return Op;
505
506  SDValue RHS = Op.getOperand(1);
507  DebugLoc dl = Op.getDebugLoc();
508
509  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
510  // node if necessary.
511  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
512
513  return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
514                     DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
515}
516
517// Creates and returns a CMovFPT/F node.
518static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
519                            SDValue False, DebugLoc DL) {
520  bool invert = InvertFPCondCode((Mips::CondCode)
521                                 cast<ConstantSDNode>(Cond.getOperand(2))
522                                 ->getSExtValue());
523
524  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
525                     True.getValueType(), True, False, Cond);
526}
527
528static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
529                                   TargetLowering::DAGCombinerInfo &DCI,
530                                   const MipsSubtarget* Subtarget) {
531  if (DCI.isBeforeLegalizeOps())
532    return SDValue();
533
534  SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
535
536  if (Cond.getOpcode() != MipsISD::FPCmp)
537    return SDValue();
538
539  SDValue True  = DAG.getConstant(1, MVT::i32);
540  SDValue False = DAG.getConstant(0, MVT::i32);
541
542  return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
543}
544
545static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
546                                 TargetLowering::DAGCombinerInfo &DCI,
547                                 const MipsSubtarget* Subtarget) {
548  // Pattern match EXT.
549  //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
550  //  => ext $dst, $src, size, pos
551  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
552    return SDValue();
553
554  SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
555
556  // Op's first operand must be a shift right.
557  if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
558    return SDValue();
559
560  // The second operand of the shift must be an immediate.
561  uint64_t Pos;
562  ConstantSDNode *CN;
563  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
564    return SDValue();
565
566  Pos = CN->getZExtValue();
567
568  uint64_t SMPos, SMSize;
569  // Op's second operand must be a shifted mask.
570  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
571      !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
572    return SDValue();
573
574  // Return if the shifted mask does not start at bit 0 or the sum of its size
575  // and Pos exceeds the word's size.
576  if (SMPos != 0 || Pos + SMSize > 32)
577    return SDValue();
578
579  return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
580                     ShiftRight.getOperand(0),
581                     DAG.getConstant(Pos, MVT::i32),
582                     DAG.getConstant(SMSize, MVT::i32));
583}
584
585static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
586                                TargetLowering::DAGCombinerInfo &DCI,
587                                const MipsSubtarget* Subtarget) {
588  // Pattern match INS.
589  //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
590  //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
591  //  => ins $dst, $src, size, pos, $src1
592  if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
593    return SDValue();
594
595  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
596  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
597  ConstantSDNode *CN;
598
599  // See if Op's first operand matches (and $src1 , mask0).
600  if (And0.getOpcode() != ISD::AND)
601    return SDValue();
602
603  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
604      !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
605    return SDValue();
606
607  // See if Op's second operand matches (and (shl $src, pos), mask1).
608  if (And1.getOpcode() != ISD::AND)
609    return SDValue();
610
611  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
612      !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
613    return SDValue();
614
615  // The shift masks must have the same position and size.
616  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
617    return SDValue();
618
619  SDValue Shl = And1.getOperand(0);
620  if (Shl.getOpcode() != ISD::SHL)
621    return SDValue();
622
623  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
624    return SDValue();
625
626  unsigned Shamt = CN->getZExtValue();
627
628  // Return if the shift amount and the first bit position of mask are not the
629  // same.
630  if (Shamt != SMPos0)
631    return SDValue();
632
633  return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
634                     Shl.getOperand(0),
635                     DAG.getConstant(SMPos0, MVT::i32),
636                     DAG.getConstant(SMSize0, MVT::i32),
637                     And0.getOperand(0));
638}
639
640SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
641  const {
642  SelectionDAG &DAG = DCI.DAG;
643  unsigned opc = N->getOpcode();
644
645  switch (opc) {
646  default: break;
647  case ISD::ADDE:
648    return PerformADDECombine(N, DAG, DCI, Subtarget);
649  case ISD::SUBE:
650    return PerformSUBECombine(N, DAG, DCI, Subtarget);
651  case ISD::SDIVREM:
652  case ISD::UDIVREM:
653    return PerformDivRemCombine(N, DAG, DCI, Subtarget);
654  case ISD::SETCC:
655    return PerformSETCCCombine(N, DAG, DCI, Subtarget);
656  case ISD::AND:
657    return PerformANDCombine(N, DAG, DCI, Subtarget);
658  case ISD::OR:
659    return PerformORCombine(N, DAG, DCI, Subtarget);
660  }
661
662  return SDValue();
663}
664
665SDValue MipsTargetLowering::
666LowerOperation(SDValue Op, SelectionDAG &DAG) const
667{
668  switch (Op.getOpcode())
669  {
670    case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
671    case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
672    case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
673    case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
674    case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
675    case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
676    case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
677    case ISD::SELECT:             return LowerSELECT(Op, DAG);
678    case ISD::VASTART:            return LowerVASTART(Op, DAG);
679    case ISD::FCOPYSIGN:          return LowerFCOPYSIGN(Op, DAG);
680    case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG);
681    case ISD::MEMBARRIER:         return LowerMEMBARRIER(Op, DAG);
682    case ISD::ATOMIC_FENCE:       return LowerATOMIC_FENCE(Op, DAG);
683  }
684  return SDValue();
685}
686
687//===----------------------------------------------------------------------===//
688//  Lower helper functions
689//===----------------------------------------------------------------------===//
690
691// AddLiveIn - This helper function adds the specified physical register to the
692// MachineFunction as a live in value.  It also creates a corresponding
693// virtual register for it.
694static unsigned
695AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
696{
697  assert(RC->contains(PReg) && "Not the correct regclass!");
698  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
699  MF.getRegInfo().addLiveIn(PReg, VReg);
700  return VReg;
701}
702
703// Get fp branch code (not opcode) from condition code.
704static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
705  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
706    return Mips::BRANCH_T;
707
708  if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
709    return Mips::BRANCH_F;
710
711  return Mips::BRANCH_INVALID;
712}
713
714/*
715static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
716                                        DebugLoc dl,
717                                        const MipsSubtarget* Subtarget,
718                                        const TargetInstrInfo *TII,
719                                        bool isFPCmp, unsigned Opc) {
720  // There is no need to expand CMov instructions if target has
721  // conditional moves.
722  if (Subtarget->hasCondMov())
723    return BB;
724
725  // To "insert" a SELECT_CC instruction, we actually have to insert the
726  // diamond control-flow pattern.  The incoming instruction knows the
727  // destination vreg to set, the condition code register to branch on, the
728  // true/false values to select between, and a branch opcode to use.
729  const BasicBlock *LLVM_BB = BB->getBasicBlock();
730  MachineFunction::iterator It = BB;
731  ++It;
732
733  //  thisMBB:
734  //  ...
735  //   TrueVal = ...
736  //   setcc r1, r2, r3
737  //   bNE   r1, r0, copy1MBB
738  //   fallthrough --> copy0MBB
739  MachineBasicBlock *thisMBB  = BB;
740  MachineFunction *F = BB->getParent();
741  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
742  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
743  F->insert(It, copy0MBB);
744  F->insert(It, sinkMBB);
745
746  // Transfer the remainder of BB and its successor edges to sinkMBB.
747  sinkMBB->splice(sinkMBB->begin(), BB,
748                  llvm::next(MachineBasicBlock::iterator(MI)),
749                  BB->end());
750  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
751
752  // Next, add the true and fallthrough blocks as its successors.
753  BB->addSuccessor(copy0MBB);
754  BB->addSuccessor(sinkMBB);
755
756  // Emit the right instruction according to the type of the operands compared
757  if (isFPCmp)
758    BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
759  else
760    BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
761      .addReg(Mips::ZERO).addMBB(sinkMBB);
762
763  //  copy0MBB:
764  //   %FalseValue = ...
765  //   # fallthrough to sinkMBB
766  BB = copy0MBB;
767
768  // Update machine-CFG edges
769  BB->addSuccessor(sinkMBB);
770
771  //  sinkMBB:
772  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
773  //  ...
774  BB = sinkMBB;
775
776  if (isFPCmp)
777    BuildMI(*BB, BB->begin(), dl,
778            TII->get(Mips::PHI), MI->getOperand(0).getReg())
779      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
780      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
781  else
782    BuildMI(*BB, BB->begin(), dl,
783            TII->get(Mips::PHI), MI->getOperand(0).getReg())
784      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
785      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
786
787  MI->eraseFromParent();   // The pseudo instruction is gone now.
788  return BB;
789}
790*/
791MachineBasicBlock *
792MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
793                                                MachineBasicBlock *BB) const {
794  switch (MI->getOpcode()) {
795  default:
796    assert(false && "Unexpected instr type to insert");
797    return NULL;
798  case Mips::ATOMIC_LOAD_ADD_I8:
799  case Mips::ATOMIC_LOAD_ADD_I8_P8:
800    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
801  case Mips::ATOMIC_LOAD_ADD_I16:
802  case Mips::ATOMIC_LOAD_ADD_I16_P8:
803    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
804  case Mips::ATOMIC_LOAD_ADD_I32:
805  case Mips::ATOMIC_LOAD_ADD_I32_P8:
806    return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
807  case Mips::ATOMIC_LOAD_ADD_I64:
808  case Mips::ATOMIC_LOAD_ADD_I64_P8:
809    return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
810
811  case Mips::ATOMIC_LOAD_AND_I8:
812  case Mips::ATOMIC_LOAD_AND_I8_P8:
813    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
814  case Mips::ATOMIC_LOAD_AND_I16:
815  case Mips::ATOMIC_LOAD_AND_I16_P8:
816    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
817  case Mips::ATOMIC_LOAD_AND_I32:
818  case Mips::ATOMIC_LOAD_AND_I32_P8:
819    return EmitAtomicBinary(MI, BB, 4, Mips::AND);
820  case Mips::ATOMIC_LOAD_AND_I64:
821  case Mips::ATOMIC_LOAD_AND_I64_P8:
822    return EmitAtomicBinary(MI, BB, 48, Mips::AND64);
823
824  case Mips::ATOMIC_LOAD_OR_I8:
825  case Mips::ATOMIC_LOAD_OR_I8_P8:
826    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
827  case Mips::ATOMIC_LOAD_OR_I16:
828  case Mips::ATOMIC_LOAD_OR_I16_P8:
829    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
830  case Mips::ATOMIC_LOAD_OR_I32:
831  case Mips::ATOMIC_LOAD_OR_I32_P8:
832    return EmitAtomicBinary(MI, BB, 4, Mips::OR);
833  case Mips::ATOMIC_LOAD_OR_I64:
834  case Mips::ATOMIC_LOAD_OR_I64_P8:
835    return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
836
837  case Mips::ATOMIC_LOAD_XOR_I8:
838  case Mips::ATOMIC_LOAD_XOR_I8_P8:
839    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
840  case Mips::ATOMIC_LOAD_XOR_I16:
841  case Mips::ATOMIC_LOAD_XOR_I16_P8:
842    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
843  case Mips::ATOMIC_LOAD_XOR_I32:
844  case Mips::ATOMIC_LOAD_XOR_I32_P8:
845    return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
846  case Mips::ATOMIC_LOAD_XOR_I64:
847  case Mips::ATOMIC_LOAD_XOR_I64_P8:
848    return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
849
850  case Mips::ATOMIC_LOAD_NAND_I8:
851  case Mips::ATOMIC_LOAD_NAND_I8_P8:
852    return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
853  case Mips::ATOMIC_LOAD_NAND_I16:
854  case Mips::ATOMIC_LOAD_NAND_I16_P8:
855    return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
856  case Mips::ATOMIC_LOAD_NAND_I32:
857  case Mips::ATOMIC_LOAD_NAND_I32_P8:
858    return EmitAtomicBinary(MI, BB, 4, 0, true);
859  case Mips::ATOMIC_LOAD_NAND_I64:
860  case Mips::ATOMIC_LOAD_NAND_I64_P8:
861    return EmitAtomicBinary(MI, BB, 8, 0, true);
862
863  case Mips::ATOMIC_LOAD_SUB_I8:
864  case Mips::ATOMIC_LOAD_SUB_I8_P8:
865    return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
866  case Mips::ATOMIC_LOAD_SUB_I16:
867  case Mips::ATOMIC_LOAD_SUB_I16_P8:
868    return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
869  case Mips::ATOMIC_LOAD_SUB_I32:
870  case Mips::ATOMIC_LOAD_SUB_I32_P8:
871    return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
872  case Mips::ATOMIC_LOAD_SUB_I64:
873  case Mips::ATOMIC_LOAD_SUB_I64_P8:
874    return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
875
876  case Mips::ATOMIC_SWAP_I8:
877  case Mips::ATOMIC_SWAP_I8_P8:
878    return EmitAtomicBinaryPartword(MI, BB, 1, 0);
879  case Mips::ATOMIC_SWAP_I16:
880  case Mips::ATOMIC_SWAP_I16_P8:
881    return EmitAtomicBinaryPartword(MI, BB, 2, 0);
882  case Mips::ATOMIC_SWAP_I32:
883  case Mips::ATOMIC_SWAP_I32_P8:
884    return EmitAtomicBinary(MI, BB, 4, 0);
885  case Mips::ATOMIC_SWAP_I64:
886  case Mips::ATOMIC_SWAP_I64_P8:
887    return EmitAtomicBinary(MI, BB, 8, 0);
888
889  case Mips::ATOMIC_CMP_SWAP_I8:
890  case Mips::ATOMIC_CMP_SWAP_I8_P8:
891    return EmitAtomicCmpSwapPartword(MI, BB, 1);
892  case Mips::ATOMIC_CMP_SWAP_I16:
893  case Mips::ATOMIC_CMP_SWAP_I16_P8:
894    return EmitAtomicCmpSwapPartword(MI, BB, 2);
895  case Mips::ATOMIC_CMP_SWAP_I32:
896  case Mips::ATOMIC_CMP_SWAP_I32_P8:
897    return EmitAtomicCmpSwap(MI, BB, 4);
898  case Mips::ATOMIC_CMP_SWAP_I64:
899  case Mips::ATOMIC_CMP_SWAP_I64_P8:
900    return EmitAtomicCmpSwap(MI, BB, 8);
901  }
902}
903
904// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
905// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
906MachineBasicBlock *
907MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
908                                     unsigned Size, unsigned BinOpcode,
909                                     bool Nand) const {
910  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
911
912  MachineFunction *MF = BB->getParent();
913  MachineRegisterInfo &RegInfo = MF->getRegInfo();
914  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
915  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
916  DebugLoc dl = MI->getDebugLoc();
917  unsigned LL, SC, AND, NOR, ZERO, BEQ;
918
919  if (Size == 4) {
920    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
921    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
922    AND = Mips::AND;
923    NOR = Mips::NOR;
924    ZERO = Mips::ZERO;
925    BEQ = Mips::BEQ;
926  }
927  else {
928    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
929    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
930    AND = Mips::AND64;
931    NOR = Mips::NOR64;
932    ZERO = Mips::ZERO_64;
933    BEQ = Mips::BEQ64;
934  }
935
936  unsigned OldVal = MI->getOperand(0).getReg();
937  unsigned Ptr = MI->getOperand(1).getReg();
938  unsigned Incr = MI->getOperand(2).getReg();
939
940  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
941  unsigned AndRes = RegInfo.createVirtualRegister(RC);
942  unsigned Success = RegInfo.createVirtualRegister(RC);
943
944  // insert new blocks after the current block
945  const BasicBlock *LLVM_BB = BB->getBasicBlock();
946  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
947  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
948  MachineFunction::iterator It = BB;
949  ++It;
950  MF->insert(It, loopMBB);
951  MF->insert(It, exitMBB);
952
953  // Transfer the remainder of BB and its successor edges to exitMBB.
954  exitMBB->splice(exitMBB->begin(), BB,
955                  llvm::next(MachineBasicBlock::iterator(MI)),
956                  BB->end());
957  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
958
959  //  thisMBB:
960  //    ...
961  //    fallthrough --> loopMBB
962  BB->addSuccessor(loopMBB);
963  loopMBB->addSuccessor(loopMBB);
964  loopMBB->addSuccessor(exitMBB);
965
966  //  loopMBB:
967  //    ll oldval, 0(ptr)
968  //    <binop> storeval, oldval, incr
969  //    sc success, storeval, 0(ptr)
970  //    beq success, $0, loopMBB
971  BB = loopMBB;
972  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
973  if (Nand) {
974    //  and andres, oldval, incr
975    //  nor storeval, $0, andres
976    BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
977    BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
978  } else if (BinOpcode) {
979    //  <binop> storeval, oldval, incr
980    BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
981  } else {
982    StoreVal = Incr;
983  }
984  BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
985  BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
986
987  MI->eraseFromParent();   // The instruction is gone now.
988
989  return exitMBB;
990}
991
992MachineBasicBlock *
993MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
994                                             MachineBasicBlock *BB,
995                                             unsigned Size, unsigned BinOpcode,
996                                             bool Nand) const {
997  assert((Size == 1 || Size == 2) &&
998      "Unsupported size for EmitAtomicBinaryPartial.");
999
1000  MachineFunction *MF = BB->getParent();
1001  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1002  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1003  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1004  DebugLoc dl = MI->getDebugLoc();
1005  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1006  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1007
1008  unsigned Dest = MI->getOperand(0).getReg();
1009  unsigned Ptr = MI->getOperand(1).getReg();
1010  unsigned Incr = MI->getOperand(2).getReg();
1011
1012  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1013  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1014  unsigned Mask = RegInfo.createVirtualRegister(RC);
1015  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1016  unsigned NewVal = RegInfo.createVirtualRegister(RC);
1017  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1018  unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1019  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1020  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1021  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1022  unsigned AndRes = RegInfo.createVirtualRegister(RC);
1023  unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1024  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1025  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1026  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1027  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1028  unsigned SllRes = RegInfo.createVirtualRegister(RC);
1029  unsigned Success = RegInfo.createVirtualRegister(RC);
1030
1031  // insert new blocks after the current block
1032  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1033  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1034  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1035  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1036  MachineFunction::iterator It = BB;
1037  ++It;
1038  MF->insert(It, loopMBB);
1039  MF->insert(It, sinkMBB);
1040  MF->insert(It, exitMBB);
1041
1042  // Transfer the remainder of BB and its successor edges to exitMBB.
1043  exitMBB->splice(exitMBB->begin(), BB,
1044                  llvm::next(MachineBasicBlock::iterator(MI)),
1045                  BB->end());
1046  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1047
1048  BB->addSuccessor(loopMBB);
1049  loopMBB->addSuccessor(loopMBB);
1050  loopMBB->addSuccessor(sinkMBB);
1051  sinkMBB->addSuccessor(exitMBB);
1052
1053  //  thisMBB:
1054  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1055  //    and     alignedaddr,ptr,masklsb2
1056  //    andi    ptrlsb2,ptr,3
1057  //    sll     shiftamt,ptrlsb2,3
1058  //    ori     maskupper,$0,255               # 0xff
1059  //    sll     mask,maskupper,shiftamt
1060  //    nor     mask2,$0,mask
1061  //    sll     incr2,incr,shiftamt
1062
1063  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1064  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1065    .addReg(Mips::ZERO).addImm(-4);
1066  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1067    .addReg(Ptr).addReg(MaskLSB2);
1068  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1069  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1070  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1071    .addReg(Mips::ZERO).addImm(MaskImm);
1072  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1073    .addReg(ShiftAmt).addReg(MaskUpper);
1074  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1075  BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1076
1077
1078  // atomic.load.binop
1079  // loopMBB:
1080  //   ll      oldval,0(alignedaddr)
1081  //   binop   binopres,oldval,incr2
1082  //   and     newval,binopres,mask
1083  //   and     maskedoldval0,oldval,mask2
1084  //   or      storeval,maskedoldval0,newval
1085  //   sc      success,storeval,0(alignedaddr)
1086  //   beq     success,$0,loopMBB
1087
1088  // atomic.swap
1089  // loopMBB:
1090  //   ll      oldval,0(alignedaddr)
1091  //   and     newval,incr2,mask
1092  //   and     maskedoldval0,oldval,mask2
1093  //   or      storeval,maskedoldval0,newval
1094  //   sc      success,storeval,0(alignedaddr)
1095  //   beq     success,$0,loopMBB
1096
1097  BB = loopMBB;
1098  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1099  if (Nand) {
1100    //  and andres, oldval, incr2
1101    //  nor binopres, $0, andres
1102    //  and newval, binopres, mask
1103    BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1104    BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1105      .addReg(Mips::ZERO).addReg(AndRes);
1106    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1107  } else if (BinOpcode) {
1108    //  <binop> binopres, oldval, incr2
1109    //  and newval, binopres, mask
1110    BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1111    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1112  } else {// atomic.swap
1113    //  and newval, incr2, mask
1114    BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1115  }
1116
1117  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1118    .addReg(OldVal).addReg(Mask2);
1119  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1120    .addReg(MaskedOldVal0).addReg(NewVal);
1121  BuildMI(BB, dl, TII->get(SC), Success)
1122    .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1123  BuildMI(BB, dl, TII->get(Mips::BEQ))
1124    .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1125
1126  //  sinkMBB:
1127  //    and     maskedoldval1,oldval,mask
1128  //    srl     srlres,maskedoldval1,shiftamt
1129  //    sll     sllres,srlres,24
1130  //    sra     dest,sllres,24
1131  BB = sinkMBB;
1132  int64_t ShiftImm = (Size == 1) ? 24 : 16;
1133
1134  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1135    .addReg(OldVal).addReg(Mask);
1136  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1137      .addReg(ShiftAmt).addReg(MaskedOldVal1);
1138  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1139      .addReg(SrlRes).addImm(ShiftImm);
1140  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1141      .addReg(SllRes).addImm(ShiftImm);
1142
1143  MI->eraseFromParent();   // The instruction is gone now.
1144
1145  return exitMBB;
1146}
1147
1148MachineBasicBlock *
1149MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1150                                      MachineBasicBlock *BB,
1151                                      unsigned Size) const {
1152  assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1153
1154  MachineFunction *MF = BB->getParent();
1155  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1156  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1157  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1158  DebugLoc dl = MI->getDebugLoc();
1159  unsigned LL, SC, ZERO, BNE, BEQ;
1160
1161  if (Size == 4) {
1162    LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1163    SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1164    ZERO = Mips::ZERO;
1165    BNE = Mips::BNE;
1166    BEQ = Mips::BEQ;
1167  }
1168  else {
1169    LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1170    SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1171    ZERO = Mips::ZERO_64;
1172    BNE = Mips::BNE64;
1173    BEQ = Mips::BEQ64;
1174  }
1175
1176  unsigned Dest    = MI->getOperand(0).getReg();
1177  unsigned Ptr     = MI->getOperand(1).getReg();
1178  unsigned OldVal  = MI->getOperand(2).getReg();
1179  unsigned NewVal  = MI->getOperand(3).getReg();
1180
1181  unsigned Success = RegInfo.createVirtualRegister(RC);
1182
1183  // insert new blocks after the current block
1184  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1185  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1186  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1187  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1188  MachineFunction::iterator It = BB;
1189  ++It;
1190  MF->insert(It, loop1MBB);
1191  MF->insert(It, loop2MBB);
1192  MF->insert(It, exitMBB);
1193
1194  // Transfer the remainder of BB and its successor edges to exitMBB.
1195  exitMBB->splice(exitMBB->begin(), BB,
1196                  llvm::next(MachineBasicBlock::iterator(MI)),
1197                  BB->end());
1198  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1199
1200  //  thisMBB:
1201  //    ...
1202  //    fallthrough --> loop1MBB
1203  BB->addSuccessor(loop1MBB);
1204  loop1MBB->addSuccessor(exitMBB);
1205  loop1MBB->addSuccessor(loop2MBB);
1206  loop2MBB->addSuccessor(loop1MBB);
1207  loop2MBB->addSuccessor(exitMBB);
1208
1209  // loop1MBB:
1210  //   ll dest, 0(ptr)
1211  //   bne dest, oldval, exitMBB
1212  BB = loop1MBB;
1213  BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1214  BuildMI(BB, dl, TII->get(BNE))
1215    .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1216
1217  // loop2MBB:
1218  //   sc success, newval, 0(ptr)
1219  //   beq success, $0, loop1MBB
1220  BB = loop2MBB;
1221  BuildMI(BB, dl, TII->get(SC), Success)
1222    .addReg(NewVal).addReg(Ptr).addImm(0);
1223  BuildMI(BB, dl, TII->get(BEQ))
1224    .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1225
1226  MI->eraseFromParent();   // The instruction is gone now.
1227
1228  return exitMBB;
1229}
1230
1231MachineBasicBlock *
1232MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1233                                              MachineBasicBlock *BB,
1234                                              unsigned Size) const {
1235  assert((Size == 1 || Size == 2) &&
1236      "Unsupported size for EmitAtomicCmpSwapPartial.");
1237
1238  MachineFunction *MF = BB->getParent();
1239  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1240  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1241  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1242  DebugLoc dl = MI->getDebugLoc();
1243  unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1244  unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1245
1246  unsigned Dest    = MI->getOperand(0).getReg();
1247  unsigned Ptr     = MI->getOperand(1).getReg();
1248  unsigned CmpVal  = MI->getOperand(2).getReg();
1249  unsigned NewVal  = MI->getOperand(3).getReg();
1250
1251  unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1252  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1253  unsigned Mask = RegInfo.createVirtualRegister(RC);
1254  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1255  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1256  unsigned OldVal = RegInfo.createVirtualRegister(RC);
1257  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1258  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1259  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1260  unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1261  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1262  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1263  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1264  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1265  unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1266  unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1267  unsigned SllRes = RegInfo.createVirtualRegister(RC);
1268  unsigned Success = RegInfo.createVirtualRegister(RC);
1269
1270  // insert new blocks after the current block
1271  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1272  MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1273  MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1274  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1275  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1276  MachineFunction::iterator It = BB;
1277  ++It;
1278  MF->insert(It, loop1MBB);
1279  MF->insert(It, loop2MBB);
1280  MF->insert(It, sinkMBB);
1281  MF->insert(It, exitMBB);
1282
1283  // Transfer the remainder of BB and its successor edges to exitMBB.
1284  exitMBB->splice(exitMBB->begin(), BB,
1285                  llvm::next(MachineBasicBlock::iterator(MI)),
1286                  BB->end());
1287  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1288
1289  BB->addSuccessor(loop1MBB);
1290  loop1MBB->addSuccessor(sinkMBB);
1291  loop1MBB->addSuccessor(loop2MBB);
1292  loop2MBB->addSuccessor(loop1MBB);
1293  loop2MBB->addSuccessor(sinkMBB);
1294  sinkMBB->addSuccessor(exitMBB);
1295
1296  // FIXME: computation of newval2 can be moved to loop2MBB.
1297  //  thisMBB:
1298  //    addiu   masklsb2,$0,-4                # 0xfffffffc
1299  //    and     alignedaddr,ptr,masklsb2
1300  //    andi    ptrlsb2,ptr,3
1301  //    sll     shiftamt,ptrlsb2,3
1302  //    ori     maskupper,$0,255               # 0xff
1303  //    sll     mask,maskupper,shiftamt
1304  //    nor     mask2,$0,mask
1305  //    andi    maskedcmpval,cmpval,255
1306  //    sll     shiftedcmpval,maskedcmpval,shiftamt
1307  //    andi    maskednewval,newval,255
1308  //    sll     shiftednewval,maskednewval,shiftamt
1309  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1310  BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1311    .addReg(Mips::ZERO).addImm(-4);
1312  BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1313    .addReg(Ptr).addReg(MaskLSB2);
1314  BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1315  BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1316  BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1317    .addReg(Mips::ZERO).addImm(MaskImm);
1318  BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1319    .addReg(ShiftAmt).addReg(MaskUpper);
1320  BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1321  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1322    .addReg(CmpVal).addImm(MaskImm);
1323  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1324    .addReg(ShiftAmt).addReg(MaskedCmpVal);
1325  BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1326    .addReg(NewVal).addImm(MaskImm);
1327  BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1328    .addReg(ShiftAmt).addReg(MaskedNewVal);
1329
1330  //  loop1MBB:
1331  //    ll      oldval,0(alginedaddr)
1332  //    and     maskedoldval0,oldval,mask
1333  //    bne     maskedoldval0,shiftedcmpval,sinkMBB
1334  BB = loop1MBB;
1335  BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1336  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1337    .addReg(OldVal).addReg(Mask);
1338  BuildMI(BB, dl, TII->get(Mips::BNE))
1339    .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1340
1341  //  loop2MBB:
1342  //    and     maskedoldval1,oldval,mask2
1343  //    or      storeval,maskedoldval1,shiftednewval
1344  //    sc      success,storeval,0(alignedaddr)
1345  //    beq     success,$0,loop1MBB
1346  BB = loop2MBB;
1347  BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1348    .addReg(OldVal).addReg(Mask2);
1349  BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1350    .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1351  BuildMI(BB, dl, TII->get(SC), Success)
1352      .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1353  BuildMI(BB, dl, TII->get(Mips::BEQ))
1354      .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1355
1356  //  sinkMBB:
1357  //    srl     srlres,maskedoldval0,shiftamt
1358  //    sll     sllres,srlres,24
1359  //    sra     dest,sllres,24
1360  BB = sinkMBB;
1361  int64_t ShiftImm = (Size == 1) ? 24 : 16;
1362
1363  BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1364      .addReg(ShiftAmt).addReg(MaskedOldVal0);
1365  BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1366      .addReg(SrlRes).addImm(ShiftImm);
1367  BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1368      .addReg(SllRes).addImm(ShiftImm);
1369
1370  MI->eraseFromParent();   // The instruction is gone now.
1371
1372  return exitMBB;
1373}
1374
1375//===----------------------------------------------------------------------===//
1376//  Misc Lower Operation implementation
1377//===----------------------------------------------------------------------===//
1378SDValue MipsTargetLowering::
1379LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
1380{
1381  MachineFunction &MF = DAG.getMachineFunction();
1382  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1383  unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP;
1384
1385  assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
1386         cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1387         "Cannot lower if the alignment of the allocated space is larger than \
1388          that of the stack.");
1389
1390  SDValue Chain = Op.getOperand(0);
1391  SDValue Size = Op.getOperand(1);
1392  DebugLoc dl = Op.getDebugLoc();
1393
1394  // Get a reference from Mips stack pointer
1395  SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy());
1396
1397  // Subtract the dynamic size from the actual stack size to
1398  // obtain the new stack size.
1399  SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size);
1400
1401  // The Sub result contains the new stack start address, so it
1402  // must be placed in the stack pointer register.
1403  Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue());
1404
1405  // This node always has two return values: a new stack pointer
1406  // value and a chain
1407  SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other);
1408  SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1409  SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1410
1411  return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
1412}
1413
1414SDValue MipsTargetLowering::
1415LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1416{
1417  // The first operand is the chain, the second is the condition, the third is
1418  // the block to branch to if the condition is true.
1419  SDValue Chain = Op.getOperand(0);
1420  SDValue Dest = Op.getOperand(2);
1421  DebugLoc dl = Op.getDebugLoc();
1422
1423  SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1424
1425  // Return if flag is not set by a floating point comparison.
1426  if (CondRes.getOpcode() != MipsISD::FPCmp)
1427    return Op;
1428
1429  SDValue CCNode  = CondRes.getOperand(2);
1430  Mips::CondCode CC =
1431    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1432  SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1433
1434  return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1435                     Dest, CondRes);
1436}
1437
1438SDValue MipsTargetLowering::
1439LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1440{
1441  SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1442
1443  // Return if flag is not set by a floating point comparison.
1444  if (Cond.getOpcode() != MipsISD::FPCmp)
1445    return Op;
1446
1447  return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1448                      Op.getDebugLoc());
1449}
1450
1451SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1452                                               SelectionDAG &DAG) const {
1453  // FIXME there isn't actually debug info here
1454  DebugLoc dl = Op.getDebugLoc();
1455  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1456
1457  if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1458    SDVTList VTs = DAG.getVTList(MVT::i32);
1459
1460    MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
1461
1462    // %gp_rel relocation
1463    if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1464      SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1465                                              MipsII::MO_GPREL);
1466      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1467      SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1468      return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
1469    }
1470    // %hi/%lo relocation
1471    SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1472                                              MipsII::MO_ABS_HI);
1473    SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1474                                              MipsII::MO_ABS_LO);
1475    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1476    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1477    return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1478  }
1479
1480  EVT ValTy = Op.getValueType();
1481  bool HasGotOfst = (GV->hasInternalLinkage() ||
1482                     (GV->hasLocalLinkage() && !isa<Function>(GV)));
1483  unsigned GotFlag = IsN64 ?
1484                     (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
1485                     MipsII::MO_GOT;
1486  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
1487  GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA);
1488  SDValue ResNode = DAG.getLoad(ValTy, dl,
1489                                DAG.getEntryNode(), GA, MachinePointerInfo(),
1490                                false, false, false, 0);
1491  // On functions and global targets not internal linked only
1492  // a load from got/GP is necessary for PIC to work.
1493  if (!HasGotOfst)
1494    return ResNode;
1495  SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
1496                                            IsN64 ? MipsII::MO_GOT_OFST :
1497                                                    MipsII::MO_ABS_LO);
1498  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1499  return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
1500}
1501
1502SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1503                                              SelectionDAG &DAG) const {
1504  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1505  // FIXME there isn't actually debug info here
1506  DebugLoc dl = Op.getDebugLoc();
1507
1508  if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1509    // %hi/%lo relocation
1510    SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
1511                                       MipsII::MO_ABS_HI);
1512    SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
1513                                       MipsII::MO_ABS_LO);
1514    SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1515    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1516    return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1517  }
1518
1519  SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1520                                            MipsII::MO_GOT);
1521  BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset);
1522  SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1523                                           MipsII::MO_ABS_LO);
1524  SDValue Load = DAG.getLoad(MVT::i32, dl,
1525                             DAG.getEntryNode(), BAGOTOffset,
1526                             MachinePointerInfo(), false, false, false, 0);
1527  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
1528  return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1529}
1530
1531SDValue MipsTargetLowering::
1532LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1533{
1534  // If the relocation model is PIC, use the General Dynamic TLS Model,
1535  // otherwise use the Initial Exec or Local Exec TLS Model.
1536  // TODO: implement Local Dynamic TLS model
1537
1538  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1539  DebugLoc dl = GA->getDebugLoc();
1540  const GlobalValue *GV = GA->getGlobal();
1541  EVT PtrVT = getPointerTy();
1542
1543  if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1544    // General Dynamic TLS Model
1545    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
1546                                             0, MipsII::MO_TLSGD);
1547    SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
1548    SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
1549    SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
1550
1551    ArgListTy Args;
1552    ArgListEntry Entry;
1553    Entry.Node = Argument;
1554    Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
1555    Args.push_back(Entry);
1556    std::pair<SDValue, SDValue> CallResult =
1557        LowerCallTo(DAG.getEntryNode(),
1558                    (Type *) Type::getInt32Ty(*DAG.getContext()),
1559                    false, false, false, false, 0, CallingConv::C, false, true,
1560                    DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
1561                    dl);
1562
1563    return CallResult.first;
1564  }
1565
1566  SDValue Offset;
1567  if (GV->isDeclaration()) {
1568    // Initial Exec TLS Model
1569    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1570                                             MipsII::MO_GOTTPREL);
1571    Offset = DAG.getLoad(MVT::i32, dl,
1572                         DAG.getEntryNode(), TGA, MachinePointerInfo(),
1573                         false, false, false, 0);
1574  } else {
1575    // Local Exec TLS Model
1576    SDVTList VTs = DAG.getVTList(MVT::i32);
1577    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1578                                               MipsII::MO_TPREL_HI);
1579    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1580                                               MipsII::MO_TPREL_LO);
1581    SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
1582    SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
1583    Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1584  }
1585
1586  SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1587  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1588}
1589
1590SDValue MipsTargetLowering::
1591LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1592{
1593  SDValue ResNode;
1594  SDValue HiPart;
1595  // FIXME there isn't actually debug info here
1596  DebugLoc dl = Op.getDebugLoc();
1597  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1598  unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
1599
1600  EVT PtrVT = Op.getValueType();
1601  JumpTableSDNode *JT  = cast<JumpTableSDNode>(Op);
1602
1603  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
1604
1605  if (!IsPIC) {
1606    SDValue Ops[] = { JTI };
1607    HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
1608  } else {// Emit Load from Global Pointer
1609    JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI);
1610    HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
1611                         MachinePointerInfo(),
1612                         false, false, false, 0);
1613  }
1614
1615  SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1616                                         MipsII::MO_ABS_LO);
1617  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
1618  ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1619
1620  return ResNode;
1621}
1622
1623SDValue MipsTargetLowering::
1624LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1625{
1626  SDValue ResNode;
1627  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1628  const Constant *C = N->getConstVal();
1629  // FIXME there isn't actually debug info here
1630  DebugLoc dl = Op.getDebugLoc();
1631
1632  // gp_rel relocation
1633  // FIXME: we should reference the constant pool using small data sections,
1634  // but the asm printer currently doesn't support this feature without
1635  // hacking it. This feature should come soon so we can uncomment the
1636  // stuff below.
1637  //if (IsInSmallSection(C->getType())) {
1638  //  SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1639  //  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1640  //  ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1641
1642  if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1643    SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1644                                             N->getOffset(), MipsII::MO_ABS_HI);
1645    SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1646                                             N->getOffset(), MipsII::MO_ABS_LO);
1647    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1648    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1649    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1650  } else {
1651    SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1652                                           N->getOffset(), MipsII::MO_GOT);
1653    CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP);
1654    SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
1655                               CP, MachinePointerInfo::getConstantPool(),
1656                               false, false, false, 0);
1657    SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1658                                             N->getOffset(), MipsII::MO_ABS_LO);
1659    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1660    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1661  }
1662
1663  return ResNode;
1664}
1665
1666SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1667  MachineFunction &MF = DAG.getMachineFunction();
1668  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1669
1670  DebugLoc dl = Op.getDebugLoc();
1671  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1672                                 getPointerTy());
1673
1674  // vastart just stores the address of the VarArgsFrameIndex slot into the
1675  // memory location argument.
1676  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1677  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1678                      MachinePointerInfo(SV),
1679                      false, false, 0);
1680}
1681
1682static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
1683  // FIXME: Use ext/ins instructions if target architecture is Mips32r2.
1684  DebugLoc dl = Op.getDebugLoc();
1685  SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
1686  SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
1687  SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
1688                             DAG.getConstant(0x7fffffff, MVT::i32));
1689  SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
1690                             DAG.getConstant(0x80000000, MVT::i32));
1691  SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1692  return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
1693}
1694
1695static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
1696  // FIXME:
1697  //  Use ext/ins instructions if target architecture is Mips32r2.
1698  //  Eliminate redundant mfc1 and mtc1 instructions.
1699  unsigned LoIdx = 0, HiIdx = 1;
1700
1701  if (!isLittle)
1702    std::swap(LoIdx, HiIdx);
1703
1704  DebugLoc dl = Op.getDebugLoc();
1705  SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1706                              Op.getOperand(0),
1707                              DAG.getConstant(LoIdx, MVT::i32));
1708  SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1709                            Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
1710  SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1711                            Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
1712  SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
1713                             DAG.getConstant(0x7fffffff, MVT::i32));
1714  SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
1715                             DAG.getConstant(0x80000000, MVT::i32));
1716  SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1717
1718  if (!isLittle)
1719    std::swap(Word0, Word1);
1720
1721  return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
1722}
1723
1724SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
1725  const {
1726  EVT Ty = Op.getValueType();
1727
1728  assert(Ty == MVT::f32 || Ty == MVT::f64);
1729
1730  if (Ty == MVT::f32)
1731    return LowerFCOPYSIGN32(Op, DAG);
1732  else
1733    return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
1734}
1735
1736SDValue MipsTargetLowering::
1737LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1738  // check the depth
1739  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1740         "Frame address can only be determined for current frame.");
1741
1742  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1743  MFI->setFrameAddressIsTaken(true);
1744  EVT VT = Op.getValueType();
1745  DebugLoc dl = Op.getDebugLoc();
1746  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1747                                         IsN64 ? Mips::FP_64 : Mips::FP, VT);
1748  return FrameAddr;
1749}
1750
1751// TODO: set SType according to the desired memory barrier behavior.
1752SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op,
1753                                            SelectionDAG& DAG) const {
1754  unsigned SType = 0;
1755  DebugLoc dl = Op.getDebugLoc();
1756  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1757                     DAG.getConstant(SType, MVT::i32));
1758}
1759
1760SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1761                                              SelectionDAG& DAG) const {
1762  // FIXME: Need pseudo-fence for 'singlethread' fences
1763  // FIXME: Set SType for weaker fences where supported/appropriate.
1764  unsigned SType = 0;
1765  DebugLoc dl = Op.getDebugLoc();
1766  return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1767                     DAG.getConstant(SType, MVT::i32));
1768}
1769
1770//===----------------------------------------------------------------------===//
1771//                      Calling Convention Implementation
1772//===----------------------------------------------------------------------===//
1773
1774#include "MipsGenCallingConv.inc"
1775
1776//===----------------------------------------------------------------------===//
1777// TODO: Implement a generic logic using tblgen that can support this.
1778// Mips O32 ABI rules:
1779// ---
1780// i32 - Passed in A0, A1, A2, A3 and stack
1781// f32 - Only passed in f32 registers if no int reg has been used yet to hold
1782//       an argument. Otherwise, passed in A1, A2, A3 and stack.
1783// f64 - Only passed in two aliased f32 registers if no int reg has been used
1784//       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
1785//       not used, it must be shadowed. If only A3 is avaiable, shadow it and
1786//       go to stack.
1787//
1788//  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
1789//===----------------------------------------------------------------------===//
1790
1791static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
1792                       MVT LocVT, CCValAssign::LocInfo LocInfo,
1793                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
1794
1795  static const unsigned IntRegsSize=4, FloatRegsSize=2;
1796
1797  static const unsigned IntRegs[] = {
1798      Mips::A0, Mips::A1, Mips::A2, Mips::A3
1799  };
1800  static const unsigned F32Regs[] = {
1801      Mips::F12, Mips::F14
1802  };
1803  static const unsigned F64Regs[] = {
1804      Mips::D6, Mips::D7
1805  };
1806
1807  // ByVal Args
1808  if (ArgFlags.isByVal()) {
1809    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
1810                      1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
1811    unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
1812    for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
1813         r < std::min(IntRegsSize, NextReg); ++r)
1814      State.AllocateReg(IntRegs[r]);
1815    return false;
1816  }
1817
1818  // Promote i8 and i16
1819  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1820    LocVT = MVT::i32;
1821    if (ArgFlags.isSExt())
1822      LocInfo = CCValAssign::SExt;
1823    else if (ArgFlags.isZExt())
1824      LocInfo = CCValAssign::ZExt;
1825    else
1826      LocInfo = CCValAssign::AExt;
1827  }
1828
1829  unsigned Reg;
1830
1831  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
1832  // is true: function is vararg, argument is 3rd or higher, there is previous
1833  // argument which is not f32 or f64.
1834  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
1835      || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
1836  unsigned OrigAlign = ArgFlags.getOrigAlign();
1837  bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
1838
1839  if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
1840    Reg = State.AllocateReg(IntRegs, IntRegsSize);
1841    // If this is the first part of an i64 arg,
1842    // the allocated register must be either A0 or A2.
1843    if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
1844      Reg = State.AllocateReg(IntRegs, IntRegsSize);
1845    LocVT = MVT::i32;
1846  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
1847    // Allocate int register and shadow next int register. If first
1848    // available register is Mips::A1 or Mips::A3, shadow it too.
1849    Reg = State.AllocateReg(IntRegs, IntRegsSize);
1850    if (Reg == Mips::A1 || Reg == Mips::A3)
1851      Reg = State.AllocateReg(IntRegs, IntRegsSize);
1852    State.AllocateReg(IntRegs, IntRegsSize);
1853    LocVT = MVT::i32;
1854  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
1855    // we are guaranteed to find an available float register
1856    if (ValVT == MVT::f32) {
1857      Reg = State.AllocateReg(F32Regs, FloatRegsSize);
1858      // Shadow int register
1859      State.AllocateReg(IntRegs, IntRegsSize);
1860    } else {
1861      Reg = State.AllocateReg(F64Regs, FloatRegsSize);
1862      // Shadow int registers
1863      unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1864      if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1865        State.AllocateReg(IntRegs, IntRegsSize);
1866      State.AllocateReg(IntRegs, IntRegsSize);
1867    }
1868  } else
1869    llvm_unreachable("Cannot handle this ValVT.");
1870
1871  unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1872  unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
1873
1874  if (!Reg)
1875    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1876  else
1877    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1878
1879  return false; // CC must always match
1880}
1881
1882//===----------------------------------------------------------------------===//
1883//                  Call Calling Convention Implementation
1884//===----------------------------------------------------------------------===//
1885
1886static const unsigned O32IntRegsSize = 4;
1887
1888static const unsigned O32IntRegs[] = {
1889  Mips::A0, Mips::A1, Mips::A2, Mips::A3
1890};
1891
1892// Return next O32 integer argument register.
1893static unsigned getNextIntArgReg(unsigned Reg) {
1894  assert((Reg == Mips::A0) || (Reg == Mips::A2));
1895  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
1896}
1897
1898// Write ByVal Arg to arg registers and stack.
1899static void
1900WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
1901              SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
1902              SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
1903              MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
1904              const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
1905              MVT PtrType, bool isLittle) {
1906  unsigned LocMemOffset = VA.getLocMemOffset();
1907  unsigned Offset = 0;
1908  uint32_t RemainingSize = Flags.getByValSize();
1909  unsigned ByValAlign = Flags.getByValAlign();
1910
1911  // Copy the first 4 words of byval arg to registers A0 - A3.
1912  // FIXME: Use a stricter alignment if it enables better optimization in passes
1913  //        run later.
1914  for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
1915       Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
1916    SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1917                                  DAG.getConstant(Offset, MVT::i32));
1918    SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
1919                                  MachinePointerInfo(),
1920                                  false, false, false, std::min(ByValAlign,
1921                                                                (unsigned )4));
1922    MemOpChains.push_back(LoadVal.getValue(1));
1923    unsigned DstReg = O32IntRegs[LocMemOffset / 4];
1924    RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1925  }
1926
1927  if (RemainingSize == 0)
1928    return;
1929
1930  // If there still is a register available for argument passing, write the
1931  // remaining part of the structure to it using subword loads and shifts.
1932  if (LocMemOffset < 4 * 4) {
1933    assert(RemainingSize <= 3 && RemainingSize >= 1 &&
1934           "There must be one to three bytes remaining.");
1935    unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
1936    SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1937                                  DAG.getConstant(Offset, MVT::i32));
1938    unsigned Alignment = std::min(ByValAlign, (unsigned )4);
1939    SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
1940                                     LoadPtr, MachinePointerInfo(),
1941                                     MVT::getIntegerVT(LoadSize * 8), false,
1942                                     false, Alignment);
1943    MemOpChains.push_back(LoadVal.getValue(1));
1944
1945    // If target is big endian, shift it to the most significant half-word or
1946    // byte.
1947    if (!isLittle)
1948      LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
1949                            DAG.getConstant(32 - LoadSize * 8, MVT::i32));
1950
1951    Offset += LoadSize;
1952    RemainingSize -= LoadSize;
1953
1954    // Read second subword if necessary.
1955    if (RemainingSize != 0)  {
1956      assert(RemainingSize == 1 && "There must be one byte remaining.");
1957      LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1958                            DAG.getConstant(Offset, MVT::i32));
1959      unsigned Alignment = std::min(ByValAlign, (unsigned )2);
1960      SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
1961                                       LoadPtr, MachinePointerInfo(),
1962                                       MVT::i8, false, false, Alignment);
1963      MemOpChains.push_back(Subword.getValue(1));
1964      // Insert the loaded byte to LoadVal.
1965      // FIXME: Use INS if supported by target.
1966      unsigned ShiftAmt = isLittle ? 16 : 8;
1967      SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
1968                                  DAG.getConstant(ShiftAmt, MVT::i32));
1969      LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
1970    }
1971
1972    unsigned DstReg = O32IntRegs[LocMemOffset / 4];
1973    RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1974    return;
1975  }
1976
1977  // Create a fixed object on stack at offset LocMemOffset and copy
1978  // remaining part of byval arg to it using memcpy.
1979  SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1980                            DAG.getConstant(Offset, MVT::i32));
1981  LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
1982  SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
1983  ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
1984                             DAG.getConstant(RemainingSize, MVT::i32),
1985                             std::min(ByValAlign, (unsigned)4),
1986                             /*isVolatile=*/false, /*AlwaysInline=*/false,
1987                             MachinePointerInfo(0), MachinePointerInfo(0));
1988}
1989
1990/// LowerCall - functions arguments are copied from virtual regs to
1991/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1992/// TODO: isTailCall.
1993SDValue
1994MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
1995                              CallingConv::ID CallConv, bool isVarArg,
1996                              bool &isTailCall,
1997                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1998                              const SmallVectorImpl<SDValue> &OutVals,
1999                              const SmallVectorImpl<ISD::InputArg> &Ins,
2000                              DebugLoc dl, SelectionDAG &DAG,
2001                              SmallVectorImpl<SDValue> &InVals) const {
2002  // MIPs target does not yet support tail call optimization.
2003  isTailCall = false;
2004
2005  MachineFunction &MF = DAG.getMachineFunction();
2006  MachineFrameInfo *MFI = MF.getFrameInfo();
2007  const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2008  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2009  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2010
2011  // Analyze operands of the call, assigning locations to each operand.
2012  SmallVector<CCValAssign, 16> ArgLocs;
2013  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2014		 getTargetMachine(), ArgLocs, *DAG.getContext());
2015
2016  if (IsO32)
2017    CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
2018  else
2019    CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
2020
2021  // Get a count of how many bytes are to be pushed on the stack.
2022  unsigned NextStackOffset = CCInfo.getNextStackOffset();
2023
2024  // Chain is the output chain of the last Load/Store or CopyToReg node.
2025  // ByValChain is the output chain of the last Memcpy node created for copying
2026  // byval arguments to the stack.
2027  SDValue Chain, CallSeqStart, ByValChain;
2028  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2029  Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
2030  ByValChain = InChain;
2031
2032  // If this is the first call, create a stack frame object that points to
2033  // a location to which .cprestore saves $gp.
2034  if (IsO32 && IsPIC && !MipsFI->getGPFI())
2035    MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
2036
2037  // Get the frame index of the stack frame object that points to the location
2038  // of dynamically allocated area on the stack.
2039  int DynAllocFI = MipsFI->getDynAllocFI();
2040
2041  // Update size of the maximum argument space.
2042  // For O32, a minimum of four words (16 bytes) of argument space is
2043  // allocated.
2044  if (IsO32)
2045    NextStackOffset = std::max(NextStackOffset, (unsigned)16);
2046
2047  unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
2048
2049  if (MaxCallFrameSize < NextStackOffset) {
2050    MipsFI->setMaxCallFrameSize(NextStackOffset);
2051
2052    // Set the offsets relative to $sp of the $gp restore slot and dynamically
2053    // allocated stack space. These offsets must be aligned to a boundary
2054    // determined by the stack alignment of the ABI.
2055    unsigned StackAlignment = TFL->getStackAlignment();
2056    NextStackOffset = (NextStackOffset + StackAlignment - 1) /
2057                      StackAlignment * StackAlignment;
2058
2059    if (MipsFI->needGPSaveRestore())
2060      MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
2061
2062    MFI->setObjectOffset(DynAllocFI, NextStackOffset);
2063  }
2064
2065  // With EABI is it possible to have 16 args on registers.
2066  SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2067  SmallVector<SDValue, 8> MemOpChains;
2068
2069  int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
2070
2071  // Walk the register/memloc assignments, inserting copies/loads.
2072  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2073    SDValue Arg = OutVals[i];
2074    CCValAssign &VA = ArgLocs[i];
2075    MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2076
2077    // Promote the value if needed.
2078    switch (VA.getLocInfo()) {
2079    default: llvm_unreachable("Unknown loc info!");
2080    case CCValAssign::Full:
2081      if (VA.isRegLoc()) {
2082        if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2083            (ValVT == MVT::f64 && LocVT == MVT::i64))
2084          Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2085        else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2086          SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2087                                   Arg, DAG.getConstant(0, MVT::i32));
2088          SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2089                                   Arg, DAG.getConstant(1, MVT::i32));
2090          if (!Subtarget->isLittle())
2091            std::swap(Lo, Hi);
2092          unsigned LocRegLo = VA.getLocReg();
2093          unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2094          RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2095          RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2096          continue;
2097        }
2098      }
2099      break;
2100    case CCValAssign::SExt:
2101      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
2102      break;
2103    case CCValAssign::ZExt:
2104      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
2105      break;
2106    case CCValAssign::AExt:
2107      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
2108      break;
2109    }
2110
2111    // Arguments that can be passed on register must be kept at
2112    // RegsToPass vector
2113    if (VA.isRegLoc()) {
2114      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2115      continue;
2116    }
2117
2118    // Register can't get to this point...
2119    assert(VA.isMemLoc());
2120
2121    // ByVal Arg.
2122    ISD::ArgFlagsTy Flags = Outs[i].Flags;
2123    if (Flags.isByVal()) {
2124      assert(IsO32 &&
2125             "No support for ByVal args by ABIs other than O32 yet.");
2126      assert(Flags.getByValSize() &&
2127             "ByVal args of size 0 should have been ignored by front-end.");
2128      WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI,
2129                    DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle());
2130      continue;
2131    }
2132
2133    // Create the frame index object for this incoming parameter
2134    LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2135                                    VA.getLocMemOffset(), true);
2136    SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2137
2138    // emit ISD::STORE whichs stores the
2139    // parameter value to a stack Location
2140    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2141                                       MachinePointerInfo(),
2142                                       false, false, 0));
2143  }
2144
2145  // Extend range of indices of frame objects for outgoing arguments that were
2146  // created during this function call. Skip this step if no such objects were
2147  // created.
2148  if (LastFI)
2149    MipsFI->extendOutArgFIRange(FirstFI, LastFI);
2150
2151  // If a memcpy has been created to copy a byval arg to a stack, replace the
2152  // chain input of CallSeqStart with ByValChain.
2153  if (InChain != ByValChain)
2154    DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
2155                           NextStackOffsetVal);
2156
2157  // Transform all store nodes into one single node because all store
2158  // nodes are independent of each other.
2159  if (!MemOpChains.empty())
2160    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2161                        &MemOpChains[0], MemOpChains.size());
2162
2163  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2164  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2165  // node so that legalize doesn't hack it.
2166  unsigned char OpFlag;
2167  bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2168  bool LoadSymAddr = false;
2169  SDValue CalleeLo;
2170
2171  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2172    if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2173      OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2174      unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2175      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2176                                          OpFlag);
2177      CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
2178                                            0, LoFlag);
2179    } else {
2180      OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
2181      Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2182                                          getPointerTy(), 0, OpFlag);
2183    }
2184
2185    LoadSymAddr = true;
2186  }
2187  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2188    if (IsN64 || (!IsO32 && IsPIC))
2189      OpFlag = MipsII::MO_GOT_DISP;
2190    else if (!IsPIC) // !N64 && static
2191      OpFlag = MipsII::MO_NO_FLAG;
2192    else // O32 & PIC
2193      OpFlag = MipsII::MO_GOT_CALL;
2194    Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
2195                                         getPointerTy(), OpFlag);
2196    LoadSymAddr = true;
2197  }
2198
2199  SDValue InFlag;
2200
2201  // Create nodes that load address of callee and copy it to T9
2202  if (IsPICCall) {
2203    if (LoadSymAddr) {
2204      // Load callee address
2205      Callee = DAG.getNode(MipsISD::WrapperPIC, dl, getPointerTy(), Callee);
2206      SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2207                                      Callee, MachinePointerInfo::getGOT(),
2208                                      false, false, false, 0);
2209
2210      // Use GOT+LO if callee has internal linkage.
2211      if (CalleeLo.getNode()) {
2212        SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2213        Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
2214      } else
2215        Callee = LoadValue;
2216    }
2217
2218    // copy to T9
2219    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2220    Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
2221    InFlag = Chain.getValue(1);
2222    Callee = DAG.getRegister(T9Reg, getPointerTy());
2223  }
2224
2225  // Build a sequence of copy-to-reg nodes chained together with token
2226  // chain and flag operands which copy the outgoing args into registers.
2227  // The InFlag in necessary since all emitted instructions must be
2228  // stuck together.
2229  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2230    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2231                             RegsToPass[i].second, InFlag);
2232    InFlag = Chain.getValue(1);
2233  }
2234
2235  // MipsJmpLink = #chain, #target_address, #opt_in_flags...
2236  //             = Chain, Callee, Reg#1, Reg#2, ...
2237  //
2238  // Returns a chain & a flag for retval copy to use.
2239  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2240  SmallVector<SDValue, 8> Ops;
2241  Ops.push_back(Chain);
2242  Ops.push_back(Callee);
2243
2244  // Add argument registers to the end of the list so that they are
2245  // known live into the call.
2246  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2247    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2248                                  RegsToPass[i].second.getValueType()));
2249
2250  if (InFlag.getNode())
2251    Ops.push_back(InFlag);
2252
2253  Chain  = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
2254  InFlag = Chain.getValue(1);
2255
2256  // Create the CALLSEQ_END node.
2257  Chain = DAG.getCALLSEQ_END(Chain,
2258                             DAG.getIntPtrConstant(NextStackOffset, true),
2259                             DAG.getIntPtrConstant(0, true), InFlag);
2260  InFlag = Chain.getValue(1);
2261
2262  // Handle result values, copying them out of physregs into vregs that we
2263  // return.
2264  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2265                         Ins, dl, DAG, InVals);
2266}
2267
2268/// LowerCallResult - Lower the result values of a call into the
2269/// appropriate copies out of appropriate physical registers.
2270SDValue
2271MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2272                                    CallingConv::ID CallConv, bool isVarArg,
2273                                    const SmallVectorImpl<ISD::InputArg> &Ins,
2274                                    DebugLoc dl, SelectionDAG &DAG,
2275                                    SmallVectorImpl<SDValue> &InVals) const {
2276  // Assign locations to each value returned by this call.
2277  SmallVector<CCValAssign, 16> RVLocs;
2278  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2279		 getTargetMachine(), RVLocs, *DAG.getContext());
2280
2281  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
2282
2283  // Copy all of the result registers out of their specified physreg.
2284  for (unsigned i = 0; i != RVLocs.size(); ++i) {
2285    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
2286                               RVLocs[i].getValVT(), InFlag).getValue(1);
2287    InFlag = Chain.getValue(2);
2288    InVals.push_back(Chain.getValue(0));
2289  }
2290
2291  return Chain;
2292}
2293
2294//===----------------------------------------------------------------------===//
2295//             Formal Arguments Calling Convention Implementation
2296//===----------------------------------------------------------------------===//
2297static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2298                         std::vector<SDValue>& OutChains,
2299                         SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
2300                         const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) {
2301  unsigned LocMem = VA.getLocMemOffset();
2302  unsigned FirstWord = LocMem / 4;
2303
2304  // copy register A0 - A3 to frame object
2305  for (unsigned i = 0; i < NumWords; ++i) {
2306    unsigned CurWord = FirstWord + i;
2307    if (CurWord >= O32IntRegsSize)
2308      break;
2309
2310    unsigned SrcReg = O32IntRegs[CurWord];
2311    unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
2312    SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2313                                   DAG.getConstant(i * 4, MVT::i32));
2314    SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
2315                                 StorePtr, MachinePointerInfo(), false,
2316                                 false, 0);
2317    OutChains.push_back(Store);
2318  }
2319}
2320
2321/// LowerFormalArguments - transform physical registers into virtual registers
2322/// and generate load operations for arguments places on the stack.
2323SDValue
2324MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2325                                         CallingConv::ID CallConv,
2326                                         bool isVarArg,
2327                                         const SmallVectorImpl<ISD::InputArg>
2328                                         &Ins,
2329                                         DebugLoc dl, SelectionDAG &DAG,
2330                                         SmallVectorImpl<SDValue> &InVals)
2331                                          const {
2332  MachineFunction &MF = DAG.getMachineFunction();
2333  MachineFrameInfo *MFI = MF.getFrameInfo();
2334  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2335
2336  MipsFI->setVarArgsFrameIndex(0);
2337
2338  // Used with vargs to acumulate store chains.
2339  std::vector<SDValue> OutChains;
2340
2341  // Assign locations to all of the incoming arguments.
2342  SmallVector<CCValAssign, 16> ArgLocs;
2343  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2344		 getTargetMachine(), ArgLocs, *DAG.getContext());
2345
2346  if (IsO32)
2347    CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
2348  else
2349    CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
2350
2351  int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
2352
2353  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2354    CCValAssign &VA = ArgLocs[i];
2355    EVT ValVT = VA.getValVT();
2356
2357    // Arguments stored on registers
2358    if (VA.isRegLoc()) {
2359      EVT RegVT = VA.getLocVT();
2360      unsigned ArgReg = VA.getLocReg();
2361      TargetRegisterClass *RC = 0;
2362
2363      if (RegVT == MVT::i32)
2364        RC = Mips::CPURegsRegisterClass;
2365      else if (RegVT == MVT::i64)
2366        RC = Mips::CPU64RegsRegisterClass;
2367      else if (RegVT == MVT::f32)
2368        RC = Mips::FGR32RegisterClass;
2369      else if (RegVT == MVT::f64)
2370        RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass;
2371      else
2372        llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2373
2374      // Transform the arguments stored on
2375      // physical registers into virtual ones
2376      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2377      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2378
2379      // If this is an 8 or 16-bit value, it has been passed promoted
2380      // to 32 bits.  Insert an assert[sz]ext to capture this, then
2381      // truncate to the right size.
2382      if (VA.getLocInfo() != CCValAssign::Full) {
2383        unsigned Opcode = 0;
2384        if (VA.getLocInfo() == CCValAssign::SExt)
2385          Opcode = ISD::AssertSext;
2386        else if (VA.getLocInfo() == CCValAssign::ZExt)
2387          Opcode = ISD::AssertZext;
2388        if (Opcode)
2389          ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
2390                                 DAG.getValueType(ValVT));
2391        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
2392      }
2393
2394      // Handle floating point arguments passed in integer registers.
2395      if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2396          (RegVT == MVT::i64 && ValVT == MVT::f64))
2397        ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
2398      else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2399        unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
2400                                  getNextIntArgReg(ArgReg), RC);
2401        SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
2402        if (!Subtarget->isLittle())
2403          std::swap(ArgValue, ArgValue2);
2404        ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2405                               ArgValue, ArgValue2);
2406      }
2407
2408      InVals.push_back(ArgValue);
2409    } else { // VA.isRegLoc()
2410
2411      // sanity check
2412      assert(VA.isMemLoc());
2413
2414      ISD::ArgFlagsTy Flags = Ins[i].Flags;
2415
2416      if (Flags.isByVal()) {
2417        assert(IsO32 &&
2418               "No support for ByVal args by ABIs other than O32 yet.");
2419        assert(Flags.getByValSize() &&
2420               "ByVal args of size 0 should have been ignored by front-end.");
2421        unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2422        LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2423                                        true);
2424        SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2425        InVals.push_back(FIN);
2426        ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags);
2427
2428        continue;
2429      }
2430
2431      // The stack pointer offset is relative to the caller stack frame.
2432      LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2433                                      VA.getLocMemOffset(), true);
2434
2435      // Create load nodes to retrieve arguments from the stack
2436      SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2437      InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
2438                                   MachinePointerInfo::getFixedStack(LastFI),
2439                                   false, false, false, 0));
2440    }
2441  }
2442
2443  // The mips ABIs for returning structs by value requires that we copy
2444  // the sret argument into $v0 for the return. Save the argument into
2445  // a virtual register so that we can access it from the return points.
2446  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2447    unsigned Reg = MipsFI->getSRetReturnReg();
2448    if (!Reg) {
2449      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
2450      MipsFI->setSRetReturnReg(Reg);
2451    }
2452    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2453    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2454  }
2455
2456  if (isVarArg && IsO32) {
2457    // Record the frame index of the first variable argument
2458    // which is a value necessary to VASTART.
2459    unsigned NextStackOffset = CCInfo.getNextStackOffset();
2460    assert(NextStackOffset % 4 == 0 &&
2461           "NextStackOffset must be aligned to 4-byte boundaries.");
2462    LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2463    MipsFI->setVarArgsFrameIndex(LastFI);
2464
2465    // If NextStackOffset is smaller than o32's 16-byte reserved argument area,
2466    // copy the integer registers that have not been used for argument passing
2467    // to the caller's stack frame.
2468    for (; NextStackOffset < 16; NextStackOffset += 4) {
2469      TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
2470      unsigned Idx = NextStackOffset / 4;
2471      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
2472      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
2473      LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2474      SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2475      OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
2476                                       MachinePointerInfo(),
2477                                       false, false, 0));
2478    }
2479  }
2480
2481  MipsFI->setLastInArgFI(LastFI);
2482
2483  // All stores are grouped in one node to allow the matching between
2484  // the size of Ins and InVals. This only happens when on varg functions
2485  if (!OutChains.empty()) {
2486    OutChains.push_back(Chain);
2487    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2488                        &OutChains[0], OutChains.size());
2489  }
2490
2491  return Chain;
2492}
2493
2494//===----------------------------------------------------------------------===//
2495//               Return Value Calling Convention Implementation
2496//===----------------------------------------------------------------------===//
2497
2498SDValue
2499MipsTargetLowering::LowerReturn(SDValue Chain,
2500                                CallingConv::ID CallConv, bool isVarArg,
2501                                const SmallVectorImpl<ISD::OutputArg> &Outs,
2502                                const SmallVectorImpl<SDValue> &OutVals,
2503                                DebugLoc dl, SelectionDAG &DAG) const {
2504
2505  // CCValAssign - represent the assignment of
2506  // the return value to a location
2507  SmallVector<CCValAssign, 16> RVLocs;
2508
2509  // CCState - Info about the registers and stack slot.
2510  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2511		 getTargetMachine(), RVLocs, *DAG.getContext());
2512
2513  // Analize return values.
2514  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
2515
2516  // If this is the first return lowered for this function, add
2517  // the regs to the liveout set for the function.
2518  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2519    for (unsigned i = 0; i != RVLocs.size(); ++i)
2520      if (RVLocs[i].isRegLoc())
2521        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2522  }
2523
2524  SDValue Flag;
2525
2526  // Copy the result values into the output registers.
2527  for (unsigned i = 0; i != RVLocs.size(); ++i) {
2528    CCValAssign &VA = RVLocs[i];
2529    assert(VA.isRegLoc() && "Can only return in registers!");
2530
2531    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2532                             OutVals[i], Flag);
2533
2534    // guarantee that all emitted copies are
2535    // stuck together, avoiding something bad
2536    Flag = Chain.getValue(1);
2537  }
2538
2539  // The mips ABIs for returning structs by value requires that we copy
2540  // the sret argument into $v0 for the return. We saved the argument into
2541  // a virtual register in the entry block, so now we copy the value out
2542  // and into $v0.
2543  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2544    MachineFunction &MF      = DAG.getMachineFunction();
2545    MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2546    unsigned Reg = MipsFI->getSRetReturnReg();
2547
2548    if (!Reg)
2549      llvm_unreachable("sret virtual register not created in the entry block");
2550    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2551
2552    Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
2553    Flag = Chain.getValue(1);
2554  }
2555
2556  // Return on Mips is always a "jr $ra"
2557  if (Flag.getNode())
2558    return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2559                       Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
2560  else // Return Void
2561    return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2562                       Chain, DAG.getRegister(Mips::RA, MVT::i32));
2563}
2564
2565//===----------------------------------------------------------------------===//
2566//                           Mips Inline Assembly Support
2567//===----------------------------------------------------------------------===//
2568
2569/// getConstraintType - Given a constraint letter, return the type of
2570/// constraint it is for this target.
2571MipsTargetLowering::ConstraintType MipsTargetLowering::
2572getConstraintType(const std::string &Constraint) const
2573{
2574  // Mips specific constrainy
2575  // GCC config/mips/constraints.md
2576  //
2577  // 'd' : An address register. Equivalent to r
2578  //       unless generating MIPS16 code.
2579  // 'y' : Equivalent to r; retained for
2580  //       backwards compatibility.
2581  // 'f' : Floating Point registers.
2582  if (Constraint.size() == 1) {
2583    switch (Constraint[0]) {
2584      default : break;
2585      case 'd':
2586      case 'y':
2587      case 'f':
2588        return C_RegisterClass;
2589        break;
2590    }
2591  }
2592  return TargetLowering::getConstraintType(Constraint);
2593}
2594
2595/// Examine constraint type and operand type and determine a weight value.
2596/// This object must already have been set up with the operand type
2597/// and the current alternative constraint selected.
2598TargetLowering::ConstraintWeight
2599MipsTargetLowering::getSingleConstraintMatchWeight(
2600    AsmOperandInfo &info, const char *constraint) const {
2601  ConstraintWeight weight = CW_Invalid;
2602  Value *CallOperandVal = info.CallOperandVal;
2603    // If we don't have a value, we can't do a match,
2604    // but allow it at the lowest weight.
2605  if (CallOperandVal == NULL)
2606    return CW_Default;
2607  Type *type = CallOperandVal->getType();
2608  // Look at the constraint type.
2609  switch (*constraint) {
2610  default:
2611    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2612    break;
2613  case 'd':
2614  case 'y':
2615    if (type->isIntegerTy())
2616      weight = CW_Register;
2617    break;
2618  case 'f':
2619    if (type->isFloatTy())
2620      weight = CW_Register;
2621    break;
2622  }
2623  return weight;
2624}
2625
2626/// Given a register class constraint, like 'r', if this corresponds directly
2627/// to an LLVM register class, return a register of 0 and the register class
2628/// pointer.
2629std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2630getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
2631{
2632  if (Constraint.size() == 1) {
2633    switch (Constraint[0]) {
2634    case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2635    case 'y': // Same as 'r'. Exists for compatibility.
2636    case 'r':
2637      return std::make_pair(0U, Mips::CPURegsRegisterClass);
2638    case 'f':
2639      if (VT == MVT::f32)
2640        return std::make_pair(0U, Mips::FGR32RegisterClass);
2641      if (VT == MVT::f64)
2642        if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
2643          return std::make_pair(0U, Mips::AFGR64RegisterClass);
2644      break;
2645    }
2646  }
2647  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2648}
2649
2650bool
2651MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2652  // The Mips target isn't yet aware of offsets.
2653  return false;
2654}
2655
2656bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2657  if (VT != MVT::f32 && VT != MVT::f64)
2658    return false;
2659  if (Imm.isNegZero())
2660    return false;
2661  return Imm.isZero();
2662}
2663