MipsISelLowering.cpp revision f1214cbf3c2d151d3a2353d82143da186313a42a 
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "mips-lower"
16#include "MipsISelLowering.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "MipsTargetObjectFile.h"
20#include "MipsSubtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/GlobalVariable.h"
24#include "llvm/Intrinsics.h"
25#include "llvm/CallingConv.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/SelectionDAGISel.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35using namespace llvm;
36
37const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
38  switch (Opcode) {
39    case MipsISD::JmpLink    : return "MipsISD::JmpLink";
40    case MipsISD::Hi         : return "MipsISD::Hi";
41    case MipsISD::Lo         : return "MipsISD::Lo";
42    case MipsISD::GPRel      : return "MipsISD::GPRel";
43    case MipsISD::Ret        : return "MipsISD::Ret";
44    case MipsISD::CMov       : return "MipsISD::CMov";
45    case MipsISD::SelectCC   : return "MipsISD::SelectCC";
46    case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
47    case MipsISD::FPBrcond   : return "MipsISD::FPBrcond";
48    case MipsISD::FPCmp      : return "MipsISD::FPCmp";
49    case MipsISD::FPRound    : return "MipsISD::FPRound";
50    default                  : return NULL;
51  }
52}
53
54MipsTargetLowering::
55MipsTargetLowering(MipsTargetMachine &TM)
56  : TargetLowering(TM, new MipsTargetObjectFile()) {
57  Subtarget = &TM.getSubtarget<MipsSubtarget>();
58
59  // Mips does not have i1 type, so use i32 for
60  // setcc operations results (slt, sgt, ...).
61  setBooleanContents(ZeroOrOneBooleanContent);
62
63  // Set up the register classes
64  addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
65  addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
66
67  // When dealing with single precision only, use libcalls
68  if (!Subtarget->isSingleFloat())
69    if (!Subtarget->isFP64bit())
70      addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
71
72  // Load extented operations for i1 types must be promoted
73  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
74  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
75  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
76
77  // MIPS doesn't have extending float->double load/store
78  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
79  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
80
81  // Used by legalize types to correctly generate the setcc result.
82  // Without this, every float setcc comes with a AND/OR with the result,
83  // we don't want this, since the fpcmp result goes to a flag register,
84  // which is used implicitly by brcond and select operations.
85  AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
86
87  // Mips Custom Operations
88  setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
89  setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
90  setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
91  setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
92  setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
93  setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
94  setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
95  setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
96  setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
97  setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
98  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Custom);
99  setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
100
101  // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
102  // with operands comming from setcc fp comparions. This is necessary since
103  // the result from these setcc are in a flag registers (FCR31).
104  setOperationAction(ISD::AND,              MVT::i32,   Custom);
105  setOperationAction(ISD::OR,               MVT::i32,   Custom);
106
107  // Operations not directly supported by Mips.
108  setOperationAction(ISD::BR_JT,             MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,             MVT::Other, Expand);
110  setOperationAction(ISD::SELECT_CC,         MVT::Other, Expand);
111  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
112  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
113  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
114  setOperationAction(ISD::CTPOP,             MVT::i32,   Expand);
115  setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
116  setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
117  setOperationAction(ISD::ROTR,              MVT::i32,   Expand);
118  setOperationAction(ISD::SHL_PARTS,         MVT::i32,   Expand);
119  setOperationAction(ISD::SRA_PARTS,         MVT::i32,   Expand);
120  setOperationAction(ISD::SRL_PARTS,         MVT::i32,   Expand);
121  setOperationAction(ISD::FCOPYSIGN,         MVT::f32,   Expand);
122  setOperationAction(ISD::FCOPYSIGN,         MVT::f64,   Expand);
123  setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
124  setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
125  setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
126  setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
127  setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
128  setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
129  setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
130  setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
131
132  setOperationAction(ISD::EH_LABEL,          MVT::Other, Expand);
133
134  // Use the default for now
135  setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
136  setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
137  setOperationAction(ISD::MEMBARRIER,        MVT::Other, Expand);
138
139  if (Subtarget->isSingleFloat())
140    setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
141
142  if (!Subtarget->hasSEInReg()) {
143    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
144    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
145  }
146
147  if (!Subtarget->hasBitCount())
148    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
149
150  if (!Subtarget->hasSwap())
151    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
152
153  setStackPointerRegisterToSaveRestore(Mips::SP);
154  computeRegisterProperties();
155}
156
157MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
158  return MVT::i32;
159}
160
161/// getFunctionAlignment - Return the Log2 alignment of this function.
162unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
163  return 2;
164}
165
166SDValue MipsTargetLowering::
167LowerOperation(SDValue Op, SelectionDAG &DAG)
168{
169  switch (Op.getOpcode())
170  {
171    case ISD::AND:                return LowerANDOR(Op, DAG);
172    case ISD::BRCOND:             return LowerBRCOND(Op, DAG);
173    case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
174    case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
175    case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
176    case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
177    case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
178    case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
179    case ISD::OR:                 return LowerANDOR(Op, DAG);
180    case ISD::SELECT:             return LowerSELECT(Op, DAG);
181    case ISD::SETCC:              return LowerSETCC(Op, DAG);
182  }
183  return SDValue();
184}
185
186//===----------------------------------------------------------------------===//
187//  Lower helper functions
188//===----------------------------------------------------------------------===//
189
190// AddLiveIn - This helper function adds the specified physical register to the
191// MachineFunction as a live in value.  It also creates a corresponding
192// virtual register for it.
193static unsigned
194AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
195{
196  assert(RC->contains(PReg) && "Not the correct regclass!");
197  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
198  MF.getRegInfo().addLiveIn(PReg, VReg);
199  return VReg;
200}
201
202// Get fp branch code (not opcode) from condition code.
203static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
204  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
205    return Mips::BRANCH_T;
206
207  if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
208    return Mips::BRANCH_F;
209
210  return Mips::BRANCH_INVALID;
211}
212
213static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
214  switch(BC) {
215    default:
216      llvm_unreachable("Unknown branch code");
217    case Mips::BRANCH_T  : return Mips::BC1T;
218    case Mips::BRANCH_F  : return Mips::BC1F;
219    case Mips::BRANCH_TL : return Mips::BC1TL;
220    case Mips::BRANCH_FL : return Mips::BC1FL;
221  }
222}
223
224static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
225  switch (CC) {
226  default: llvm_unreachable("Unknown fp condition code!");
227  case ISD::SETEQ:
228  case ISD::SETOEQ: return Mips::FCOND_EQ;
229  case ISD::SETUNE: return Mips::FCOND_OGL;
230  case ISD::SETLT:
231  case ISD::SETOLT: return Mips::FCOND_OLT;
232  case ISD::SETGT:
233  case ISD::SETOGT: return Mips::FCOND_OGT;
234  case ISD::SETLE:
235  case ISD::SETOLE: return Mips::FCOND_OLE;
236  case ISD::SETGE:
237  case ISD::SETOGE: return Mips::FCOND_OGE;
238  case ISD::SETULT: return Mips::FCOND_ULT;
239  case ISD::SETULE: return Mips::FCOND_ULE;
240  case ISD::SETUGT: return Mips::FCOND_UGT;
241  case ISD::SETUGE: return Mips::FCOND_UGE;
242  case ISD::SETUO:  return Mips::FCOND_UN;
243  case ISD::SETO:   return Mips::FCOND_OR;
244  case ISD::SETNE:
245  case ISD::SETONE: return Mips::FCOND_NEQ;
246  case ISD::SETUEQ: return Mips::FCOND_UEQ;
247  }
248}
249
250MachineBasicBlock *
251MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
252                                                MachineBasicBlock *BB,
253                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
254  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
255  bool isFPCmp = false;
256  DebugLoc dl = MI->getDebugLoc();
257
258  switch (MI->getOpcode()) {
259  default: assert(false && "Unexpected instr type to insert");
260  case Mips::Select_FCC:
261  case Mips::Select_FCC_S32:
262  case Mips::Select_FCC_D32:
263    isFPCmp = true; // FALL THROUGH
264  case Mips::Select_CC:
265  case Mips::Select_CC_S32:
266  case Mips::Select_CC_D32: {
267    // To "insert" a SELECT_CC instruction, we actually have to insert the
268    // diamond control-flow pattern.  The incoming instruction knows the
269    // destination vreg to set, the condition code register to branch on, the
270    // true/false values to select between, and a branch opcode to use.
271    const BasicBlock *LLVM_BB = BB->getBasicBlock();
272    MachineFunction::iterator It = BB;
273    ++It;
274
275    //  thisMBB:
276    //  ...
277    //   TrueVal = ...
278    //   setcc r1, r2, r3
279    //   bNE   r1, r0, copy1MBB
280    //   fallthrough --> copy0MBB
281    MachineBasicBlock *thisMBB  = BB;
282    MachineFunction *F = BB->getParent();
283    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
284    MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
285
286    // Emit the right instruction according to the type of the operands compared
287    if (isFPCmp) {
288      // Find the condiction code present in the setcc operation.
289      Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
290      // Get the branch opcode from the branch code.
291      unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
292      BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
293    } else
294      BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
295        .addReg(Mips::ZERO).addMBB(sinkMBB);
296
297    F->insert(It, copy0MBB);
298    F->insert(It, sinkMBB);
299    // Update machine-CFG edges by first adding all successors of the current
300    // block to the new block which will contain the Phi node for the select.
301    // Also inform sdisel of the edge changes.
302    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
303          e = BB->succ_end(); i != e; ++i) {
304      EM->insert(std::make_pair(*i, sinkMBB));
305      sinkMBB->addSuccessor(*i);
306    }
307    // Next, remove all successors of the current block, and add the true
308    // and fallthrough blocks as its successors.
309    while(!BB->succ_empty())
310      BB->removeSuccessor(BB->succ_begin());
311    BB->addSuccessor(copy0MBB);
312    BB->addSuccessor(sinkMBB);
313
314    //  copy0MBB:
315    //   %FalseValue = ...
316    //   # fallthrough to sinkMBB
317    BB = copy0MBB;
318
319    // Update machine-CFG edges
320    BB->addSuccessor(sinkMBB);
321
322    //  sinkMBB:
323    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
324    //  ...
325    BB = sinkMBB;
326    BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
327      .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
328      .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
329
330    F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
331    return BB;
332  }
333  }
334}
335
336//===----------------------------------------------------------------------===//
337//  Misc Lower Operation implementation
338//===----------------------------------------------------------------------===//
339
340SDValue MipsTargetLowering::
341LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
342{
343  if (!Subtarget->isMips1())
344    return Op;
345
346  MachineFunction &MF = DAG.getMachineFunction();
347  unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
348
349  SDValue Chain = DAG.getEntryNode();
350  DebugLoc dl = Op.getDebugLoc();
351  SDValue Src = Op.getOperand(0);
352
353  // Set the condition register
354  SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
355  CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
356  CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
357
358  SDValue Cst = DAG.getConstant(3, MVT::i32);
359  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
360  Cst = DAG.getConstant(2, MVT::i32);
361  SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
362
363  SDValue InFlag(0, 0);
364  CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
365
366  // Emit the round instruction and bit convert to integer
367  SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
368                              Src, CondReg.getValue(1));
369  SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
370  return BitCvt;
371}
372
373SDValue MipsTargetLowering::
374LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
375{
376  SDValue Chain = Op.getOperand(0);
377  SDValue Size = Op.getOperand(1);
378  DebugLoc dl = Op.getDebugLoc();
379
380  // Get a reference from Mips stack pointer
381  SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
382
383  // Subtract the dynamic size from the actual stack size to
384  // obtain the new stack size.
385  SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
386
387  // The Sub result contains the new stack start address, so it
388  // must be placed in the stack pointer register.
389  Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
390
391  // This node always has two return values: a new stack pointer
392  // value and a chain
393  SDValue Ops[2] = { Sub, Chain };
394  return DAG.getMergeValues(Ops, 2, dl);
395}
396
397SDValue MipsTargetLowering::
398LowerANDOR(SDValue Op, SelectionDAG &DAG)
399{
400  SDValue LHS   = Op.getOperand(0);
401  SDValue RHS   = Op.getOperand(1);
402  DebugLoc dl   = Op.getDebugLoc();
403
404  if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
405    return Op;
406
407  SDValue True  = DAG.getConstant(1, MVT::i32);
408  SDValue False = DAG.getConstant(0, MVT::i32);
409
410  SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
411                             LHS, True, False, LHS.getOperand(2));
412  SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
413                             RHS, True, False, RHS.getOperand(2));
414
415  return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
416}
417
418SDValue MipsTargetLowering::
419LowerBRCOND(SDValue Op, SelectionDAG &DAG)
420{
421  // The first operand is the chain, the second is the condition, the third is
422  // the block to branch to if the condition is true.
423  SDValue Chain = Op.getOperand(0);
424  SDValue Dest = Op.getOperand(2);
425  DebugLoc dl = Op.getDebugLoc();
426
427  if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
428    return Op;
429
430  SDValue CondRes = Op.getOperand(1);
431  SDValue CCNode  = CondRes.getOperand(2);
432  Mips::CondCode CC =
433    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
434  SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
435
436  return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
437             Dest, CondRes);
438}
439
440SDValue MipsTargetLowering::
441LowerSETCC(SDValue Op, SelectionDAG &DAG)
442{
443  // The operands to this are the left and right operands to compare (ops #0,
444  // and #1) and the condition code to compare them with (op #2) as a
445  // CondCodeSDNode.
446  SDValue LHS = Op.getOperand(0);
447  SDValue RHS = Op.getOperand(1);
448  DebugLoc dl = Op.getDebugLoc();
449
450  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
451
452  return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
453                 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
454}
455
456SDValue MipsTargetLowering::
457LowerSELECT(SDValue Op, SelectionDAG &DAG)
458{
459  SDValue Cond  = Op.getOperand(0);
460  SDValue True  = Op.getOperand(1);
461  SDValue False = Op.getOperand(2);
462  DebugLoc dl = Op.getDebugLoc();
463
464  // if the incomming condition comes from a integer compare, the select
465  // operation must be SelectCC or a conditional move if the subtarget
466  // supports it.
467  if (Cond.getOpcode() != MipsISD::FPCmp) {
468    if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
469      return Op;
470    return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
471                       Cond, True, False);
472  }
473
474  // if the incomming condition comes from fpcmp, the select
475  // operation must use FPSelectCC.
476  SDValue CCNode = Cond.getOperand(2);
477  return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
478                     Cond, True, False, CCNode);
479}
480
481SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
482  // FIXME there isn't actually debug info here
483  DebugLoc dl = Op.getDebugLoc();
484  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
485
486  if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
487    SDVTList VTs = DAG.getVTList(MVT::i32);
488
489    MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
490
491    // %gp_rel relocation
492    if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
493      SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
494                                              MipsII::MO_GPREL);
495      SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
496      SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
497      return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
498    }
499    // %hi/%lo relocation
500    SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
501                                            MipsII::MO_ABS_HILO);
502    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
503    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
504    return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
505
506  } else {
507    SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
508                                            MipsII::MO_GOT);
509    SDValue ResNode = DAG.getLoad(MVT::i32, dl,
510                                  DAG.getEntryNode(), GA, NULL, 0);
511    // On functions and global targets not internal linked only
512    // a load from got/GP is necessary for PIC to work.
513    if (!GV->hasLocalLinkage() || isa<Function>(GV))
514      return ResNode;
515    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
516    return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
517  }
518
519  llvm_unreachable("Dont know how to handle GlobalAddress");
520  return SDValue(0,0);
521}
522
523SDValue MipsTargetLowering::
524LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
525{
526  llvm_unreachable("TLS not implemented for MIPS.");
527  return SDValue(); // Not reached
528}
529
530SDValue MipsTargetLowering::
531LowerJumpTable(SDValue Op, SelectionDAG &DAG)
532{
533  SDValue ResNode;
534  SDValue HiPart;
535  // FIXME there isn't actually debug info here
536  DebugLoc dl = Op.getDebugLoc();
537  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
538  unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
539
540  EVT PtrVT = Op.getValueType();
541  JumpTableSDNode *JT  = cast<JumpTableSDNode>(Op);
542
543  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
544
545  if (IsPIC) {
546    SDValue Ops[] = { JTI };
547    HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
548  } else // Emit Load from Global Pointer
549    HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
550
551  SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
552  ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
553
554  return ResNode;
555}
556
557SDValue MipsTargetLowering::
558LowerConstantPool(SDValue Op, SelectionDAG &DAG)
559{
560  SDValue ResNode;
561  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
562  Constant *C = N->getConstVal();
563  // FIXME there isn't actually debug info here
564  DebugLoc dl = Op.getDebugLoc();
565
566  // gp_rel relocation
567  // FIXME: we should reference the constant pool using small data sections,
568  // but the asm printer currently doens't support this feature without
569  // hacking it. This feature should come soon so we can uncomment the
570  // stuff below.
571  //if (IsInSmallSection(C->getType())) {
572  //  SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
573  //  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
574  //  ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
575
576  if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
577    SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
578                                      N->getOffset(), MipsII::MO_ABS_HILO);
579    SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
580    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
581    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
582  } else {
583    SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
584                                      N->getOffset(), MipsII::MO_GOT);
585    SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
586                                 CP, NULL, 0);
587    SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
588    ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
589  }
590
591  return ResNode;
592}
593
594//===----------------------------------------------------------------------===//
595//                      Calling Convention Implementation
596//===----------------------------------------------------------------------===//
597
598#include "MipsGenCallingConv.inc"
599
600//===----------------------------------------------------------------------===//
601// TODO: Implement a generic logic using tblgen that can support this.
602// Mips O32 ABI rules:
603// ---
604// i32 - Passed in A0, A1, A2, A3 and stack
605// f32 - Only passed in f32 registers if no int reg has been used yet to hold
606//       an argument. Otherwise, passed in A1, A2, A3 and stack.
607// f64 - Only passed in two aliased f32 registers if no int reg has been used
608//       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
609//       not used, it must be shadowed. If only A3 is avaiable, shadow it and
610//       go to stack.
611//===----------------------------------------------------------------------===//
612
613static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
614                       EVT LocVT, CCValAssign::LocInfo LocInfo,
615                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
616
617  static const unsigned IntRegsSize=4, FloatRegsSize=2;
618
619  static const unsigned IntRegs[] = {
620      Mips::A0, Mips::A1, Mips::A2, Mips::A3
621  };
622  static const unsigned F32Regs[] = {
623      Mips::F12, Mips::F14
624  };
625  static const unsigned F64Regs[] = {
626      Mips::D6, Mips::D7
627  };
628
629  unsigned Reg=0;
630  unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
631  bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
632
633  // Promote i8 and i16
634  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
635    LocVT = MVT::i32;
636    if (ArgFlags.isSExt())
637      LocInfo = CCValAssign::SExt;
638    else if (ArgFlags.isZExt())
639      LocInfo = CCValAssign::ZExt;
640    else
641      LocInfo = CCValAssign::AExt;
642  }
643
644  if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
645    Reg = State.AllocateReg(IntRegs, IntRegsSize);
646    IntRegUsed = true;
647    LocVT = MVT::i32;
648  }
649
650  if (ValVT.isFloatingPoint() && !IntRegUsed) {
651    if (ValVT == MVT::f32)
652      Reg = State.AllocateReg(F32Regs, FloatRegsSize);
653    else
654      Reg = State.AllocateReg(F64Regs, FloatRegsSize);
655  }
656
657  if (ValVT == MVT::f64 && IntRegUsed) {
658    if (UnallocIntReg != IntRegsSize) {
659      // If we hit register A3 as the first not allocated, we must
660      // mark it as allocated (shadow) and use the stack instead.
661      if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
662        Reg = Mips::A2;
663      for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
664        State.AllocateReg(UnallocIntReg);
665    }
666    LocVT = MVT::i32;
667  }
668
669  if (!Reg) {
670    unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
671    unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
672    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
673  } else
674    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
675
676  return false; // CC must always match
677}
678
679//===----------------------------------------------------------------------===//
680//                  Call Calling Convention Implementation
681//===----------------------------------------------------------------------===//
682
683/// LowerCall - functions arguments are copied from virtual regs to
684/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
685/// TODO: isVarArg, isTailCall.
686SDValue
687MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
688                              CallingConv::ID CallConv, bool isVarArg,
689                              bool isTailCall,
690                              const SmallVectorImpl<ISD::OutputArg> &Outs,
691                              const SmallVectorImpl<ISD::InputArg> &Ins,
692                              DebugLoc dl, SelectionDAG &DAG,
693                              SmallVectorImpl<SDValue> &InVals) {
694
695  MachineFunction &MF = DAG.getMachineFunction();
696  MachineFrameInfo *MFI = MF.getFrameInfo();
697  bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
698
699  // Analyze operands of the call, assigning locations to each operand.
700  SmallVector<CCValAssign, 16> ArgLocs;
701  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
702                 *DAG.getContext());
703
704  // To meet O32 ABI, Mips must always allocate 16 bytes on
705  // the stack (even if less than 4 are used as arguments)
706  if (Subtarget->isABI_O32()) {
707    int VTsize = EVT(MVT::i32).getSizeInBits()/8;
708    MFI->CreateFixedObject(VTsize, (VTsize*3), true, false);
709    CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
710  } else
711    CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
712
713  // Get a count of how many bytes are to be pushed on the stack.
714  unsigned NumBytes = CCInfo.getNextStackOffset();
715  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
716
717  // With EABI is it possible to have 16 args on registers.
718  SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
719  SmallVector<SDValue, 8> MemOpChains;
720
721  // First/LastArgStackLoc contains the first/last
722  // "at stack" argument location.
723  int LastArgStackLoc = 0;
724  unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
725
726  // Walk the register/memloc assignments, inserting copies/loads.
727  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
728    SDValue Arg = Outs[i].Val;
729    CCValAssign &VA = ArgLocs[i];
730
731    // Promote the value if needed.
732    switch (VA.getLocInfo()) {
733    default: llvm_unreachable("Unknown loc info!");
734    case CCValAssign::Full:
735      if (Subtarget->isABI_O32() && VA.isRegLoc()) {
736        if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
737          Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
738        if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
739          Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
740          SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
741                                   DAG.getConstant(0, getPointerTy()));
742          SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
743                                   DAG.getConstant(1, getPointerTy()));
744          RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
745          RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
746          continue;
747        }
748      }
749      break;
750    case CCValAssign::SExt:
751      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
752      break;
753    case CCValAssign::ZExt:
754      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
755      break;
756    case CCValAssign::AExt:
757      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
758      break;
759    }
760
761    // Arguments that can be passed on register must be kept at
762    // RegsToPass vector
763    if (VA.isRegLoc()) {
764      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
765      continue;
766    }
767
768    // Register can't get to this point...
769    assert(VA.isMemLoc());
770
771    // Create the frame index object for this incoming parameter
772    // This guarantees that when allocating Local Area the firsts
773    // 16 bytes which are alwayes reserved won't be overwritten
774    // if O32 ABI is used. For EABI the first address is zero.
775    LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
776    int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
777                                    LastArgStackLoc, true, false);
778
779    SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
780
781    // emit ISD::STORE whichs stores the
782    // parameter value to a stack Location
783    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
784  }
785
786  // Transform all store nodes into one single node because all store
787  // nodes are independent of each other.
788  if (!MemOpChains.empty())
789    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
790                        &MemOpChains[0], MemOpChains.size());
791
792  // Build a sequence of copy-to-reg nodes chained together with token
793  // chain and flag operands which copy the outgoing args into registers.
794  // The InFlag in necessary since all emited instructions must be
795  // stuck together.
796  SDValue InFlag;
797  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
798    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
799                             RegsToPass[i].second, InFlag);
800    InFlag = Chain.getValue(1);
801  }
802
803  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
804  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
805  // node so that legalize doesn't hack it.
806  unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
807  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
808    Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
809                                getPointerTy(), 0, OpFlag);
810  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
811    Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
812                                getPointerTy(), OpFlag);
813
814  // MipsJmpLink = #chain, #target_address, #opt_in_flags...
815  //             = Chain, Callee, Reg#1, Reg#2, ...
816  //
817  // Returns a chain & a flag for retval copy to use.
818  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
819  SmallVector<SDValue, 8> Ops;
820  Ops.push_back(Chain);
821  Ops.push_back(Callee);
822
823  // Add argument registers to the end of the list so that they are
824  // known live into the call.
825  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
826    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
827                                  RegsToPass[i].second.getValueType()));
828
829  if (InFlag.getNode())
830    Ops.push_back(InFlag);
831
832  Chain  = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
833  InFlag = Chain.getValue(1);
834
835  // Create the CALLSEQ_END node.
836  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
837                             DAG.getIntPtrConstant(0, true), InFlag);
838  InFlag = Chain.getValue(1);
839
840  // Create a stack location to hold GP when PIC is used. This stack
841  // location is used on function prologue to save GP and also after all
842  // emited CALL's to restore GP.
843  if (IsPIC) {
844      // Function can have an arbitrary number of calls, so
845      // hold the LastArgStackLoc with the biggest offset.
846      int FI;
847      MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
848      if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
849        LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
850        // Create the frame index only once. SPOffset here can be anything
851        // (this will be fixed on processFunctionBeforeFrameFinalized)
852        if (MipsFI->getGPStackOffset() == -1) {
853          FI = MFI->CreateFixedObject(4, 0, true, false);
854          MipsFI->setGPFI(FI);
855        }
856        MipsFI->setGPStackOffset(LastArgStackLoc);
857      }
858
859      // Reload GP value.
860      FI = MipsFI->getGPFI();
861      SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
862      SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
863      Chain = GPLoad.getValue(1);
864      Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
865                               GPLoad, SDValue(0,0));
866      InFlag = Chain.getValue(1);
867  }
868
869  // Handle result values, copying them out of physregs into vregs that we
870  // return.
871  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
872                         Ins, dl, DAG, InVals);
873}
874
875/// LowerCallResult - Lower the result values of a call into the
876/// appropriate copies out of appropriate physical registers.
877SDValue
878MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
879                                    CallingConv::ID CallConv, bool isVarArg,
880                                    const SmallVectorImpl<ISD::InputArg> &Ins,
881                                    DebugLoc dl, SelectionDAG &DAG,
882                                    SmallVectorImpl<SDValue> &InVals) {
883
884  // Assign locations to each value returned by this call.
885  SmallVector<CCValAssign, 16> RVLocs;
886  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
887                 RVLocs, *DAG.getContext());
888
889  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
890
891  // Copy all of the result registers out of their specified physreg.
892  for (unsigned i = 0; i != RVLocs.size(); ++i) {
893    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
894                               RVLocs[i].getValVT(), InFlag).getValue(1);
895    InFlag = Chain.getValue(2);
896    InVals.push_back(Chain.getValue(0));
897  }
898
899  return Chain;
900}
901
902//===----------------------------------------------------------------------===//
903//             Formal Arguments Calling Convention Implementation
904//===----------------------------------------------------------------------===//
905
906/// LowerFormalArguments - transform physical registers into
907/// virtual registers and generate load operations for
908/// arguments places on the stack.
909/// TODO: isVarArg
910SDValue
911MipsTargetLowering::LowerFormalArguments(SDValue Chain,
912                                         CallingConv::ID CallConv, bool isVarArg,
913                                         const SmallVectorImpl<ISD::InputArg>
914                                           &Ins,
915                                         DebugLoc dl, SelectionDAG &DAG,
916                                         SmallVectorImpl<SDValue> &InVals) {
917
918  MachineFunction &MF = DAG.getMachineFunction();
919  MachineFrameInfo *MFI = MF.getFrameInfo();
920  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
921
922  unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
923
924  // Assign locations to all of the incoming arguments.
925  SmallVector<CCValAssign, 16> ArgLocs;
926  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
927                 ArgLocs, *DAG.getContext());
928
929  if (Subtarget->isABI_O32())
930    CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
931  else
932    CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
933
934  SDValue StackPtr;
935
936  unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
937
938  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
939    CCValAssign &VA = ArgLocs[i];
940
941    // Arguments stored on registers
942    if (VA.isRegLoc()) {
943      EVT RegVT = VA.getLocVT();
944      TargetRegisterClass *RC = 0;
945
946      if (RegVT == MVT::i32)
947        RC = Mips::CPURegsRegisterClass;
948      else if (RegVT == MVT::f32)
949        RC = Mips::FGR32RegisterClass;
950      else if (RegVT == MVT::f64) {
951        if (!Subtarget->isSingleFloat())
952          RC = Mips::AFGR64RegisterClass;
953      } else
954        llvm_unreachable("RegVT not supported by LowerFormalArguments Lowering");
955
956      // Transform the arguments stored on
957      // physical registers into virtual ones
958      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
959      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
960
961      // If this is an 8 or 16-bit value, it has been passed promoted
962      // to 32 bits.  Insert an assert[sz]ext to capture this, then
963      // truncate to the right size.
964      if (VA.getLocInfo() != CCValAssign::Full) {
965        unsigned Opcode = 0;
966        if (VA.getLocInfo() == CCValAssign::SExt)
967          Opcode = ISD::AssertSext;
968        else if (VA.getLocInfo() == CCValAssign::ZExt)
969          Opcode = ISD::AssertZext;
970        if (Opcode)
971          ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
972                                 DAG.getValueType(VA.getValVT()));
973        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
974      }
975
976      // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
977      if (Subtarget->isABI_O32()) {
978        if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
979          ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
980        if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
981          unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
982                                    VA.getLocReg()+1, RC);
983          SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
984          SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
985          SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
986          ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
987        }
988      }
989
990      InVals.push_back(ArgValue);
991
992      // To meet ABI, when VARARGS are passed on registers, the registers
993      // must have their values written to the caller stack frame.
994      if ((isVarArg) && (Subtarget->isABI_O32())) {
995        if (StackPtr.getNode() == 0)
996          StackPtr = DAG.getRegister(StackReg, getPointerTy());
997
998        // The stack pointer offset is relative to the caller stack frame.
999        // Since the real stack size is unknown here, a negative SPOffset
1000        // is used so there's a way to adjust these offsets when the stack
1001        // size get known (on EliminateFrameIndex). A dummy SPOffset is
1002        // used instead of a direct negative address (which is recorded to
1003        // be used on emitPrologue) to avoid mis-calc of the first stack
1004        // offset on PEI::calculateFrameObjectOffsets.
1005        // Arguments are always 32-bit.
1006        int FI = MFI->CreateFixedObject(4, 0, true, false);
1007        MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
1008        SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1009
1010        // emit ISD::STORE whichs stores the
1011        // parameter value to a stack Location
1012        InVals.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0));
1013      }
1014
1015    } else { // VA.isRegLoc()
1016
1017      // sanity check
1018      assert(VA.isMemLoc());
1019
1020      // The stack pointer offset is relative to the caller stack frame.
1021      // Since the real stack size is unknown here, a negative SPOffset
1022      // is used so there's a way to adjust these offsets when the stack
1023      // size get known (on EliminateFrameIndex). A dummy SPOffset is
1024      // used instead of a direct negative address (which is recorded to
1025      // be used on emitPrologue) to avoid mis-calc of the first stack
1026      // offset on PEI::calculateFrameObjectOffsets.
1027      // Arguments are always 32-bit.
1028      unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1029      int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
1030      MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1031        (FirstStackArgLoc + VA.getLocMemOffset())));
1032
1033      // Create load nodes to retrieve arguments from the stack
1034      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1035      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1036    }
1037  }
1038
1039  // The mips ABIs for returning structs by value requires that we copy
1040  // the sret argument into $v0 for the return. Save the argument into
1041  // a virtual register so that we can access it from the return points.
1042  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1043    unsigned Reg = MipsFI->getSRetReturnReg();
1044    if (!Reg) {
1045      Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1046      MipsFI->setSRetReturnReg(Reg);
1047    }
1048    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1049    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1050  }
1051
1052  return Chain;
1053}
1054
1055//===----------------------------------------------------------------------===//
1056//               Return Value Calling Convention Implementation
1057//===----------------------------------------------------------------------===//
1058
1059SDValue
1060MipsTargetLowering::LowerReturn(SDValue Chain,
1061                                CallingConv::ID CallConv, bool isVarArg,
1062                                const SmallVectorImpl<ISD::OutputArg> &Outs,
1063                                DebugLoc dl, SelectionDAG &DAG) {
1064
1065  // CCValAssign - represent the assignment of
1066  // the return value to a location
1067  SmallVector<CCValAssign, 16> RVLocs;
1068
1069  // CCState - Info about the registers and stack slot.
1070  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1071                 RVLocs, *DAG.getContext());
1072
1073  // Analize return values.
1074  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1075
1076  // If this is the first return lowered for this function, add
1077  // the regs to the liveout set for the function.
1078  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1079    for (unsigned i = 0; i != RVLocs.size(); ++i)
1080      if (RVLocs[i].isRegLoc())
1081        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1082  }
1083
1084  SDValue Flag;
1085
1086  // Copy the result values into the output registers.
1087  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1088    CCValAssign &VA = RVLocs[i];
1089    assert(VA.isRegLoc() && "Can only return in registers!");
1090
1091    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1092                             Outs[i].Val, Flag);
1093
1094    // guarantee that all emitted copies are
1095    // stuck together, avoiding something bad
1096    Flag = Chain.getValue(1);
1097  }
1098
1099  // The mips ABIs for returning structs by value requires that we copy
1100  // the sret argument into $v0 for the return. We saved the argument into
1101  // a virtual register in the entry block, so now we copy the value out
1102  // and into $v0.
1103  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1104    MachineFunction &MF      = DAG.getMachineFunction();
1105    MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1106    unsigned Reg = MipsFI->getSRetReturnReg();
1107
1108    if (!Reg)
1109      llvm_unreachable("sret virtual register not created in the entry block");
1110    SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1111
1112    Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1113    Flag = Chain.getValue(1);
1114  }
1115
1116  // Return on Mips is always a "jr $ra"
1117  if (Flag.getNode())
1118    return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1119                       Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1120  else // Return Void
1121    return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1122                       Chain, DAG.getRegister(Mips::RA, MVT::i32));
1123}
1124
1125//===----------------------------------------------------------------------===//
1126//                           Mips Inline Assembly Support
1127//===----------------------------------------------------------------------===//
1128
1129/// getConstraintType - Given a constraint letter, return the type of
1130/// constraint it is for this target.
1131MipsTargetLowering::ConstraintType MipsTargetLowering::
1132getConstraintType(const std::string &Constraint) const
1133{
1134  // Mips specific constrainy
1135  // GCC config/mips/constraints.md
1136  //
1137  // 'd' : An address register. Equivalent to r
1138  //       unless generating MIPS16 code.
1139  // 'y' : Equivalent to r; retained for
1140  //       backwards compatibility.
1141  // 'f' : Floating Point registers.
1142  if (Constraint.size() == 1) {
1143    switch (Constraint[0]) {
1144      default : break;
1145      case 'd':
1146      case 'y':
1147      case 'f':
1148        return C_RegisterClass;
1149        break;
1150    }
1151  }
1152  return TargetLowering::getConstraintType(Constraint);
1153}
1154
1155/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1156/// return a list of registers that can be used to satisfy the constraint.
1157/// This should only be used for C_RegisterClass constraints.
1158std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1159getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1160{
1161  if (Constraint.size() == 1) {
1162    switch (Constraint[0]) {
1163    case 'r':
1164      return std::make_pair(0U, Mips::CPURegsRegisterClass);
1165    case 'f':
1166      if (VT == MVT::f32)
1167        return std::make_pair(0U, Mips::FGR32RegisterClass);
1168      if (VT == MVT::f64)
1169        if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1170          return std::make_pair(0U, Mips::AFGR64RegisterClass);
1171    }
1172  }
1173  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1174}
1175
1176/// Given a register class constraint, like 'r', if this corresponds directly
1177/// to an LLVM register class, return a register of 0 and the register class
1178/// pointer.
1179std::vector<unsigned> MipsTargetLowering::
1180getRegClassForInlineAsmConstraint(const std::string &Constraint,
1181                                  EVT VT) const
1182{
1183  if (Constraint.size() != 1)
1184    return std::vector<unsigned>();
1185
1186  switch (Constraint[0]) {
1187    default : break;
1188    case 'r':
1189    // GCC Mips Constraint Letters
1190    case 'd':
1191    case 'y':
1192      return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1193             Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1194             Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1195             Mips::T8, 0);
1196
1197    case 'f':
1198      if (VT == MVT::f32) {
1199        if (Subtarget->isSingleFloat())
1200          return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1201                 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1202                 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1203                 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1204                 Mips::F30, Mips::F31, 0);
1205        else
1206          return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1207                 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1208                 Mips::F28, Mips::F30, 0);
1209      }
1210
1211      if (VT == MVT::f64)
1212        if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1213          return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1214                 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1215                 Mips::D14, Mips::D15, 0);
1216  }
1217  return std::vector<unsigned>();
1218}
1219
1220bool
1221MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1222  // The Mips target isn't yet aware of offsets.
1223  return false;
1224}
1225
1226bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1227  if (VT != MVT::f32 && VT != MVT::f64)
1228    return false;
1229  return Imm.isZero();
1230}
1231