MipsISelLowering.cpp revision f7f3b50cd8c10c20f68045c5322f134bd83b06c7
1//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-lower" 16 17#include "MipsISelLowering.h" 18#include "MipsMachineFunction.h" 19#include "MipsTargetMachine.h" 20#include "MipsSubtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Intrinsics.h" 25#include "llvm/CallingConv.h" 26#include "llvm/CodeGen/CallingConvLower.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/SelectionDAGISel.h" 32#include "llvm/CodeGen/ValueTypes.h" 33#include "llvm/Support/Debug.h" 34#include <queue> 35#include <set> 36 37using namespace llvm; 38 39const char *MipsTargetLowering:: 40getTargetNodeName(unsigned Opcode) const 41{ 42 switch (Opcode) 43 { 44 case MipsISD::JmpLink : return "MipsISD::JmpLink"; 45 case MipsISD::Hi : return "MipsISD::Hi"; 46 case MipsISD::Lo : return "MipsISD::Lo"; 47 case MipsISD::GPRel : return "MipsISD::GPRel"; 48 case MipsISD::Ret : return "MipsISD::Ret"; 49 case MipsISD::SelectCC : return "MipsISD::SelectCC"; 50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC"; 51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond"; 52 case MipsISD::FPCmp : return "MipsISD::FPCmp"; 53 default : return NULL; 54 } 55} 56 57MipsTargetLowering:: 58MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) 59{ 60 Subtarget = &TM.getSubtarget<MipsSubtarget>(); 61 62 // Mips does not have i1 type, so use i32 for 63 // setcc operations results (slt, sgt, ...). 64 setSetCCResultContents(ZeroOrOneSetCCResult); 65 66 // JumpTable targets must use GOT when using PIC_ 67 setUsesGlobalOffsetTable(true); 68 69 // Set up the register classes 70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 71 72 // When dealing with single precision only, use libcalls 73 if (!Subtarget->isSingleFloat()) { 74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass); 75 if (!Subtarget->isFP64bit()) 76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 77 } else 78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 79 80 // Legal fp constants 81 addLegalFPImmediate(APFloat(+0.0f)); 82 83 // Load extented operations for i1 types must be promoted 84 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); 85 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); 86 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 87 88 // Used by legalize types to correctly generate the setcc result. 89 // Without this, every float setcc comes with a AND/OR with the result, 90 // we don't want this, since the fpcmp result goes to a flag register, 91 // which is used implicitly by brcond and select operations. 92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 93 94 // Mips Custom Operations 95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 96 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 97 setOperationAction(ISD::RET, MVT::Other, Custom); 98 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 100 setOperationAction(ISD::SELECT, MVT::f32, Custom); 101 setOperationAction(ISD::SELECT, MVT::i32, Custom); 102 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 103 setOperationAction(ISD::SETCC, MVT::f32, Custom); 104 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 105 106 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors' 107 // with operands comming from setcc fp comparions. This is necessary since 108 // the result from these setcc are in a flag registers (FCR31). 109 setOperationAction(ISD::AND, MVT::i32, Custom); 110 setOperationAction(ISD::OR, MVT::i32, Custom); 111 112 // Operations not directly supported by Mips. 113 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 114 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 115 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 116 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 117 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 119 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 120 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 121 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 122 setOperationAction(ISD::ROTL, MVT::i32, Expand); 123 setOperationAction(ISD::ROTR, MVT::i32, Expand); 124 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 125 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 126 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 127 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 128 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 129 130 // We don't have line number support yet. 131 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 132 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 133 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 134 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 135 136 // Use the default for now 137 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 138 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 139 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 140 141 if (Subtarget->isSingleFloat()) 142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 143 144 if (!Subtarget->hasSEInReg()) { 145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 147 } 148 149 setStackPointerRegisterToSaveRestore(Mips::SP); 150 computeRegisterProperties(); 151} 152 153 154MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const { 155 return MVT::i32; 156} 157 158 159SDValue MipsTargetLowering:: 160LowerOperation(SDValue Op, SelectionDAG &DAG) 161{ 162 switch (Op.getOpcode()) 163 { 164 case ISD::AND: return LowerANDOR(Op, DAG); 165 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 166 case ISD::CALL: return LowerCALL(Op, DAG); 167 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 168 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 171 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 172 case ISD::OR: return LowerANDOR(Op, DAG); 173 case ISD::RET: return LowerRET(Op, DAG); 174 case ISD::SELECT: return LowerSELECT(Op, DAG); 175 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 176 case ISD::SETCC: return LowerSETCC(Op, DAG); 177 } 178 return SDValue(); 179} 180 181//===----------------------------------------------------------------------===// 182// Lower helper functions 183//===----------------------------------------------------------------------===// 184 185// AddLiveIn - This helper function adds the specified physical register to the 186// MachineFunction as a live in value. It also creates a corresponding 187// virtual register for it. 188static unsigned 189AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 190{ 191 assert(RC->contains(PReg) && "Not the correct regclass!"); 192 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 193 MF.getRegInfo().addLiveIn(PReg, VReg); 194 return VReg; 195} 196 197// A address must be loaded from a small section if its size is less than the 198// small section size threshold. Data in this section must be addressed using 199// gp_rel operator. 200bool MipsTargetLowering::IsInSmallSection(unsigned Size) { 201 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold())); 202} 203 204// Discover if this global address can be placed into small data/bss section. 205bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV) 206{ 207 const TargetData *TD = getTargetData(); 208 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV); 209 210 if (!GVA) 211 return false; 212 213 const Type *Ty = GV->getType()->getElementType(); 214 unsigned Size = TD->getABITypeSize(Ty); 215 216 // if this is a internal constant string, there is a special 217 // section for it, but not in small data/bss. 218 if (GVA->hasInitializer() && GV->hasInternalLinkage()) { 219 Constant *C = GVA->getInitializer(); 220 const ConstantArray *CVA = dyn_cast<ConstantArray>(C); 221 if (CVA && CVA->isCString()) 222 return false; 223 } 224 225 return IsInSmallSection(Size); 226} 227 228// Get fp branch code (not opcode) from condition code. 229static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 230 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 231 return Mips::BRANCH_T; 232 233 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 234 return Mips::BRANCH_F; 235 236 return Mips::BRANCH_INVALID; 237} 238 239static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) { 240 switch(BC) { 241 default: 242 assert(0 && "Unknown branch code"); 243 case Mips::BRANCH_T : return Mips::BC1T; 244 case Mips::BRANCH_F : return Mips::BC1F; 245 case Mips::BRANCH_TL : return Mips::BC1TL; 246 case Mips::BRANCH_FL : return Mips::BC1FL; 247 } 248} 249 250static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 251 switch (CC) { 252 default: assert(0 && "Unknown fp condition code!"); 253 case ISD::SETEQ: 254 case ISD::SETOEQ: return Mips::FCOND_EQ; 255 case ISD::SETUNE: return Mips::FCOND_OGL; 256 case ISD::SETLT: 257 case ISD::SETOLT: return Mips::FCOND_OLT; 258 case ISD::SETGT: 259 case ISD::SETOGT: return Mips::FCOND_OGT; 260 case ISD::SETLE: 261 case ISD::SETOLE: return Mips::FCOND_OLE; 262 case ISD::SETGE: 263 case ISD::SETOGE: return Mips::FCOND_OGE; 264 case ISD::SETULT: return Mips::FCOND_ULT; 265 case ISD::SETULE: return Mips::FCOND_ULE; 266 case ISD::SETUGT: return Mips::FCOND_UGT; 267 case ISD::SETUGE: return Mips::FCOND_UGE; 268 case ISD::SETUO: return Mips::FCOND_UN; 269 case ISD::SETO: return Mips::FCOND_OR; 270 case ISD::SETNE: 271 case ISD::SETONE: return Mips::FCOND_NEQ; 272 case ISD::SETUEQ: return Mips::FCOND_UEQ; 273 } 274} 275 276MachineBasicBlock * 277MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 278 MachineBasicBlock *BB) 279{ 280 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 281 bool isFPCmp = false; 282 283 switch (MI->getOpcode()) { 284 default: assert(false && "Unexpected instr type to insert"); 285 case Mips::Select_FCC: 286 case Mips::Select_FCC_SO32: 287 case Mips::Select_FCC_AS32: 288 case Mips::Select_FCC_D32: 289 isFPCmp = true; // FALL THROUGH 290 case Mips::Select_CC: 291 case Mips::Select_CC_SO32: 292 case Mips::Select_CC_AS32: 293 case Mips::Select_CC_D32: { 294 // To "insert" a SELECT_CC instruction, we actually have to insert the 295 // diamond control-flow pattern. The incoming instruction knows the 296 // destination vreg to set, the condition code register to branch on, the 297 // true/false values to select between, and a branch opcode to use. 298 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 299 MachineFunction::iterator It = BB; 300 ++It; 301 302 // thisMBB: 303 // ... 304 // TrueVal = ... 305 // setcc r1, r2, r3 306 // bNE r1, r0, copy1MBB 307 // fallthrough --> copy0MBB 308 MachineBasicBlock *thisMBB = BB; 309 MachineFunction *F = BB->getParent(); 310 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 311 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 312 313 // Emit the right instruction according to the type of the operands compared 314 if (isFPCmp) { 315 // Find the condiction code present in the setcc operation. 316 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm(); 317 // Get the branch opcode from the branch code. 318 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC)); 319 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); 320 } else 321 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) 322 .addReg(Mips::ZERO).addMBB(sinkMBB); 323 324 F->insert(It, copy0MBB); 325 F->insert(It, sinkMBB); 326 // Update machine-CFG edges by first adding all successors of the current 327 // block to the new block which will contain the Phi node for the select. 328 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 329 e = BB->succ_end(); i != e; ++i) 330 sinkMBB->addSuccessor(*i); 331 // Next, remove all successors of the current block, and add the true 332 // and fallthrough blocks as its successors. 333 while(!BB->succ_empty()) 334 BB->removeSuccessor(BB->succ_begin()); 335 BB->addSuccessor(copy0MBB); 336 BB->addSuccessor(sinkMBB); 337 338 // copy0MBB: 339 // %FalseValue = ... 340 // # fallthrough to sinkMBB 341 BB = copy0MBB; 342 343 // Update machine-CFG edges 344 BB->addSuccessor(sinkMBB); 345 346 // sinkMBB: 347 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 348 // ... 349 BB = sinkMBB; 350 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg()) 351 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 352 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB); 353 354 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 355 return BB; 356 } 357 } 358} 359 360//===----------------------------------------------------------------------===// 361// Misc Lower Operation implementation 362//===----------------------------------------------------------------------===// 363 364SDValue MipsTargetLowering:: 365LowerANDOR(SDValue Op, SelectionDAG &DAG) 366{ 367 SDValue LHS = Op.getOperand(0); 368 SDValue RHS = Op.getOperand(1); 369 370 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp) 371 return Op; 372 373 SDValue True = DAG.getConstant(1, MVT::i32); 374 SDValue False = DAG.getConstant(0, MVT::i32); 375 376 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), 377 LHS, True, False, LHS.getOperand(2)); 378 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), 379 RHS, True, False, RHS.getOperand(2)); 380 381 return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL); 382} 383 384SDValue MipsTargetLowering:: 385LowerBRCOND(SDValue Op, SelectionDAG &DAG) 386{ 387 // The first operand is the chain, the second is the condition, the third is 388 // the block to branch to if the condition is true. 389 SDValue Chain = Op.getOperand(0); 390 SDValue Dest = Op.getOperand(2); 391 392 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp) 393 return Op; 394 395 SDValue CondRes = Op.getOperand(1); 396 SDValue CCNode = CondRes.getOperand(2); 397 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue(); 398 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 399 400 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode, 401 Dest, CondRes); 402} 403 404SDValue MipsTargetLowering:: 405LowerSETCC(SDValue Op, SelectionDAG &DAG) 406{ 407 // The operands to this are the left and right operands to compare (ops #0, 408 // and #1) and the condition code to compare them with (op #2) as a 409 // CondCodeSDNode. 410 SDValue LHS = Op.getOperand(0); 411 SDValue RHS = Op.getOperand(1); 412 413 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 414 415 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS, 416 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 417} 418 419SDValue MipsTargetLowering:: 420LowerSELECT(SDValue Op, SelectionDAG &DAG) 421{ 422 SDValue Cond = Op.getOperand(0); 423 SDValue True = Op.getOperand(1); 424 SDValue False = Op.getOperand(2); 425 426 // if the incomming condition comes from fpcmp, the select 427 // operation must use FPSelectCC, otherwise SelectCC. 428 if (Cond.getOpcode() != MipsISD::FPCmp) 429 return DAG.getNode(MipsISD::SelectCC, True.getValueType(), 430 Cond, True, False); 431 432 SDValue CCNode = Cond.getOperand(2); 433 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(), 434 Cond, True, False, CCNode); 435} 436 437SDValue MipsTargetLowering:: 438LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) 439{ 440 SDValue LHS = Op.getOperand(0); 441 SDValue RHS = Op.getOperand(1); 442 SDValue True = Op.getOperand(2); 443 SDValue False = Op.getOperand(3); 444 SDValue CC = Op.getOperand(4); 445 446 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC); 447 return DAG.getNode(MipsISD::SelectCC, True.getValueType(), 448 SetCCRes, True, False); 449} 450 451SDValue MipsTargetLowering:: 452LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) 453{ 454 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 455 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 456 457 if (!Subtarget->hasABICall()) { 458 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); 459 SDValue Ops[] = { GA }; 460 // %gp_rel relocation 461 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) { 462 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1); 463 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); 464 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 465 } 466 // %hi/%lo relocation 467 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); 468 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); 469 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); 470 471 } else { // Abicall relocations, TODO: make this cleaner. 472 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0); 473 // On functions and global targets not internal linked only 474 // a load from got/GP is necessary for PIC to work. 475 if (!GV->hasInternalLinkage() || isa<Function>(GV)) 476 return ResNode; 477 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA); 478 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo); 479 } 480 481 assert(0 && "Dont know how to handle GlobalAddress"); 482 return SDValue(0,0); 483} 484 485SDValue MipsTargetLowering:: 486LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) 487{ 488 assert(0 && "TLS not implemented for MIPS."); 489 return SDValue(); // Not reached 490} 491 492SDValue MipsTargetLowering:: 493LowerJumpTable(SDValue Op, SelectionDAG &DAG) 494{ 495 SDValue ResNode; 496 SDValue HiPart; 497 498 MVT PtrVT = Op.getValueType(); 499 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 500 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 501 502 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 503 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32); 504 SDValue Ops[] = { JTI }; 505 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1); 506 } else // Emit Load from Global Pointer 507 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0); 508 509 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI); 510 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); 511 512 return ResNode; 513} 514 515SDValue MipsTargetLowering:: 516LowerConstantPool(SDValue Op, SelectionDAG &DAG) 517{ 518 SDValue ResNode; 519 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 520 Constant *C = N->getConstVal(); 521 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 522 523 // gp_rel relocation 524 // FIXME: we should reference the constant pool using small data sections, 525 // but the asm printer currently doens't support this feature without 526 // hacking it. This feature should come soon so we can uncomment the 527 // stuff below. 528 //if (!Subtarget->hasABICall() && 529 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) { 530 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 531 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32); 532 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 533 //} else { // %hi/%lo relocation 534 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP); 535 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP); 536 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo); 537 //} 538 539 return ResNode; 540} 541 542//===----------------------------------------------------------------------===// 543// Calling Convention Implementation 544// 545// The lower operations present on calling convention works on this order: 546// LowerCALL (virt regs --> phys regs, virt regs --> stack) 547// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs) 548// LowerRET (virt regs --> phys regs) 549// LowerCALL (phys regs --> virt regs) 550// 551//===----------------------------------------------------------------------===// 552 553#include "MipsGenCallingConv.inc" 554 555//===----------------------------------------------------------------------===// 556// CALL Calling Convention Implementation 557//===----------------------------------------------------------------------===// 558 559/// LowerCCCCallTo - functions arguments are copied from virtual 560/// regs to (physical regs)/(stack frame), CALLSEQ_START and 561/// CALLSEQ_END are emitted. 562/// TODO: isVarArg, isTailCall. 563SDValue MipsTargetLowering:: 564LowerCALL(SDValue Op, SelectionDAG &DAG) 565{ 566 MachineFunction &MF = DAG.getMachineFunction(); 567 568 SDValue Chain = Op.getOperand(0); 569 SDValue Callee = Op.getOperand(4); 570 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 571 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 572 573 MachineFrameInfo *MFI = MF.getFrameInfo(); 574 575 // Analyze operands of the call, assigning locations to each operand. 576 SmallVector<CCValAssign, 16> ArgLocs; 577 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 578 579 // To meet O32 ABI, Mips must always allocate 16 bytes on 580 // the stack (even if less than 4 are used as arguments) 581 if (Subtarget->isABI_O32()) { 582 int VTsize = MVT(MVT::i32).getSizeInBits()/8; 583 MFI->CreateFixedObject(VTsize, (VTsize*3)); 584 } 585 586 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips); 587 588 // Get a count of how many bytes are to be pushed on the stack. 589 unsigned NumBytes = CCInfo.getNextStackOffset(); 590 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 591 getPointerTy())); 592 593 // With EABI is it possible to have 16 args on registers. 594 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 595 SmallVector<SDValue, 8> MemOpChains; 596 597 // First/LastArgStackLoc contains the first/last 598 // "at stack" argument location. 599 int LastArgStackLoc = 0; 600 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16); 601 602 // Walk the register/memloc assignments, inserting copies/loads. 603 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 604 CCValAssign &VA = ArgLocs[i]; 605 606 // Arguments start after the 5 first operands of ISD::CALL 607 SDValue Arg = Op.getOperand(5+2*VA.getValNo()); 608 609 // Promote the value if needed. 610 switch (VA.getLocInfo()) { 611 default: assert(0 && "Unknown loc info!"); 612 case CCValAssign::Full: break; 613 case CCValAssign::SExt: 614 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 615 break; 616 case CCValAssign::ZExt: 617 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 618 break; 619 case CCValAssign::AExt: 620 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 621 break; 622 } 623 624 // Arguments that can be passed on register must be kept at 625 // RegsToPass vector 626 if (VA.isRegLoc()) { 627 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 628 continue; 629 } 630 631 // Register cant get to this point... 632 assert(VA.isMemLoc()); 633 634 // Create the frame index object for this incoming parameter 635 // This guarantees that when allocating Local Area the firsts 636 // 16 bytes which are alwayes reserved won't be overwritten 637 // if O32 ABI is used. For EABI the first address is zero. 638 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset()); 639 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 640 LastArgStackLoc); 641 642 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy()); 643 644 // emit ISD::STORE whichs stores the 645 // parameter value to a stack Location 646 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 647 } 648 649 // Transform all store nodes into one single node because all store 650 // nodes are independent of each other. 651 if (!MemOpChains.empty()) 652 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 653 &MemOpChains[0], MemOpChains.size()); 654 655 // Build a sequence of copy-to-reg nodes chained together with token 656 // chain and flag operands which copy the outgoing args into registers. 657 // The InFlag in necessary since all emited instructions must be 658 // stuck together. 659 SDValue InFlag; 660 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 661 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, 662 RegsToPass[i].second, InFlag); 663 InFlag = Chain.getValue(1); 664 } 665 666 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 667 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 668 // node so that legalize doesn't hack it. 669 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 670 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 671 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 672 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 673 674 675 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 676 // = Chain, Callee, Reg#1, Reg#2, ... 677 // 678 // Returns a chain & a flag for retval copy to use. 679 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 680 SmallVector<SDValue, 8> Ops; 681 Ops.push_back(Chain); 682 Ops.push_back(Callee); 683 684 // Add argument registers to the end of the list so that they are 685 // known live into the call. 686 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 687 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 688 RegsToPass[i].second.getValueType())); 689 690 if (InFlag.Val) 691 Ops.push_back(InFlag); 692 693 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size()); 694 InFlag = Chain.getValue(1); 695 696 // Create the CALLSEQ_END node. 697 Chain = DAG.getCALLSEQ_END(Chain, 698 DAG.getConstant(NumBytes, getPointerTy()), 699 DAG.getConstant(0, getPointerTy()), 700 InFlag); 701 InFlag = Chain.getValue(1); 702 703 // Create a stack location to hold GP when PIC is used. This stack 704 // location is used on function prologue to save GP and also after all 705 // emited CALL's to restore GP. 706 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 707 // Function can have an arbitrary number of calls, so 708 // hold the LastArgStackLoc with the biggest offset. 709 int FI; 710 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 711 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) { 712 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4); 713 // Create the frame index only once. SPOffset here can be anything 714 // (this will be fixed on processFunctionBeforeFrameFinalized) 715 if (MipsFI->getGPStackOffset() == -1) { 716 FI = MFI->CreateFixedObject(4, 0); 717 MipsFI->setGPFI(FI); 718 } 719 MipsFI->setGPStackOffset(LastArgStackLoc); 720 } 721 722 // Reload GP value. 723 FI = MipsFI->getGPFI(); 724 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy()); 725 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0); 726 Chain = GPLoad.getValue(1); 727 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32), 728 GPLoad, SDValue(0,0)); 729 InFlag = Chain.getValue(1); 730 } 731 732 // Handle result values, copying them out of physregs into vregs that we 733 // return. 734 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 735} 736 737/// LowerCallResult - Lower the result values of an ISD::CALL into the 738/// appropriate copies out of appropriate physical registers. This assumes that 739/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 740/// being lowered. Returns a SDNode with the same number of values as the 741/// ISD::CALL. 742SDNode *MipsTargetLowering:: 743LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall, 744 unsigned CallingConv, SelectionDAG &DAG) { 745 746 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; 747 748 // Assign locations to each value returned by this call. 749 SmallVector<CCValAssign, 16> RVLocs; 750 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 751 752 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips); 753 SmallVector<SDValue, 8> ResultVals; 754 755 // Copy all of the result registers out of their specified physreg. 756 for (unsigned i = 0; i != RVLocs.size(); ++i) { 757 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 758 RVLocs[i].getValVT(), InFlag).getValue(1); 759 InFlag = Chain.getValue(2); 760 ResultVals.push_back(Chain.getValue(0)); 761 } 762 763 ResultVals.push_back(Chain); 764 765 // Merge everything together with a MERGE_VALUES node. 766 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], 767 ResultVals.size()).Val; 768} 769 770//===----------------------------------------------------------------------===// 771// FORMAL_ARGUMENTS Calling Convention Implementation 772//===----------------------------------------------------------------------===// 773 774/// LowerFORMAL_ARGUMENTS - transform physical registers into 775/// virtual registers and generate load operations for 776/// arguments places on the stack. 777/// TODO: isVarArg 778SDValue MipsTargetLowering:: 779LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) 780{ 781 SDValue Root = Op.getOperand(0); 782 MachineFunction &MF = DAG.getMachineFunction(); 783 MachineFrameInfo *MFI = MF.getFrameInfo(); 784 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 785 786 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 787 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 788 789 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF); 790 791 // GP must be live into PIC and non-PIC call target. 792 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass); 793 794 // Assign locations to all of the incoming arguments. 795 SmallVector<CCValAssign, 16> ArgLocs; 796 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 797 798 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips); 799 SmallVector<SDValue, 16> ArgValues; 800 SDValue StackPtr; 801 802 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16); 803 804 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 805 806 CCValAssign &VA = ArgLocs[i]; 807 808 // Arguments stored on registers 809 if (VA.isRegLoc()) { 810 MVT RegVT = VA.getLocVT(); 811 TargetRegisterClass *RC = 0; 812 813 if (RegVT == MVT::i32) 814 RC = Mips::CPURegsRegisterClass; 815 else if (RegVT == MVT::f32) { 816 if (Subtarget->isSingleFloat()) 817 RC = Mips::FGR32RegisterClass; 818 else 819 RC = Mips::AFGR32RegisterClass; 820 } else if (RegVT == MVT::f64) { 821 if (!Subtarget->isSingleFloat()) 822 RC = Mips::AFGR64RegisterClass; 823 } else 824 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering"); 825 826 // Transform the arguments stored on 827 // physical registers into virtual ones 828 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 829 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 830 831 // If this is an 8 or 16-bit value, it is really passed promoted 832 // to 32 bits. Insert an assert[sz]ext to capture this, then 833 // truncate to the right size. 834 if (VA.getLocInfo() == CCValAssign::SExt) 835 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 836 DAG.getValueType(VA.getValVT())); 837 else if (VA.getLocInfo() == CCValAssign::ZExt) 838 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 839 DAG.getValueType(VA.getValVT())); 840 841 if (VA.getLocInfo() != CCValAssign::Full) 842 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 843 844 ArgValues.push_back(ArgValue); 845 846 // To meet ABI, when VARARGS are passed on registers, the registers 847 // must have their values written to the caller stack frame. 848 if ((isVarArg) && (Subtarget->isABI_O32())) { 849 if (StackPtr.Val == 0) 850 StackPtr = DAG.getRegister(StackReg, getPointerTy()); 851 852 // The stack pointer offset is relative to the caller stack frame. 853 // Since the real stack size is unknown here, a negative SPOffset 854 // is used so there's a way to adjust these offsets when the stack 855 // size get known (on EliminateFrameIndex). A dummy SPOffset is 856 // used instead of a direct negative address (which is recorded to 857 // be used on emitPrologue) to avoid mis-calc of the first stack 858 // offset on PEI::calculateFrameObjectOffsets. 859 // Arguments are always 32-bit. 860 int FI = MFI->CreateFixedObject(4, 0); 861 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4))); 862 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 863 864 // emit ISD::STORE whichs stores the 865 // parameter value to a stack Location 866 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0)); 867 } 868 869 } else { // VA.isRegLoc() 870 871 // sanity check 872 assert(VA.isMemLoc()); 873 874 // The stack pointer offset is relative to the caller stack frame. 875 // Since the real stack size is unknown here, a negative SPOffset 876 // is used so there's a way to adjust these offsets when the stack 877 // size get known (on EliminateFrameIndex). A dummy SPOffset is 878 // used instead of a direct negative address (which is recorded to 879 // be used on emitPrologue) to avoid mis-calc of the first stack 880 // offset on PEI::calculateFrameObjectOffsets. 881 // Arguments are always 32-bit. 882 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 883 int FI = MFI->CreateFixedObject(ArgSize, 0); 884 MipsFI->recordLoadArgsFI(FI, -(ArgSize+ 885 (FirstStackArgLoc + VA.getLocMemOffset()))); 886 887 // Create load nodes to retrieve arguments from the stack 888 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 889 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0)); 890 } 891 } 892 893 // The mips ABIs for returning structs by value requires that we copy 894 // the sret argument into $v0 for the return. Save the argument into 895 // a virtual register so that we can access it from the return points. 896 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 897 unsigned Reg = MipsFI->getSRetReturnReg(); 898 if (!Reg) { 899 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 900 MipsFI->setSRetReturnReg(Reg); 901 } 902 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); 903 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); 904 } 905 906 ArgValues.push_back(Root); 907 908 // Return the new list of results. 909 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], 910 ArgValues.size()).getValue(Op.ResNo); 911} 912 913//===----------------------------------------------------------------------===// 914// Return Value Calling Convention Implementation 915//===----------------------------------------------------------------------===// 916 917SDValue MipsTargetLowering:: 918LowerRET(SDValue Op, SelectionDAG &DAG) 919{ 920 // CCValAssign - represent the assignment of 921 // the return value to a location 922 SmallVector<CCValAssign, 16> RVLocs; 923 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 924 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 925 926 // CCState - Info about the registers and stack slot. 927 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 928 929 // Analize return values of ISD::RET 930 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips); 931 932 // If this is the first return lowered for this function, add 933 // the regs to the liveout set for the function. 934 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 935 for (unsigned i = 0; i != RVLocs.size(); ++i) 936 if (RVLocs[i].isRegLoc()) 937 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 938 } 939 940 // The chain is always operand #0 941 SDValue Chain = Op.getOperand(0); 942 SDValue Flag; 943 944 // Copy the result values into the output registers. 945 for (unsigned i = 0; i != RVLocs.size(); ++i) { 946 CCValAssign &VA = RVLocs[i]; 947 assert(VA.isRegLoc() && "Can only return in registers!"); 948 949 // ISD::RET => ret chain, (regnum1,val1), ... 950 // So i*2+1 index only the regnums 951 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 952 953 // guarantee that all emitted copies are 954 // stuck together, avoiding something bad 955 Flag = Chain.getValue(1); 956 } 957 958 // The mips ABIs for returning structs by value requires that we copy 959 // the sret argument into $v0 for the return. We saved the argument into 960 // a virtual register in the entry block, so now we copy the value out 961 // and into $v0. 962 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 963 MachineFunction &MF = DAG.getMachineFunction(); 964 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 965 unsigned Reg = MipsFI->getSRetReturnReg(); 966 967 if (!Reg) 968 assert(0 && "sret virtual register not created in the entry block"); 969 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); 970 971 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag); 972 Flag = Chain.getValue(1); 973 } 974 975 // Return on Mips is always a "jr $ra" 976 if (Flag.Val) 977 return DAG.getNode(MipsISD::Ret, MVT::Other, 978 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 979 else // Return Void 980 return DAG.getNode(MipsISD::Ret, MVT::Other, 981 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 982} 983 984//===----------------------------------------------------------------------===// 985// Mips Inline Assembly Support 986//===----------------------------------------------------------------------===// 987 988/// getConstraintType - Given a constraint letter, return the type of 989/// constraint it is for this target. 990MipsTargetLowering::ConstraintType MipsTargetLowering:: 991getConstraintType(const std::string &Constraint) const 992{ 993 // Mips specific constrainy 994 // GCC config/mips/constraints.md 995 // 996 // 'd' : An address register. Equivalent to r 997 // unless generating MIPS16 code. 998 // 'y' : Equivalent to r; retained for 999 // backwards compatibility. 1000 // 'f' : Floating Point registers. 1001 if (Constraint.size() == 1) { 1002 switch (Constraint[0]) { 1003 default : break; 1004 case 'd': 1005 case 'y': 1006 case 'f': 1007 return C_RegisterClass; 1008 break; 1009 } 1010 } 1011 return TargetLowering::getConstraintType(Constraint); 1012} 1013 1014/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1015/// return a list of registers that can be used to satisfy the constraint. 1016/// This should only be used for C_RegisterClass constraints. 1017std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 1018getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 1019{ 1020 if (Constraint.size() == 1) { 1021 switch (Constraint[0]) { 1022 case 'r': 1023 return std::make_pair(0U, Mips::CPURegsRegisterClass); 1024 case 'f': 1025 if (VT == MVT::f32) { 1026 if (Subtarget->isSingleFloat()) 1027 return std::make_pair(0U, Mips::FGR32RegisterClass); 1028 else 1029 return std::make_pair(0U, Mips::AFGR32RegisterClass); 1030 } 1031 if (VT == MVT::f64) 1032 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1033 return std::make_pair(0U, Mips::AFGR64RegisterClass); 1034 } 1035 } 1036 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1037} 1038 1039/// Given a register class constraint, like 'r', if this corresponds directly 1040/// to an LLVM register class, return a register of 0 and the register class 1041/// pointer. 1042std::vector<unsigned> MipsTargetLowering:: 1043getRegClassForInlineAsmConstraint(const std::string &Constraint, 1044 MVT VT) const 1045{ 1046 if (Constraint.size() != 1) 1047 return std::vector<unsigned>(); 1048 1049 switch (Constraint[0]) { 1050 default : break; 1051 case 'r': 1052 // GCC Mips Constraint Letters 1053 case 'd': 1054 case 'y': 1055 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3, 1056 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, 1057 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, 1058 Mips::T8, 0); 1059 1060 case 'f': 1061 if (VT == MVT::f32) { 1062 if (Subtarget->isSingleFloat()) 1063 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5, 1064 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, 1065 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, 1066 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, 1067 Mips::F30, Mips::F31, 0); 1068 else 1069 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8, 1070 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26, 1071 Mips::F28, Mips::F30, 0); 1072 } 1073 1074 if (VT == MVT::f64) 1075 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 1076 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4, 1077 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13, 1078 Mips::D14, Mips::D15, 0); 1079 } 1080 return std::vector<unsigned>(); 1081} 1082