PPCInstrInfo.h revision 44eb65cf58e3ab9b5621ce72256d1621a18aeed7
1//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PowerPC implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef POWERPC32_INSTRUCTIONINFO_H 15#define POWERPC32_INSTRUCTIONINFO_H 16 17#include "PPC.h" 18#include "llvm/Target/TargetInstrInfo.h" 19#include "PPCRegisterInfo.h" 20 21namespace llvm { 22 23/// PPCII - This namespace holds all of the PowerPC target-specific 24/// per-instruction flags. These must match the corresponding definitions in 25/// PPC.td and PPCInstrFormats.td. 26namespace PPCII { 27enum { 28 // PPC970 Instruction Flags. These flags describe the characteristics of the 29 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 30 // raw machine instructions. 31 32 /// PPC970_First - This instruction starts a new dispatch group, so it will 33 /// always be the first one in the group. 34 PPC970_First = 0x1, 35 36 /// PPC970_Single - This instruction starts a new dispatch group and 37 /// terminates it, so it will be the sole instruction in the group. 38 PPC970_Single = 0x2, 39 40 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 41 /// two dispatch pipes to be available to issue. 42 PPC970_Cracked = 0x4, 43 44 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 45 /// an instruction is issued to. 46 PPC970_Shift = 3, 47 PPC970_Mask = 0x07 << PPC970_Shift 48}; 49enum PPC970_Unit { 50 /// These are the various PPC970 execution unit pipelines. Each instruction 51 /// is one of these. 52 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 53 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 54 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 55 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 56 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 57 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 58 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 59 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 60}; 61} 62 63 64class PPCInstrInfo : public TargetInstrInfoImpl { 65 PPCTargetMachine &TM; 66 const PPCRegisterInfo RI; 67 68 bool StoreRegToStackSlot(MachineFunction &MF, 69 unsigned SrcReg, bool isKill, int FrameIdx, 70 const TargetRegisterClass *RC, 71 SmallVectorImpl<MachineInstr*> &NewMIs) const; 72 void LoadRegFromStackSlot(MachineFunction &MF, 73 unsigned DestReg, int FrameIdx, 74 const TargetRegisterClass *RC, 75 SmallVectorImpl<MachineInstr*> &NewMIs) const; 76public: 77 explicit PPCInstrInfo(PPCTargetMachine &TM); 78 79 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 80 /// such, whenever a client has an instance of instruction info, it should 81 /// always be able to get register info as well (through this method). 82 /// 83 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 84 85 /// getPointerRegClass - Return the register class to use to hold pointers. 86 /// This is used for addressing modes. 87 virtual const TargetRegisterClass *getPointerRegClass() const; 88 89 // Return true if the instruction is a register to register move and 90 // leave the source and dest operands in the passed parameters. 91 // 92 virtual bool isMoveInstr(const MachineInstr& MI, 93 unsigned& sourceReg, 94 unsigned& destReg) const; 95 96 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; 97 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; 98 99 // commuteInstruction - We can commute rlwimi instructions, but only if the 100 // rotate amt is zero. We also have to munge the immediates a bit. 101 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 102 103 virtual void insertNoop(MachineBasicBlock &MBB, 104 MachineBasicBlock::iterator MI) const; 105 106 107 // Branch analysis. 108 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 109 MachineBasicBlock *&FBB, 110 SmallVectorImpl<MachineOperand> &Cond) const; 111 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 112 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 113 MachineBasicBlock *FBB, 114 const SmallVectorImpl<MachineOperand> &Cond) const; 115 virtual void copyRegToReg(MachineBasicBlock &MBB, 116 MachineBasicBlock::iterator MI, 117 unsigned DestReg, unsigned SrcReg, 118 const TargetRegisterClass *DestRC, 119 const TargetRegisterClass *SrcRC) const; 120 121 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 122 MachineBasicBlock::iterator MBBI, 123 unsigned SrcReg, bool isKill, int FrameIndex, 124 const TargetRegisterClass *RC) const; 125 126 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 127 SmallVectorImpl<MachineOperand> &Addr, 128 const TargetRegisterClass *RC, 129 SmallVectorImpl<MachineInstr*> &NewMIs) const; 130 131 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 132 MachineBasicBlock::iterator MBBI, 133 unsigned DestReg, int FrameIndex, 134 const TargetRegisterClass *RC) const; 135 136 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 137 SmallVectorImpl<MachineOperand> &Addr, 138 const TargetRegisterClass *RC, 139 SmallVectorImpl<MachineInstr*> &NewMIs) const; 140 141 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 142 /// copy instructions, turning them into load/store instructions. 143 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 144 MachineInstr* MI, 145 SmallVectorImpl<unsigned> &Ops, 146 int FrameIndex) const; 147 148 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 149 MachineInstr* MI, 150 SmallVectorImpl<unsigned> &Ops, 151 MachineInstr* LoadMI) const { 152 return 0; 153 } 154 155 virtual bool canFoldMemoryOperand(MachineInstr *MI, 156 SmallVectorImpl<unsigned> &Ops) const; 157 158 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; 159 virtual 160 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 161 162 /// GetInstSize - Return the number of bytes of code the specified 163 /// instruction may be. This returns the maximum number of bytes. 164 /// 165 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 166}; 167 168} 169 170#endif 171