PPCInstrInfo.h revision 770bcc7b15adbc978800db70dbb1c3c22913b52c 
1//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPC32_INSTRUCTIONINFO_H
15#define POWERPC32_INSTRUCTIONINFO_H
16
17#include "PPC.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "PPCRegisterInfo.h"
20
21namespace llvm {
22
23/// PPCII - This namespace holds all of the PowerPC target-specific
24/// per-instruction flags.  These must match the corresponding definitions in
25/// PPC.td and PPCInstrFormats.td.
26namespace PPCII {
27enum {
28  // PPC970 Instruction Flags.  These flags describe the characteristics of the
29  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
30  // raw machine instructions.
31
32  /// PPC970_First - This instruction starts a new dispatch group, so it will
33  /// always be the first one in the group.
34  PPC970_First = 0x1,
35
36  /// PPC970_Single - This instruction starts a new dispatch group and
37  /// terminates it, so it will be the sole instruction in the group.
38  PPC970_Single = 0x2,
39
40  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
41  /// two dispatch pipes to be available to issue.
42  PPC970_Cracked = 0x4,
43
44  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
45  /// an instruction is issued to.
46  PPC970_Shift = 3,
47  PPC970_Mask = 0x07 << PPC970_Shift
48};
49enum PPC970_Unit {
50  /// These are the various PPC970 execution unit pipelines.  Each instruction
51  /// is one of these.
52  PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
53  PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
54  PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
55  PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
56  PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
57  PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
58  PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
59  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
60};
61}
62
63
64class PPCInstrInfo : public TargetInstrInfoImpl {
65  PPCTargetMachine &TM;
66  const PPCRegisterInfo RI;
67
68  bool StoreRegToStackSlot(MachineFunction &MF,
69                           unsigned SrcReg, bool isKill, int FrameIdx,
70                           const TargetRegisterClass *RC,
71                           SmallVectorImpl<MachineInstr*> &NewMIs) const;
72  void LoadRegFromStackSlot(MachineFunction &MF,
73                            unsigned DestReg, int FrameIdx,
74                            const TargetRegisterClass *RC,
75                            SmallVectorImpl<MachineInstr*> &NewMIs) const;
76public:
77  explicit PPCInstrInfo(PPCTargetMachine &TM);
78
79  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
80  /// such, whenever a client has an instance of instruction info, it should
81  /// always be able to get register info as well (through this method).
82  ///
83  virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
84
85  /// Return true if the instruction is a register to register move and return
86  /// the source and dest operands and their sub-register indices by reference.
87  virtual bool isMoveInstr(const MachineInstr &MI,
88                           unsigned &SrcReg, unsigned &DstReg,
89                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
90
91  unsigned isLoadFromStackSlot(const MachineInstr *MI,
92                               int &FrameIndex) const;
93  unsigned isStoreToStackSlot(const MachineInstr *MI,
94                              int &FrameIndex) const;
95
96  // commuteInstruction - We can commute rlwimi instructions, but only if the
97  // rotate amt is zero.  We also have to munge the immediates a bit.
98  virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
99
100  virtual void insertNoop(MachineBasicBlock &MBB,
101                          MachineBasicBlock::iterator MI) const;
102
103
104  // Branch analysis.
105  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
106                             MachineBasicBlock *&FBB,
107                             SmallVectorImpl<MachineOperand> &Cond) const;
108  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
109  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
110                                MachineBasicBlock *FBB,
111                            const SmallVectorImpl<MachineOperand> &Cond) const;
112  virtual bool copyRegToReg(MachineBasicBlock &MBB,
113                            MachineBasicBlock::iterator MI,
114                            unsigned DestReg, unsigned SrcReg,
115                            const TargetRegisterClass *DestRC,
116                            const TargetRegisterClass *SrcRC) const;
117
118  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
119                                   MachineBasicBlock::iterator MBBI,
120                                   unsigned SrcReg, bool isKill, int FrameIndex,
121                                   const TargetRegisterClass *RC) const;
122
123  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
124                              SmallVectorImpl<MachineOperand> &Addr,
125                              const TargetRegisterClass *RC,
126                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
127
128  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
129                                    MachineBasicBlock::iterator MBBI,
130                                    unsigned DestReg, int FrameIndex,
131                                    const TargetRegisterClass *RC) const;
132
133  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
134                               SmallVectorImpl<MachineOperand> &Addr,
135                               const TargetRegisterClass *RC,
136                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
137
138  /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
139  /// copy instructions, turning them into load/store instructions.
140  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
141                                              MachineInstr* MI,
142                                              const SmallVectorImpl<unsigned> &Ops,
143                                              int FrameIndex) const;
144
145  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
146                                              MachineInstr* MI,
147                                              const SmallVectorImpl<unsigned> &Ops,
148                                              MachineInstr* LoadMI) const {
149    return 0;
150  }
151
152  virtual bool canFoldMemoryOperand(const MachineInstr *MI,
153                                    const SmallVectorImpl<unsigned> &Ops) const;
154
155  virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
156  virtual
157  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
158
159  /// GetInstSize - Return the number of bytes of code the specified
160  /// instruction may be.  This returns the maximum number of bytes.
161  ///
162  virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
163};
164
165}
166
167#endif
168