PPCInstrInfo.h revision d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 
1//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPC32_INSTRUCTIONINFO_H
15#define POWERPC32_INSTRUCTIONINFO_H
16
17#include "PPC.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "PPCRegisterInfo.h"
20
21namespace llvm {
22
23/// PPCII - This namespace holds all of the PowerPC target-specific
24/// per-instruction flags.  These must match the corresponding definitions in
25/// PPC.td and PPCInstrFormats.td.
26namespace PPCII {
27enum {
28  // PPC970 Instruction Flags.  These flags describe the characteristics of the
29  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
30  // raw machine instructions.
31
32  /// PPC970_First - This instruction starts a new dispatch group, so it will
33  /// always be the first one in the group.
34  PPC970_First = 0x1,
35
36  /// PPC970_Single - This instruction starts a new dispatch group and
37  /// terminates it, so it will be the sole instruction in the group.
38  PPC970_Single = 0x2,
39
40  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
41  /// two dispatch pipes to be available to issue.
42  PPC970_Cracked = 0x4,
43
44  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
45  /// an instruction is issued to.
46  PPC970_Shift = 3,
47  PPC970_Mask = 0x07 << PPC970_Shift
48};
49enum PPC970_Unit {
50  /// These are the various PPC970 execution unit pipelines.  Each instruction
51  /// is one of these.
52  PPC970_Pseudo = 0 << PPC970_Shift,   // Pseudo instruction
53  PPC970_FXU    = 1 << PPC970_Shift,   // Fixed Point (aka Integer/ALU) Unit
54  PPC970_LSU    = 2 << PPC970_Shift,   // Load Store Unit
55  PPC970_FPU    = 3 << PPC970_Shift,   // Floating Point Unit
56  PPC970_CRU    = 4 << PPC970_Shift,   // Control Register Unit
57  PPC970_VALU   = 5 << PPC970_Shift,   // Vector ALU
58  PPC970_VPERM  = 6 << PPC970_Shift,   // Vector Permute Unit
59  PPC970_BRU    = 7 << PPC970_Shift    // Branch Unit
60};
61}
62
63
64class PPCInstrInfo : public TargetInstrInfo {
65  PPCTargetMachine &TM;
66  const PPCRegisterInfo RI;
67public:
68  PPCInstrInfo(PPCTargetMachine &TM);
69
70  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
71  /// such, whenever a client has an instance of instruction info, it should
72  /// always be able to get register info as well (through this method).
73  ///
74  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
75
76  /// getPointerRegClass - Return the register class to use to hold pointers.
77  /// This is used for addressing modes.
78  virtual const TargetRegisterClass *getPointerRegClass() const;
79
80  // Return true if the instruction is a register to register move and
81  // leave the source and dest operands in the passed parameters.
82  //
83  virtual bool isMoveInstr(const MachineInstr& MI,
84                           unsigned& sourceReg,
85                           unsigned& destReg) const;
86
87  unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
88  unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
89
90  // commuteInstruction - We can commute rlwimi instructions, but only if the
91  // rotate amt is zero.  We also have to munge the immediates a bit.
92  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
93
94  virtual void insertNoop(MachineBasicBlock &MBB,
95                          MachineBasicBlock::iterator MI) const;
96
97
98  // Branch analysis.
99  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
100                             MachineBasicBlock *&FBB,
101                             std::vector<MachineOperand> &Cond) const;
102  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
103  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
104                                MachineBasicBlock *FBB,
105                                const std::vector<MachineOperand> &Cond) const;
106  void copyRegToReg(MachineBasicBlock &MBB,
107                    MachineBasicBlock::iterator MI,
108                    unsigned DestReg, unsigned SrcReg,
109                    const TargetRegisterClass *DestRC,
110                    const TargetRegisterClass *SrcRC) const;
111  virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
112  virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
113};
114
115}
116
117#endif
118