X86FastISel.cpp revision 7e7f06e70a07be4a5fad81883da6bebf33e1b3f6
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Instructions.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/CodeGen/FastISel.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/Support/CallSite.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/GetElementPtrTypeIterator.h" 34#include "llvm/Target/TargetOptions.h" 35using namespace llvm; 36 37namespace { 38 39class X86FastISel : public FastISel { 40 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 41 /// make the right decision when generating code for different targets. 42 const X86Subtarget *Subtarget; 43 44 /// StackPtr - Register used as the stack pointer. 45 /// 46 unsigned StackPtr; 47 48 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 49 /// floating point ops. 50 /// When SSE is available, use it for f32 operations. 51 /// When SSE2 is available, use it for f64 operations. 52 bool X86ScalarSSEf64; 53 bool X86ScalarSSEf32; 54 55public: 56 explicit X86FastISel(MachineFunction &mf, 57 MachineModuleInfo *mmi, 58 DwarfWriter *dw, 59 DenseMap<const Value *, unsigned> &vm, 60 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 61 DenseMap<const AllocaInst *, int> &am 62#ifndef NDEBUG 63 , SmallSet<Instruction*, 8> &cil 64#endif 65 ) 66 : FastISel(mf, mmi, dw, vm, bm, am 67#ifndef NDEBUG 68 , cil 69#endif 70 ) { 71 Subtarget = &TM.getSubtarget<X86Subtarget>(); 72 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 73 X86ScalarSSEf64 = Subtarget->hasSSE2(); 74 X86ScalarSSEf32 = Subtarget->hasSSE1(); 75 } 76 77 virtual bool TargetSelectInstruction(Instruction *I); 78 79#include "X86GenFastISel.inc" 80 81private: 82 bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT); 83 84 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 85 86 bool X86FastEmitStore(EVT VT, Value *Val, 87 const X86AddressMode &AM); 88 bool X86FastEmitStore(EVT VT, unsigned Val, 89 const X86AddressMode &AM); 90 91 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 92 unsigned &ResultReg); 93 94 bool X86SelectAddress(Value *V, X86AddressMode &AM); 95 bool X86SelectCallAddress(Value *V, X86AddressMode &AM); 96 97 bool X86SelectLoad(Instruction *I); 98 99 bool X86SelectStore(Instruction *I); 100 101 bool X86SelectCmp(Instruction *I); 102 103 bool X86SelectZExt(Instruction *I); 104 105 bool X86SelectBranch(Instruction *I); 106 107 bool X86SelectShift(Instruction *I); 108 109 bool X86SelectSelect(Instruction *I); 110 111 bool X86SelectTrunc(Instruction *I); 112 113 bool X86SelectFPExt(Instruction *I); 114 bool X86SelectFPTrunc(Instruction *I); 115 116 bool X86SelectExtractValue(Instruction *I); 117 118 bool X86VisitIntrinsicCall(IntrinsicInst &I); 119 bool X86SelectCall(Instruction *I); 120 121 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false); 122 123 const X86InstrInfo *getInstrInfo() const { 124 return getTargetMachine()->getInstrInfo(); 125 } 126 const X86TargetMachine *getTargetMachine() const { 127 return static_cast<const X86TargetMachine *>(&TM); 128 } 129 130 unsigned TargetMaterializeConstant(Constant *C); 131 132 unsigned TargetMaterializeAlloca(AllocaInst *C); 133 134 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 135 /// computed in an SSE register, not on the X87 floating point stack. 136 bool isScalarFPTypeInSSEReg(EVT VT) const { 137 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 138 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 139 } 140 141 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); 142}; 143 144} // end anonymous namespace. 145 146bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { 147 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 148 if (VT == MVT::Other || !VT.isSimple()) 149 // Unhandled type. Halt "fast" selection and bail. 150 return false; 151 152 // For now, require SSE/SSE2 for performing floating-point operations, 153 // since x87 requires additional work. 154 if (VT == MVT::f64 && !X86ScalarSSEf64) 155 return false; 156 if (VT == MVT::f32 && !X86ScalarSSEf32) 157 return false; 158 // Similarly, no f80 support yet. 159 if (VT == MVT::f80) 160 return false; 161 // We only handle legal types. For example, on x86-32 the instruction 162 // selector contains all of the 64-bit instructions from x86-64, 163 // under the assumption that i64 won't be used if the target doesn't 164 // support it. 165 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 166} 167 168#include "X86GenCallingConv.inc" 169 170/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 171/// convention. 172CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) { 173 if (Subtarget->is64Bit()) { 174 if (Subtarget->isTargetWin64()) 175 return CC_X86_Win64_C; 176 else 177 return CC_X86_64_C; 178 } 179 180 if (CC == CallingConv::X86_FastCall) 181 return CC_X86_32_FastCall; 182 else if (CC == CallingConv::Fast) 183 return CC_X86_32_FastCC; 184 else 185 return CC_X86_32_C; 186} 187 188/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 189/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 190/// Return true and the result register by reference if it is possible. 191bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 192 unsigned &ResultReg) { 193 // Get opcode and regclass of the output for the given load instruction. 194 unsigned Opc = 0; 195 const TargetRegisterClass *RC = NULL; 196 switch (VT.getSimpleVT().SimpleTy) { 197 default: return false; 198 case MVT::i1: 199 case MVT::i8: 200 Opc = X86::MOV8rm; 201 RC = X86::GR8RegisterClass; 202 break; 203 case MVT::i16: 204 Opc = X86::MOV16rm; 205 RC = X86::GR16RegisterClass; 206 break; 207 case MVT::i32: 208 Opc = X86::MOV32rm; 209 RC = X86::GR32RegisterClass; 210 break; 211 case MVT::i64: 212 // Must be in x86-64 mode. 213 Opc = X86::MOV64rm; 214 RC = X86::GR64RegisterClass; 215 break; 216 case MVT::f32: 217 if (Subtarget->hasSSE1()) { 218 Opc = X86::MOVSSrm; 219 RC = X86::FR32RegisterClass; 220 } else { 221 Opc = X86::LD_Fp32m; 222 RC = X86::RFP32RegisterClass; 223 } 224 break; 225 case MVT::f64: 226 if (Subtarget->hasSSE2()) { 227 Opc = X86::MOVSDrm; 228 RC = X86::FR64RegisterClass; 229 } else { 230 Opc = X86::LD_Fp64m; 231 RC = X86::RFP64RegisterClass; 232 } 233 break; 234 case MVT::f80: 235 // No f80 support yet. 236 return false; 237 } 238 239 ResultReg = createResultReg(RC); 240 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 241 return true; 242} 243 244/// X86FastEmitStore - Emit a machine instruction to store a value Val of 245/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 246/// and a displacement offset, or a GlobalAddress, 247/// i.e. V. Return true if it is possible. 248bool 249X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, 250 const X86AddressMode &AM) { 251 // Get opcode and regclass of the output for the given store instruction. 252 unsigned Opc = 0; 253 switch (VT.getSimpleVT().SimpleTy) { 254 case MVT::f80: // No f80 support yet. 255 default: return false; 256 case MVT::i1: { 257 // Mask out all but lowest bit. 258 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 259 BuildMI(MBB, DL, 260 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 261 Val = AndResult; 262 } 263 // FALLTHROUGH, handling i1 as i8. 264 case MVT::i8: Opc = X86::MOV8mr; break; 265 case MVT::i16: Opc = X86::MOV16mr; break; 266 case MVT::i32: Opc = X86::MOV32mr; break; 267 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 268 case MVT::f32: 269 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 270 break; 271 case MVT::f64: 272 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 273 break; 274 } 275 276 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); 277 return true; 278} 279 280bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, 281 const X86AddressMode &AM) { 282 // Handle 'null' like i32/i64 0. 283 if (isa<ConstantPointerNull>(Val)) 284 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 285 286 // If this is a store of a simple constant, fold the constant into the store. 287 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 288 unsigned Opc = 0; 289 bool Signed = true; 290 switch (VT.getSimpleVT().SimpleTy) { 291 default: break; 292 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 293 case MVT::i8: Opc = X86::MOV8mi; break; 294 case MVT::i16: Opc = X86::MOV16mi; break; 295 case MVT::i32: Opc = X86::MOV32mi; break; 296 case MVT::i64: 297 // Must be a 32-bit sign extended value. 298 if ((int)CI->getSExtValue() == CI->getSExtValue()) 299 Opc = X86::MOV64mi32; 300 break; 301 } 302 303 if (Opc) { 304 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) 305 .addImm(Signed ? CI->getSExtValue() : 306 CI->getZExtValue()); 307 return true; 308 } 309 } 310 311 unsigned ValReg = getRegForValue(Val); 312 if (ValReg == 0) 313 return false; 314 315 return X86FastEmitStore(VT, ValReg, AM); 316} 317 318/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 319/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 320/// ISD::SIGN_EXTEND). 321bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 322 unsigned Src, EVT SrcVT, 323 unsigned &ResultReg) { 324 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); 325 326 if (RR != 0) { 327 ResultReg = RR; 328 return true; 329 } else 330 return false; 331} 332 333/// X86SelectAddress - Attempt to fill in an address from the given value. 334/// 335bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { 336 User *U = NULL; 337 unsigned Opcode = Instruction::UserOp1; 338 if (Instruction *I = dyn_cast<Instruction>(V)) { 339 Opcode = I->getOpcode(); 340 U = I; 341 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 342 Opcode = C->getOpcode(); 343 U = C; 344 } 345 346 switch (Opcode) { 347 default: break; 348 case Instruction::BitCast: 349 // Look past bitcasts. 350 return X86SelectAddress(U->getOperand(0), AM); 351 352 case Instruction::IntToPtr: 353 // Look past no-op inttoptrs. 354 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 355 return X86SelectAddress(U->getOperand(0), AM); 356 break; 357 358 case Instruction::PtrToInt: 359 // Look past no-op ptrtoints. 360 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 361 return X86SelectAddress(U->getOperand(0), AM); 362 break; 363 364 case Instruction::Alloca: { 365 // Do static allocas. 366 const AllocaInst *A = cast<AllocaInst>(V); 367 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 368 if (SI != StaticAllocaMap.end()) { 369 AM.BaseType = X86AddressMode::FrameIndexBase; 370 AM.Base.FrameIndex = SI->second; 371 return true; 372 } 373 break; 374 } 375 376 case Instruction::Add: { 377 // Adds of constants are common and easy enough. 378 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 379 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 380 // They have to fit in the 32-bit signed displacement field though. 381 if (isInt32(Disp)) { 382 AM.Disp = (uint32_t)Disp; 383 return X86SelectAddress(U->getOperand(0), AM); 384 } 385 } 386 break; 387 } 388 389 case Instruction::GetElementPtr: { 390 // Pattern-match simple GEPs. 391 uint64_t Disp = (int32_t)AM.Disp; 392 unsigned IndexReg = AM.IndexReg; 393 unsigned Scale = AM.Scale; 394 gep_type_iterator GTI = gep_type_begin(U); 395 // Iterate through the indices, folding what we can. Constants can be 396 // folded, and one dynamic index can be handled, if the scale is supported. 397 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end(); 398 i != e; ++i, ++GTI) { 399 Value *Op = *i; 400 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 401 const StructLayout *SL = TD.getStructLayout(STy); 402 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 403 Disp += SL->getElementOffset(Idx); 404 } else { 405 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 406 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 407 // Constant-offset addressing. 408 Disp += CI->getSExtValue() * S; 409 } else if (IndexReg == 0 && 410 (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 411 (S == 1 || S == 2 || S == 4 || S == 8)) { 412 // Scaled-index addressing. 413 Scale = S; 414 IndexReg = getRegForGEPIndex(Op); 415 if (IndexReg == 0) 416 return false; 417 } else 418 // Unsupported. 419 goto unsupported_gep; 420 } 421 } 422 // Check for displacement overflow. 423 if (!isInt32(Disp)) 424 break; 425 // Ok, the GEP indices were covered by constant-offset and scaled-index 426 // addressing. Update the address state and move on to examining the base. 427 AM.IndexReg = IndexReg; 428 AM.Scale = Scale; 429 AM.Disp = (uint32_t)Disp; 430 return X86SelectAddress(U->getOperand(0), AM); 431 unsupported_gep: 432 // Ok, the GEP indices weren't all covered. 433 break; 434 } 435 } 436 437 // Handle constant address. 438 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 439 // Can't handle alternate code models yet. 440 if (TM.getCodeModel() != CodeModel::Small) 441 return false; 442 443 // RIP-relative addresses can't have additional register operands. 444 if (Subtarget->isPICStyleRIPRel() && 445 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 446 return false; 447 448 // Can't handle TLS yet. 449 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 450 if (GVar->isThreadLocal()) 451 return false; 452 453 // Okay, we've committed to selecting this global. Set up the basic address. 454 AM.GV = GV; 455 456 // Allow the subtarget to classify the global. 457 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 458 459 // If this reference is relative to the pic base, set it now. 460 if (isGlobalRelativeToPICBase(GVFlags)) { 461 // FIXME: How do we know Base.Reg is free?? 462 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 463 } 464 465 // Unless the ABI requires an extra load, return a direct reference to 466 // the global. 467 if (!isGlobalStubReference(GVFlags)) { 468 if (Subtarget->isPICStyleRIPRel()) { 469 // Use rip-relative addressing if we can. Above we verified that the 470 // base and index registers are unused. 471 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 472 AM.Base.Reg = X86::RIP; 473 } 474 AM.GVOpFlags = GVFlags; 475 return true; 476 } 477 478 // Ok, we need to do a load from a stub. If we've already loaded from this 479 // stub, reuse the loaded pointer, otherwise emit the load now. 480 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 481 unsigned LoadReg; 482 if (I != LocalValueMap.end() && I->second != 0) { 483 LoadReg = I->second; 484 } else { 485 // Issue load from stub. 486 unsigned Opc = 0; 487 const TargetRegisterClass *RC = NULL; 488 X86AddressMode StubAM; 489 StubAM.Base.Reg = AM.Base.Reg; 490 StubAM.GV = GV; 491 StubAM.GVOpFlags = GVFlags; 492 493 if (TLI.getPointerTy() == MVT::i64) { 494 Opc = X86::MOV64rm; 495 RC = X86::GR64RegisterClass; 496 497 if (Subtarget->isPICStyleRIPRel()) 498 StubAM.Base.Reg = X86::RIP; 499 } else { 500 Opc = X86::MOV32rm; 501 RC = X86::GR32RegisterClass; 502 } 503 504 LoadReg = createResultReg(RC); 505 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM); 506 507 // Prevent loading GV stub multiple times in same MBB. 508 LocalValueMap[V] = LoadReg; 509 } 510 511 // Now construct the final address. Note that the Disp, Scale, 512 // and Index values may already be set here. 513 AM.Base.Reg = LoadReg; 514 AM.GV = 0; 515 return true; 516 } 517 518 // If all else fails, try to materialize the value in a register. 519 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 520 if (AM.Base.Reg == 0) { 521 AM.Base.Reg = getRegForValue(V); 522 return AM.Base.Reg != 0; 523 } 524 if (AM.IndexReg == 0) { 525 assert(AM.Scale == 1 && "Scale with no index!"); 526 AM.IndexReg = getRegForValue(V); 527 return AM.IndexReg != 0; 528 } 529 } 530 531 return false; 532} 533 534/// X86SelectCallAddress - Attempt to fill in an address from the given value. 535/// 536bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) { 537 User *U = NULL; 538 unsigned Opcode = Instruction::UserOp1; 539 if (Instruction *I = dyn_cast<Instruction>(V)) { 540 Opcode = I->getOpcode(); 541 U = I; 542 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 543 Opcode = C->getOpcode(); 544 U = C; 545 } 546 547 switch (Opcode) { 548 default: break; 549 case Instruction::BitCast: 550 // Look past bitcasts. 551 return X86SelectCallAddress(U->getOperand(0), AM); 552 553 case Instruction::IntToPtr: 554 // Look past no-op inttoptrs. 555 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 556 return X86SelectCallAddress(U->getOperand(0), AM); 557 break; 558 559 case Instruction::PtrToInt: 560 // Look past no-op ptrtoints. 561 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 562 return X86SelectCallAddress(U->getOperand(0), AM); 563 break; 564 } 565 566 // Handle constant address. 567 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 568 // Can't handle alternate code models yet. 569 if (TM.getCodeModel() != CodeModel::Small) 570 return false; 571 572 // RIP-relative addresses can't have additional register operands. 573 if (Subtarget->isPICStyleRIPRel() && 574 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 575 return false; 576 577 // Can't handle TLS or DLLImport. 578 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 579 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage()) 580 return false; 581 582 // Okay, we've committed to selecting this global. Set up the basic address. 583 AM.GV = GV; 584 585 // No ABI requires an extra load for anything other than DLLImport, which 586 // we rejected above. Return a direct reference to the global. 587 if (Subtarget->isPICStyleRIPRel()) { 588 // Use rip-relative addressing if we can. Above we verified that the 589 // base and index registers are unused. 590 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 591 AM.Base.Reg = X86::RIP; 592 } else if (Subtarget->isPICStyleStubPIC()) { 593 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 594 } else if (Subtarget->isPICStyleGOT()) { 595 AM.GVOpFlags = X86II::MO_GOTOFF; 596 } 597 598 return true; 599 } 600 601 // If all else fails, try to materialize the value in a register. 602 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 603 if (AM.Base.Reg == 0) { 604 AM.Base.Reg = getRegForValue(V); 605 return AM.Base.Reg != 0; 606 } 607 if (AM.IndexReg == 0) { 608 assert(AM.Scale == 1 && "Scale with no index!"); 609 AM.IndexReg = getRegForValue(V); 610 return AM.IndexReg != 0; 611 } 612 } 613 614 return false; 615} 616 617 618/// X86SelectStore - Select and emit code to implement store instructions. 619bool X86FastISel::X86SelectStore(Instruction* I) { 620 EVT VT; 621 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 622 return false; 623 624 X86AddressMode AM; 625 if (!X86SelectAddress(I->getOperand(1), AM)) 626 return false; 627 628 return X86FastEmitStore(VT, I->getOperand(0), AM); 629} 630 631/// X86SelectLoad - Select and emit code to implement load instructions. 632/// 633bool X86FastISel::X86SelectLoad(Instruction *I) { 634 EVT VT; 635 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 636 return false; 637 638 X86AddressMode AM; 639 if (!X86SelectAddress(I->getOperand(0), AM)) 640 return false; 641 642 unsigned ResultReg = 0; 643 if (X86FastEmitLoad(VT, AM, ResultReg)) { 644 UpdateValueMap(I, ResultReg); 645 return true; 646 } 647 return false; 648} 649 650static unsigned X86ChooseCmpOpcode(EVT VT) { 651 switch (VT.getSimpleVT().SimpleTy) { 652 default: return 0; 653 case MVT::i8: return X86::CMP8rr; 654 case MVT::i16: return X86::CMP16rr; 655 case MVT::i32: return X86::CMP32rr; 656 case MVT::i64: return X86::CMP64rr; 657 case MVT::f32: return X86::UCOMISSrr; 658 case MVT::f64: return X86::UCOMISDrr; 659 } 660} 661 662/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 663/// of the comparison, return an opcode that works for the compare (e.g. 664/// CMP32ri) otherwise return 0. 665static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) { 666 switch (VT.getSimpleVT().SimpleTy) { 667 // Otherwise, we can't fold the immediate into this comparison. 668 default: return 0; 669 case MVT::i8: return X86::CMP8ri; 670 case MVT::i16: return X86::CMP16ri; 671 case MVT::i32: return X86::CMP32ri; 672 case MVT::i64: 673 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 674 // field. 675 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 676 return X86::CMP64ri32; 677 return 0; 678 } 679} 680 681bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) { 682 unsigned Op0Reg = getRegForValue(Op0); 683 if (Op0Reg == 0) return false; 684 685 // Handle 'null' like i32/i64 0. 686 if (isa<ConstantPointerNull>(Op1)) 687 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 688 689 // We have two options: compare with register or immediate. If the RHS of 690 // the compare is an immediate that we can fold into this compare, use 691 // CMPri, otherwise use CMPrr. 692 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 693 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 694 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) 695 .addImm(Op1C->getSExtValue()); 696 return true; 697 } 698 } 699 700 unsigned CompareOpc = X86ChooseCmpOpcode(VT); 701 if (CompareOpc == 0) return false; 702 703 unsigned Op1Reg = getRegForValue(Op1); 704 if (Op1Reg == 0) return false; 705 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 706 707 return true; 708} 709 710bool X86FastISel::X86SelectCmp(Instruction *I) { 711 CmpInst *CI = cast<CmpInst>(I); 712 713 EVT VT; 714 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 715 return false; 716 717 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 718 unsigned SetCCOpc; 719 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 720 switch (CI->getPredicate()) { 721 case CmpInst::FCMP_OEQ: { 722 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 723 return false; 724 725 unsigned EReg = createResultReg(&X86::GR8RegClass); 726 unsigned NPReg = createResultReg(&X86::GR8RegClass); 727 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); 728 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); 729 BuildMI(MBB, DL, 730 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 731 UpdateValueMap(I, ResultReg); 732 return true; 733 } 734 case CmpInst::FCMP_UNE: { 735 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 736 return false; 737 738 unsigned NEReg = createResultReg(&X86::GR8RegClass); 739 unsigned PReg = createResultReg(&X86::GR8RegClass); 740 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); 741 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); 742 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 743 UpdateValueMap(I, ResultReg); 744 return true; 745 } 746 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 747 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 748 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 749 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 750 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 751 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 752 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 753 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 754 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 755 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 756 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 757 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 758 759 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 760 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 761 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 762 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 763 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 764 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 765 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 766 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 767 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 768 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 769 default: 770 return false; 771 } 772 773 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 774 if (SwapArgs) 775 std::swap(Op0, Op1); 776 777 // Emit a compare of Op0/Op1. 778 if (!X86FastEmitCompare(Op0, Op1, VT)) 779 return false; 780 781 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); 782 UpdateValueMap(I, ResultReg); 783 return true; 784} 785 786bool X86FastISel::X86SelectZExt(Instruction *I) { 787 // Handle zero-extension from i1 to i8, which is common. 788 if (I->getType() == Type::getInt8Ty(I->getContext()) && 789 I->getOperand(0)->getType() == Type::getInt1Ty(I->getContext())) { 790 unsigned ResultReg = getRegForValue(I->getOperand(0)); 791 if (ResultReg == 0) return false; 792 // Set the high bits to zero. 793 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg); 794 if (ResultReg == 0) return false; 795 UpdateValueMap(I, ResultReg); 796 return true; 797 } 798 799 return false; 800} 801 802 803bool X86FastISel::X86SelectBranch(Instruction *I) { 804 // Unconditional branches are selected by tablegen-generated code. 805 // Handle a conditional branch. 806 BranchInst *BI = cast<BranchInst>(I); 807 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 808 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 809 810 // Fold the common case of a conditional branch with a comparison. 811 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 812 if (CI->hasOneUse()) { 813 EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 814 815 // Try to take advantage of fallthrough opportunities. 816 CmpInst::Predicate Predicate = CI->getPredicate(); 817 if (MBB->isLayoutSuccessor(TrueMBB)) { 818 std::swap(TrueMBB, FalseMBB); 819 Predicate = CmpInst::getInversePredicate(Predicate); 820 } 821 822 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 823 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 824 825 switch (Predicate) { 826 case CmpInst::FCMP_OEQ: 827 std::swap(TrueMBB, FalseMBB); 828 Predicate = CmpInst::FCMP_UNE; 829 // FALL THROUGH 830 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break; 831 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break; 832 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break; 833 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break; 834 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break; 835 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break; 836 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break; 837 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break; 838 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break; 839 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break; 840 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break; 841 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break; 842 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break; 843 844 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break; 845 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break; 846 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break; 847 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break; 848 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break; 849 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break; 850 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break; 851 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break; 852 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break; 853 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break; 854 default: 855 return false; 856 } 857 858 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 859 if (SwapArgs) 860 std::swap(Op0, Op1); 861 862 // Emit a compare of the LHS and RHS, setting the flags. 863 if (!X86FastEmitCompare(Op0, Op1, VT)) 864 return false; 865 866 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); 867 868 if (Predicate == CmpInst::FCMP_UNE) { 869 // X86 requires a second branch to handle UNE (and OEQ, 870 // which is mapped to UNE above). 871 BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB); 872 } 873 874 FastEmitBranch(FalseMBB); 875 MBB->addSuccessor(TrueMBB); 876 return true; 877 } 878 } else if (ExtractValueInst *EI = 879 dyn_cast<ExtractValueInst>(BI->getCondition())) { 880 // Check to see if the branch instruction is from an "arithmetic with 881 // overflow" intrinsic. The main way these intrinsics are used is: 882 // 883 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 884 // %sum = extractvalue { i32, i1 } %t, 0 885 // %obit = extractvalue { i32, i1 } %t, 1 886 // br i1 %obit, label %overflow, label %normal 887 // 888 // The %sum and %obit are converted in an ADD and a SETO/SETB before 889 // reaching the branch. Therefore, we search backwards through the MBB 890 // looking for the SETO/SETB instruction. If an instruction modifies the 891 // EFLAGS register before we reach the SETO/SETB instruction, then we can't 892 // convert the branch into a JO/JB instruction. 893 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){ 894 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || 895 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { 896 const MachineInstr *SetMI = 0; 897 unsigned Reg = lookUpRegForValue(EI); 898 899 for (MachineBasicBlock::const_reverse_iterator 900 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 901 const MachineInstr &MI = *RI; 902 903 if (MI.modifiesRegister(Reg)) { 904 unsigned Src, Dst, SrcSR, DstSR; 905 906 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { 907 Reg = Src; 908 continue; 909 } 910 911 SetMI = &MI; 912 break; 913 } 914 915 const TargetInstrDesc &TID = MI.getDesc(); 916 if (TID.hasUnmodeledSideEffects() || 917 TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) 918 break; 919 } 920 921 if (SetMI) { 922 unsigned OpCode = SetMI->getOpcode(); 923 924 if (OpCode == X86::SETOr || OpCode == X86::SETBr) { 925 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO : X86::JB)) 926 .addMBB(TrueMBB); 927 FastEmitBranch(FalseMBB); 928 MBB->addSuccessor(TrueMBB); 929 return true; 930 } 931 } 932 } 933 } 934 } 935 936 // Otherwise do a clumsy setcc and re-test it. 937 unsigned OpReg = getRegForValue(BI->getCondition()); 938 if (OpReg == 0) return false; 939 940 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 941 BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB); 942 FastEmitBranch(FalseMBB); 943 MBB->addSuccessor(TrueMBB); 944 return true; 945} 946 947bool X86FastISel::X86SelectShift(Instruction *I) { 948 unsigned CReg = 0, OpReg = 0, OpImm = 0; 949 const TargetRegisterClass *RC = NULL; 950 if (I->getType() == Type::getInt8Ty(I->getContext())) { 951 CReg = X86::CL; 952 RC = &X86::GR8RegClass; 953 switch (I->getOpcode()) { 954 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 955 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 956 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 957 default: return false; 958 } 959 } else if (I->getType() == Type::getInt16Ty(I->getContext())) { 960 CReg = X86::CX; 961 RC = &X86::GR16RegClass; 962 switch (I->getOpcode()) { 963 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 964 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 965 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 966 default: return false; 967 } 968 } else if (I->getType() == Type::getInt32Ty(I->getContext())) { 969 CReg = X86::ECX; 970 RC = &X86::GR32RegClass; 971 switch (I->getOpcode()) { 972 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 973 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 974 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 975 default: return false; 976 } 977 } else if (I->getType() == Type::getInt64Ty(I->getContext())) { 978 CReg = X86::RCX; 979 RC = &X86::GR64RegClass; 980 switch (I->getOpcode()) { 981 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 982 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 983 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 984 default: return false; 985 } 986 } else { 987 return false; 988 } 989 990 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 991 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 992 return false; 993 994 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 995 if (Op0Reg == 0) return false; 996 997 // Fold immediate in shl(x,3). 998 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 999 unsigned ResultReg = createResultReg(RC); 1000 BuildMI(MBB, DL, TII.get(OpImm), 1001 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); 1002 UpdateValueMap(I, ResultReg); 1003 return true; 1004 } 1005 1006 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1007 if (Op1Reg == 0) return false; 1008 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC); 1009 1010 // The shift instruction uses X86::CL. If we defined a super-register 1011 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 1012 // we're doing here. 1013 if (CReg != X86::CL) 1014 BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL) 1015 .addReg(CReg).addImm(X86::SUBREG_8BIT); 1016 1017 unsigned ResultReg = createResultReg(RC); 1018 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); 1019 UpdateValueMap(I, ResultReg); 1020 return true; 1021} 1022 1023bool X86FastISel::X86SelectSelect(Instruction *I) { 1024 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1025 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1026 return false; 1027 1028 unsigned Opc = 0; 1029 const TargetRegisterClass *RC = NULL; 1030 if (VT.getSimpleVT() == MVT::i16) { 1031 Opc = X86::CMOVE16rr; 1032 RC = &X86::GR16RegClass; 1033 } else if (VT.getSimpleVT() == MVT::i32) { 1034 Opc = X86::CMOVE32rr; 1035 RC = &X86::GR32RegClass; 1036 } else if (VT.getSimpleVT() == MVT::i64) { 1037 Opc = X86::CMOVE64rr; 1038 RC = &X86::GR64RegClass; 1039 } else { 1040 return false; 1041 } 1042 1043 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1044 if (Op0Reg == 0) return false; 1045 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1046 if (Op1Reg == 0) return false; 1047 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1048 if (Op2Reg == 0) return false; 1049 1050 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 1051 unsigned ResultReg = createResultReg(RC); 1052 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 1053 UpdateValueMap(I, ResultReg); 1054 return true; 1055} 1056 1057bool X86FastISel::X86SelectFPExt(Instruction *I) { 1058 // fpext from float to double. 1059 if (Subtarget->hasSSE2() && 1060 I->getType() == Type::getDoubleTy(I->getContext())) { 1061 Value *V = I->getOperand(0); 1062 if (V->getType() == Type::getFloatTy(I->getContext())) { 1063 unsigned OpReg = getRegForValue(V); 1064 if (OpReg == 0) return false; 1065 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 1066 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 1067 UpdateValueMap(I, ResultReg); 1068 return true; 1069 } 1070 } 1071 1072 return false; 1073} 1074 1075bool X86FastISel::X86SelectFPTrunc(Instruction *I) { 1076 if (Subtarget->hasSSE2()) { 1077 if (I->getType() == Type::getFloatTy(I->getContext())) { 1078 Value *V = I->getOperand(0); 1079 if (V->getType() == Type::getDoubleTy(I->getContext())) { 1080 unsigned OpReg = getRegForValue(V); 1081 if (OpReg == 0) return false; 1082 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 1083 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 1084 UpdateValueMap(I, ResultReg); 1085 return true; 1086 } 1087 } 1088 } 1089 1090 return false; 1091} 1092 1093bool X86FastISel::X86SelectTrunc(Instruction *I) { 1094 if (Subtarget->is64Bit()) 1095 // All other cases should be handled by the tblgen generated code. 1096 return false; 1097 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1098 EVT DstVT = TLI.getValueType(I->getType()); 1099 1100 // This code only handles truncation to byte right now. 1101 if (DstVT != MVT::i8 && DstVT != MVT::i1) 1102 // All other cases should be handled by the tblgen generated code. 1103 return false; 1104 if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 1105 // All other cases should be handled by the tblgen generated code. 1106 return false; 1107 1108 unsigned InputReg = getRegForValue(I->getOperand(0)); 1109 if (!InputReg) 1110 // Unhandled operand. Halt "fast" selection and bail. 1111 return false; 1112 1113 // First issue a copy to GR16_ABCD or GR32_ABCD. 1114 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; 1115 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1116 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 1117 unsigned CopyReg = createResultReg(CopyRC); 1118 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); 1119 1120 // Then issue an extract_subreg. 1121 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1122 CopyReg, X86::SUBREG_8BIT); 1123 if (!ResultReg) 1124 return false; 1125 1126 UpdateValueMap(I, ResultReg); 1127 return true; 1128} 1129 1130bool X86FastISel::X86SelectExtractValue(Instruction *I) { 1131 ExtractValueInst *EI = cast<ExtractValueInst>(I); 1132 Value *Agg = EI->getAggregateOperand(); 1133 1134 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) { 1135 switch (CI->getIntrinsicID()) { 1136 default: break; 1137 case Intrinsic::sadd_with_overflow: 1138 case Intrinsic::uadd_with_overflow: 1139 // Cheat a little. We know that the registers for "add" and "seto" are 1140 // allocated sequentially. However, we only keep track of the register 1141 // for "add" in the value map. Use extractvalue's index to get the 1142 // correct register for "seto". 1143 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 1144 return true; 1145 } 1146 } 1147 1148 return false; 1149} 1150 1151bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { 1152 // FIXME: Handle more intrinsics. 1153 switch (I.getIntrinsicID()) { 1154 default: return false; 1155 case Intrinsic::sadd_with_overflow: 1156 case Intrinsic::uadd_with_overflow: { 1157 // Replace "add with overflow" intrinsics with an "add" instruction followed 1158 // by a seto/setc instruction. Later on, when the "extractvalue" 1159 // instructions are encountered, we use the fact that two registers were 1160 // created sequentially to get the correct registers for the "sum" and the 1161 // "overflow bit". 1162 const Function *Callee = I.getCalledFunction(); 1163 const Type *RetTy = 1164 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1165 1166 EVT VT; 1167 if (!isTypeLegal(RetTy, VT)) 1168 return false; 1169 1170 Value *Op1 = I.getOperand(1); 1171 Value *Op2 = I.getOperand(2); 1172 unsigned Reg1 = getRegForValue(Op1); 1173 unsigned Reg2 = getRegForValue(Op2); 1174 1175 if (Reg1 == 0 || Reg2 == 0) 1176 // FIXME: Handle values *not* in registers. 1177 return false; 1178 1179 unsigned OpC = 0; 1180 if (VT == MVT::i32) 1181 OpC = X86::ADD32rr; 1182 else if (VT == MVT::i64) 1183 OpC = X86::ADD64rr; 1184 else 1185 return false; 1186 1187 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1188 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 1189 unsigned DestReg1 = UpdateValueMap(&I, ResultReg); 1190 1191 // If the add with overflow is an intra-block value then we just want to 1192 // create temporaries for it like normal. If it is a cross-block value then 1193 // UpdateValueMap will return the cross-block register used. Since we 1194 // *really* want the value to be live in the register pair known by 1195 // UpdateValueMap, we have to use DestReg1+1 as the destination register in 1196 // the cross block case. In the non-cross-block case, we should just make 1197 // another register for the value. 1198 if (DestReg1 != ResultReg) 1199 ResultReg = DestReg1+1; 1200 else 1201 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 1202 1203 unsigned Opc = X86::SETBr; 1204 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1205 Opc = X86::SETOr; 1206 BuildMI(MBB, DL, TII.get(Opc), ResultReg); 1207 return true; 1208 } 1209 } 1210} 1211 1212bool X86FastISel::X86SelectCall(Instruction *I) { 1213 CallInst *CI = cast<CallInst>(I); 1214 Value *Callee = I->getOperand(0); 1215 1216 // Can't handle inline asm yet. 1217 if (isa<InlineAsm>(Callee)) 1218 return false; 1219 1220 // Handle intrinsic calls. 1221 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1222 return X86VisitIntrinsicCall(*II); 1223 1224 // Handle only C and fastcc calling conventions for now. 1225 CallSite CS(CI); 1226 unsigned CC = CS.getCallingConv(); 1227 if (CC != CallingConv::C && 1228 CC != CallingConv::Fast && 1229 CC != CallingConv::X86_FastCall) 1230 return false; 1231 1232 // On X86, -tailcallopt changes the fastcc ABI. FastISel doesn't 1233 // handle this for now. 1234 if (CC == CallingConv::Fast && PerformTailCallOpt) 1235 return false; 1236 1237 // Let SDISel handle vararg functions. 1238 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1239 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1240 if (FTy->isVarArg()) 1241 return false; 1242 1243 // Handle *simple* calls for now. 1244 const Type *RetTy = CS.getType(); 1245 EVT RetVT; 1246 if (RetTy == Type::getVoidTy(I->getContext())) 1247 RetVT = MVT::isVoid; 1248 else if (!isTypeLegal(RetTy, RetVT, true)) 1249 return false; 1250 1251 // Materialize callee address in a register. FIXME: GV address can be 1252 // handled with a CALLpcrel32 instead. 1253 X86AddressMode CalleeAM; 1254 if (!X86SelectCallAddress(Callee, CalleeAM)) 1255 return false; 1256 unsigned CalleeOp = 0; 1257 GlobalValue *GV = 0; 1258 if (CalleeAM.GV != 0) { 1259 GV = CalleeAM.GV; 1260 } else if (CalleeAM.Base.Reg != 0) { 1261 CalleeOp = CalleeAM.Base.Reg; 1262 } else 1263 return false; 1264 1265 // Allow calls which produce i1 results. 1266 bool AndToI1 = false; 1267 if (RetVT == MVT::i1) { 1268 RetVT = MVT::i8; 1269 AndToI1 = true; 1270 } 1271 1272 // Deal with call operands first. 1273 SmallVector<Value*, 8> ArgVals; 1274 SmallVector<unsigned, 8> Args; 1275 SmallVector<EVT, 8> ArgVTs; 1276 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1277 Args.reserve(CS.arg_size()); 1278 ArgVals.reserve(CS.arg_size()); 1279 ArgVTs.reserve(CS.arg_size()); 1280 ArgFlags.reserve(CS.arg_size()); 1281 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1282 i != e; ++i) { 1283 unsigned Arg = getRegForValue(*i); 1284 if (Arg == 0) 1285 return false; 1286 ISD::ArgFlagsTy Flags; 1287 unsigned AttrInd = i - CS.arg_begin() + 1; 1288 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1289 Flags.setSExt(); 1290 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1291 Flags.setZExt(); 1292 1293 // FIXME: Only handle *easy* calls for now. 1294 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1295 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1296 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1297 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1298 return false; 1299 1300 const Type *ArgTy = (*i)->getType(); 1301 EVT ArgVT; 1302 if (!isTypeLegal(ArgTy, ArgVT)) 1303 return false; 1304 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1305 Flags.setOrigAlign(OriginalAlignment); 1306 1307 Args.push_back(Arg); 1308 ArgVals.push_back(*i); 1309 ArgVTs.push_back(ArgVT); 1310 ArgFlags.push_back(Flags); 1311 } 1312 1313 // Analyze operands of the call, assigning locations to each operand. 1314 SmallVector<CCValAssign, 16> ArgLocs; 1315 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext()); 1316 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 1317 1318 // Get a count of how many bytes are to be pushed on the stack. 1319 unsigned NumBytes = CCInfo.getNextStackOffset(); 1320 1321 // Issue CALLSEQ_START 1322 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1323 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); 1324 1325 // Process argument: walk the register/memloc assignments, inserting 1326 // copies / loads. 1327 SmallVector<unsigned, 4> RegArgs; 1328 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1329 CCValAssign &VA = ArgLocs[i]; 1330 unsigned Arg = Args[VA.getValNo()]; 1331 EVT ArgVT = ArgVTs[VA.getValNo()]; 1332 1333 // Promote the value if needed. 1334 switch (VA.getLocInfo()) { 1335 default: llvm_unreachable("Unknown loc info!"); 1336 case CCValAssign::Full: break; 1337 case CCValAssign::SExt: { 1338 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1339 Arg, ArgVT, Arg); 1340 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1341 Emitted = true; 1342 ArgVT = VA.getLocVT(); 1343 break; 1344 } 1345 case CCValAssign::ZExt: { 1346 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1347 Arg, ArgVT, Arg); 1348 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1349 Emitted = true; 1350 ArgVT = VA.getLocVT(); 1351 break; 1352 } 1353 case CCValAssign::AExt: { 1354 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1355 Arg, ArgVT, Arg); 1356 if (!Emitted) 1357 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1358 Arg, ArgVT, Arg); 1359 if (!Emitted) 1360 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1361 Arg, ArgVT, Arg); 1362 1363 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1364 ArgVT = VA.getLocVT(); 1365 break; 1366 } 1367 case CCValAssign::BCvt: { 1368 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(), 1369 ISD::BIT_CONVERT, Arg); 1370 assert(BC != 0 && "Failed to emit a bitcast!"); 1371 Arg = BC; 1372 ArgVT = VA.getLocVT(); 1373 break; 1374 } 1375 } 1376 1377 if (VA.isRegLoc()) { 1378 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 1379 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 1380 Arg, RC, RC); 1381 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1382 Emitted = true; 1383 RegArgs.push_back(VA.getLocReg()); 1384 } else { 1385 unsigned LocMemOffset = VA.getLocMemOffset(); 1386 X86AddressMode AM; 1387 AM.Base.Reg = StackPtr; 1388 AM.Disp = LocMemOffset; 1389 Value *ArgVal = ArgVals[VA.getValNo()]; 1390 1391 // If this is a really simple value, emit this with the Value* version of 1392 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 1393 // can cause us to reevaluate the argument. 1394 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 1395 X86FastEmitStore(ArgVT, ArgVal, AM); 1396 else 1397 X86FastEmitStore(ArgVT, Arg, AM); 1398 } 1399 } 1400 1401 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1402 // GOT pointer. 1403 if (Subtarget->isPICStyleGOT()) { 1404 TargetRegisterClass *RC = X86::GR32RegisterClass; 1405 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 1406 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); 1407 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1408 Emitted = true; 1409 } 1410 1411 // Issue the call. 1412 MachineInstrBuilder MIB; 1413 if (CalleeOp) { 1414 // Register-indirect call. 1415 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r; 1416 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp); 1417 1418 } else { 1419 // Direct call. 1420 assert(GV && "Not a direct call"); 1421 unsigned CallOpc = 1422 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; 1423 1424 // See if we need any target-specific flags on the GV operand. 1425 unsigned char OpFlags = 0; 1426 1427 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1428 // external symbols most go through the PLT in PIC mode. If the symbol 1429 // has hidden or protected visibility, or if it is static or local, then 1430 // we don't need to use the PLT - we can directly call it. 1431 if (Subtarget->isTargetELF() && 1432 TM.getRelocationModel() == Reloc::PIC_ && 1433 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1434 OpFlags = X86II::MO_PLT; 1435 } else if (Subtarget->isPICStyleStubAny() && 1436 (GV->isDeclaration() || GV->isWeakForLinker()) && 1437 Subtarget->getDarwinVers() < 9) { 1438 // PC-relative references to external symbols should go through $stub, 1439 // unless we're building with the leopard linker or later, which 1440 // automatically synthesizes these stubs. 1441 OpFlags = X86II::MO_DARWIN_STUB; 1442 } 1443 1444 1445 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags); 1446 } 1447 1448 // Add an implicit use GOT pointer in EBX. 1449 if (Subtarget->isPICStyleGOT()) 1450 MIB.addReg(X86::EBX); 1451 1452 // Add implicit physical register uses to the call. 1453 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1454 MIB.addReg(RegArgs[i]); 1455 1456 // Issue CALLSEQ_END 1457 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1458 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 1459 1460 // Now handle call return value (if any). 1461 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { 1462 SmallVector<CCValAssign, 16> RVLocs; 1463 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); 1464 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 1465 1466 // Copy all of the result registers out of their specified physreg. 1467 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 1468 EVT CopyVT = RVLocs[0].getValVT(); 1469 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1470 TargetRegisterClass *SrcRC = DstRC; 1471 1472 // If this is a call to a function that returns an fp value on the x87 fp 1473 // stack, but where we prefer to use the value in xmm registers, copy it 1474 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1475 if ((RVLocs[0].getLocReg() == X86::ST0 || 1476 RVLocs[0].getLocReg() == X86::ST1) && 1477 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 1478 CopyVT = MVT::f80; 1479 SrcRC = X86::RSTRegisterClass; 1480 DstRC = X86::RFP80RegisterClass; 1481 } 1482 1483 unsigned ResultReg = createResultReg(DstRC); 1484 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1485 RVLocs[0].getLocReg(), DstRC, SrcRC); 1486 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1487 Emitted = true; 1488 if (CopyVT != RVLocs[0].getValVT()) { 1489 // Round the F80 the right size, which also moves to the appropriate xmm 1490 // register. This is accomplished by storing the F80 value in memory and 1491 // then loading it back. Ewww... 1492 EVT ResVT = RVLocs[0].getValVT(); 1493 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1494 unsigned MemSize = ResVT.getSizeInBits()/8; 1495 int FI = MFI.CreateStackObject(MemSize, MemSize); 1496 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); 1497 DstRC = ResVT == MVT::f32 1498 ? X86::FR32RegisterClass : X86::FR64RegisterClass; 1499 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1500 ResultReg = createResultReg(DstRC); 1501 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); 1502 } 1503 1504 if (AndToI1) { 1505 // Mask out all but lowest bit for some call which produces an i1. 1506 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 1507 BuildMI(MBB, DL, 1508 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 1509 ResultReg = AndResult; 1510 } 1511 1512 UpdateValueMap(I, ResultReg); 1513 } 1514 1515 return true; 1516} 1517 1518 1519bool 1520X86FastISel::TargetSelectInstruction(Instruction *I) { 1521 switch (I->getOpcode()) { 1522 default: break; 1523 case Instruction::Load: 1524 return X86SelectLoad(I); 1525 case Instruction::Store: 1526 return X86SelectStore(I); 1527 case Instruction::ICmp: 1528 case Instruction::FCmp: 1529 return X86SelectCmp(I); 1530 case Instruction::ZExt: 1531 return X86SelectZExt(I); 1532 case Instruction::Br: 1533 return X86SelectBranch(I); 1534 case Instruction::Call: 1535 return X86SelectCall(I); 1536 case Instruction::LShr: 1537 case Instruction::AShr: 1538 case Instruction::Shl: 1539 return X86SelectShift(I); 1540 case Instruction::Select: 1541 return X86SelectSelect(I); 1542 case Instruction::Trunc: 1543 return X86SelectTrunc(I); 1544 case Instruction::FPExt: 1545 return X86SelectFPExt(I); 1546 case Instruction::FPTrunc: 1547 return X86SelectFPTrunc(I); 1548 case Instruction::ExtractValue: 1549 return X86SelectExtractValue(I); 1550 case Instruction::IntToPtr: // Deliberate fall-through. 1551 case Instruction::PtrToInt: { 1552 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1553 EVT DstVT = TLI.getValueType(I->getType()); 1554 if (DstVT.bitsGT(SrcVT)) 1555 return X86SelectZExt(I); 1556 if (DstVT.bitsLT(SrcVT)) 1557 return X86SelectTrunc(I); 1558 unsigned Reg = getRegForValue(I->getOperand(0)); 1559 if (Reg == 0) return false; 1560 UpdateValueMap(I, Reg); 1561 return true; 1562 } 1563 } 1564 1565 return false; 1566} 1567 1568unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { 1569 EVT VT; 1570 if (!isTypeLegal(C->getType(), VT)) 1571 return false; 1572 1573 // Get opcode and regclass of the output for the given load instruction. 1574 unsigned Opc = 0; 1575 const TargetRegisterClass *RC = NULL; 1576 switch (VT.getSimpleVT().SimpleTy) { 1577 default: return false; 1578 case MVT::i8: 1579 Opc = X86::MOV8rm; 1580 RC = X86::GR8RegisterClass; 1581 break; 1582 case MVT::i16: 1583 Opc = X86::MOV16rm; 1584 RC = X86::GR16RegisterClass; 1585 break; 1586 case MVT::i32: 1587 Opc = X86::MOV32rm; 1588 RC = X86::GR32RegisterClass; 1589 break; 1590 case MVT::i64: 1591 // Must be in x86-64 mode. 1592 Opc = X86::MOV64rm; 1593 RC = X86::GR64RegisterClass; 1594 break; 1595 case MVT::f32: 1596 if (Subtarget->hasSSE1()) { 1597 Opc = X86::MOVSSrm; 1598 RC = X86::FR32RegisterClass; 1599 } else { 1600 Opc = X86::LD_Fp32m; 1601 RC = X86::RFP32RegisterClass; 1602 } 1603 break; 1604 case MVT::f64: 1605 if (Subtarget->hasSSE2()) { 1606 Opc = X86::MOVSDrm; 1607 RC = X86::FR64RegisterClass; 1608 } else { 1609 Opc = X86::LD_Fp64m; 1610 RC = X86::RFP64RegisterClass; 1611 } 1612 break; 1613 case MVT::f80: 1614 // No f80 support yet. 1615 return false; 1616 } 1617 1618 // Materialize addresses with LEA instructions. 1619 if (isa<GlobalValue>(C)) { 1620 X86AddressMode AM; 1621 if (X86SelectAddress(C, AM)) { 1622 if (TLI.getPointerTy() == MVT::i32) 1623 Opc = X86::LEA32r; 1624 else 1625 Opc = X86::LEA64r; 1626 unsigned ResultReg = createResultReg(RC); 1627 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1628 return ResultReg; 1629 } 1630 return 0; 1631 } 1632 1633 // MachineConstantPool wants an explicit alignment. 1634 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 1635 if (Align == 0) { 1636 // Alignment of vector types. FIXME! 1637 Align = TD.getTypeAllocSize(C->getType()); 1638 } 1639 1640 // x86-32 PIC requires a PIC base register for constant pools. 1641 unsigned PICBase = 0; 1642 unsigned char OpFlag = 0; 1643 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 1644 OpFlag = X86II::MO_PIC_BASE_OFFSET; 1645 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1646 } else if (Subtarget->isPICStyleGOT()) { 1647 OpFlag = X86II::MO_GOTOFF; 1648 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1649 } else if (Subtarget->isPICStyleRIPRel() && 1650 TM.getCodeModel() == CodeModel::Small) { 1651 PICBase = X86::RIP; 1652 } 1653 1654 // Create the load from the constant pool. 1655 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 1656 unsigned ResultReg = createResultReg(RC); 1657 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), 1658 MCPOffset, PICBase, OpFlag); 1659 1660 return ResultReg; 1661} 1662 1663unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { 1664 // Fail on dynamic allocas. At this point, getRegForValue has already 1665 // checked its CSE maps, so if we're here trying to handle a dynamic 1666 // alloca, we're not going to succeed. X86SelectAddress has a 1667 // check for dynamic allocas, because it's called directly from 1668 // various places, but TargetMaterializeAlloca also needs a check 1669 // in order to avoid recursion between getRegForValue, 1670 // X86SelectAddrss, and TargetMaterializeAlloca. 1671 if (!StaticAllocaMap.count(C)) 1672 return 0; 1673 1674 X86AddressMode AM; 1675 if (!X86SelectAddress(C, AM)) 1676 return 0; 1677 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 1678 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 1679 unsigned ResultReg = createResultReg(RC); 1680 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1681 return ResultReg; 1682} 1683 1684namespace llvm { 1685 llvm::FastISel *X86::createFastISel(MachineFunction &mf, 1686 MachineModuleInfo *mmi, 1687 DwarfWriter *dw, 1688 DenseMap<const Value *, unsigned> &vm, 1689 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 1690 DenseMap<const AllocaInst *, int> &am 1691#ifndef NDEBUG 1692 , SmallSet<Instruction*, 8> &cil 1693#endif 1694 ) { 1695 return new X86FastISel(mf, mmi, dw, vm, bm, am 1696#ifndef NDEBUG 1697 , cil 1698#endif 1699 ); 1700 } 1701} 1702