X86FastISel.cpp revision a33649e98ce6512ed95a5e5f7b72dd28e243a289
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/Instructions.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/CodeGen/FastISel.h" 27#include "llvm/CodeGen/MachineConstantPool.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/Support/CallSite.h" 31#include "llvm/Support/GetElementPtrTypeIterator.h" 32 33using namespace llvm; 34 35class X86FastISel : public FastISel { 36 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 37 /// make the right decision when generating code for different targets. 38 const X86Subtarget *Subtarget; 39 40 /// StackPtr - Register used as the stack pointer. 41 /// 42 unsigned StackPtr; 43 44 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 45 /// floating point ops. 46 /// When SSE is available, use it for f32 operations. 47 /// When SSE2 is available, use it for f64 operations. 48 bool X86ScalarSSEf64; 49 bool X86ScalarSSEf32; 50 51public: 52 explicit X86FastISel(MachineFunction &mf, 53 MachineModuleInfo *mmi, 54 DenseMap<const Value *, unsigned> &vm, 55 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 56 DenseMap<const AllocaInst *, int> &am 57#ifndef NDEBUG 58 , SmallSet<Instruction*, 8> &cil 59#endif 60 ) 61 : FastISel(mf, mmi, vm, bm, am 62#ifndef NDEBUG 63 , cil 64#endif 65 ) { 66 Subtarget = &TM.getSubtarget<X86Subtarget>(); 67 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 68 X86ScalarSSEf64 = Subtarget->hasSSE2(); 69 X86ScalarSSEf32 = Subtarget->hasSSE1(); 70 } 71 72 virtual bool TargetSelectInstruction(Instruction *I); 73 74#include "X86GenFastISel.inc" 75 76private: 77 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT); 78 79 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR); 80 81 bool X86FastEmitStore(MVT VT, Value *Val, 82 const X86AddressMode &AM); 83 bool X86FastEmitStore(MVT VT, unsigned Val, 84 const X86AddressMode &AM); 85 86 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT, 87 unsigned &ResultReg); 88 89 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall); 90 91 bool X86SelectLoad(Instruction *I); 92 93 bool X86SelectStore(Instruction *I); 94 95 bool X86SelectCmp(Instruction *I); 96 97 bool X86SelectZExt(Instruction *I); 98 99 bool X86SelectBranch(Instruction *I); 100 101 bool X86SelectShift(Instruction *I); 102 103 bool X86SelectSelect(Instruction *I); 104 105 bool X86SelectTrunc(Instruction *I); 106 107 bool X86SelectFPExt(Instruction *I); 108 bool X86SelectFPTrunc(Instruction *I); 109 110 bool X86SelectExtractValue(Instruction *I); 111 112 bool X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic); 113 bool X86SelectCall(Instruction *I); 114 115 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false); 116 117 const X86InstrInfo *getInstrInfo() const { 118 return getTargetMachine()->getInstrInfo(); 119 } 120 const X86TargetMachine *getTargetMachine() const { 121 return static_cast<const X86TargetMachine *>(&TM); 122 } 123 124 unsigned TargetMaterializeConstant(Constant *C); 125 126 unsigned TargetMaterializeAlloca(AllocaInst *C); 127 128 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 129 /// computed in an SSE register, not on the X87 floating point stack. 130 bool isScalarFPTypeInSSEReg(MVT VT) const { 131 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 132 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 133 } 134 135 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false); 136}; 137 138bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) { 139 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 140 if (VT == MVT::Other || !VT.isSimple()) 141 // Unhandled type. Halt "fast" selection and bail. 142 return false; 143 144 // For now, require SSE/SSE2 for performing floating-point operations, 145 // since x87 requires additional work. 146 if (VT == MVT::f64 && !X86ScalarSSEf64) 147 return false; 148 if (VT == MVT::f32 && !X86ScalarSSEf32) 149 return false; 150 // Similarly, no f80 support yet. 151 if (VT == MVT::f80) 152 return false; 153 // We only handle legal types. For example, on x86-32 the instruction 154 // selector contains all of the 64-bit instructions from x86-64, 155 // under the assumption that i64 won't be used if the target doesn't 156 // support it. 157 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 158} 159 160#include "X86GenCallingConv.inc" 161 162/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 163/// convention. 164CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) { 165 if (Subtarget->is64Bit()) { 166 if (Subtarget->isTargetWin64()) 167 return CC_X86_Win64_C; 168 else if (CC == CallingConv::Fast && isTaillCall) 169 return CC_X86_64_TailCall; 170 else 171 return CC_X86_64_C; 172 } 173 174 if (CC == CallingConv::X86_FastCall) 175 return CC_X86_32_FastCall; 176 else if (CC == CallingConv::Fast) 177 return CC_X86_32_FastCC; 178 else 179 return CC_X86_32_C; 180} 181 182/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 183/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 184/// Return true and the result register by reference if it is possible. 185bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM, 186 unsigned &ResultReg) { 187 // Get opcode and regclass of the output for the given load instruction. 188 unsigned Opc = 0; 189 const TargetRegisterClass *RC = NULL; 190 switch (VT.getSimpleVT()) { 191 default: return false; 192 case MVT::i8: 193 Opc = X86::MOV8rm; 194 RC = X86::GR8RegisterClass; 195 break; 196 case MVT::i16: 197 Opc = X86::MOV16rm; 198 RC = X86::GR16RegisterClass; 199 break; 200 case MVT::i32: 201 Opc = X86::MOV32rm; 202 RC = X86::GR32RegisterClass; 203 break; 204 case MVT::i64: 205 // Must be in x86-64 mode. 206 Opc = X86::MOV64rm; 207 RC = X86::GR64RegisterClass; 208 break; 209 case MVT::f32: 210 if (Subtarget->hasSSE1()) { 211 Opc = X86::MOVSSrm; 212 RC = X86::FR32RegisterClass; 213 } else { 214 Opc = X86::LD_Fp32m; 215 RC = X86::RFP32RegisterClass; 216 } 217 break; 218 case MVT::f64: 219 if (Subtarget->hasSSE2()) { 220 Opc = X86::MOVSDrm; 221 RC = X86::FR64RegisterClass; 222 } else { 223 Opc = X86::LD_Fp64m; 224 RC = X86::RFP64RegisterClass; 225 } 226 break; 227 case MVT::f80: 228 // No f80 support yet. 229 return false; 230 } 231 232 ResultReg = createResultReg(RC); 233 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM); 234 return true; 235} 236 237/// X86FastEmitStore - Emit a machine instruction to store a value Val of 238/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 239/// and a displacement offset, or a GlobalAddress, 240/// i.e. V. Return true if it is possible. 241bool 242X86FastISel::X86FastEmitStore(MVT VT, unsigned Val, 243 const X86AddressMode &AM) { 244 // Get opcode and regclass of the output for the given store instruction. 245 unsigned Opc = 0; 246 switch (VT.getSimpleVT()) { 247 case MVT::f80: // No f80 support yet. 248 default: return false; 249 case MVT::i8: Opc = X86::MOV8mr; break; 250 case MVT::i16: Opc = X86::MOV16mr; break; 251 case MVT::i32: Opc = X86::MOV32mr; break; 252 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 253 case MVT::f32: 254 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 255 break; 256 case MVT::f64: 257 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 258 break; 259 } 260 261 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val); 262 return true; 263} 264 265bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val, 266 const X86AddressMode &AM) { 267 // Handle 'null' like i32/i64 0. 268 if (isa<ConstantPointerNull>(Val)) 269 Val = Constant::getNullValue(TD.getIntPtrType()); 270 271 // If this is a store of a simple constant, fold the constant into the store. 272 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 273 unsigned Opc = 0; 274 switch (VT.getSimpleVT()) { 275 default: break; 276 case MVT::i8: Opc = X86::MOV8mi; break; 277 case MVT::i16: Opc = X86::MOV16mi; break; 278 case MVT::i32: Opc = X86::MOV32mi; break; 279 case MVT::i64: 280 // Must be a 32-bit sign extended value. 281 if ((int)CI->getSExtValue() == CI->getSExtValue()) 282 Opc = X86::MOV64mi32; 283 break; 284 } 285 286 if (Opc) { 287 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addImm(CI->getSExtValue()); 288 return true; 289 } 290 } 291 292 unsigned ValReg = getRegForValue(Val); 293 if (ValReg == 0) 294 return false; 295 296 return X86FastEmitStore(VT, ValReg, AM); 297} 298 299/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 300/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 301/// ISD::SIGN_EXTEND). 302bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, 303 unsigned Src, MVT SrcVT, 304 unsigned &ResultReg) { 305 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); 306 307 if (RR != 0) { 308 ResultReg = RR; 309 return true; 310 } else 311 return false; 312} 313 314/// X86SelectAddress - Attempt to fill in an address from the given value. 315/// 316bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) { 317 User *U; 318 unsigned Opcode = Instruction::UserOp1; 319 if (Instruction *I = dyn_cast<Instruction>(V)) { 320 Opcode = I->getOpcode(); 321 U = I; 322 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 323 Opcode = C->getOpcode(); 324 U = C; 325 } 326 327 switch (Opcode) { 328 default: break; 329 case Instruction::BitCast: 330 // Look past bitcasts. 331 return X86SelectAddress(U->getOperand(0), AM, isCall); 332 333 case Instruction::IntToPtr: 334 // Look past no-op inttoptrs. 335 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 336 return X86SelectAddress(U->getOperand(0), AM, isCall); 337 break; 338 339 case Instruction::PtrToInt: 340 // Look past no-op ptrtoints. 341 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 342 return X86SelectAddress(U->getOperand(0), AM, isCall); 343 break; 344 345 case Instruction::Alloca: { 346 if (isCall) break; 347 // Do static allocas. 348 const AllocaInst *A = cast<AllocaInst>(V); 349 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 350 if (SI != StaticAllocaMap.end()) { 351 AM.BaseType = X86AddressMode::FrameIndexBase; 352 AM.Base.FrameIndex = SI->second; 353 return true; 354 } 355 break; 356 } 357 358 case Instruction::Add: { 359 if (isCall) break; 360 // Adds of constants are common and easy enough. 361 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 362 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 363 // They have to fit in the 32-bit signed displacement field though. 364 if (isInt32(Disp)) { 365 AM.Disp = (uint32_t)Disp; 366 return X86SelectAddress(U->getOperand(0), AM, isCall); 367 } 368 } 369 break; 370 } 371 372 case Instruction::GetElementPtr: { 373 if (isCall) break; 374 // Pattern-match simple GEPs. 375 uint64_t Disp = (int32_t)AM.Disp; 376 unsigned IndexReg = AM.IndexReg; 377 unsigned Scale = AM.Scale; 378 gep_type_iterator GTI = gep_type_begin(U); 379 // Iterate through the indices, folding what we can. Constants can be 380 // folded, and one dynamic index can be handled, if the scale is supported. 381 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end(); 382 i != e; ++i, ++GTI) { 383 Value *Op = *i; 384 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 385 const StructLayout *SL = TD.getStructLayout(STy); 386 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 387 Disp += SL->getElementOffset(Idx); 388 } else { 389 uint64_t S = TD.getABITypeSize(GTI.getIndexedType()); 390 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 391 // Constant-offset addressing. 392 Disp += CI->getSExtValue() * S; 393 } else if (IndexReg == 0 && 394 (!AM.GV || 395 !getTargetMachine()->symbolicAddressesAreRIPRel()) && 396 (S == 1 || S == 2 || S == 4 || S == 8)) { 397 // Scaled-index addressing. 398 Scale = S; 399 IndexReg = getRegForGEPIndex(Op); 400 if (IndexReg == 0) 401 return false; 402 } else 403 // Unsupported. 404 goto unsupported_gep; 405 } 406 } 407 // Check for displacement overflow. 408 if (!isInt32(Disp)) 409 break; 410 // Ok, the GEP indices were covered by constant-offset and scaled-index 411 // addressing. Update the address state and move on to examining the base. 412 AM.IndexReg = IndexReg; 413 AM.Scale = Scale; 414 AM.Disp = (uint32_t)Disp; 415 return X86SelectAddress(U->getOperand(0), AM, isCall); 416 unsupported_gep: 417 // Ok, the GEP indices weren't all covered. 418 break; 419 } 420 } 421 422 // Handle constant address. 423 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 424 // Can't handle alternate code models yet. 425 if (TM.getCodeModel() != CodeModel::Default && 426 TM.getCodeModel() != CodeModel::Small) 427 return false; 428 429 // RIP-relative addresses can't have additional register operands. 430 if (getTargetMachine()->symbolicAddressesAreRIPRel() && 431 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 432 return false; 433 434 // Set up the basic address. 435 AM.GV = GV; 436 if (!isCall && 437 TM.getRelocationModel() == Reloc::PIC_ && 438 !Subtarget->is64Bit()) 439 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 440 441 // Emit an extra load if the ABI requires it. 442 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) { 443 // Check to see if we've already materialized this 444 // value in a register in this block. 445 if (unsigned Reg = LocalValueMap[V]) { 446 AM.Base.Reg = Reg; 447 AM.GV = 0; 448 return true; 449 } 450 // Issue load from stub if necessary. 451 unsigned Opc = 0; 452 const TargetRegisterClass *RC = NULL; 453 if (TLI.getPointerTy() == MVT::i32) { 454 Opc = X86::MOV32rm; 455 RC = X86::GR32RegisterClass; 456 } else { 457 Opc = X86::MOV64rm; 458 RC = X86::GR64RegisterClass; 459 } 460 461 X86AddressMode StubAM; 462 StubAM.Base.Reg = AM.Base.Reg; 463 StubAM.GV = AM.GV; 464 unsigned ResultReg = createResultReg(RC); 465 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM); 466 467 // Now construct the final address. Note that the Disp, Scale, 468 // and Index values may already be set here. 469 AM.Base.Reg = ResultReg; 470 AM.GV = 0; 471 472 // Prevent loading GV stub multiple times in same MBB. 473 LocalValueMap[V] = AM.Base.Reg; 474 } 475 return true; 476 } 477 478 // If all else fails, try to materialize the value in a register. 479 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) { 480 if (AM.Base.Reg == 0) { 481 AM.Base.Reg = getRegForValue(V); 482 return AM.Base.Reg != 0; 483 } 484 if (AM.IndexReg == 0) { 485 assert(AM.Scale == 1 && "Scale with no index!"); 486 AM.IndexReg = getRegForValue(V); 487 return AM.IndexReg != 0; 488 } 489 } 490 491 return false; 492} 493 494/// X86SelectStore - Select and emit code to implement store instructions. 495bool X86FastISel::X86SelectStore(Instruction* I) { 496 MVT VT; 497 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 498 return false; 499 500 X86AddressMode AM; 501 if (!X86SelectAddress(I->getOperand(1), AM, false)) 502 return false; 503 504 return X86FastEmitStore(VT, I->getOperand(0), AM); 505} 506 507/// X86SelectLoad - Select and emit code to implement load instructions. 508/// 509bool X86FastISel::X86SelectLoad(Instruction *I) { 510 MVT VT; 511 if (!isTypeLegal(I->getType(), VT)) 512 return false; 513 514 X86AddressMode AM; 515 if (!X86SelectAddress(I->getOperand(0), AM, false)) 516 return false; 517 518 unsigned ResultReg = 0; 519 if (X86FastEmitLoad(VT, AM, ResultReg)) { 520 UpdateValueMap(I, ResultReg); 521 return true; 522 } 523 return false; 524} 525 526static unsigned X86ChooseCmpOpcode(MVT VT) { 527 switch (VT.getSimpleVT()) { 528 default: return 0; 529 case MVT::i8: return X86::CMP8rr; 530 case MVT::i16: return X86::CMP16rr; 531 case MVT::i32: return X86::CMP32rr; 532 case MVT::i64: return X86::CMP64rr; 533 case MVT::f32: return X86::UCOMISSrr; 534 case MVT::f64: return X86::UCOMISDrr; 535 } 536} 537 538/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 539/// of the comparison, return an opcode that works for the compare (e.g. 540/// CMP32ri) otherwise return 0. 541static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) { 542 switch (VT.getSimpleVT()) { 543 // Otherwise, we can't fold the immediate into this comparison. 544 default: return 0; 545 case MVT::i8: return X86::CMP8ri; 546 case MVT::i16: return X86::CMP16ri; 547 case MVT::i32: return X86::CMP32ri; 548 case MVT::i64: 549 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 550 // field. 551 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 552 return X86::CMP64ri32; 553 return 0; 554 } 555} 556 557bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) { 558 unsigned Op0Reg = getRegForValue(Op0); 559 if (Op0Reg == 0) return false; 560 561 // Handle 'null' like i32/i64 0. 562 if (isa<ConstantPointerNull>(Op1)) 563 Op1 = Constant::getNullValue(TD.getIntPtrType()); 564 565 // We have two options: compare with register or immediate. If the RHS of 566 // the compare is an immediate that we can fold into this compare, use 567 // CMPri, otherwise use CMPrr. 568 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 569 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 570 BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg) 571 .addImm(Op1C->getSExtValue()); 572 return true; 573 } 574 } 575 576 unsigned CompareOpc = X86ChooseCmpOpcode(VT); 577 if (CompareOpc == 0) return false; 578 579 unsigned Op1Reg = getRegForValue(Op1); 580 if (Op1Reg == 0) return false; 581 BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 582 583 return true; 584} 585 586bool X86FastISel::X86SelectCmp(Instruction *I) { 587 CmpInst *CI = cast<CmpInst>(I); 588 589 MVT VT; 590 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 591 return false; 592 593 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 594 unsigned SetCCOpc; 595 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 596 switch (CI->getPredicate()) { 597 case CmpInst::FCMP_OEQ: { 598 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 599 return false; 600 601 unsigned EReg = createResultReg(&X86::GR8RegClass); 602 unsigned NPReg = createResultReg(&X86::GR8RegClass); 603 BuildMI(MBB, TII.get(X86::SETEr), EReg); 604 BuildMI(MBB, TII.get(X86::SETNPr), NPReg); 605 BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 606 UpdateValueMap(I, ResultReg); 607 return true; 608 } 609 case CmpInst::FCMP_UNE: { 610 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 611 return false; 612 613 unsigned NEReg = createResultReg(&X86::GR8RegClass); 614 unsigned PReg = createResultReg(&X86::GR8RegClass); 615 BuildMI(MBB, TII.get(X86::SETNEr), NEReg); 616 BuildMI(MBB, TII.get(X86::SETPr), PReg); 617 BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 618 UpdateValueMap(I, ResultReg); 619 return true; 620 } 621 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 622 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 623 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 624 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 625 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 626 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 627 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 628 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 629 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 630 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 631 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 632 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 633 634 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 635 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 636 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 637 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 638 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 639 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 640 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 641 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 642 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 643 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 644 default: 645 return false; 646 } 647 648 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 649 if (SwapArgs) 650 std::swap(Op0, Op1); 651 652 // Emit a compare of Op0/Op1. 653 if (!X86FastEmitCompare(Op0, Op1, VT)) 654 return false; 655 656 BuildMI(MBB, TII.get(SetCCOpc), ResultReg); 657 UpdateValueMap(I, ResultReg); 658 return true; 659} 660 661bool X86FastISel::X86SelectZExt(Instruction *I) { 662 // Special-case hack: The only i1 values we know how to produce currently 663 // set the upper bits of an i8 value to zero. 664 if (I->getType() == Type::Int8Ty && 665 I->getOperand(0)->getType() == Type::Int1Ty) { 666 unsigned ResultReg = getRegForValue(I->getOperand(0)); 667 if (ResultReg == 0) return false; 668 UpdateValueMap(I, ResultReg); 669 return true; 670 } 671 672 return false; 673} 674 675 676bool X86FastISel::X86SelectBranch(Instruction *I) { 677 // Unconditional branches are selected by tablegen-generated code. 678 // Handle a conditional branch. 679 BranchInst *BI = cast<BranchInst>(I); 680 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 681 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 682 683 // Fold the common case of a conditional branch with a comparison. 684 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 685 if (CI->hasOneUse()) { 686 MVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 687 688 // Try to take advantage of fallthrough opportunities. 689 CmpInst::Predicate Predicate = CI->getPredicate(); 690 if (MBB->isLayoutSuccessor(TrueMBB)) { 691 std::swap(TrueMBB, FalseMBB); 692 Predicate = CmpInst::getInversePredicate(Predicate); 693 } 694 695 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 696 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 697 698 switch (Predicate) { 699 case CmpInst::FCMP_OEQ: 700 std::swap(TrueMBB, FalseMBB); 701 Predicate = CmpInst::FCMP_UNE; 702 // FALL THROUGH 703 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break; 704 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break; 705 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break; 706 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break; 707 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break; 708 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break; 709 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break; 710 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break; 711 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break; 712 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break; 713 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break; 714 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break; 715 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break; 716 717 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break; 718 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break; 719 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break; 720 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break; 721 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break; 722 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break; 723 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break; 724 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break; 725 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break; 726 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break; 727 default: 728 return false; 729 } 730 731 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 732 if (SwapArgs) 733 std::swap(Op0, Op1); 734 735 // Emit a compare of the LHS and RHS, setting the flags. 736 if (!X86FastEmitCompare(Op0, Op1, VT)) 737 return false; 738 739 BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB); 740 741 if (Predicate == CmpInst::FCMP_UNE) { 742 // X86 requires a second branch to handle UNE (and OEQ, 743 // which is mapped to UNE above). 744 BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB); 745 } 746 747 FastEmitBranch(FalseMBB); 748 MBB->addSuccessor(TrueMBB); 749 return true; 750 } 751 } else if (ExtractValueInst *EI = 752 dyn_cast<ExtractValueInst>(BI->getCondition())) { 753 // Check to see if the branch instruction is from an "arithmetic with 754 // overflow" intrinsic. The main way these intrinsics are used is: 755 // 756 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 757 // %sum = extractvalue { i32, i1 } %t, 0 758 // %obit = extractvalue { i32, i1 } %t, 1 759 // br i1 %obit, label %overflow, label %normal 760 // 761 // The %sum and %obit are converted in an ADD and a SETO/SETC before 762 // reaching the branch. Therefore, we search backwards through the MBB 763 // looking for the SETO/SETC instruction. If an instruction modifies the 764 // EFLAGS register before we reach the SETO/SETC instruction, then we can't 765 // convert the branch into a JO/JC instruction. 766 767 Value *Agg = EI->getAggregateOperand(); 768 769 if (CallInst *CI = dyn_cast<CallInst>(Agg)) { 770 Function *F = CI->getCalledFunction(); 771 772 if (F && F->isDeclaration()) { 773 switch (F->getIntrinsicID()) { 774 default: break; 775 case Intrinsic::sadd_with_overflow: 776 case Intrinsic::uadd_with_overflow: { 777 const MachineInstr *SetMI = 0; 778 unsigned Reg = lookUpRegForValue(EI); 779 780 for (MachineBasicBlock::const_reverse_iterator 781 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 782 const MachineInstr &MI = *RI; 783 784 if (MI.modifiesRegister(Reg)) { 785 unsigned Src, Dst; 786 787 if (getInstrInfo()->isMoveInstr(MI, Src, Dst)) { 788 Reg = Src; 789 continue; 790 } 791 792 SetMI = &MI; 793 break; 794 } 795 796 const TargetInstrDesc &TID = MI.getDesc(); 797 const unsigned *ImpDefs = TID.getImplicitDefs(); 798 799 if (TID.hasUnmodeledSideEffects()) break; 800 801 bool ModifiesEFlags = false; 802 803 if (ImpDefs) { 804 for (unsigned u = 0; ImpDefs[u]; ++u) 805 if (ImpDefs[u] == X86::EFLAGS) { 806 ModifiesEFlags = true; 807 break; 808 } 809 } 810 811 if (ModifiesEFlags) break; 812 } 813 814 if (SetMI) { 815 unsigned OpCode = SetMI->getOpcode(); 816 817 if (OpCode == X86::SETOr || OpCode == X86::SETCr) { 818 BuildMI(MBB, TII.get((OpCode == X86::SETOr) ? 819 X86::JO : X86::JC)).addMBB(TrueMBB); 820 FastEmitBranch(FalseMBB); 821 MBB->addSuccessor(TrueMBB); 822 return true; 823 } 824 } 825 } 826 } 827 } 828 } 829 } 830 831 // Otherwise do a clumsy setcc and re-test it. 832 unsigned OpReg = getRegForValue(BI->getCondition()); 833 if (OpReg == 0) return false; 834 835 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 836 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB); 837 FastEmitBranch(FalseMBB); 838 MBB->addSuccessor(TrueMBB); 839 return true; 840} 841 842bool X86FastISel::X86SelectShift(Instruction *I) { 843 unsigned CReg = 0, OpReg = 0, OpImm = 0; 844 const TargetRegisterClass *RC = NULL; 845 if (I->getType() == Type::Int8Ty) { 846 CReg = X86::CL; 847 RC = &X86::GR8RegClass; 848 switch (I->getOpcode()) { 849 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 850 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 851 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 852 default: return false; 853 } 854 } else if (I->getType() == Type::Int16Ty) { 855 CReg = X86::CX; 856 RC = &X86::GR16RegClass; 857 switch (I->getOpcode()) { 858 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 859 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 860 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 861 default: return false; 862 } 863 } else if (I->getType() == Type::Int32Ty) { 864 CReg = X86::ECX; 865 RC = &X86::GR32RegClass; 866 switch (I->getOpcode()) { 867 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 868 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 869 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 870 default: return false; 871 } 872 } else if (I->getType() == Type::Int64Ty) { 873 CReg = X86::RCX; 874 RC = &X86::GR64RegClass; 875 switch (I->getOpcode()) { 876 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 877 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 878 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 879 default: return false; 880 } 881 } else { 882 return false; 883 } 884 885 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 886 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 887 return false; 888 889 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 890 if (Op0Reg == 0) return false; 891 892 // Fold immediate in shl(x,3). 893 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 894 unsigned ResultReg = createResultReg(RC); 895 BuildMI(MBB, TII.get(OpImm), 896 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue()); 897 UpdateValueMap(I, ResultReg); 898 return true; 899 } 900 901 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 902 if (Op1Reg == 0) return false; 903 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC); 904 905 // The shift instruction uses X86::CL. If we defined a super-register 906 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 907 // we're doing here. 908 if (CReg != X86::CL) 909 BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL) 910 .addReg(CReg).addImm(X86::SUBREG_8BIT); 911 912 unsigned ResultReg = createResultReg(RC); 913 BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg); 914 UpdateValueMap(I, ResultReg); 915 return true; 916} 917 918bool X86FastISel::X86SelectSelect(Instruction *I) { 919 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 920 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 921 return false; 922 923 unsigned Opc = 0; 924 const TargetRegisterClass *RC = NULL; 925 if (VT.getSimpleVT() == MVT::i16) { 926 Opc = X86::CMOVE16rr; 927 RC = &X86::GR16RegClass; 928 } else if (VT.getSimpleVT() == MVT::i32) { 929 Opc = X86::CMOVE32rr; 930 RC = &X86::GR32RegClass; 931 } else if (VT.getSimpleVT() == MVT::i64) { 932 Opc = X86::CMOVE64rr; 933 RC = &X86::GR64RegClass; 934 } else { 935 return false; 936 } 937 938 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 939 if (Op0Reg == 0) return false; 940 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 941 if (Op1Reg == 0) return false; 942 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 943 if (Op2Reg == 0) return false; 944 945 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 946 unsigned ResultReg = createResultReg(RC); 947 BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 948 UpdateValueMap(I, ResultReg); 949 return true; 950} 951 952bool X86FastISel::X86SelectFPExt(Instruction *I) { 953 // fpext from float to double. 954 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) { 955 Value *V = I->getOperand(0); 956 if (V->getType() == Type::FloatTy) { 957 unsigned OpReg = getRegForValue(V); 958 if (OpReg == 0) return false; 959 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 960 BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 961 UpdateValueMap(I, ResultReg); 962 return true; 963 } 964 } 965 966 return false; 967} 968 969bool X86FastISel::X86SelectFPTrunc(Instruction *I) { 970 if (Subtarget->hasSSE2()) { 971 if (I->getType() == Type::FloatTy) { 972 Value *V = I->getOperand(0); 973 if (V->getType() == Type::DoubleTy) { 974 unsigned OpReg = getRegForValue(V); 975 if (OpReg == 0) return false; 976 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 977 BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 978 UpdateValueMap(I, ResultReg); 979 return true; 980 } 981 } 982 } 983 984 return false; 985} 986 987bool X86FastISel::X86SelectTrunc(Instruction *I) { 988 if (Subtarget->is64Bit()) 989 // All other cases should be handled by the tblgen generated code. 990 return false; 991 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 992 MVT DstVT = TLI.getValueType(I->getType()); 993 if (DstVT != MVT::i8) 994 // All other cases should be handled by the tblgen generated code. 995 return false; 996 if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 997 // All other cases should be handled by the tblgen generated code. 998 return false; 999 1000 unsigned InputReg = getRegForValue(I->getOperand(0)); 1001 if (!InputReg) 1002 // Unhandled operand. Halt "fast" selection and bail. 1003 return false; 1004 1005 // First issue a copy to GR16_ or GR32_. 1006 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_; 1007 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1008 ? X86::GR16_RegisterClass : X86::GR32_RegisterClass; 1009 unsigned CopyReg = createResultReg(CopyRC); 1010 BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg); 1011 1012 // Then issue an extract_subreg. 1013 unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT); 1014 if (!ResultReg) 1015 return false; 1016 1017 UpdateValueMap(I, ResultReg); 1018 return true; 1019} 1020 1021bool X86FastISel::X86SelectExtractValue(Instruction *I) { 1022 ExtractValueInst *EI = cast<ExtractValueInst>(I); 1023 Value *Agg = EI->getAggregateOperand(); 1024 1025 if (CallInst *CI = dyn_cast<CallInst>(Agg)) { 1026 Function *F = CI->getCalledFunction(); 1027 1028 if (F && F->isDeclaration()) { 1029 switch (F->getIntrinsicID()) { 1030 default: break; 1031 case Intrinsic::sadd_with_overflow: 1032 case Intrinsic::uadd_with_overflow: 1033 // Cheat a little. We know that the registers for "add" and "seto" are 1034 // allocated sequentially. However, we only keep track of the register 1035 // for "add" in the value map. Use extractvalue's index to get the 1036 // correct register for "seto". 1037 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 1038 return true; 1039 } 1040 } 1041 } 1042 1043 return false; 1044} 1045 1046bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) { 1047 // FIXME: Handle more intrinsics. 1048 switch (Intrinsic) { 1049 default: return false; 1050 case Intrinsic::sadd_with_overflow: 1051 case Intrinsic::uadd_with_overflow: { 1052 // Replace "add with overflow" intrinsics with an "add" instruction followed 1053 // by a seto/setc instruction. Later on, when the "extractvalue" 1054 // instructions are encountered, we use the fact that two registers were 1055 // created sequentially to get the correct registers for the "sum" and the 1056 // "overflow bit". 1057 MVT VT; 1058 const Function *Callee = I.getCalledFunction(); 1059 const Type *RetTy = 1060 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1061 1062 if (!isTypeLegal(RetTy, VT)) 1063 return false; 1064 1065 Value *Op1 = I.getOperand(1); 1066 Value *Op2 = I.getOperand(2); 1067 unsigned Reg1 = getRegForValue(Op1); 1068 unsigned Reg2 = getRegForValue(Op2); 1069 1070 if (Reg1 == 0 || Reg2 == 0) 1071 // FIXME: Handle values *not* in registers. 1072 return false; 1073 1074 unsigned OpC = 0; 1075 1076 if (VT == MVT::i32) 1077 OpC = X86::ADD32rr; 1078 else if (VT == MVT::i64) 1079 OpC = X86::ADD64rr; 1080 else 1081 return false; 1082 1083 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1084 BuildMI(MBB, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 1085 UpdateValueMap(&I, ResultReg); 1086 1087 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 1088 BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ? 1089 X86::SETOr : X86::SETCr), ResultReg); 1090 return true; 1091 } 1092 } 1093} 1094 1095bool X86FastISel::X86SelectCall(Instruction *I) { 1096 CallInst *CI = cast<CallInst>(I); 1097 Value *Callee = I->getOperand(0); 1098 1099 // Can't handle inline asm yet. 1100 if (isa<InlineAsm>(Callee)) 1101 return false; 1102 1103 // Handle intrinsic calls. 1104 if (Function *F = CI->getCalledFunction()) 1105 if (F->isDeclaration()) 1106 if (unsigned IID = F->getIntrinsicID()) 1107 return X86VisitIntrinsicCall(*CI, IID); 1108 1109 // Handle only C and fastcc calling conventions for now. 1110 CallSite CS(CI); 1111 unsigned CC = CS.getCallingConv(); 1112 if (CC != CallingConv::C && 1113 CC != CallingConv::Fast && 1114 CC != CallingConv::X86_FastCall) 1115 return false; 1116 1117 // Let SDISel handle vararg functions. 1118 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1119 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1120 if (FTy->isVarArg()) 1121 return false; 1122 1123 // Handle *simple* calls for now. 1124 const Type *RetTy = CS.getType(); 1125 MVT RetVT; 1126 if (RetTy == Type::VoidTy) 1127 RetVT = MVT::isVoid; 1128 else if (!isTypeLegal(RetTy, RetVT, true)) 1129 return false; 1130 1131 // Materialize callee address in a register. FIXME: GV address can be 1132 // handled with a CALLpcrel32 instead. 1133 X86AddressMode CalleeAM; 1134 if (!X86SelectAddress(Callee, CalleeAM, true)) 1135 return false; 1136 unsigned CalleeOp = 0; 1137 GlobalValue *GV = 0; 1138 if (CalleeAM.Base.Reg != 0) { 1139 assert(CalleeAM.GV == 0); 1140 CalleeOp = CalleeAM.Base.Reg; 1141 } else if (CalleeAM.GV != 0) { 1142 assert(CalleeAM.GV != 0); 1143 GV = CalleeAM.GV; 1144 } else 1145 return false; 1146 1147 // Allow calls which produce i1 results. 1148 bool AndToI1 = false; 1149 if (RetVT == MVT::i1) { 1150 RetVT = MVT::i8; 1151 AndToI1 = true; 1152 } 1153 1154 // Deal with call operands first. 1155 SmallVector<Value*, 8> ArgVals; 1156 SmallVector<unsigned, 8> Args; 1157 SmallVector<MVT, 8> ArgVTs; 1158 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1159 Args.reserve(CS.arg_size()); 1160 ArgVals.reserve(CS.arg_size()); 1161 ArgVTs.reserve(CS.arg_size()); 1162 ArgFlags.reserve(CS.arg_size()); 1163 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1164 i != e; ++i) { 1165 unsigned Arg = getRegForValue(*i); 1166 if (Arg == 0) 1167 return false; 1168 ISD::ArgFlagsTy Flags; 1169 unsigned AttrInd = i - CS.arg_begin() + 1; 1170 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1171 Flags.setSExt(); 1172 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1173 Flags.setZExt(); 1174 1175 // FIXME: Only handle *easy* calls for now. 1176 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1177 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1178 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1179 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1180 return false; 1181 1182 const Type *ArgTy = (*i)->getType(); 1183 MVT ArgVT; 1184 if (!isTypeLegal(ArgTy, ArgVT)) 1185 return false; 1186 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1187 Flags.setOrigAlign(OriginalAlignment); 1188 1189 Args.push_back(Arg); 1190 ArgVals.push_back(*i); 1191 ArgVTs.push_back(ArgVT); 1192 ArgFlags.push_back(Flags); 1193 } 1194 1195 // Analyze operands of the call, assigning locations to each operand. 1196 SmallVector<CCValAssign, 16> ArgLocs; 1197 CCState CCInfo(CC, false, TM, ArgLocs); 1198 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 1199 1200 // Get a count of how many bytes are to be pushed on the stack. 1201 unsigned NumBytes = CCInfo.getNextStackOffset(); 1202 1203 // Issue CALLSEQ_START 1204 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1205 BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes); 1206 1207 // Process argument: walk the register/memloc assignments, inserting 1208 // copies / loads. 1209 SmallVector<unsigned, 4> RegArgs; 1210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1211 CCValAssign &VA = ArgLocs[i]; 1212 unsigned Arg = Args[VA.getValNo()]; 1213 MVT ArgVT = ArgVTs[VA.getValNo()]; 1214 1215 // Promote the value if needed. 1216 switch (VA.getLocInfo()) { 1217 default: assert(0 && "Unknown loc info!"); 1218 case CCValAssign::Full: break; 1219 case CCValAssign::SExt: { 1220 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1221 Arg, ArgVT, Arg); 1222 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1223 ArgVT = VA.getLocVT(); 1224 break; 1225 } 1226 case CCValAssign::ZExt: { 1227 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1228 Arg, ArgVT, Arg); 1229 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1230 ArgVT = VA.getLocVT(); 1231 break; 1232 } 1233 case CCValAssign::AExt: { 1234 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1235 Arg, ArgVT, Arg); 1236 if (!Emitted) 1237 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1238 Arg, ArgVT, Arg); 1239 if (!Emitted) 1240 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1241 Arg, ArgVT, Arg); 1242 1243 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1244 ArgVT = VA.getLocVT(); 1245 break; 1246 } 1247 } 1248 1249 if (VA.isRegLoc()) { 1250 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 1251 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 1252 Arg, RC, RC); 1253 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1254 RegArgs.push_back(VA.getLocReg()); 1255 } else { 1256 unsigned LocMemOffset = VA.getLocMemOffset(); 1257 X86AddressMode AM; 1258 AM.Base.Reg = StackPtr; 1259 AM.Disp = LocMemOffset; 1260 Value *ArgVal = ArgVals[VA.getValNo()]; 1261 1262 // If this is a really simple value, emit this with the Value* version of 1263 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 1264 // can cause us to reevaluate the argument. 1265 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 1266 X86FastEmitStore(ArgVT, ArgVal, AM); 1267 else 1268 X86FastEmitStore(ArgVT, Arg, AM); 1269 } 1270 } 1271 1272 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1273 // GOT pointer. 1274 if (!Subtarget->is64Bit() && 1275 TM.getRelocationModel() == Reloc::PIC_ && 1276 Subtarget->isPICStyleGOT()) { 1277 TargetRegisterClass *RC = X86::GR32RegisterClass; 1278 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 1279 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); 1280 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1281 } 1282 1283 // Issue the call. 1284 unsigned CallOpc = CalleeOp 1285 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r) 1286 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32); 1287 MachineInstrBuilder MIB = CalleeOp 1288 ? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp) 1289 : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV); 1290 1291 // Add an implicit use GOT pointer in EBX. 1292 if (!Subtarget->is64Bit() && 1293 TM.getRelocationModel() == Reloc::PIC_ && 1294 Subtarget->isPICStyleGOT()) 1295 MIB.addReg(X86::EBX); 1296 1297 // Add implicit physical register uses to the call. 1298 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1299 MIB.addReg(RegArgs[i]); 1300 1301 // Issue CALLSEQ_END 1302 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1303 BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 1304 1305 // Now handle call return value (if any). 1306 if (RetVT.getSimpleVT() != MVT::isVoid) { 1307 SmallVector<CCValAssign, 16> RVLocs; 1308 CCState CCInfo(CC, false, TM, RVLocs); 1309 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 1310 1311 // Copy all of the result registers out of their specified physreg. 1312 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 1313 MVT CopyVT = RVLocs[0].getValVT(); 1314 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1315 TargetRegisterClass *SrcRC = DstRC; 1316 1317 // If this is a call to a function that returns an fp value on the x87 fp 1318 // stack, but where we prefer to use the value in xmm registers, copy it 1319 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1320 if ((RVLocs[0].getLocReg() == X86::ST0 || 1321 RVLocs[0].getLocReg() == X86::ST1) && 1322 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 1323 CopyVT = MVT::f80; 1324 SrcRC = X86::RSTRegisterClass; 1325 DstRC = X86::RFP80RegisterClass; 1326 } 1327 1328 unsigned ResultReg = createResultReg(DstRC); 1329 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1330 RVLocs[0].getLocReg(), DstRC, SrcRC); 1331 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1332 if (CopyVT != RVLocs[0].getValVT()) { 1333 // Round the F80 the right size, which also moves to the appropriate xmm 1334 // register. This is accomplished by storing the F80 value in memory and 1335 // then loading it back. Ewww... 1336 MVT ResVT = RVLocs[0].getValVT(); 1337 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1338 unsigned MemSize = ResVT.getSizeInBits()/8; 1339 int FI = MFI.CreateStackObject(MemSize, MemSize); 1340 addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg); 1341 DstRC = ResVT == MVT::f32 1342 ? X86::FR32RegisterClass : X86::FR64RegisterClass; 1343 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1344 ResultReg = createResultReg(DstRC); 1345 addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI); 1346 } 1347 1348 if (AndToI1) { 1349 // Mask out all but lowest bit for some call which produces an i1. 1350 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 1351 BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 1352 ResultReg = AndResult; 1353 } 1354 1355 UpdateValueMap(I, ResultReg); 1356 } 1357 1358 return true; 1359} 1360 1361 1362bool 1363X86FastISel::TargetSelectInstruction(Instruction *I) { 1364 switch (I->getOpcode()) { 1365 default: break; 1366 case Instruction::Load: 1367 return X86SelectLoad(I); 1368 case Instruction::Store: 1369 return X86SelectStore(I); 1370 case Instruction::ICmp: 1371 case Instruction::FCmp: 1372 return X86SelectCmp(I); 1373 case Instruction::ZExt: 1374 return X86SelectZExt(I); 1375 case Instruction::Br: 1376 return X86SelectBranch(I); 1377 case Instruction::Call: 1378 return X86SelectCall(I); 1379 case Instruction::LShr: 1380 case Instruction::AShr: 1381 case Instruction::Shl: 1382 return X86SelectShift(I); 1383 case Instruction::Select: 1384 return X86SelectSelect(I); 1385 case Instruction::Trunc: 1386 return X86SelectTrunc(I); 1387 case Instruction::FPExt: 1388 return X86SelectFPExt(I); 1389 case Instruction::FPTrunc: 1390 return X86SelectFPTrunc(I); 1391 case Instruction::ExtractValue: 1392 return X86SelectExtractValue(I); 1393 } 1394 1395 return false; 1396} 1397 1398unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { 1399 MVT VT; 1400 if (!isTypeLegal(C->getType(), VT)) 1401 return false; 1402 1403 // Get opcode and regclass of the output for the given load instruction. 1404 unsigned Opc = 0; 1405 const TargetRegisterClass *RC = NULL; 1406 switch (VT.getSimpleVT()) { 1407 default: return false; 1408 case MVT::i8: 1409 Opc = X86::MOV8rm; 1410 RC = X86::GR8RegisterClass; 1411 break; 1412 case MVT::i16: 1413 Opc = X86::MOV16rm; 1414 RC = X86::GR16RegisterClass; 1415 break; 1416 case MVT::i32: 1417 Opc = X86::MOV32rm; 1418 RC = X86::GR32RegisterClass; 1419 break; 1420 case MVT::i64: 1421 // Must be in x86-64 mode. 1422 Opc = X86::MOV64rm; 1423 RC = X86::GR64RegisterClass; 1424 break; 1425 case MVT::f32: 1426 if (Subtarget->hasSSE1()) { 1427 Opc = X86::MOVSSrm; 1428 RC = X86::FR32RegisterClass; 1429 } else { 1430 Opc = X86::LD_Fp32m; 1431 RC = X86::RFP32RegisterClass; 1432 } 1433 break; 1434 case MVT::f64: 1435 if (Subtarget->hasSSE2()) { 1436 Opc = X86::MOVSDrm; 1437 RC = X86::FR64RegisterClass; 1438 } else { 1439 Opc = X86::LD_Fp64m; 1440 RC = X86::RFP64RegisterClass; 1441 } 1442 break; 1443 case MVT::f80: 1444 // No f80 support yet. 1445 return false; 1446 } 1447 1448 // Materialize addresses with LEA instructions. 1449 if (isa<GlobalValue>(C)) { 1450 X86AddressMode AM; 1451 if (X86SelectAddress(C, AM, false)) { 1452 if (TLI.getPointerTy() == MVT::i32) 1453 Opc = X86::LEA32r; 1454 else 1455 Opc = X86::LEA64r; 1456 unsigned ResultReg = createResultReg(RC); 1457 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM); 1458 return ResultReg; 1459 } 1460 return 0; 1461 } 1462 1463 // MachineConstantPool wants an explicit alignment. 1464 unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType()); 1465 if (Align == 0) { 1466 // Alignment of vector types. FIXME! 1467 Align = TD.getABITypeSize(C->getType()); 1468 Align = Log2_64(Align); 1469 } 1470 1471 // x86-32 PIC requires a PIC base register for constant pools. 1472 unsigned PICBase = 0; 1473 if (TM.getRelocationModel() == Reloc::PIC_ && 1474 !Subtarget->is64Bit()) 1475 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1476 1477 // Create the load from the constant pool. 1478 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 1479 unsigned ResultReg = createResultReg(RC); 1480 addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset, 1481 PICBase); 1482 1483 return ResultReg; 1484} 1485 1486unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { 1487 // Fail on dynamic allocas. At this point, getRegForValue has already 1488 // checked its CSE maps, so if we're here trying to handle a dynamic 1489 // alloca, we're not going to succeed. X86SelectAddress has a 1490 // check for dynamic allocas, because it's called directly from 1491 // various places, but TargetMaterializeAlloca also needs a check 1492 // in order to avoid recursion between getRegForValue, 1493 // X86SelectAddrss, and TargetMaterializeAlloca. 1494 if (!StaticAllocaMap.count(C)) 1495 return 0; 1496 1497 X86AddressMode AM; 1498 if (!X86SelectAddress(C, AM, false)) 1499 return 0; 1500 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 1501 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 1502 unsigned ResultReg = createResultReg(RC); 1503 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM); 1504 return ResultReg; 1505} 1506 1507namespace llvm { 1508 llvm::FastISel *X86::createFastISel(MachineFunction &mf, 1509 MachineModuleInfo *mmi, 1510 DenseMap<const Value *, unsigned> &vm, 1511 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 1512 DenseMap<const AllocaInst *, int> &am 1513#ifndef NDEBUG 1514 , SmallSet<Instruction*, 8> &cil 1515#endif 1516 ) { 1517 return new X86FastISel(mf, mmi, vm, bm, am 1518#ifndef NDEBUG 1519 , cil 1520#endif 1521 ); 1522 } 1523} 1524