X86FastISel.cpp revision bd13fb62541136a4891d702feec8b7aba5bf695a
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Instructions.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/CodeGen/FastISel.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/Support/CallSite.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/GetElementPtrTypeIterator.h" 34#include "llvm/Target/TargetOptions.h" 35using namespace llvm; 36 37namespace { 38 39class X86FastISel : public FastISel { 40 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 41 /// make the right decision when generating code for different targets. 42 const X86Subtarget *Subtarget; 43 44 /// StackPtr - Register used as the stack pointer. 45 /// 46 unsigned StackPtr; 47 48 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 49 /// floating point ops. 50 /// When SSE is available, use it for f32 operations. 51 /// When SSE2 is available, use it for f64 operations. 52 bool X86ScalarSSEf64; 53 bool X86ScalarSSEf32; 54 55public: 56 explicit X86FastISel(MachineFunction &mf, 57 MachineModuleInfo *mmi, 58 DwarfWriter *dw, 59 DenseMap<const Value *, unsigned> &vm, 60 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 61 DenseMap<const AllocaInst *, int> &am 62#ifndef NDEBUG 63 , SmallSet<Instruction*, 8> &cil 64#endif 65 ) 66 : FastISel(mf, mmi, dw, vm, bm, am 67#ifndef NDEBUG 68 , cil 69#endif 70 ) { 71 Subtarget = &TM.getSubtarget<X86Subtarget>(); 72 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 73 X86ScalarSSEf64 = Subtarget->hasSSE2(); 74 X86ScalarSSEf32 = Subtarget->hasSSE1(); 75 } 76 77 virtual bool TargetSelectInstruction(Instruction *I); 78 79#include "X86GenFastISel.inc" 80 81private: 82 bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT); 83 84 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 85 86 bool X86FastEmitStore(EVT VT, Value *Val, 87 const X86AddressMode &AM); 88 bool X86FastEmitStore(EVT VT, unsigned Val, 89 const X86AddressMode &AM); 90 91 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 92 unsigned &ResultReg); 93 94 bool X86SelectAddress(Value *V, X86AddressMode &AM); 95 bool X86SelectCallAddress(Value *V, X86AddressMode &AM); 96 97 bool X86SelectLoad(Instruction *I); 98 99 bool X86SelectStore(Instruction *I); 100 101 bool X86SelectCmp(Instruction *I); 102 103 bool X86SelectZExt(Instruction *I); 104 105 bool X86SelectBranch(Instruction *I); 106 107 bool X86SelectShift(Instruction *I); 108 109 bool X86SelectSelect(Instruction *I); 110 111 bool X86SelectTrunc(Instruction *I); 112 113 bool X86SelectFPExt(Instruction *I); 114 bool X86SelectFPTrunc(Instruction *I); 115 116 bool X86SelectExtractValue(Instruction *I); 117 118 bool X86VisitIntrinsicCall(IntrinsicInst &I); 119 bool X86SelectCall(Instruction *I); 120 121 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false); 122 123 const X86InstrInfo *getInstrInfo() const { 124 return getTargetMachine()->getInstrInfo(); 125 } 126 const X86TargetMachine *getTargetMachine() const { 127 return static_cast<const X86TargetMachine *>(&TM); 128 } 129 130 unsigned TargetMaterializeConstant(Constant *C); 131 132 unsigned TargetMaterializeAlloca(AllocaInst *C); 133 134 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 135 /// computed in an SSE register, not on the X87 floating point stack. 136 bool isScalarFPTypeInSSEReg(EVT VT) const { 137 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 138 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 139 } 140 141 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); 142}; 143 144} // end anonymous namespace. 145 146bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { 147 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 148 if (VT == MVT::Other || !VT.isSimple()) 149 // Unhandled type. Halt "fast" selection and bail. 150 return false; 151 152 // For now, require SSE/SSE2 for performing floating-point operations, 153 // since x87 requires additional work. 154 if (VT == MVT::f64 && !X86ScalarSSEf64) 155 return false; 156 if (VT == MVT::f32 && !X86ScalarSSEf32) 157 return false; 158 // Similarly, no f80 support yet. 159 if (VT == MVT::f80) 160 return false; 161 // We only handle legal types. For example, on x86-32 the instruction 162 // selector contains all of the 64-bit instructions from x86-64, 163 // under the assumption that i64 won't be used if the target doesn't 164 // support it. 165 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 166} 167 168#include "X86GenCallingConv.inc" 169 170/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 171/// convention. 172CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC, 173 bool isTaillCall) { 174 if (Subtarget->is64Bit()) { 175 if (Subtarget->isTargetWin64()) 176 return CC_X86_Win64_C; 177 else 178 return CC_X86_64_C; 179 } 180 181 if (CC == CallingConv::X86_FastCall) 182 return CC_X86_32_FastCall; 183 else if (CC == CallingConv::Fast) 184 return CC_X86_32_FastCC; 185 else 186 return CC_X86_32_C; 187} 188 189/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 190/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 191/// Return true and the result register by reference if it is possible. 192bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 193 unsigned &ResultReg) { 194 // Get opcode and regclass of the output for the given load instruction. 195 unsigned Opc = 0; 196 const TargetRegisterClass *RC = NULL; 197 switch (VT.getSimpleVT().SimpleTy) { 198 default: return false; 199 case MVT::i1: 200 case MVT::i8: 201 Opc = X86::MOV8rm; 202 RC = X86::GR8RegisterClass; 203 break; 204 case MVT::i16: 205 Opc = X86::MOV16rm; 206 RC = X86::GR16RegisterClass; 207 break; 208 case MVT::i32: 209 Opc = X86::MOV32rm; 210 RC = X86::GR32RegisterClass; 211 break; 212 case MVT::i64: 213 // Must be in x86-64 mode. 214 Opc = X86::MOV64rm; 215 RC = X86::GR64RegisterClass; 216 break; 217 case MVT::f32: 218 if (Subtarget->hasSSE1()) { 219 Opc = X86::MOVSSrm; 220 RC = X86::FR32RegisterClass; 221 } else { 222 Opc = X86::LD_Fp32m; 223 RC = X86::RFP32RegisterClass; 224 } 225 break; 226 case MVT::f64: 227 if (Subtarget->hasSSE2()) { 228 Opc = X86::MOVSDrm; 229 RC = X86::FR64RegisterClass; 230 } else { 231 Opc = X86::LD_Fp64m; 232 RC = X86::RFP64RegisterClass; 233 } 234 break; 235 case MVT::f80: 236 // No f80 support yet. 237 return false; 238 } 239 240 ResultReg = createResultReg(RC); 241 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 242 return true; 243} 244 245/// X86FastEmitStore - Emit a machine instruction to store a value Val of 246/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 247/// and a displacement offset, or a GlobalAddress, 248/// i.e. V. Return true if it is possible. 249bool 250X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, 251 const X86AddressMode &AM) { 252 // Get opcode and regclass of the output for the given store instruction. 253 unsigned Opc = 0; 254 switch (VT.getSimpleVT().SimpleTy) { 255 case MVT::f80: // No f80 support yet. 256 default: return false; 257 case MVT::i1: { 258 // Mask out all but lowest bit. 259 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 260 BuildMI(MBB, DL, 261 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 262 Val = AndResult; 263 } 264 // FALLTHROUGH, handling i1 as i8. 265 case MVT::i8: Opc = X86::MOV8mr; break; 266 case MVT::i16: Opc = X86::MOV16mr; break; 267 case MVT::i32: Opc = X86::MOV32mr; break; 268 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 269 case MVT::f32: 270 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 271 break; 272 case MVT::f64: 273 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 274 break; 275 } 276 277 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); 278 return true; 279} 280 281bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, 282 const X86AddressMode &AM) { 283 // Handle 'null' like i32/i64 0. 284 if (isa<ConstantPointerNull>(Val)) 285 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 286 287 // If this is a store of a simple constant, fold the constant into the store. 288 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 289 unsigned Opc = 0; 290 bool Signed = true; 291 switch (VT.getSimpleVT().SimpleTy) { 292 default: break; 293 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 294 case MVT::i8: Opc = X86::MOV8mi; break; 295 case MVT::i16: Opc = X86::MOV16mi; break; 296 case MVT::i32: Opc = X86::MOV32mi; break; 297 case MVT::i64: 298 // Must be a 32-bit sign extended value. 299 if ((int)CI->getSExtValue() == CI->getSExtValue()) 300 Opc = X86::MOV64mi32; 301 break; 302 } 303 304 if (Opc) { 305 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) 306 .addImm(Signed ? CI->getSExtValue() : 307 CI->getZExtValue()); 308 return true; 309 } 310 } 311 312 unsigned ValReg = getRegForValue(Val); 313 if (ValReg == 0) 314 return false; 315 316 return X86FastEmitStore(VT, ValReg, AM); 317} 318 319/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 320/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 321/// ISD::SIGN_EXTEND). 322bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 323 unsigned Src, EVT SrcVT, 324 unsigned &ResultReg) { 325 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); 326 327 if (RR != 0) { 328 ResultReg = RR; 329 return true; 330 } else 331 return false; 332} 333 334/// X86SelectAddress - Attempt to fill in an address from the given value. 335/// 336bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { 337 User *U = NULL; 338 unsigned Opcode = Instruction::UserOp1; 339 if (Instruction *I = dyn_cast<Instruction>(V)) { 340 Opcode = I->getOpcode(); 341 U = I; 342 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 343 Opcode = C->getOpcode(); 344 U = C; 345 } 346 347 switch (Opcode) { 348 default: break; 349 case Instruction::BitCast: 350 // Look past bitcasts. 351 return X86SelectAddress(U->getOperand(0), AM); 352 353 case Instruction::IntToPtr: 354 // Look past no-op inttoptrs. 355 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 356 return X86SelectAddress(U->getOperand(0), AM); 357 break; 358 359 case Instruction::PtrToInt: 360 // Look past no-op ptrtoints. 361 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 362 return X86SelectAddress(U->getOperand(0), AM); 363 break; 364 365 case Instruction::Alloca: { 366 // Do static allocas. 367 const AllocaInst *A = cast<AllocaInst>(V); 368 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 369 if (SI != StaticAllocaMap.end()) { 370 AM.BaseType = X86AddressMode::FrameIndexBase; 371 AM.Base.FrameIndex = SI->second; 372 return true; 373 } 374 break; 375 } 376 377 case Instruction::Add: { 378 // Adds of constants are common and easy enough. 379 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 380 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 381 // They have to fit in the 32-bit signed displacement field though. 382 if (isInt32(Disp)) { 383 AM.Disp = (uint32_t)Disp; 384 return X86SelectAddress(U->getOperand(0), AM); 385 } 386 } 387 break; 388 } 389 390 case Instruction::GetElementPtr: { 391 // Pattern-match simple GEPs. 392 uint64_t Disp = (int32_t)AM.Disp; 393 unsigned IndexReg = AM.IndexReg; 394 unsigned Scale = AM.Scale; 395 gep_type_iterator GTI = gep_type_begin(U); 396 // Iterate through the indices, folding what we can. Constants can be 397 // folded, and one dynamic index can be handled, if the scale is supported. 398 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end(); 399 i != e; ++i, ++GTI) { 400 Value *Op = *i; 401 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 402 const StructLayout *SL = TD.getStructLayout(STy); 403 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 404 Disp += SL->getElementOffset(Idx); 405 } else { 406 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 407 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 408 // Constant-offset addressing. 409 Disp += CI->getSExtValue() * S; 410 } else if (IndexReg == 0 && 411 (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 412 (S == 1 || S == 2 || S == 4 || S == 8)) { 413 // Scaled-index addressing. 414 Scale = S; 415 IndexReg = getRegForGEPIndex(Op); 416 if (IndexReg == 0) 417 return false; 418 } else 419 // Unsupported. 420 goto unsupported_gep; 421 } 422 } 423 // Check for displacement overflow. 424 if (!isInt32(Disp)) 425 break; 426 // Ok, the GEP indices were covered by constant-offset and scaled-index 427 // addressing. Update the address state and move on to examining the base. 428 AM.IndexReg = IndexReg; 429 AM.Scale = Scale; 430 AM.Disp = (uint32_t)Disp; 431 return X86SelectAddress(U->getOperand(0), AM); 432 unsupported_gep: 433 // Ok, the GEP indices weren't all covered. 434 break; 435 } 436 } 437 438 // Handle constant address. 439 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 440 // Can't handle alternate code models yet. 441 if (TM.getCodeModel() != CodeModel::Small) 442 return false; 443 444 // RIP-relative addresses can't have additional register operands. 445 if (Subtarget->isPICStyleRIPRel() && 446 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 447 return false; 448 449 // Can't handle TLS yet. 450 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 451 if (GVar->isThreadLocal()) 452 return false; 453 454 // Okay, we've committed to selecting this global. Set up the basic address. 455 AM.GV = GV; 456 457 // Allow the subtarget to classify the global. 458 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 459 460 // If this reference is relative to the pic base, set it now. 461 if (isGlobalRelativeToPICBase(GVFlags)) { 462 // FIXME: How do we know Base.Reg is free?? 463 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 464 } 465 466 // Unless the ABI requires an extra load, return a direct reference to 467 // the global. 468 if (!isGlobalStubReference(GVFlags)) { 469 if (Subtarget->isPICStyleRIPRel()) { 470 // Use rip-relative addressing if we can. Above we verified that the 471 // base and index registers are unused. 472 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 473 AM.Base.Reg = X86::RIP; 474 } 475 AM.GVOpFlags = GVFlags; 476 return true; 477 } 478 479 // Ok, we need to do a load from a stub. If we've already loaded from this 480 // stub, reuse the loaded pointer, otherwise emit the load now. 481 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 482 unsigned LoadReg; 483 if (I != LocalValueMap.end() && I->second != 0) { 484 LoadReg = I->second; 485 } else { 486 // Issue load from stub. 487 unsigned Opc = 0; 488 const TargetRegisterClass *RC = NULL; 489 X86AddressMode StubAM; 490 StubAM.Base.Reg = AM.Base.Reg; 491 StubAM.GV = GV; 492 StubAM.GVOpFlags = GVFlags; 493 494 if (TLI.getPointerTy() == MVT::i64) { 495 Opc = X86::MOV64rm; 496 RC = X86::GR64RegisterClass; 497 498 if (Subtarget->isPICStyleRIPRel()) 499 StubAM.Base.Reg = X86::RIP; 500 } else { 501 Opc = X86::MOV32rm; 502 RC = X86::GR32RegisterClass; 503 } 504 505 LoadReg = createResultReg(RC); 506 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM); 507 508 // Prevent loading GV stub multiple times in same MBB. 509 LocalValueMap[V] = LoadReg; 510 } 511 512 // Now construct the final address. Note that the Disp, Scale, 513 // and Index values may already be set here. 514 AM.Base.Reg = LoadReg; 515 AM.GV = 0; 516 return true; 517 } 518 519 // If all else fails, try to materialize the value in a register. 520 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 521 if (AM.Base.Reg == 0) { 522 AM.Base.Reg = getRegForValue(V); 523 return AM.Base.Reg != 0; 524 } 525 if (AM.IndexReg == 0) { 526 assert(AM.Scale == 1 && "Scale with no index!"); 527 AM.IndexReg = getRegForValue(V); 528 return AM.IndexReg != 0; 529 } 530 } 531 532 return false; 533} 534 535/// X86SelectCallAddress - Attempt to fill in an address from the given value. 536/// 537bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) { 538 User *U = NULL; 539 unsigned Opcode = Instruction::UserOp1; 540 if (Instruction *I = dyn_cast<Instruction>(V)) { 541 Opcode = I->getOpcode(); 542 U = I; 543 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 544 Opcode = C->getOpcode(); 545 U = C; 546 } 547 548 switch (Opcode) { 549 default: break; 550 case Instruction::BitCast: 551 // Look past bitcasts. 552 return X86SelectCallAddress(U->getOperand(0), AM); 553 554 case Instruction::IntToPtr: 555 // Look past no-op inttoptrs. 556 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 557 return X86SelectCallAddress(U->getOperand(0), AM); 558 break; 559 560 case Instruction::PtrToInt: 561 // Look past no-op ptrtoints. 562 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 563 return X86SelectCallAddress(U->getOperand(0), AM); 564 break; 565 } 566 567 // Handle constant address. 568 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 569 // Can't handle alternate code models yet. 570 if (TM.getCodeModel() != CodeModel::Small) 571 return false; 572 573 // RIP-relative addresses can't have additional register operands. 574 if (Subtarget->isPICStyleRIPRel() && 575 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 576 return false; 577 578 // Can't handle TLS or DLLImport. 579 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 580 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage()) 581 return false; 582 583 // Okay, we've committed to selecting this global. Set up the basic address. 584 AM.GV = GV; 585 586 // No ABI requires an extra load for anything other than DLLImport, which 587 // we rejected above. Return a direct reference to the global. 588 if (Subtarget->isPICStyleRIPRel()) { 589 // Use rip-relative addressing if we can. Above we verified that the 590 // base and index registers are unused. 591 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 592 AM.Base.Reg = X86::RIP; 593 } else if (Subtarget->isPICStyleStubPIC()) { 594 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 595 } else if (Subtarget->isPICStyleGOT()) { 596 AM.GVOpFlags = X86II::MO_GOTOFF; 597 } 598 599 return true; 600 } 601 602 // If all else fails, try to materialize the value in a register. 603 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 604 if (AM.Base.Reg == 0) { 605 AM.Base.Reg = getRegForValue(V); 606 return AM.Base.Reg != 0; 607 } 608 if (AM.IndexReg == 0) { 609 assert(AM.Scale == 1 && "Scale with no index!"); 610 AM.IndexReg = getRegForValue(V); 611 return AM.IndexReg != 0; 612 } 613 } 614 615 return false; 616} 617 618 619/// X86SelectStore - Select and emit code to implement store instructions. 620bool X86FastISel::X86SelectStore(Instruction* I) { 621 EVT VT; 622 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 623 return false; 624 625 X86AddressMode AM; 626 if (!X86SelectAddress(I->getOperand(1), AM)) 627 return false; 628 629 return X86FastEmitStore(VT, I->getOperand(0), AM); 630} 631 632/// X86SelectLoad - Select and emit code to implement load instructions. 633/// 634bool X86FastISel::X86SelectLoad(Instruction *I) { 635 EVT VT; 636 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 637 return false; 638 639 X86AddressMode AM; 640 if (!X86SelectAddress(I->getOperand(0), AM)) 641 return false; 642 643 unsigned ResultReg = 0; 644 if (X86FastEmitLoad(VT, AM, ResultReg)) { 645 UpdateValueMap(I, ResultReg); 646 return true; 647 } 648 return false; 649} 650 651static unsigned X86ChooseCmpOpcode(EVT VT) { 652 switch (VT.getSimpleVT().SimpleTy) { 653 default: return 0; 654 case MVT::i8: return X86::CMP8rr; 655 case MVT::i16: return X86::CMP16rr; 656 case MVT::i32: return X86::CMP32rr; 657 case MVT::i64: return X86::CMP64rr; 658 case MVT::f32: return X86::UCOMISSrr; 659 case MVT::f64: return X86::UCOMISDrr; 660 } 661} 662 663/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 664/// of the comparison, return an opcode that works for the compare (e.g. 665/// CMP32ri) otherwise return 0. 666static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) { 667 switch (VT.getSimpleVT().SimpleTy) { 668 // Otherwise, we can't fold the immediate into this comparison. 669 default: return 0; 670 case MVT::i8: return X86::CMP8ri; 671 case MVT::i16: return X86::CMP16ri; 672 case MVT::i32: return X86::CMP32ri; 673 case MVT::i64: 674 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 675 // field. 676 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 677 return X86::CMP64ri32; 678 return 0; 679 } 680} 681 682bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) { 683 unsigned Op0Reg = getRegForValue(Op0); 684 if (Op0Reg == 0) return false; 685 686 // Handle 'null' like i32/i64 0. 687 if (isa<ConstantPointerNull>(Op1)) 688 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 689 690 // We have two options: compare with register or immediate. If the RHS of 691 // the compare is an immediate that we can fold into this compare, use 692 // CMPri, otherwise use CMPrr. 693 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 694 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 695 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) 696 .addImm(Op1C->getSExtValue()); 697 return true; 698 } 699 } 700 701 unsigned CompareOpc = X86ChooseCmpOpcode(VT); 702 if (CompareOpc == 0) return false; 703 704 unsigned Op1Reg = getRegForValue(Op1); 705 if (Op1Reg == 0) return false; 706 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 707 708 return true; 709} 710 711bool X86FastISel::X86SelectCmp(Instruction *I) { 712 CmpInst *CI = cast<CmpInst>(I); 713 714 EVT VT; 715 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 716 return false; 717 718 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 719 unsigned SetCCOpc; 720 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 721 switch (CI->getPredicate()) { 722 case CmpInst::FCMP_OEQ: { 723 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 724 return false; 725 726 unsigned EReg = createResultReg(&X86::GR8RegClass); 727 unsigned NPReg = createResultReg(&X86::GR8RegClass); 728 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); 729 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); 730 BuildMI(MBB, DL, 731 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 732 UpdateValueMap(I, ResultReg); 733 return true; 734 } 735 case CmpInst::FCMP_UNE: { 736 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 737 return false; 738 739 unsigned NEReg = createResultReg(&X86::GR8RegClass); 740 unsigned PReg = createResultReg(&X86::GR8RegClass); 741 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); 742 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); 743 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 744 UpdateValueMap(I, ResultReg); 745 return true; 746 } 747 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 748 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 749 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 750 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 751 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 752 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 753 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 754 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 755 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 756 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 757 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 758 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 759 760 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 761 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 762 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 763 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 764 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 765 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 766 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 767 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 768 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 769 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 770 default: 771 return false; 772 } 773 774 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 775 if (SwapArgs) 776 std::swap(Op0, Op1); 777 778 // Emit a compare of Op0/Op1. 779 if (!X86FastEmitCompare(Op0, Op1, VT)) 780 return false; 781 782 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); 783 UpdateValueMap(I, ResultReg); 784 return true; 785} 786 787bool X86FastISel::X86SelectZExt(Instruction *I) { 788 // Handle zero-extension from i1 to i8, which is common. 789 if (I->getType()->isInteger(8) && 790 I->getOperand(0)->getType()->isInteger(1)) { 791 unsigned ResultReg = getRegForValue(I->getOperand(0)); 792 if (ResultReg == 0) return false; 793 // Set the high bits to zero. 794 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg); 795 if (ResultReg == 0) return false; 796 UpdateValueMap(I, ResultReg); 797 return true; 798 } 799 800 return false; 801} 802 803 804bool X86FastISel::X86SelectBranch(Instruction *I) { 805 // Unconditional branches are selected by tablegen-generated code. 806 // Handle a conditional branch. 807 BranchInst *BI = cast<BranchInst>(I); 808 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 809 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 810 811 // Fold the common case of a conditional branch with a comparison. 812 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 813 if (CI->hasOneUse()) { 814 EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 815 816 // Try to take advantage of fallthrough opportunities. 817 CmpInst::Predicate Predicate = CI->getPredicate(); 818 if (MBB->isLayoutSuccessor(TrueMBB)) { 819 std::swap(TrueMBB, FalseMBB); 820 Predicate = CmpInst::getInversePredicate(Predicate); 821 } 822 823 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 824 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 825 826 switch (Predicate) { 827 case CmpInst::FCMP_OEQ: 828 std::swap(TrueMBB, FalseMBB); 829 Predicate = CmpInst::FCMP_UNE; 830 // FALL THROUGH 831 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 832 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 833 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 834 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break; 835 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break; 836 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 837 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break; 838 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break; 839 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 840 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break; 841 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break; 842 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 843 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 844 845 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 846 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 847 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 848 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 849 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 850 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 851 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break; 852 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break; 853 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break; 854 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break; 855 default: 856 return false; 857 } 858 859 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 860 if (SwapArgs) 861 std::swap(Op0, Op1); 862 863 // Emit a compare of the LHS and RHS, setting the flags. 864 if (!X86FastEmitCompare(Op0, Op1, VT)) 865 return false; 866 867 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); 868 869 if (Predicate == CmpInst::FCMP_UNE) { 870 // X86 requires a second branch to handle UNE (and OEQ, 871 // which is mapped to UNE above). 872 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB); 873 } 874 875 FastEmitBranch(FalseMBB); 876 MBB->addSuccessor(TrueMBB); 877 return true; 878 } 879 } else if (ExtractValueInst *EI = 880 dyn_cast<ExtractValueInst>(BI->getCondition())) { 881 // Check to see if the branch instruction is from an "arithmetic with 882 // overflow" intrinsic. The main way these intrinsics are used is: 883 // 884 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 885 // %sum = extractvalue { i32, i1 } %t, 0 886 // %obit = extractvalue { i32, i1 } %t, 1 887 // br i1 %obit, label %overflow, label %normal 888 // 889 // The %sum and %obit are converted in an ADD and a SETO/SETB before 890 // reaching the branch. Therefore, we search backwards through the MBB 891 // looking for the SETO/SETB instruction. If an instruction modifies the 892 // EFLAGS register before we reach the SETO/SETB instruction, then we can't 893 // convert the branch into a JO/JB instruction. 894 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){ 895 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || 896 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { 897 const MachineInstr *SetMI = 0; 898 unsigned Reg = lookUpRegForValue(EI); 899 900 for (MachineBasicBlock::const_reverse_iterator 901 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 902 const MachineInstr &MI = *RI; 903 904 if (MI.modifiesRegister(Reg)) { 905 unsigned Src, Dst, SrcSR, DstSR; 906 907 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { 908 Reg = Src; 909 continue; 910 } 911 912 SetMI = &MI; 913 break; 914 } 915 916 const TargetInstrDesc &TID = MI.getDesc(); 917 if (TID.hasUnmodeledSideEffects() || 918 TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) 919 break; 920 } 921 922 if (SetMI) { 923 unsigned OpCode = SetMI->getOpcode(); 924 925 if (OpCode == X86::SETOr || OpCode == X86::SETBr) { 926 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? 927 X86::JO_4 : X86::JB_4)) 928 .addMBB(TrueMBB); 929 FastEmitBranch(FalseMBB); 930 MBB->addSuccessor(TrueMBB); 931 return true; 932 } 933 } 934 } 935 } 936 } 937 938 // Otherwise do a clumsy setcc and re-test it. 939 unsigned OpReg = getRegForValue(BI->getCondition()); 940 if (OpReg == 0) return false; 941 942 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 943 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB); 944 FastEmitBranch(FalseMBB); 945 MBB->addSuccessor(TrueMBB); 946 return true; 947} 948 949bool X86FastISel::X86SelectShift(Instruction *I) { 950 unsigned CReg = 0, OpReg = 0, OpImm = 0; 951 const TargetRegisterClass *RC = NULL; 952 if (I->getType()->isInteger(8)) { 953 CReg = X86::CL; 954 RC = &X86::GR8RegClass; 955 switch (I->getOpcode()) { 956 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 957 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 958 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 959 default: return false; 960 } 961 } else if (I->getType()->isInteger(16)) { 962 CReg = X86::CX; 963 RC = &X86::GR16RegClass; 964 switch (I->getOpcode()) { 965 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 966 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 967 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 968 default: return false; 969 } 970 } else if (I->getType()->isInteger(32)) { 971 CReg = X86::ECX; 972 RC = &X86::GR32RegClass; 973 switch (I->getOpcode()) { 974 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 975 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 976 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 977 default: return false; 978 } 979 } else if (I->getType()->isInteger(64)) { 980 CReg = X86::RCX; 981 RC = &X86::GR64RegClass; 982 switch (I->getOpcode()) { 983 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 984 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 985 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 986 default: return false; 987 } 988 } else { 989 return false; 990 } 991 992 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 993 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 994 return false; 995 996 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 997 if (Op0Reg == 0) return false; 998 999 // Fold immediate in shl(x,3). 1000 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 1001 unsigned ResultReg = createResultReg(RC); 1002 BuildMI(MBB, DL, TII.get(OpImm), 1003 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); 1004 UpdateValueMap(I, ResultReg); 1005 return true; 1006 } 1007 1008 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1009 if (Op1Reg == 0) return false; 1010 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC); 1011 1012 // The shift instruction uses X86::CL. If we defined a super-register 1013 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 1014 // we're doing here. 1015 if (CReg != X86::CL) 1016 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL) 1017 .addReg(CReg).addImm(X86::SUBREG_8BIT); 1018 1019 unsigned ResultReg = createResultReg(RC); 1020 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); 1021 UpdateValueMap(I, ResultReg); 1022 return true; 1023} 1024 1025bool X86FastISel::X86SelectSelect(Instruction *I) { 1026 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1027 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1028 return false; 1029 1030 unsigned Opc = 0; 1031 const TargetRegisterClass *RC = NULL; 1032 if (VT.getSimpleVT() == MVT::i16) { 1033 Opc = X86::CMOVE16rr; 1034 RC = &X86::GR16RegClass; 1035 } else if (VT.getSimpleVT() == MVT::i32) { 1036 Opc = X86::CMOVE32rr; 1037 RC = &X86::GR32RegClass; 1038 } else if (VT.getSimpleVT() == MVT::i64) { 1039 Opc = X86::CMOVE64rr; 1040 RC = &X86::GR64RegClass; 1041 } else { 1042 return false; 1043 } 1044 1045 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1046 if (Op0Reg == 0) return false; 1047 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1048 if (Op1Reg == 0) return false; 1049 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1050 if (Op2Reg == 0) return false; 1051 1052 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 1053 unsigned ResultReg = createResultReg(RC); 1054 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 1055 UpdateValueMap(I, ResultReg); 1056 return true; 1057} 1058 1059bool X86FastISel::X86SelectFPExt(Instruction *I) { 1060 // fpext from float to double. 1061 if (Subtarget->hasSSE2() && 1062 I->getType()->isDoubleTy()) { 1063 Value *V = I->getOperand(0); 1064 if (V->getType()->isFloatTy()) { 1065 unsigned OpReg = getRegForValue(V); 1066 if (OpReg == 0) return false; 1067 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 1068 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 1069 UpdateValueMap(I, ResultReg); 1070 return true; 1071 } 1072 } 1073 1074 return false; 1075} 1076 1077bool X86FastISel::X86SelectFPTrunc(Instruction *I) { 1078 if (Subtarget->hasSSE2()) { 1079 if (I->getType()->isFloatTy()) { 1080 Value *V = I->getOperand(0); 1081 if (V->getType()->isDoubleTy()) { 1082 unsigned OpReg = getRegForValue(V); 1083 if (OpReg == 0) return false; 1084 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 1085 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 1086 UpdateValueMap(I, ResultReg); 1087 return true; 1088 } 1089 } 1090 } 1091 1092 return false; 1093} 1094 1095bool X86FastISel::X86SelectTrunc(Instruction *I) { 1096 if (Subtarget->is64Bit()) 1097 // All other cases should be handled by the tblgen generated code. 1098 return false; 1099 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1100 EVT DstVT = TLI.getValueType(I->getType()); 1101 1102 // This code only handles truncation to byte right now. 1103 if (DstVT != MVT::i8 && DstVT != MVT::i1) 1104 // All other cases should be handled by the tblgen generated code. 1105 return false; 1106 if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 1107 // All other cases should be handled by the tblgen generated code. 1108 return false; 1109 1110 unsigned InputReg = getRegForValue(I->getOperand(0)); 1111 if (!InputReg) 1112 // Unhandled operand. Halt "fast" selection and bail. 1113 return false; 1114 1115 // First issue a copy to GR16_ABCD or GR32_ABCD. 1116 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; 1117 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1118 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 1119 unsigned CopyReg = createResultReg(CopyRC); 1120 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); 1121 1122 // Then issue an extract_subreg. 1123 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1124 CopyReg, X86::SUBREG_8BIT); 1125 if (!ResultReg) 1126 return false; 1127 1128 UpdateValueMap(I, ResultReg); 1129 return true; 1130} 1131 1132bool X86FastISel::X86SelectExtractValue(Instruction *I) { 1133 ExtractValueInst *EI = cast<ExtractValueInst>(I); 1134 Value *Agg = EI->getAggregateOperand(); 1135 1136 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) { 1137 switch (CI->getIntrinsicID()) { 1138 default: break; 1139 case Intrinsic::sadd_with_overflow: 1140 case Intrinsic::uadd_with_overflow: 1141 // Cheat a little. We know that the registers for "add" and "seto" are 1142 // allocated sequentially. However, we only keep track of the register 1143 // for "add" in the value map. Use extractvalue's index to get the 1144 // correct register for "seto". 1145 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 1146 return true; 1147 } 1148 } 1149 1150 return false; 1151} 1152 1153bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { 1154 // FIXME: Handle more intrinsics. 1155 switch (I.getIntrinsicID()) { 1156 default: return false; 1157 case Intrinsic::dbg_declare: { 1158 DbgDeclareInst *DI = cast<DbgDeclareInst>(&I); 1159 X86AddressMode AM; 1160 assert(DI->getAddress() && "Null address should be checked earlier!"); 1161 if (!X86SelectAddress(DI->getAddress(), AM)) 1162 return false; 1163 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 1164 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0). 1165 addMetadata(DI->getVariable()); 1166 return true; 1167 } 1168 case Intrinsic::trap: { 1169 BuildMI(MBB, DL, TII.get(X86::TRAP)); 1170 return true; 1171 } 1172 case Intrinsic::sadd_with_overflow: 1173 case Intrinsic::uadd_with_overflow: { 1174 // Replace "add with overflow" intrinsics with an "add" instruction followed 1175 // by a seto/setc instruction. Later on, when the "extractvalue" 1176 // instructions are encountered, we use the fact that two registers were 1177 // created sequentially to get the correct registers for the "sum" and the 1178 // "overflow bit". 1179 const Function *Callee = I.getCalledFunction(); 1180 const Type *RetTy = 1181 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1182 1183 EVT VT; 1184 if (!isTypeLegal(RetTy, VT)) 1185 return false; 1186 1187 Value *Op1 = I.getOperand(1); 1188 Value *Op2 = I.getOperand(2); 1189 unsigned Reg1 = getRegForValue(Op1); 1190 unsigned Reg2 = getRegForValue(Op2); 1191 1192 if (Reg1 == 0 || Reg2 == 0) 1193 // FIXME: Handle values *not* in registers. 1194 return false; 1195 1196 unsigned OpC = 0; 1197 if (VT == MVT::i32) 1198 OpC = X86::ADD32rr; 1199 else if (VT == MVT::i64) 1200 OpC = X86::ADD64rr; 1201 else 1202 return false; 1203 1204 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1205 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 1206 unsigned DestReg1 = UpdateValueMap(&I, ResultReg); 1207 1208 // If the add with overflow is an intra-block value then we just want to 1209 // create temporaries for it like normal. If it is a cross-block value then 1210 // UpdateValueMap will return the cross-block register used. Since we 1211 // *really* want the value to be live in the register pair known by 1212 // UpdateValueMap, we have to use DestReg1+1 as the destination register in 1213 // the cross block case. In the non-cross-block case, we should just make 1214 // another register for the value. 1215 if (DestReg1 != ResultReg) 1216 ResultReg = DestReg1+1; 1217 else 1218 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 1219 1220 unsigned Opc = X86::SETBr; 1221 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1222 Opc = X86::SETOr; 1223 BuildMI(MBB, DL, TII.get(Opc), ResultReg); 1224 return true; 1225 } 1226 } 1227} 1228 1229bool X86FastISel::X86SelectCall(Instruction *I) { 1230 CallInst *CI = cast<CallInst>(I); 1231 Value *Callee = I->getOperand(0); 1232 1233 // Can't handle inline asm yet. 1234 if (isa<InlineAsm>(Callee)) 1235 return false; 1236 1237 // Handle intrinsic calls. 1238 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1239 return X86VisitIntrinsicCall(*II); 1240 1241 // Handle only C and fastcc calling conventions for now. 1242 CallSite CS(CI); 1243 CallingConv::ID CC = CS.getCallingConv(); 1244 if (CC != CallingConv::C && 1245 CC != CallingConv::Fast && 1246 CC != CallingConv::X86_FastCall) 1247 return false; 1248 1249 // fastcc with -tailcallopt is intended to provide a guaranteed 1250 // tail call optimization. Fastisel doesn't know how to do that. 1251 if (CC == CallingConv::Fast && GuaranteedTailCallOpt) 1252 return false; 1253 1254 // Let SDISel handle vararg functions. 1255 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1256 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1257 if (FTy->isVarArg()) 1258 return false; 1259 1260 // Handle *simple* calls for now. 1261 const Type *RetTy = CS.getType(); 1262 EVT RetVT; 1263 if (RetTy->isVoidTy()) 1264 RetVT = MVT::isVoid; 1265 else if (!isTypeLegal(RetTy, RetVT, true)) 1266 return false; 1267 1268 // Materialize callee address in a register. FIXME: GV address can be 1269 // handled with a CALLpcrel32 instead. 1270 X86AddressMode CalleeAM; 1271 if (!X86SelectCallAddress(Callee, CalleeAM)) 1272 return false; 1273 unsigned CalleeOp = 0; 1274 GlobalValue *GV = 0; 1275 if (CalleeAM.GV != 0) { 1276 GV = CalleeAM.GV; 1277 } else if (CalleeAM.Base.Reg != 0) { 1278 CalleeOp = CalleeAM.Base.Reg; 1279 } else 1280 return false; 1281 1282 // Allow calls which produce i1 results. 1283 bool AndToI1 = false; 1284 if (RetVT == MVT::i1) { 1285 RetVT = MVT::i8; 1286 AndToI1 = true; 1287 } 1288 1289 // Deal with call operands first. 1290 SmallVector<Value*, 8> ArgVals; 1291 SmallVector<unsigned, 8> Args; 1292 SmallVector<EVT, 8> ArgVTs; 1293 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1294 Args.reserve(CS.arg_size()); 1295 ArgVals.reserve(CS.arg_size()); 1296 ArgVTs.reserve(CS.arg_size()); 1297 ArgFlags.reserve(CS.arg_size()); 1298 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1299 i != e; ++i) { 1300 unsigned Arg = getRegForValue(*i); 1301 if (Arg == 0) 1302 return false; 1303 ISD::ArgFlagsTy Flags; 1304 unsigned AttrInd = i - CS.arg_begin() + 1; 1305 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1306 Flags.setSExt(); 1307 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1308 Flags.setZExt(); 1309 1310 // FIXME: Only handle *easy* calls for now. 1311 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1312 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1313 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1314 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1315 return false; 1316 1317 const Type *ArgTy = (*i)->getType(); 1318 EVT ArgVT; 1319 if (!isTypeLegal(ArgTy, ArgVT)) 1320 return false; 1321 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1322 Flags.setOrigAlign(OriginalAlignment); 1323 1324 Args.push_back(Arg); 1325 ArgVals.push_back(*i); 1326 ArgVTs.push_back(ArgVT); 1327 ArgFlags.push_back(Flags); 1328 } 1329 1330 // Analyze operands of the call, assigning locations to each operand. 1331 SmallVector<CCValAssign, 16> ArgLocs; 1332 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext()); 1333 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 1334 1335 // Get a count of how many bytes are to be pushed on the stack. 1336 unsigned NumBytes = CCInfo.getNextStackOffset(); 1337 1338 // Issue CALLSEQ_START 1339 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1340 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); 1341 1342 // Process argument: walk the register/memloc assignments, inserting 1343 // copies / loads. 1344 SmallVector<unsigned, 4> RegArgs; 1345 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1346 CCValAssign &VA = ArgLocs[i]; 1347 unsigned Arg = Args[VA.getValNo()]; 1348 EVT ArgVT = ArgVTs[VA.getValNo()]; 1349 1350 // Promote the value if needed. 1351 switch (VA.getLocInfo()) { 1352 default: llvm_unreachable("Unknown loc info!"); 1353 case CCValAssign::Full: break; 1354 case CCValAssign::SExt: { 1355 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1356 Arg, ArgVT, Arg); 1357 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1358 Emitted = true; 1359 ArgVT = VA.getLocVT(); 1360 break; 1361 } 1362 case CCValAssign::ZExt: { 1363 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1364 Arg, ArgVT, Arg); 1365 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1366 Emitted = true; 1367 ArgVT = VA.getLocVT(); 1368 break; 1369 } 1370 case CCValAssign::AExt: { 1371 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1372 Arg, ArgVT, Arg); 1373 if (!Emitted) 1374 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1375 Arg, ArgVT, Arg); 1376 if (!Emitted) 1377 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1378 Arg, ArgVT, Arg); 1379 1380 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1381 ArgVT = VA.getLocVT(); 1382 break; 1383 } 1384 case CCValAssign::BCvt: { 1385 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(), 1386 ISD::BIT_CONVERT, Arg); 1387 assert(BC != 0 && "Failed to emit a bitcast!"); 1388 Arg = BC; 1389 ArgVT = VA.getLocVT(); 1390 break; 1391 } 1392 } 1393 1394 if (VA.isRegLoc()) { 1395 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 1396 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 1397 Arg, RC, RC); 1398 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1399 Emitted = true; 1400 RegArgs.push_back(VA.getLocReg()); 1401 } else { 1402 unsigned LocMemOffset = VA.getLocMemOffset(); 1403 X86AddressMode AM; 1404 AM.Base.Reg = StackPtr; 1405 AM.Disp = LocMemOffset; 1406 Value *ArgVal = ArgVals[VA.getValNo()]; 1407 1408 // If this is a really simple value, emit this with the Value* version of 1409 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 1410 // can cause us to reevaluate the argument. 1411 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 1412 X86FastEmitStore(ArgVT, ArgVal, AM); 1413 else 1414 X86FastEmitStore(ArgVT, Arg, AM); 1415 } 1416 } 1417 1418 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1419 // GOT pointer. 1420 if (Subtarget->isPICStyleGOT()) { 1421 TargetRegisterClass *RC = X86::GR32RegisterClass; 1422 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 1423 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); 1424 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1425 Emitted = true; 1426 } 1427 1428 // Issue the call. 1429 MachineInstrBuilder MIB; 1430 if (CalleeOp) { 1431 // Register-indirect call. 1432 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r; 1433 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp); 1434 1435 } else { 1436 // Direct call. 1437 assert(GV && "Not a direct call"); 1438 unsigned CallOpc = 1439 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; 1440 1441 // See if we need any target-specific flags on the GV operand. 1442 unsigned char OpFlags = 0; 1443 1444 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1445 // external symbols most go through the PLT in PIC mode. If the symbol 1446 // has hidden or protected visibility, or if it is static or local, then 1447 // we don't need to use the PLT - we can directly call it. 1448 if (Subtarget->isTargetELF() && 1449 TM.getRelocationModel() == Reloc::PIC_ && 1450 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1451 OpFlags = X86II::MO_PLT; 1452 } else if (Subtarget->isPICStyleStubAny() && 1453 (GV->isDeclaration() || GV->isWeakForLinker()) && 1454 Subtarget->getDarwinVers() < 9) { 1455 // PC-relative references to external symbols should go through $stub, 1456 // unless we're building with the leopard linker or later, which 1457 // automatically synthesizes these stubs. 1458 OpFlags = X86II::MO_DARWIN_STUB; 1459 } 1460 1461 1462 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags); 1463 } 1464 1465 // Add an implicit use GOT pointer in EBX. 1466 if (Subtarget->isPICStyleGOT()) 1467 MIB.addReg(X86::EBX); 1468 1469 // Add implicit physical register uses to the call. 1470 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1471 MIB.addReg(RegArgs[i]); 1472 1473 // Issue CALLSEQ_END 1474 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1475 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 1476 1477 // Now handle call return value (if any). 1478 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { 1479 SmallVector<CCValAssign, 16> RVLocs; 1480 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); 1481 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 1482 1483 // Copy all of the result registers out of their specified physreg. 1484 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 1485 EVT CopyVT = RVLocs[0].getValVT(); 1486 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1487 TargetRegisterClass *SrcRC = DstRC; 1488 1489 // If this is a call to a function that returns an fp value on the x87 fp 1490 // stack, but where we prefer to use the value in xmm registers, copy it 1491 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1492 if ((RVLocs[0].getLocReg() == X86::ST0 || 1493 RVLocs[0].getLocReg() == X86::ST1) && 1494 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 1495 CopyVT = MVT::f80; 1496 SrcRC = X86::RSTRegisterClass; 1497 DstRC = X86::RFP80RegisterClass; 1498 } 1499 1500 unsigned ResultReg = createResultReg(DstRC); 1501 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1502 RVLocs[0].getLocReg(), DstRC, SrcRC); 1503 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1504 Emitted = true; 1505 if (CopyVT != RVLocs[0].getValVT()) { 1506 // Round the F80 the right size, which also moves to the appropriate xmm 1507 // register. This is accomplished by storing the F80 value in memory and 1508 // then loading it back. Ewww... 1509 EVT ResVT = RVLocs[0].getValVT(); 1510 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1511 unsigned MemSize = ResVT.getSizeInBits()/8; 1512 int FI = MFI.CreateStackObject(MemSize, MemSize, false); 1513 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); 1514 DstRC = ResVT == MVT::f32 1515 ? X86::FR32RegisterClass : X86::FR64RegisterClass; 1516 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1517 ResultReg = createResultReg(DstRC); 1518 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); 1519 } 1520 1521 if (AndToI1) { 1522 // Mask out all but lowest bit for some call which produces an i1. 1523 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 1524 BuildMI(MBB, DL, 1525 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 1526 ResultReg = AndResult; 1527 } 1528 1529 UpdateValueMap(I, ResultReg); 1530 } 1531 1532 return true; 1533} 1534 1535 1536bool 1537X86FastISel::TargetSelectInstruction(Instruction *I) { 1538 switch (I->getOpcode()) { 1539 default: break; 1540 case Instruction::Load: 1541 return X86SelectLoad(I); 1542 case Instruction::Store: 1543 return X86SelectStore(I); 1544 case Instruction::ICmp: 1545 case Instruction::FCmp: 1546 return X86SelectCmp(I); 1547 case Instruction::ZExt: 1548 return X86SelectZExt(I); 1549 case Instruction::Br: 1550 return X86SelectBranch(I); 1551 case Instruction::Call: 1552 return X86SelectCall(I); 1553 case Instruction::LShr: 1554 case Instruction::AShr: 1555 case Instruction::Shl: 1556 return X86SelectShift(I); 1557 case Instruction::Select: 1558 return X86SelectSelect(I); 1559 case Instruction::Trunc: 1560 return X86SelectTrunc(I); 1561 case Instruction::FPExt: 1562 return X86SelectFPExt(I); 1563 case Instruction::FPTrunc: 1564 return X86SelectFPTrunc(I); 1565 case Instruction::ExtractValue: 1566 return X86SelectExtractValue(I); 1567 case Instruction::IntToPtr: // Deliberate fall-through. 1568 case Instruction::PtrToInt: { 1569 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1570 EVT DstVT = TLI.getValueType(I->getType()); 1571 if (DstVT.bitsGT(SrcVT)) 1572 return X86SelectZExt(I); 1573 if (DstVT.bitsLT(SrcVT)) 1574 return X86SelectTrunc(I); 1575 unsigned Reg = getRegForValue(I->getOperand(0)); 1576 if (Reg == 0) return false; 1577 UpdateValueMap(I, Reg); 1578 return true; 1579 } 1580 } 1581 1582 return false; 1583} 1584 1585unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { 1586 EVT VT; 1587 if (!isTypeLegal(C->getType(), VT)) 1588 return false; 1589 1590 // Get opcode and regclass of the output for the given load instruction. 1591 unsigned Opc = 0; 1592 const TargetRegisterClass *RC = NULL; 1593 switch (VT.getSimpleVT().SimpleTy) { 1594 default: return false; 1595 case MVT::i8: 1596 Opc = X86::MOV8rm; 1597 RC = X86::GR8RegisterClass; 1598 break; 1599 case MVT::i16: 1600 Opc = X86::MOV16rm; 1601 RC = X86::GR16RegisterClass; 1602 break; 1603 case MVT::i32: 1604 Opc = X86::MOV32rm; 1605 RC = X86::GR32RegisterClass; 1606 break; 1607 case MVT::i64: 1608 // Must be in x86-64 mode. 1609 Opc = X86::MOV64rm; 1610 RC = X86::GR64RegisterClass; 1611 break; 1612 case MVT::f32: 1613 if (Subtarget->hasSSE1()) { 1614 Opc = X86::MOVSSrm; 1615 RC = X86::FR32RegisterClass; 1616 } else { 1617 Opc = X86::LD_Fp32m; 1618 RC = X86::RFP32RegisterClass; 1619 } 1620 break; 1621 case MVT::f64: 1622 if (Subtarget->hasSSE2()) { 1623 Opc = X86::MOVSDrm; 1624 RC = X86::FR64RegisterClass; 1625 } else { 1626 Opc = X86::LD_Fp64m; 1627 RC = X86::RFP64RegisterClass; 1628 } 1629 break; 1630 case MVT::f80: 1631 // No f80 support yet. 1632 return false; 1633 } 1634 1635 // Materialize addresses with LEA instructions. 1636 if (isa<GlobalValue>(C)) { 1637 X86AddressMode AM; 1638 if (X86SelectAddress(C, AM)) { 1639 if (TLI.getPointerTy() == MVT::i32) 1640 Opc = X86::LEA32r; 1641 else 1642 Opc = X86::LEA64r; 1643 unsigned ResultReg = createResultReg(RC); 1644 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1645 return ResultReg; 1646 } 1647 return 0; 1648 } 1649 1650 // MachineConstantPool wants an explicit alignment. 1651 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 1652 if (Align == 0) { 1653 // Alignment of vector types. FIXME! 1654 Align = TD.getTypeAllocSize(C->getType()); 1655 } 1656 1657 // x86-32 PIC requires a PIC base register for constant pools. 1658 unsigned PICBase = 0; 1659 unsigned char OpFlag = 0; 1660 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 1661 OpFlag = X86II::MO_PIC_BASE_OFFSET; 1662 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1663 } else if (Subtarget->isPICStyleGOT()) { 1664 OpFlag = X86II::MO_GOTOFF; 1665 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1666 } else if (Subtarget->isPICStyleRIPRel() && 1667 TM.getCodeModel() == CodeModel::Small) { 1668 PICBase = X86::RIP; 1669 } 1670 1671 // Create the load from the constant pool. 1672 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 1673 unsigned ResultReg = createResultReg(RC); 1674 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), 1675 MCPOffset, PICBase, OpFlag); 1676 1677 return ResultReg; 1678} 1679 1680unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { 1681 // Fail on dynamic allocas. At this point, getRegForValue has already 1682 // checked its CSE maps, so if we're here trying to handle a dynamic 1683 // alloca, we're not going to succeed. X86SelectAddress has a 1684 // check for dynamic allocas, because it's called directly from 1685 // various places, but TargetMaterializeAlloca also needs a check 1686 // in order to avoid recursion between getRegForValue, 1687 // X86SelectAddrss, and TargetMaterializeAlloca. 1688 if (!StaticAllocaMap.count(C)) 1689 return 0; 1690 1691 X86AddressMode AM; 1692 if (!X86SelectAddress(C, AM)) 1693 return 0; 1694 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 1695 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 1696 unsigned ResultReg = createResultReg(RC); 1697 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1698 return ResultReg; 1699} 1700 1701namespace llvm { 1702 llvm::FastISel *X86::createFastISel(MachineFunction &mf, 1703 MachineModuleInfo *mmi, 1704 DwarfWriter *dw, 1705 DenseMap<const Value *, unsigned> &vm, 1706 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 1707 DenseMap<const AllocaInst *, int> &am 1708#ifndef NDEBUG 1709 , SmallSet<Instruction*, 8> &cil 1710#endif 1711 ) { 1712 return new X86FastISel(mf, mmi, dw, vm, bm, am 1713#ifndef NDEBUG 1714 , cil 1715#endif 1716 ); 1717 } 1718} 1719