X86FastISel.cpp revision ed3a8067a60ecf2c215e77327a57904c3ebc3355
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Instructions.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/CodeGen/FastISel.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/Support/CallSite.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/GetElementPtrTypeIterator.h" 34#include "llvm/Target/TargetOptions.h" 35using namespace llvm; 36 37namespace { 38 39class X86FastISel : public FastISel { 40 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 41 /// make the right decision when generating code for different targets. 42 const X86Subtarget *Subtarget; 43 44 /// StackPtr - Register used as the stack pointer. 45 /// 46 unsigned StackPtr; 47 48 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 49 /// floating point ops. 50 /// When SSE is available, use it for f32 operations. 51 /// When SSE2 is available, use it for f64 operations. 52 bool X86ScalarSSEf64; 53 bool X86ScalarSSEf32; 54 55public: 56 explicit X86FastISel(MachineFunction &mf, 57 DenseMap<const Value *, unsigned> &vm, 58 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 59 DenseMap<const AllocaInst *, int> &am 60#ifndef NDEBUG 61 , SmallSet<Instruction*, 8> &cil 62#endif 63 ) 64 : FastISel(mf, vm, bm, am 65#ifndef NDEBUG 66 , cil 67#endif 68 ) { 69 Subtarget = &TM.getSubtarget<X86Subtarget>(); 70 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 71 X86ScalarSSEf64 = Subtarget->hasSSE2(); 72 X86ScalarSSEf32 = Subtarget->hasSSE1(); 73 } 74 75 virtual bool TargetSelectInstruction(Instruction *I); 76 77#include "X86GenFastISel.inc" 78 79private: 80 bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT); 81 82 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 83 84 bool X86FastEmitStore(EVT VT, Value *Val, 85 const X86AddressMode &AM); 86 bool X86FastEmitStore(EVT VT, unsigned Val, 87 const X86AddressMode &AM); 88 89 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 90 unsigned &ResultReg); 91 92 bool X86SelectAddress(Value *V, X86AddressMode &AM); 93 bool X86SelectCallAddress(Value *V, X86AddressMode &AM); 94 95 bool X86SelectLoad(Instruction *I); 96 97 bool X86SelectStore(Instruction *I); 98 99 bool X86SelectCmp(Instruction *I); 100 101 bool X86SelectZExt(Instruction *I); 102 103 bool X86SelectBranch(Instruction *I); 104 105 bool X86SelectShift(Instruction *I); 106 107 bool X86SelectSelect(Instruction *I); 108 109 bool X86SelectTrunc(Instruction *I); 110 111 bool X86SelectFPExt(Instruction *I); 112 bool X86SelectFPTrunc(Instruction *I); 113 114 bool X86SelectExtractValue(Instruction *I); 115 116 bool X86VisitIntrinsicCall(IntrinsicInst &I); 117 bool X86SelectCall(Instruction *I); 118 119 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false); 120 121 const X86InstrInfo *getInstrInfo() const { 122 return getTargetMachine()->getInstrInfo(); 123 } 124 const X86TargetMachine *getTargetMachine() const { 125 return static_cast<const X86TargetMachine *>(&TM); 126 } 127 128 unsigned TargetMaterializeConstant(Constant *C); 129 130 unsigned TargetMaterializeAlloca(AllocaInst *C); 131 132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 133 /// computed in an SSE register, not on the X87 floating point stack. 134 bool isScalarFPTypeInSSEReg(EVT VT) const { 135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 137 } 138 139 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); 140}; 141 142} // end anonymous namespace. 143 144bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { 145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 146 if (VT == MVT::Other || !VT.isSimple()) 147 // Unhandled type. Halt "fast" selection and bail. 148 return false; 149 150 // For now, require SSE/SSE2 for performing floating-point operations, 151 // since x87 requires additional work. 152 if (VT == MVT::f64 && !X86ScalarSSEf64) 153 return false; 154 if (VT == MVT::f32 && !X86ScalarSSEf32) 155 return false; 156 // Similarly, no f80 support yet. 157 if (VT == MVT::f80) 158 return false; 159 // We only handle legal types. For example, on x86-32 the instruction 160 // selector contains all of the 64-bit instructions from x86-64, 161 // under the assumption that i64 won't be used if the target doesn't 162 // support it. 163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 164} 165 166#include "X86GenCallingConv.inc" 167 168/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 169/// convention. 170CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC, 171 bool isTaillCall) { 172 if (Subtarget->is64Bit()) { 173 if (CC == CallingConv::GHC) 174 return CC_X86_64_GHC; 175 else if (Subtarget->isTargetWin64()) 176 return CC_X86_Win64_C; 177 else 178 return CC_X86_64_C; 179 } 180 181 if (CC == CallingConv::X86_FastCall) 182 return CC_X86_32_FastCall; 183 else if (CC == CallingConv::Fast) 184 return CC_X86_32_FastCC; 185 else if (CC == CallingConv::GHC) 186 return CC_X86_32_GHC; 187 else 188 return CC_X86_32_C; 189} 190 191/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 192/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 193/// Return true and the result register by reference if it is possible. 194bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 195 unsigned &ResultReg) { 196 // Get opcode and regclass of the output for the given load instruction. 197 unsigned Opc = 0; 198 const TargetRegisterClass *RC = NULL; 199 switch (VT.getSimpleVT().SimpleTy) { 200 default: return false; 201 case MVT::i1: 202 case MVT::i8: 203 Opc = X86::MOV8rm; 204 RC = X86::GR8RegisterClass; 205 break; 206 case MVT::i16: 207 Opc = X86::MOV16rm; 208 RC = X86::GR16RegisterClass; 209 break; 210 case MVT::i32: 211 Opc = X86::MOV32rm; 212 RC = X86::GR32RegisterClass; 213 break; 214 case MVT::i64: 215 // Must be in x86-64 mode. 216 Opc = X86::MOV64rm; 217 RC = X86::GR64RegisterClass; 218 break; 219 case MVT::f32: 220 if (Subtarget->hasSSE1()) { 221 Opc = X86::MOVSSrm; 222 RC = X86::FR32RegisterClass; 223 } else { 224 Opc = X86::LD_Fp32m; 225 RC = X86::RFP32RegisterClass; 226 } 227 break; 228 case MVT::f64: 229 if (Subtarget->hasSSE2()) { 230 Opc = X86::MOVSDrm; 231 RC = X86::FR64RegisterClass; 232 } else { 233 Opc = X86::LD_Fp64m; 234 RC = X86::RFP64RegisterClass; 235 } 236 break; 237 case MVT::f80: 238 // No f80 support yet. 239 return false; 240 } 241 242 ResultReg = createResultReg(RC); 243 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 244 return true; 245} 246 247/// X86FastEmitStore - Emit a machine instruction to store a value Val of 248/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 249/// and a displacement offset, or a GlobalAddress, 250/// i.e. V. Return true if it is possible. 251bool 252X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, 253 const X86AddressMode &AM) { 254 // Get opcode and regclass of the output for the given store instruction. 255 unsigned Opc = 0; 256 switch (VT.getSimpleVT().SimpleTy) { 257 case MVT::f80: // No f80 support yet. 258 default: return false; 259 case MVT::i1: { 260 // Mask out all but lowest bit. 261 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 262 BuildMI(MBB, DL, 263 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 264 Val = AndResult; 265 } 266 // FALLTHROUGH, handling i1 as i8. 267 case MVT::i8: Opc = X86::MOV8mr; break; 268 case MVT::i16: Opc = X86::MOV16mr; break; 269 case MVT::i32: Opc = X86::MOV32mr; break; 270 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 271 case MVT::f32: 272 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 273 break; 274 case MVT::f64: 275 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 276 break; 277 } 278 279 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); 280 return true; 281} 282 283bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, 284 const X86AddressMode &AM) { 285 // Handle 'null' like i32/i64 0. 286 if (isa<ConstantPointerNull>(Val)) 287 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 288 289 // If this is a store of a simple constant, fold the constant into the store. 290 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 291 unsigned Opc = 0; 292 bool Signed = true; 293 switch (VT.getSimpleVT().SimpleTy) { 294 default: break; 295 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 296 case MVT::i8: Opc = X86::MOV8mi; break; 297 case MVT::i16: Opc = X86::MOV16mi; break; 298 case MVT::i32: Opc = X86::MOV32mi; break; 299 case MVT::i64: 300 // Must be a 32-bit sign extended value. 301 if ((int)CI->getSExtValue() == CI->getSExtValue()) 302 Opc = X86::MOV64mi32; 303 break; 304 } 305 306 if (Opc) { 307 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) 308 .addImm(Signed ? CI->getSExtValue() : 309 CI->getZExtValue()); 310 return true; 311 } 312 } 313 314 unsigned ValReg = getRegForValue(Val); 315 if (ValReg == 0) 316 return false; 317 318 return X86FastEmitStore(VT, ValReg, AM); 319} 320 321/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 322/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 323/// ISD::SIGN_EXTEND). 324bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 325 unsigned Src, EVT SrcVT, 326 unsigned &ResultReg) { 327 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); 328 329 if (RR != 0) { 330 ResultReg = RR; 331 return true; 332 } else 333 return false; 334} 335 336/// X86SelectAddress - Attempt to fill in an address from the given value. 337/// 338bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { 339 User *U = NULL; 340 unsigned Opcode = Instruction::UserOp1; 341 if (Instruction *I = dyn_cast<Instruction>(V)) { 342 Opcode = I->getOpcode(); 343 U = I; 344 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 345 Opcode = C->getOpcode(); 346 U = C; 347 } 348 349 switch (Opcode) { 350 default: break; 351 case Instruction::BitCast: 352 // Look past bitcasts. 353 return X86SelectAddress(U->getOperand(0), AM); 354 355 case Instruction::IntToPtr: 356 // Look past no-op inttoptrs. 357 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 358 return X86SelectAddress(U->getOperand(0), AM); 359 break; 360 361 case Instruction::PtrToInt: 362 // Look past no-op ptrtoints. 363 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 364 return X86SelectAddress(U->getOperand(0), AM); 365 break; 366 367 case Instruction::Alloca: { 368 // Do static allocas. 369 const AllocaInst *A = cast<AllocaInst>(V); 370 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 371 if (SI != StaticAllocaMap.end()) { 372 AM.BaseType = X86AddressMode::FrameIndexBase; 373 AM.Base.FrameIndex = SI->second; 374 return true; 375 } 376 break; 377 } 378 379 case Instruction::Add: { 380 // Adds of constants are common and easy enough. 381 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 382 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 383 // They have to fit in the 32-bit signed displacement field though. 384 if (isInt<32>(Disp)) { 385 AM.Disp = (uint32_t)Disp; 386 return X86SelectAddress(U->getOperand(0), AM); 387 } 388 } 389 break; 390 } 391 392 case Instruction::GetElementPtr: { 393 X86AddressMode SavedAM = AM; 394 395 // Pattern-match simple GEPs. 396 uint64_t Disp = (int32_t)AM.Disp; 397 unsigned IndexReg = AM.IndexReg; 398 unsigned Scale = AM.Scale; 399 gep_type_iterator GTI = gep_type_begin(U); 400 // Iterate through the indices, folding what we can. Constants can be 401 // folded, and one dynamic index can be handled, if the scale is supported. 402 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end(); 403 i != e; ++i, ++GTI) { 404 Value *Op = *i; 405 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 406 const StructLayout *SL = TD.getStructLayout(STy); 407 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 408 Disp += SL->getElementOffset(Idx); 409 } else { 410 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 411 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 412 // Constant-offset addressing. 413 Disp += CI->getSExtValue() * S; 414 } else if (IndexReg == 0 && 415 (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 416 (S == 1 || S == 2 || S == 4 || S == 8)) { 417 // Scaled-index addressing. 418 Scale = S; 419 IndexReg = getRegForGEPIndex(Op); 420 if (IndexReg == 0) 421 return false; 422 } else 423 // Unsupported. 424 goto unsupported_gep; 425 } 426 } 427 // Check for displacement overflow. 428 if (!isInt<32>(Disp)) 429 break; 430 // Ok, the GEP indices were covered by constant-offset and scaled-index 431 // addressing. Update the address state and move on to examining the base. 432 AM.IndexReg = IndexReg; 433 AM.Scale = Scale; 434 AM.Disp = (uint32_t)Disp; 435 if (X86SelectAddress(U->getOperand(0), AM)) 436 return true; 437 438 // If we couldn't merge the sub value into this addr mode, revert back to 439 // our address and just match the value instead of completely failing. 440 AM = SavedAM; 441 break; 442 unsupported_gep: 443 // Ok, the GEP indices weren't all covered. 444 break; 445 } 446 } 447 448 // Handle constant address. 449 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 450 // Can't handle alternate code models yet. 451 if (TM.getCodeModel() != CodeModel::Small) 452 return false; 453 454 // RIP-relative addresses can't have additional register operands. 455 if (Subtarget->isPICStyleRIPRel() && 456 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 457 return false; 458 459 // Can't handle TLS yet. 460 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 461 if (GVar->isThreadLocal()) 462 return false; 463 464 // Okay, we've committed to selecting this global. Set up the basic address. 465 AM.GV = GV; 466 467 // Allow the subtarget to classify the global. 468 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 469 470 // If this reference is relative to the pic base, set it now. 471 if (isGlobalRelativeToPICBase(GVFlags)) { 472 // FIXME: How do we know Base.Reg is free?? 473 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 474 } 475 476 // Unless the ABI requires an extra load, return a direct reference to 477 // the global. 478 if (!isGlobalStubReference(GVFlags)) { 479 if (Subtarget->isPICStyleRIPRel()) { 480 // Use rip-relative addressing if we can. Above we verified that the 481 // base and index registers are unused. 482 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 483 AM.Base.Reg = X86::RIP; 484 } 485 AM.GVOpFlags = GVFlags; 486 return true; 487 } 488 489 // Ok, we need to do a load from a stub. If we've already loaded from this 490 // stub, reuse the loaded pointer, otherwise emit the load now. 491 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 492 unsigned LoadReg; 493 if (I != LocalValueMap.end() && I->second != 0) { 494 LoadReg = I->second; 495 } else { 496 // Issue load from stub. 497 unsigned Opc = 0; 498 const TargetRegisterClass *RC = NULL; 499 X86AddressMode StubAM; 500 StubAM.Base.Reg = AM.Base.Reg; 501 StubAM.GV = GV; 502 StubAM.GVOpFlags = GVFlags; 503 504 if (TLI.getPointerTy() == MVT::i64) { 505 Opc = X86::MOV64rm; 506 RC = X86::GR64RegisterClass; 507 508 if (Subtarget->isPICStyleRIPRel()) 509 StubAM.Base.Reg = X86::RIP; 510 } else { 511 Opc = X86::MOV32rm; 512 RC = X86::GR32RegisterClass; 513 } 514 515 LoadReg = createResultReg(RC); 516 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM); 517 518 // Prevent loading GV stub multiple times in same MBB. 519 LocalValueMap[V] = LoadReg; 520 } 521 522 // Now construct the final address. Note that the Disp, Scale, 523 // and Index values may already be set here. 524 AM.Base.Reg = LoadReg; 525 AM.GV = 0; 526 return true; 527 } 528 529 // If all else fails, try to materialize the value in a register. 530 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 531 if (AM.Base.Reg == 0) { 532 AM.Base.Reg = getRegForValue(V); 533 return AM.Base.Reg != 0; 534 } 535 if (AM.IndexReg == 0) { 536 assert(AM.Scale == 1 && "Scale with no index!"); 537 AM.IndexReg = getRegForValue(V); 538 return AM.IndexReg != 0; 539 } 540 } 541 542 return false; 543} 544 545/// X86SelectCallAddress - Attempt to fill in an address from the given value. 546/// 547bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) { 548 User *U = NULL; 549 unsigned Opcode = Instruction::UserOp1; 550 if (Instruction *I = dyn_cast<Instruction>(V)) { 551 Opcode = I->getOpcode(); 552 U = I; 553 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 554 Opcode = C->getOpcode(); 555 U = C; 556 } 557 558 switch (Opcode) { 559 default: break; 560 case Instruction::BitCast: 561 // Look past bitcasts. 562 return X86SelectCallAddress(U->getOperand(0), AM); 563 564 case Instruction::IntToPtr: 565 // Look past no-op inttoptrs. 566 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 567 return X86SelectCallAddress(U->getOperand(0), AM); 568 break; 569 570 case Instruction::PtrToInt: 571 // Look past no-op ptrtoints. 572 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 573 return X86SelectCallAddress(U->getOperand(0), AM); 574 break; 575 } 576 577 // Handle constant address. 578 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 579 // Can't handle alternate code models yet. 580 if (TM.getCodeModel() != CodeModel::Small) 581 return false; 582 583 // RIP-relative addresses can't have additional register operands. 584 if (Subtarget->isPICStyleRIPRel() && 585 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 586 return false; 587 588 // Can't handle TLS or DLLImport. 589 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 590 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage()) 591 return false; 592 593 // Okay, we've committed to selecting this global. Set up the basic address. 594 AM.GV = GV; 595 596 // No ABI requires an extra load for anything other than DLLImport, which 597 // we rejected above. Return a direct reference to the global. 598 if (Subtarget->isPICStyleRIPRel()) { 599 // Use rip-relative addressing if we can. Above we verified that the 600 // base and index registers are unused. 601 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 602 AM.Base.Reg = X86::RIP; 603 } else if (Subtarget->isPICStyleStubPIC()) { 604 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 605 } else if (Subtarget->isPICStyleGOT()) { 606 AM.GVOpFlags = X86II::MO_GOTOFF; 607 } 608 609 return true; 610 } 611 612 // If all else fails, try to materialize the value in a register. 613 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 614 if (AM.Base.Reg == 0) { 615 AM.Base.Reg = getRegForValue(V); 616 return AM.Base.Reg != 0; 617 } 618 if (AM.IndexReg == 0) { 619 assert(AM.Scale == 1 && "Scale with no index!"); 620 AM.IndexReg = getRegForValue(V); 621 return AM.IndexReg != 0; 622 } 623 } 624 625 return false; 626} 627 628 629/// X86SelectStore - Select and emit code to implement store instructions. 630bool X86FastISel::X86SelectStore(Instruction* I) { 631 EVT VT; 632 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 633 return false; 634 635 X86AddressMode AM; 636 if (!X86SelectAddress(I->getOperand(1), AM)) 637 return false; 638 639 return X86FastEmitStore(VT, I->getOperand(0), AM); 640} 641 642/// X86SelectLoad - Select and emit code to implement load instructions. 643/// 644bool X86FastISel::X86SelectLoad(Instruction *I) { 645 EVT VT; 646 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 647 return false; 648 649 X86AddressMode AM; 650 if (!X86SelectAddress(I->getOperand(0), AM)) 651 return false; 652 653 unsigned ResultReg = 0; 654 if (X86FastEmitLoad(VT, AM, ResultReg)) { 655 UpdateValueMap(I, ResultReg); 656 return true; 657 } 658 return false; 659} 660 661static unsigned X86ChooseCmpOpcode(EVT VT) { 662 switch (VT.getSimpleVT().SimpleTy) { 663 default: return 0; 664 case MVT::i8: return X86::CMP8rr; 665 case MVT::i16: return X86::CMP16rr; 666 case MVT::i32: return X86::CMP32rr; 667 case MVT::i64: return X86::CMP64rr; 668 case MVT::f32: return X86::UCOMISSrr; 669 case MVT::f64: return X86::UCOMISDrr; 670 } 671} 672 673/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 674/// of the comparison, return an opcode that works for the compare (e.g. 675/// CMP32ri) otherwise return 0. 676static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) { 677 switch (VT.getSimpleVT().SimpleTy) { 678 // Otherwise, we can't fold the immediate into this comparison. 679 default: return 0; 680 case MVT::i8: return X86::CMP8ri; 681 case MVT::i16: return X86::CMP16ri; 682 case MVT::i32: return X86::CMP32ri; 683 case MVT::i64: 684 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 685 // field. 686 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 687 return X86::CMP64ri32; 688 return 0; 689 } 690} 691 692bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) { 693 unsigned Op0Reg = getRegForValue(Op0); 694 if (Op0Reg == 0) return false; 695 696 // Handle 'null' like i32/i64 0. 697 if (isa<ConstantPointerNull>(Op1)) 698 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 699 700 // We have two options: compare with register or immediate. If the RHS of 701 // the compare is an immediate that we can fold into this compare, use 702 // CMPri, otherwise use CMPrr. 703 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 704 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 705 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) 706 .addImm(Op1C->getSExtValue()); 707 return true; 708 } 709 } 710 711 unsigned CompareOpc = X86ChooseCmpOpcode(VT); 712 if (CompareOpc == 0) return false; 713 714 unsigned Op1Reg = getRegForValue(Op1); 715 if (Op1Reg == 0) return false; 716 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 717 718 return true; 719} 720 721bool X86FastISel::X86SelectCmp(Instruction *I) { 722 CmpInst *CI = cast<CmpInst>(I); 723 724 EVT VT; 725 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 726 return false; 727 728 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 729 unsigned SetCCOpc; 730 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 731 switch (CI->getPredicate()) { 732 case CmpInst::FCMP_OEQ: { 733 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 734 return false; 735 736 unsigned EReg = createResultReg(&X86::GR8RegClass); 737 unsigned NPReg = createResultReg(&X86::GR8RegClass); 738 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); 739 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); 740 BuildMI(MBB, DL, 741 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 742 UpdateValueMap(I, ResultReg); 743 return true; 744 } 745 case CmpInst::FCMP_UNE: { 746 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 747 return false; 748 749 unsigned NEReg = createResultReg(&X86::GR8RegClass); 750 unsigned PReg = createResultReg(&X86::GR8RegClass); 751 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); 752 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); 753 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 754 UpdateValueMap(I, ResultReg); 755 return true; 756 } 757 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 758 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 759 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 760 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 761 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 762 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 763 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 764 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 765 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 766 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 767 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 768 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 769 770 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 771 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 772 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 773 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 774 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 775 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 776 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 777 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 778 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 779 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 780 default: 781 return false; 782 } 783 784 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 785 if (SwapArgs) 786 std::swap(Op0, Op1); 787 788 // Emit a compare of Op0/Op1. 789 if (!X86FastEmitCompare(Op0, Op1, VT)) 790 return false; 791 792 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); 793 UpdateValueMap(I, ResultReg); 794 return true; 795} 796 797bool X86FastISel::X86SelectZExt(Instruction *I) { 798 // Handle zero-extension from i1 to i8, which is common. 799 if (I->getType()->isIntegerTy(8) && 800 I->getOperand(0)->getType()->isIntegerTy(1)) { 801 unsigned ResultReg = getRegForValue(I->getOperand(0)); 802 if (ResultReg == 0) return false; 803 // Set the high bits to zero. 804 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg); 805 if (ResultReg == 0) return false; 806 UpdateValueMap(I, ResultReg); 807 return true; 808 } 809 810 return false; 811} 812 813 814bool X86FastISel::X86SelectBranch(Instruction *I) { 815 // Unconditional branches are selected by tablegen-generated code. 816 // Handle a conditional branch. 817 BranchInst *BI = cast<BranchInst>(I); 818 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 819 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 820 821 // Fold the common case of a conditional branch with a comparison. 822 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 823 if (CI->hasOneUse()) { 824 EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 825 826 // Try to take advantage of fallthrough opportunities. 827 CmpInst::Predicate Predicate = CI->getPredicate(); 828 if (MBB->isLayoutSuccessor(TrueMBB)) { 829 std::swap(TrueMBB, FalseMBB); 830 Predicate = CmpInst::getInversePredicate(Predicate); 831 } 832 833 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 834 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 835 836 switch (Predicate) { 837 case CmpInst::FCMP_OEQ: 838 std::swap(TrueMBB, FalseMBB); 839 Predicate = CmpInst::FCMP_UNE; 840 // FALL THROUGH 841 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 842 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 843 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 844 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break; 845 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break; 846 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 847 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break; 848 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break; 849 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 850 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break; 851 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break; 852 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 853 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 854 855 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 856 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 857 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 858 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 859 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 860 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 861 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break; 862 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break; 863 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break; 864 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break; 865 default: 866 return false; 867 } 868 869 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 870 if (SwapArgs) 871 std::swap(Op0, Op1); 872 873 // Emit a compare of the LHS and RHS, setting the flags. 874 if (!X86FastEmitCompare(Op0, Op1, VT)) 875 return false; 876 877 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); 878 879 if (Predicate == CmpInst::FCMP_UNE) { 880 // X86 requires a second branch to handle UNE (and OEQ, 881 // which is mapped to UNE above). 882 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB); 883 } 884 885 FastEmitBranch(FalseMBB); 886 MBB->addSuccessor(TrueMBB); 887 return true; 888 } 889 } else if (ExtractValueInst *EI = 890 dyn_cast<ExtractValueInst>(BI->getCondition())) { 891 // Check to see if the branch instruction is from an "arithmetic with 892 // overflow" intrinsic. The main way these intrinsics are used is: 893 // 894 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 895 // %sum = extractvalue { i32, i1 } %t, 0 896 // %obit = extractvalue { i32, i1 } %t, 1 897 // br i1 %obit, label %overflow, label %normal 898 // 899 // The %sum and %obit are converted in an ADD and a SETO/SETB before 900 // reaching the branch. Therefore, we search backwards through the MBB 901 // looking for the SETO/SETB instruction. If an instruction modifies the 902 // EFLAGS register before we reach the SETO/SETB instruction, then we can't 903 // convert the branch into a JO/JB instruction. 904 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){ 905 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || 906 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { 907 const MachineInstr *SetMI = 0; 908 unsigned Reg = lookUpRegForValue(EI); 909 910 for (MachineBasicBlock::const_reverse_iterator 911 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 912 const MachineInstr &MI = *RI; 913 914 if (MI.modifiesRegister(Reg)) { 915 unsigned Src, Dst, SrcSR, DstSR; 916 917 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { 918 Reg = Src; 919 continue; 920 } 921 922 SetMI = &MI; 923 break; 924 } 925 926 const TargetInstrDesc &TID = MI.getDesc(); 927 if (TID.hasUnmodeledSideEffects() || 928 TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) 929 break; 930 } 931 932 if (SetMI) { 933 unsigned OpCode = SetMI->getOpcode(); 934 935 if (OpCode == X86::SETOr || OpCode == X86::SETBr) { 936 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? 937 X86::JO_4 : X86::JB_4)) 938 .addMBB(TrueMBB); 939 FastEmitBranch(FalseMBB); 940 MBB->addSuccessor(TrueMBB); 941 return true; 942 } 943 } 944 } 945 } 946 } 947 948 // Otherwise do a clumsy setcc and re-test it. 949 unsigned OpReg = getRegForValue(BI->getCondition()); 950 if (OpReg == 0) return false; 951 952 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 953 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB); 954 FastEmitBranch(FalseMBB); 955 MBB->addSuccessor(TrueMBB); 956 return true; 957} 958 959bool X86FastISel::X86SelectShift(Instruction *I) { 960 unsigned CReg = 0, OpReg = 0, OpImm = 0; 961 const TargetRegisterClass *RC = NULL; 962 if (I->getType()->isIntegerTy(8)) { 963 CReg = X86::CL; 964 RC = &X86::GR8RegClass; 965 switch (I->getOpcode()) { 966 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 967 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 968 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 969 default: return false; 970 } 971 } else if (I->getType()->isIntegerTy(16)) { 972 CReg = X86::CX; 973 RC = &X86::GR16RegClass; 974 switch (I->getOpcode()) { 975 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 976 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 977 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 978 default: return false; 979 } 980 } else if (I->getType()->isIntegerTy(32)) { 981 CReg = X86::ECX; 982 RC = &X86::GR32RegClass; 983 switch (I->getOpcode()) { 984 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 985 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 986 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 987 default: return false; 988 } 989 } else if (I->getType()->isIntegerTy(64)) { 990 CReg = X86::RCX; 991 RC = &X86::GR64RegClass; 992 switch (I->getOpcode()) { 993 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 994 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 995 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 996 default: return false; 997 } 998 } else { 999 return false; 1000 } 1001 1002 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1003 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1004 return false; 1005 1006 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1007 if (Op0Reg == 0) return false; 1008 1009 // Fold immediate in shl(x,3). 1010 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 1011 unsigned ResultReg = createResultReg(RC); 1012 BuildMI(MBB, DL, TII.get(OpImm), 1013 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); 1014 UpdateValueMap(I, ResultReg); 1015 return true; 1016 } 1017 1018 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1019 if (Op1Reg == 0) return false; 1020 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC); 1021 1022 // The shift instruction uses X86::CL. If we defined a super-register 1023 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 1024 // we're doing here. 1025 if (CReg != X86::CL) 1026 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL) 1027 .addReg(CReg).addImm(X86::SUBREG_8BIT); 1028 1029 unsigned ResultReg = createResultReg(RC); 1030 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); 1031 UpdateValueMap(I, ResultReg); 1032 return true; 1033} 1034 1035bool X86FastISel::X86SelectSelect(Instruction *I) { 1036 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1037 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1038 return false; 1039 1040 unsigned Opc = 0; 1041 const TargetRegisterClass *RC = NULL; 1042 if (VT.getSimpleVT() == MVT::i16) { 1043 Opc = X86::CMOVE16rr; 1044 RC = &X86::GR16RegClass; 1045 } else if (VT.getSimpleVT() == MVT::i32) { 1046 Opc = X86::CMOVE32rr; 1047 RC = &X86::GR32RegClass; 1048 } else if (VT.getSimpleVT() == MVT::i64) { 1049 Opc = X86::CMOVE64rr; 1050 RC = &X86::GR64RegClass; 1051 } else { 1052 return false; 1053 } 1054 1055 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1056 if (Op0Reg == 0) return false; 1057 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1058 if (Op1Reg == 0) return false; 1059 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1060 if (Op2Reg == 0) return false; 1061 1062 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 1063 unsigned ResultReg = createResultReg(RC); 1064 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 1065 UpdateValueMap(I, ResultReg); 1066 return true; 1067} 1068 1069bool X86FastISel::X86SelectFPExt(Instruction *I) { 1070 // fpext from float to double. 1071 if (Subtarget->hasSSE2() && 1072 I->getType()->isDoubleTy()) { 1073 Value *V = I->getOperand(0); 1074 if (V->getType()->isFloatTy()) { 1075 unsigned OpReg = getRegForValue(V); 1076 if (OpReg == 0) return false; 1077 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 1078 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 1079 UpdateValueMap(I, ResultReg); 1080 return true; 1081 } 1082 } 1083 1084 return false; 1085} 1086 1087bool X86FastISel::X86SelectFPTrunc(Instruction *I) { 1088 if (Subtarget->hasSSE2()) { 1089 if (I->getType()->isFloatTy()) { 1090 Value *V = I->getOperand(0); 1091 if (V->getType()->isDoubleTy()) { 1092 unsigned OpReg = getRegForValue(V); 1093 if (OpReg == 0) return false; 1094 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 1095 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 1096 UpdateValueMap(I, ResultReg); 1097 return true; 1098 } 1099 } 1100 } 1101 1102 return false; 1103} 1104 1105bool X86FastISel::X86SelectTrunc(Instruction *I) { 1106 if (Subtarget->is64Bit()) 1107 // All other cases should be handled by the tblgen generated code. 1108 return false; 1109 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1110 EVT DstVT = TLI.getValueType(I->getType()); 1111 1112 // This code only handles truncation to byte right now. 1113 if (DstVT != MVT::i8 && DstVT != MVT::i1) 1114 // All other cases should be handled by the tblgen generated code. 1115 return false; 1116 if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 1117 // All other cases should be handled by the tblgen generated code. 1118 return false; 1119 1120 unsigned InputReg = getRegForValue(I->getOperand(0)); 1121 if (!InputReg) 1122 // Unhandled operand. Halt "fast" selection and bail. 1123 return false; 1124 1125 // First issue a copy to GR16_ABCD or GR32_ABCD. 1126 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; 1127 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1128 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 1129 unsigned CopyReg = createResultReg(CopyRC); 1130 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); 1131 1132 // Then issue an extract_subreg. 1133 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1134 CopyReg, X86::SUBREG_8BIT); 1135 if (!ResultReg) 1136 return false; 1137 1138 UpdateValueMap(I, ResultReg); 1139 return true; 1140} 1141 1142bool X86FastISel::X86SelectExtractValue(Instruction *I) { 1143 ExtractValueInst *EI = cast<ExtractValueInst>(I); 1144 Value *Agg = EI->getAggregateOperand(); 1145 1146 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) { 1147 switch (CI->getIntrinsicID()) { 1148 default: break; 1149 case Intrinsic::sadd_with_overflow: 1150 case Intrinsic::uadd_with_overflow: 1151 // Cheat a little. We know that the registers for "add" and "seto" are 1152 // allocated sequentially. However, we only keep track of the register 1153 // for "add" in the value map. Use extractvalue's index to get the 1154 // correct register for "seto". 1155 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 1156 return true; 1157 } 1158 } 1159 1160 return false; 1161} 1162 1163bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { 1164 // FIXME: Handle more intrinsics. 1165 switch (I.getIntrinsicID()) { 1166 default: return false; 1167 case Intrinsic::stackprotector: { 1168 // Emit code inline code to store the stack guard onto the stack. 1169 EVT PtrTy = TLI.getPointerTy(); 1170 1171 Value *Op1 = I.getOperand(1); // The guard's value. 1172 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); 1173 1174 // Grab the frame index. 1175 X86AddressMode AM; 1176 if (!X86SelectAddress(Slot, AM)) return false; 1177 1178 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false; 1179 1180 return true; 1181 } 1182 case Intrinsic::objectsize: { 1183 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2)); 1184 const Type *Ty = I.getCalledFunction()->getReturnType(); 1185 1186 assert(CI && "Non-constant type in Intrinsic::objectsize?"); 1187 1188 EVT VT; 1189 if (!isTypeLegal(Ty, VT)) 1190 return false; 1191 1192 unsigned OpC = 0; 1193 if (VT == MVT::i32) 1194 OpC = X86::MOV32ri; 1195 else if (VT == MVT::i64) 1196 OpC = X86::MOV64ri; 1197 else 1198 return false; 1199 1200 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1201 BuildMI(MBB, DL, TII.get(OpC), ResultReg). 1202 addImm(CI->getZExtValue() == 0 ? -1ULL : 0); 1203 UpdateValueMap(&I, ResultReg); 1204 return true; 1205 } 1206 case Intrinsic::dbg_declare: { 1207 DbgDeclareInst *DI = cast<DbgDeclareInst>(&I); 1208 X86AddressMode AM; 1209 assert(DI->getAddress() && "Null address should be checked earlier!"); 1210 if (!X86SelectAddress(DI->getAddress(), AM)) 1211 return false; 1212 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 1213 // FIXME may need to add RegState::Debug to any registers produced, 1214 // although ESP/EBP should be the only ones at the moment. 1215 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0). 1216 addMetadata(DI->getVariable()); 1217 return true; 1218 } 1219 case Intrinsic::trap: { 1220 BuildMI(MBB, DL, TII.get(X86::TRAP)); 1221 return true; 1222 } 1223 case Intrinsic::sadd_with_overflow: 1224 case Intrinsic::uadd_with_overflow: { 1225 // Replace "add with overflow" intrinsics with an "add" instruction followed 1226 // by a seto/setc instruction. Later on, when the "extractvalue" 1227 // instructions are encountered, we use the fact that two registers were 1228 // created sequentially to get the correct registers for the "sum" and the 1229 // "overflow bit". 1230 const Function *Callee = I.getCalledFunction(); 1231 const Type *RetTy = 1232 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1233 1234 EVT VT; 1235 if (!isTypeLegal(RetTy, VT)) 1236 return false; 1237 1238 Value *Op1 = I.getOperand(1); 1239 Value *Op2 = I.getOperand(2); 1240 unsigned Reg1 = getRegForValue(Op1); 1241 unsigned Reg2 = getRegForValue(Op2); 1242 1243 if (Reg1 == 0 || Reg2 == 0) 1244 // FIXME: Handle values *not* in registers. 1245 return false; 1246 1247 unsigned OpC = 0; 1248 if (VT == MVT::i32) 1249 OpC = X86::ADD32rr; 1250 else if (VT == MVT::i64) 1251 OpC = X86::ADD64rr; 1252 else 1253 return false; 1254 1255 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1256 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 1257 unsigned DestReg1 = UpdateValueMap(&I, ResultReg); 1258 1259 // If the add with overflow is an intra-block value then we just want to 1260 // create temporaries for it like normal. If it is a cross-block value then 1261 // UpdateValueMap will return the cross-block register used. Since we 1262 // *really* want the value to be live in the register pair known by 1263 // UpdateValueMap, we have to use DestReg1+1 as the destination register in 1264 // the cross block case. In the non-cross-block case, we should just make 1265 // another register for the value. 1266 if (DestReg1 != ResultReg) 1267 ResultReg = DestReg1+1; 1268 else 1269 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 1270 1271 unsigned Opc = X86::SETBr; 1272 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1273 Opc = X86::SETOr; 1274 BuildMI(MBB, DL, TII.get(Opc), ResultReg); 1275 return true; 1276 } 1277 } 1278} 1279 1280bool X86FastISel::X86SelectCall(Instruction *I) { 1281 CallInst *CI = cast<CallInst>(I); 1282 Value *Callee = I->getOperand(0); 1283 1284 // Can't handle inline asm yet. 1285 if (isa<InlineAsm>(Callee)) 1286 return false; 1287 1288 // Handle intrinsic calls. 1289 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1290 return X86VisitIntrinsicCall(*II); 1291 1292 // Handle only C and fastcc calling conventions for now. 1293 CallSite CS(CI); 1294 CallingConv::ID CC = CS.getCallingConv(); 1295 if (CC != CallingConv::C && 1296 CC != CallingConv::Fast && 1297 CC != CallingConv::X86_FastCall) 1298 return false; 1299 1300 // fastcc with -tailcallopt is intended to provide a guaranteed 1301 // tail call optimization. Fastisel doesn't know how to do that. 1302 if (CC == CallingConv::Fast && GuaranteedTailCallOpt) 1303 return false; 1304 1305 // Let SDISel handle vararg functions. 1306 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1307 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1308 if (FTy->isVarArg()) 1309 return false; 1310 1311 // Handle *simple* calls for now. 1312 const Type *RetTy = CS.getType(); 1313 EVT RetVT; 1314 if (RetTy->isVoidTy()) 1315 RetVT = MVT::isVoid; 1316 else if (!isTypeLegal(RetTy, RetVT, true)) 1317 return false; 1318 1319 // Materialize callee address in a register. FIXME: GV address can be 1320 // handled with a CALLpcrel32 instead. 1321 X86AddressMode CalleeAM; 1322 if (!X86SelectCallAddress(Callee, CalleeAM)) 1323 return false; 1324 unsigned CalleeOp = 0; 1325 GlobalValue *GV = 0; 1326 if (CalleeAM.GV != 0) { 1327 GV = CalleeAM.GV; 1328 } else if (CalleeAM.Base.Reg != 0) { 1329 CalleeOp = CalleeAM.Base.Reg; 1330 } else 1331 return false; 1332 1333 // Allow calls which produce i1 results. 1334 bool AndToI1 = false; 1335 if (RetVT == MVT::i1) { 1336 RetVT = MVT::i8; 1337 AndToI1 = true; 1338 } 1339 1340 // Deal with call operands first. 1341 SmallVector<Value*, 8> ArgVals; 1342 SmallVector<unsigned, 8> Args; 1343 SmallVector<EVT, 8> ArgVTs; 1344 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1345 Args.reserve(CS.arg_size()); 1346 ArgVals.reserve(CS.arg_size()); 1347 ArgVTs.reserve(CS.arg_size()); 1348 ArgFlags.reserve(CS.arg_size()); 1349 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1350 i != e; ++i) { 1351 unsigned Arg = getRegForValue(*i); 1352 if (Arg == 0) 1353 return false; 1354 ISD::ArgFlagsTy Flags; 1355 unsigned AttrInd = i - CS.arg_begin() + 1; 1356 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1357 Flags.setSExt(); 1358 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1359 Flags.setZExt(); 1360 1361 // FIXME: Only handle *easy* calls for now. 1362 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1363 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1364 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1365 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1366 return false; 1367 1368 const Type *ArgTy = (*i)->getType(); 1369 EVT ArgVT; 1370 if (!isTypeLegal(ArgTy, ArgVT)) 1371 return false; 1372 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1373 Flags.setOrigAlign(OriginalAlignment); 1374 1375 Args.push_back(Arg); 1376 ArgVals.push_back(*i); 1377 ArgVTs.push_back(ArgVT); 1378 ArgFlags.push_back(Flags); 1379 } 1380 1381 // Analyze operands of the call, assigning locations to each operand. 1382 SmallVector<CCValAssign, 16> ArgLocs; 1383 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext()); 1384 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 1385 1386 // Get a count of how many bytes are to be pushed on the stack. 1387 unsigned NumBytes = CCInfo.getNextStackOffset(); 1388 1389 // Issue CALLSEQ_START 1390 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1391 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); 1392 1393 // Process argument: walk the register/memloc assignments, inserting 1394 // copies / loads. 1395 SmallVector<unsigned, 4> RegArgs; 1396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1397 CCValAssign &VA = ArgLocs[i]; 1398 unsigned Arg = Args[VA.getValNo()]; 1399 EVT ArgVT = ArgVTs[VA.getValNo()]; 1400 1401 // Promote the value if needed. 1402 switch (VA.getLocInfo()) { 1403 default: llvm_unreachable("Unknown loc info!"); 1404 case CCValAssign::Full: break; 1405 case CCValAssign::SExt: { 1406 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1407 Arg, ArgVT, Arg); 1408 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1409 Emitted = true; 1410 ArgVT = VA.getLocVT(); 1411 break; 1412 } 1413 case CCValAssign::ZExt: { 1414 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1415 Arg, ArgVT, Arg); 1416 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1417 Emitted = true; 1418 ArgVT = VA.getLocVT(); 1419 break; 1420 } 1421 case CCValAssign::AExt: { 1422 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1423 Arg, ArgVT, Arg); 1424 if (!Emitted) 1425 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1426 Arg, ArgVT, Arg); 1427 if (!Emitted) 1428 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1429 Arg, ArgVT, Arg); 1430 1431 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1432 ArgVT = VA.getLocVT(); 1433 break; 1434 } 1435 case CCValAssign::BCvt: { 1436 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(), 1437 ISD::BIT_CONVERT, Arg); 1438 assert(BC != 0 && "Failed to emit a bitcast!"); 1439 Arg = BC; 1440 ArgVT = VA.getLocVT(); 1441 break; 1442 } 1443 } 1444 1445 if (VA.isRegLoc()) { 1446 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 1447 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 1448 Arg, RC, RC); 1449 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1450 Emitted = true; 1451 RegArgs.push_back(VA.getLocReg()); 1452 } else { 1453 unsigned LocMemOffset = VA.getLocMemOffset(); 1454 X86AddressMode AM; 1455 AM.Base.Reg = StackPtr; 1456 AM.Disp = LocMemOffset; 1457 Value *ArgVal = ArgVals[VA.getValNo()]; 1458 1459 // If this is a really simple value, emit this with the Value* version of 1460 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 1461 // can cause us to reevaluate the argument. 1462 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 1463 X86FastEmitStore(ArgVT, ArgVal, AM); 1464 else 1465 X86FastEmitStore(ArgVT, Arg, AM); 1466 } 1467 } 1468 1469 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1470 // GOT pointer. 1471 if (Subtarget->isPICStyleGOT()) { 1472 TargetRegisterClass *RC = X86::GR32RegisterClass; 1473 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 1474 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); 1475 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1476 Emitted = true; 1477 } 1478 1479 // Issue the call. 1480 MachineInstrBuilder MIB; 1481 if (CalleeOp) { 1482 // Register-indirect call. 1483 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r; 1484 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp); 1485 1486 } else { 1487 // Direct call. 1488 assert(GV && "Not a direct call"); 1489 unsigned CallOpc = 1490 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; 1491 1492 // See if we need any target-specific flags on the GV operand. 1493 unsigned char OpFlags = 0; 1494 1495 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1496 // external symbols most go through the PLT in PIC mode. If the symbol 1497 // has hidden or protected visibility, or if it is static or local, then 1498 // we don't need to use the PLT - we can directly call it. 1499 if (Subtarget->isTargetELF() && 1500 TM.getRelocationModel() == Reloc::PIC_ && 1501 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1502 OpFlags = X86II::MO_PLT; 1503 } else if (Subtarget->isPICStyleStubAny() && 1504 (GV->isDeclaration() || GV->isWeakForLinker()) && 1505 Subtarget->getDarwinVers() < 9) { 1506 // PC-relative references to external symbols should go through $stub, 1507 // unless we're building with the leopard linker or later, which 1508 // automatically synthesizes these stubs. 1509 OpFlags = X86II::MO_DARWIN_STUB; 1510 } 1511 1512 1513 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags); 1514 } 1515 1516 // Add an implicit use GOT pointer in EBX. 1517 if (Subtarget->isPICStyleGOT()) 1518 MIB.addReg(X86::EBX); 1519 1520 // Add implicit physical register uses to the call. 1521 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1522 MIB.addReg(RegArgs[i]); 1523 1524 // Issue CALLSEQ_END 1525 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1526 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 1527 1528 // Now handle call return value (if any). 1529 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { 1530 SmallVector<CCValAssign, 16> RVLocs; 1531 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); 1532 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 1533 1534 // Copy all of the result registers out of their specified physreg. 1535 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 1536 EVT CopyVT = RVLocs[0].getValVT(); 1537 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1538 TargetRegisterClass *SrcRC = DstRC; 1539 1540 // If this is a call to a function that returns an fp value on the x87 fp 1541 // stack, but where we prefer to use the value in xmm registers, copy it 1542 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1543 if ((RVLocs[0].getLocReg() == X86::ST0 || 1544 RVLocs[0].getLocReg() == X86::ST1) && 1545 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 1546 CopyVT = MVT::f80; 1547 SrcRC = X86::RSTRegisterClass; 1548 DstRC = X86::RFP80RegisterClass; 1549 } 1550 1551 unsigned ResultReg = createResultReg(DstRC); 1552 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1553 RVLocs[0].getLocReg(), DstRC, SrcRC); 1554 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1555 Emitted = true; 1556 if (CopyVT != RVLocs[0].getValVT()) { 1557 // Round the F80 the right size, which also moves to the appropriate xmm 1558 // register. This is accomplished by storing the F80 value in memory and 1559 // then loading it back. Ewww... 1560 EVT ResVT = RVLocs[0].getValVT(); 1561 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1562 unsigned MemSize = ResVT.getSizeInBits()/8; 1563 int FI = MFI.CreateStackObject(MemSize, MemSize, false); 1564 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); 1565 DstRC = ResVT == MVT::f32 1566 ? X86::FR32RegisterClass : X86::FR64RegisterClass; 1567 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1568 ResultReg = createResultReg(DstRC); 1569 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); 1570 } 1571 1572 if (AndToI1) { 1573 // Mask out all but lowest bit for some call which produces an i1. 1574 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 1575 BuildMI(MBB, DL, 1576 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 1577 ResultReg = AndResult; 1578 } 1579 1580 UpdateValueMap(I, ResultReg); 1581 } 1582 1583 return true; 1584} 1585 1586 1587bool 1588X86FastISel::TargetSelectInstruction(Instruction *I) { 1589 switch (I->getOpcode()) { 1590 default: break; 1591 case Instruction::Load: 1592 return X86SelectLoad(I); 1593 case Instruction::Store: 1594 return X86SelectStore(I); 1595 case Instruction::ICmp: 1596 case Instruction::FCmp: 1597 return X86SelectCmp(I); 1598 case Instruction::ZExt: 1599 return X86SelectZExt(I); 1600 case Instruction::Br: 1601 return X86SelectBranch(I); 1602 case Instruction::Call: 1603 return X86SelectCall(I); 1604 case Instruction::LShr: 1605 case Instruction::AShr: 1606 case Instruction::Shl: 1607 return X86SelectShift(I); 1608 case Instruction::Select: 1609 return X86SelectSelect(I); 1610 case Instruction::Trunc: 1611 return X86SelectTrunc(I); 1612 case Instruction::FPExt: 1613 return X86SelectFPExt(I); 1614 case Instruction::FPTrunc: 1615 return X86SelectFPTrunc(I); 1616 case Instruction::ExtractValue: 1617 return X86SelectExtractValue(I); 1618 case Instruction::IntToPtr: // Deliberate fall-through. 1619 case Instruction::PtrToInt: { 1620 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1621 EVT DstVT = TLI.getValueType(I->getType()); 1622 if (DstVT.bitsGT(SrcVT)) 1623 return X86SelectZExt(I); 1624 if (DstVT.bitsLT(SrcVT)) 1625 return X86SelectTrunc(I); 1626 unsigned Reg = getRegForValue(I->getOperand(0)); 1627 if (Reg == 0) return false; 1628 UpdateValueMap(I, Reg); 1629 return true; 1630 } 1631 } 1632 1633 return false; 1634} 1635 1636unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { 1637 EVT VT; 1638 if (!isTypeLegal(C->getType(), VT)) 1639 return false; 1640 1641 // Get opcode and regclass of the output for the given load instruction. 1642 unsigned Opc = 0; 1643 const TargetRegisterClass *RC = NULL; 1644 switch (VT.getSimpleVT().SimpleTy) { 1645 default: return false; 1646 case MVT::i8: 1647 Opc = X86::MOV8rm; 1648 RC = X86::GR8RegisterClass; 1649 break; 1650 case MVT::i16: 1651 Opc = X86::MOV16rm; 1652 RC = X86::GR16RegisterClass; 1653 break; 1654 case MVT::i32: 1655 Opc = X86::MOV32rm; 1656 RC = X86::GR32RegisterClass; 1657 break; 1658 case MVT::i64: 1659 // Must be in x86-64 mode. 1660 Opc = X86::MOV64rm; 1661 RC = X86::GR64RegisterClass; 1662 break; 1663 case MVT::f32: 1664 if (Subtarget->hasSSE1()) { 1665 Opc = X86::MOVSSrm; 1666 RC = X86::FR32RegisterClass; 1667 } else { 1668 Opc = X86::LD_Fp32m; 1669 RC = X86::RFP32RegisterClass; 1670 } 1671 break; 1672 case MVT::f64: 1673 if (Subtarget->hasSSE2()) { 1674 Opc = X86::MOVSDrm; 1675 RC = X86::FR64RegisterClass; 1676 } else { 1677 Opc = X86::LD_Fp64m; 1678 RC = X86::RFP64RegisterClass; 1679 } 1680 break; 1681 case MVT::f80: 1682 // No f80 support yet. 1683 return false; 1684 } 1685 1686 // Materialize addresses with LEA instructions. 1687 if (isa<GlobalValue>(C)) { 1688 X86AddressMode AM; 1689 if (X86SelectAddress(C, AM)) { 1690 if (TLI.getPointerTy() == MVT::i32) 1691 Opc = X86::LEA32r; 1692 else 1693 Opc = X86::LEA64r; 1694 unsigned ResultReg = createResultReg(RC); 1695 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1696 return ResultReg; 1697 } 1698 return 0; 1699 } 1700 1701 // MachineConstantPool wants an explicit alignment. 1702 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 1703 if (Align == 0) { 1704 // Alignment of vector types. FIXME! 1705 Align = TD.getTypeAllocSize(C->getType()); 1706 } 1707 1708 // x86-32 PIC requires a PIC base register for constant pools. 1709 unsigned PICBase = 0; 1710 unsigned char OpFlag = 0; 1711 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 1712 OpFlag = X86II::MO_PIC_BASE_OFFSET; 1713 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1714 } else if (Subtarget->isPICStyleGOT()) { 1715 OpFlag = X86II::MO_GOTOFF; 1716 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1717 } else if (Subtarget->isPICStyleRIPRel() && 1718 TM.getCodeModel() == CodeModel::Small) { 1719 PICBase = X86::RIP; 1720 } 1721 1722 // Create the load from the constant pool. 1723 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 1724 unsigned ResultReg = createResultReg(RC); 1725 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), 1726 MCPOffset, PICBase, OpFlag); 1727 1728 return ResultReg; 1729} 1730 1731unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { 1732 // Fail on dynamic allocas. At this point, getRegForValue has already 1733 // checked its CSE maps, so if we're here trying to handle a dynamic 1734 // alloca, we're not going to succeed. X86SelectAddress has a 1735 // check for dynamic allocas, because it's called directly from 1736 // various places, but TargetMaterializeAlloca also needs a check 1737 // in order to avoid recursion between getRegForValue, 1738 // X86SelectAddrss, and TargetMaterializeAlloca. 1739 if (!StaticAllocaMap.count(C)) 1740 return 0; 1741 1742 X86AddressMode AM; 1743 if (!X86SelectAddress(C, AM)) 1744 return 0; 1745 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 1746 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 1747 unsigned ResultReg = createResultReg(RC); 1748 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1749 return ResultReg; 1750} 1751 1752namespace llvm { 1753 llvm::FastISel *X86::createFastISel(MachineFunction &mf, 1754 DenseMap<const Value *, unsigned> &vm, 1755 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 1756 DenseMap<const AllocaInst *, int> &am 1757#ifndef NDEBUG 1758 , SmallSet<Instruction*, 8> &cil 1759#endif 1760 ) { 1761 return new X86FastISel(mf, vm, bm, am 1762#ifndef NDEBUG 1763 , cil 1764#endif 1765 ); 1766 } 1767} 1768