X86ISelLowering.cpp revision 910cd3cfa2286baa683180a0d888f6d3c77f9d54
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86ISelLowering.h" 17#include "X86TargetMachine.h" 18#include "llvm/CallingConv.h" 19#include "llvm/Function.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetOptions.h" 25using namespace llvm; 26 27// FIXME: temporary. 28#include "llvm/Support/CommandLine.h" 29static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, 30 cl::desc("Enable fastcc on X86")); 31 32X86TargetLowering::X86TargetLowering(TargetMachine &TM) 33 : TargetLowering(TM) { 34 // Set up the TargetLowering object. 35 36 // X86 is weird, it always uses i8 for shift amounts and setcc results. 37 setShiftAmountType(MVT::i8); 38 setSetCCResultType(MVT::i8); 39 setSetCCResultContents(ZeroOrOneSetCCResult); 40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 41 42 // Set up the register classes. 43 addRegisterClass(MVT::i8, X86::R8RegisterClass); 44 addRegisterClass(MVT::i16, X86::R16RegisterClass); 45 addRegisterClass(MVT::i32, X86::R32RegisterClass); 46 47 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 48 // operation. 49 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 50 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 51 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 52 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 53 54 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 55 // this operation. 56 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 57 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 58 59 if (!X86ScalarSSE) { 60 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64 61 // isn't legal. 62 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 63 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 64 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 65 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 66 } 67 68 // Handle FP_TO_UINT by promoting the destination to a larger signed 69 // conversion. 70 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 71 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 72 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 73 74 if (!X86ScalarSSE) 75 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 76 77 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 78 // this operation. 79 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 80 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 81 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 82 83 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 84 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 85 86 if (X86DAGIsel) { 87 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 88 } 89 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); 90 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); 91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); 93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 95 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 96 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); 97 setOperationAction(ISD::FREM , MVT::f64 , Expand); 98 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 99 setOperationAction(ISD::CTTZ , MVT::i8 , Expand); 100 setOperationAction(ISD::CTLZ , MVT::i8 , Expand); 101 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 102 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 103 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 104 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 105 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 106 setOperationAction(ISD::CTLZ , MVT::i32 , Expand); 107 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 108 109 setOperationAction(ISD::READIO , MVT::i1 , Expand); 110 setOperationAction(ISD::READIO , MVT::i8 , Expand); 111 setOperationAction(ISD::READIO , MVT::i16 , Expand); 112 setOperationAction(ISD::READIO , MVT::i32 , Expand); 113 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand); 114 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand); 115 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand); 116 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand); 117 118 // These should be promoted to a larger select which is supported. 119 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 120 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 121 if (X86DAGIsel) { 122 // X86 wants to expand cmov itself. 123 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 124 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 125 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 126 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 127 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 128 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 129 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 130 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 131 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 132 // X86 ret instruction may pop stack. 133 setOperationAction(ISD::RET , MVT::Other, Custom); 134 // Darwin ABI issue. 135 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 136 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 137 setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom); 138 setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom); 139 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 140 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 141 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 142 } 143 144 // We don't have line number support yet. 145 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 146 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 147 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 148 149 if (X86ScalarSSE) { 150 // Set up the FP register classes. 151 addRegisterClass(MVT::f32, X86::V4F4RegisterClass); 152 addRegisterClass(MVT::f64, X86::V2F8RegisterClass); 153 154 // SSE has no load+extend ops 155 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 156 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); 157 158 // SSE has no i16 to fp conversion, only i32 159 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 160 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 161 162 // Expand FP_TO_UINT into a select. 163 // FIXME: We would like to use a Custom expander here eventually to do 164 // the optimal thing for SSE vs. the default expansion in the legalizer. 165 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 166 167 // We don't support sin/cos/sqrt/fmod 168 setOperationAction(ISD::FSIN , MVT::f64, Expand); 169 setOperationAction(ISD::FCOS , MVT::f64, Expand); 170 setOperationAction(ISD::FABS , MVT::f64, Expand); 171 setOperationAction(ISD::FNEG , MVT::f64, Expand); 172 setOperationAction(ISD::FREM , MVT::f64, Expand); 173 setOperationAction(ISD::FSIN , MVT::f32, Expand); 174 setOperationAction(ISD::FCOS , MVT::f32, Expand); 175 setOperationAction(ISD::FABS , MVT::f32, Expand); 176 setOperationAction(ISD::FNEG , MVT::f32, Expand); 177 setOperationAction(ISD::FREM , MVT::f32, Expand); 178 179 addLegalFPImmediate(+0.0); // xorps / xorpd 180 } else { 181 // Set up the FP register classes. 182 addRegisterClass(MVT::f64, X86::RFPRegisterClass); 183 184 if (!UnsafeFPMath) { 185 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 186 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 187 } 188 189 addLegalFPImmediate(+0.0); // FLD0 190 addLegalFPImmediate(+1.0); // FLD1 191 addLegalFPImmediate(-0.0); // FLD0/FCHS 192 addLegalFPImmediate(-1.0); // FLD1/FCHS 193 } 194 computeRegisterProperties(); 195 196 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores 197 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores 198 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores 199 allowUnalignedMemoryAccesses = true; // x86 supports it! 200} 201 202std::vector<SDOperand> 203X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 204 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC) 205 return LowerFastCCArguments(F, DAG); 206 return LowerCCCArguments(F, DAG); 207} 208 209std::pair<SDOperand, SDOperand> 210X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 211 bool isVarArg, unsigned CallingConv, 212 bool isTailCall, 213 SDOperand Callee, ArgListTy &Args, 214 SelectionDAG &DAG) { 215 assert((!isVarArg || CallingConv == CallingConv::C) && 216 "Only C takes varargs!"); 217 218 // If the callee is a GlobalAddress node (quite common, every direct call is) 219 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 220 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 221 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 222 223 if (CallingConv == CallingConv::Fast && EnableFastCC) 224 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG); 225 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG); 226} 227 228SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 229 SelectionDAG &DAG) { 230 if (!X86DAGIsel) 231 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op); 232 233 SDOperand Copy; 234 MVT::ValueType OpVT = Op.getValueType(); 235 switch (OpVT) { 236 default: assert(0 && "Unknown type to return!"); 237 case MVT::i32: 238 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand()); 239 break; 240 case MVT::i64: { 241 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 242 DAG.getConstant(1, MVT::i32)); 243 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 244 DAG.getConstant(0, MVT::i32)); 245 Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand()); 246 Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1)); 247 break; 248 } 249 case MVT::f32: 250 case MVT::f64: 251 if (!X86ScalarSSE) { 252 if (OpVT == MVT::f32) 253 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op); 254 std::vector<MVT::ValueType> Tys; 255 Tys.push_back(MVT::Other); 256 Tys.push_back(MVT::Flag); 257 std::vector<SDOperand> Ops; 258 Ops.push_back(Chain); 259 Ops.push_back(Op); 260 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); 261 } else { 262 // Spill the value to memory and reload it into top of stack. 263 unsigned Size = MVT::getSizeInBits(OpVT)/8; 264 MachineFunction &MF = DAG.getMachineFunction(); 265 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 266 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 267 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op, 268 StackSlot, DAG.getSrcValue(NULL)); 269 std::vector<MVT::ValueType> Tys; 270 Tys.push_back(MVT::f64); 271 Tys.push_back(MVT::Other); 272 std::vector<SDOperand> Ops; 273 Ops.push_back(Chain); 274 Ops.push_back(StackSlot); 275 Ops.push_back(DAG.getValueType(OpVT)); 276 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops); 277 Tys.clear(); 278 Tys.push_back(MVT::Other); 279 Tys.push_back(MVT::Flag); 280 Ops.clear(); 281 Ops.push_back(Copy.getValue(1)); 282 Ops.push_back(Copy); 283 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); 284 } 285 break; 286 } 287 288 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, 289 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16), 290 Copy.getValue(1)); 291} 292 293//===----------------------------------------------------------------------===// 294// C Calling Convention implementation 295//===----------------------------------------------------------------------===// 296 297std::vector<SDOperand> 298X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) { 299 std::vector<SDOperand> ArgValues; 300 301 MachineFunction &MF = DAG.getMachineFunction(); 302 MachineFrameInfo *MFI = MF.getFrameInfo(); 303 304 // Add DAG nodes to load the arguments... On entry to a function on the X86, 305 // the stack frame looks like this: 306 // 307 // [ESP] -- return address 308 // [ESP + 4] -- first argument (leftmost lexically) 309 // [ESP + 8] -- second argument, if first argument is four bytes in size 310 // ... 311 // 312 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 313 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 314 MVT::ValueType ObjectVT = getValueType(I->getType()); 315 unsigned ArgIncrement = 4; 316 unsigned ObjSize; 317 switch (ObjectVT) { 318 default: assert(0 && "Unhandled argument type!"); 319 case MVT::i1: 320 case MVT::i8: ObjSize = 1; break; 321 case MVT::i16: ObjSize = 2; break; 322 case MVT::i32: ObjSize = 4; break; 323 case MVT::i64: ObjSize = ArgIncrement = 8; break; 324 case MVT::f32: ObjSize = 4; break; 325 case MVT::f64: ObjSize = ArgIncrement = 8; break; 326 } 327 // Create the frame index object for this incoming parameter... 328 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 329 330 // Create the SelectionDAG nodes corresponding to a load from this parameter 331 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 332 333 // Don't codegen dead arguments. FIXME: remove this check when we can nuke 334 // dead loads. 335 SDOperand ArgValue; 336 if (!I->use_empty()) 337 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 338 DAG.getSrcValue(NULL)); 339 else { 340 if (MVT::isInteger(ObjectVT)) 341 ArgValue = DAG.getConstant(0, ObjectVT); 342 else 343 ArgValue = DAG.getConstantFP(0, ObjectVT); 344 } 345 ArgValues.push_back(ArgValue); 346 347 ArgOffset += ArgIncrement; // Move on to the next argument... 348 } 349 350 // If the function takes variable number of arguments, make a frame index for 351 // the start of the first vararg value... for expansion of llvm.va_start. 352 if (F.isVarArg()) 353 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 354 ReturnAddrIndex = 0; // No return address slot generated yet. 355 BytesToPopOnReturn = 0; // Callee pops nothing. 356 BytesCallerReserves = ArgOffset; 357 358 // Finally, inform the code generator which regs we return values in. 359 switch (getValueType(F.getReturnType())) { 360 default: assert(0 && "Unknown type!"); 361 case MVT::isVoid: break; 362 case MVT::i1: 363 case MVT::i8: 364 case MVT::i16: 365 case MVT::i32: 366 MF.addLiveOut(X86::EAX); 367 break; 368 case MVT::i64: 369 MF.addLiveOut(X86::EAX); 370 MF.addLiveOut(X86::EDX); 371 break; 372 case MVT::f32: 373 case MVT::f64: 374 MF.addLiveOut(X86::ST0); 375 break; 376 } 377 return ArgValues; 378} 379 380std::pair<SDOperand, SDOperand> 381X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy, 382 bool isVarArg, bool isTailCall, 383 SDOperand Callee, ArgListTy &Args, 384 SelectionDAG &DAG) { 385 // Count how many bytes are to be pushed on the stack. 386 unsigned NumBytes = 0; 387 388 if (Args.empty()) { 389 // Save zero bytes. 390 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 391 DAG.getConstant(0, getPointerTy())); 392 } else { 393 for (unsigned i = 0, e = Args.size(); i != e; ++i) 394 switch (getValueType(Args[i].second)) { 395 default: assert(0 && "Unknown value type!"); 396 case MVT::i1: 397 case MVT::i8: 398 case MVT::i16: 399 case MVT::i32: 400 case MVT::f32: 401 NumBytes += 4; 402 break; 403 case MVT::i64: 404 case MVT::f64: 405 NumBytes += 8; 406 break; 407 } 408 409 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 410 DAG.getConstant(NumBytes, getPointerTy())); 411 412 // Arguments go on the stack in reverse order, as specified by the ABI. 413 unsigned ArgOffset = 0; 414 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 415 X86::ESP, MVT::i32); 416 std::vector<SDOperand> Stores; 417 418 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 419 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 420 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 421 422 switch (getValueType(Args[i].second)) { 423 default: assert(0 && "Unexpected ValueType for argument!"); 424 case MVT::i1: 425 case MVT::i8: 426 case MVT::i16: 427 // Promote the integer to 32 bits. If the input type is signed use a 428 // sign extend, otherwise use a zero extend. 429 if (Args[i].second->isSigned()) 430 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 431 else 432 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 433 434 // FALL THROUGH 435 case MVT::i32: 436 case MVT::f32: 437 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 438 Args[i].first, PtrOff, 439 DAG.getSrcValue(NULL))); 440 ArgOffset += 4; 441 break; 442 case MVT::i64: 443 case MVT::f64: 444 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 445 Args[i].first, PtrOff, 446 DAG.getSrcValue(NULL))); 447 ArgOffset += 8; 448 break; 449 } 450 } 451 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 452 } 453 454 std::vector<MVT::ValueType> RetVals; 455 MVT::ValueType RetTyVT = getValueType(RetTy); 456 RetVals.push_back(MVT::Other); 457 458 // The result values produced have to be legal. Promote the result. 459 switch (RetTyVT) { 460 case MVT::isVoid: break; 461 default: 462 RetVals.push_back(RetTyVT); 463 break; 464 case MVT::i1: 465 case MVT::i8: 466 case MVT::i16: 467 RetVals.push_back(MVT::i32); 468 break; 469 case MVT::f32: 470 if (X86ScalarSSE) 471 RetVals.push_back(MVT::f32); 472 else 473 RetVals.push_back(MVT::f64); 474 break; 475 case MVT::i64: 476 RetVals.push_back(MVT::i32); 477 RetVals.push_back(MVT::i32); 478 break; 479 } 480 481 if (X86DAGIsel) { 482 std::vector<MVT::ValueType> NodeTys; 483 NodeTys.push_back(MVT::Other); // Returns a chain 484 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 485 std::vector<SDOperand> Ops; 486 Ops.push_back(Chain); 487 Ops.push_back(Callee); 488 489 // FIXME: Do not generate X86ISD::TAILCALL for now. 490 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); 491 SDOperand InFlag = Chain.getValue(1); 492 493 SDOperand RetVal; 494 if (RetTyVT != MVT::isVoid) { 495 switch (RetTyVT) { 496 default: assert(0 && "Unknown value type to return!"); 497 case MVT::i1: 498 case MVT::i8: 499 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); 500 Chain = RetVal.getValue(1); 501 break; 502 case MVT::i16: 503 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); 504 Chain = RetVal.getValue(1); 505 break; 506 case MVT::i32: 507 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 508 Chain = RetVal.getValue(1); 509 break; 510 case MVT::i64: { 511 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 512 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, 513 Lo.getValue(2)); 514 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 515 Chain = Hi.getValue(1); 516 break; 517 } 518 case MVT::f32: 519 case MVT::f64: { 520 std::vector<MVT::ValueType> Tys; 521 Tys.push_back(MVT::f64); 522 Tys.push_back(MVT::Other); 523 std::vector<SDOperand> Ops; 524 Ops.push_back(Chain); 525 Ops.push_back(InFlag); 526 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); 527 Chain = RetVal.getValue(1); 528 if (X86ScalarSSE) { 529 unsigned Size = MVT::getSizeInBits(MVT::f64)/8; 530 MachineFunction &MF = DAG.getMachineFunction(); 531 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 532 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 533 Tys.clear(); 534 Tys.push_back(MVT::Other); 535 Ops.clear(); 536 Ops.push_back(Chain); 537 Ops.push_back(RetVal); 538 Ops.push_back(StackSlot); 539 Ops.push_back(DAG.getValueType(RetTyVT)); 540 Chain = DAG.getNode(X86ISD::FST, Tys, Ops); 541 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, 542 DAG.getSrcValue(NULL)); 543 Chain = RetVal.getValue(1); 544 } else if (RetTyVT == MVT::f32) 545 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 546 break; 547 } 548 } 549 } 550 551 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 552 DAG.getConstant(NumBytes, getPointerTy()), 553 DAG.getConstant(0, getPointerTy())); 554 return std::make_pair(RetVal, Chain); 555 } else { 556 std::vector<SDOperand> Ops; 557 Ops.push_back(Chain); 558 Ops.push_back(Callee); 559 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 560 Ops.push_back(DAG.getConstant(0, getPointerTy())); 561 562 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 563 RetVals, Ops); 564 565 SDOperand ResultVal; 566 switch (RetTyVT) { 567 case MVT::isVoid: break; 568 default: 569 ResultVal = TheCall.getValue(1); 570 break; 571 case MVT::i1: 572 case MVT::i8: 573 case MVT::i16: 574 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); 575 break; 576 case MVT::f32: 577 // FIXME: we would really like to remember that this FP_ROUND operation is 578 // okay to eliminate if we allow excess FP precision. 579 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); 580 break; 581 case MVT::i64: 582 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), 583 TheCall.getValue(2)); 584 break; 585 } 586 587 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); 588 return std::make_pair(ResultVal, Chain); 589 } 590} 591 592SDOperand 593X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, 594 Value *VAListV, SelectionDAG &DAG) { 595 // vastart just stores the address of the VarArgsFrameIndex slot. 596 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 597 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 598 DAG.getSrcValue(VAListV)); 599} 600 601 602std::pair<SDOperand,SDOperand> 603X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, 604 Value *VAListV, const Type *ArgTy, 605 SelectionDAG &DAG) { 606 MVT::ValueType ArgVT = getValueType(ArgTy); 607 SDOperand Val = DAG.getLoad(MVT::i32, Chain, 608 VAListP, DAG.getSrcValue(VAListV)); 609 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val, 610 DAG.getSrcValue(NULL)); 611 unsigned Amt; 612 if (ArgVT == MVT::i32) 613 Amt = 4; 614 else { 615 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && 616 "Other types should have been promoted for varargs!"); 617 Amt = 8; 618 } 619 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, 620 DAG.getConstant(Amt, Val.getValueType())); 621 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, 622 Val, VAListP, DAG.getSrcValue(VAListV)); 623 return std::make_pair(Result, Chain); 624} 625 626//===----------------------------------------------------------------------===// 627// Fast Calling Convention implementation 628//===----------------------------------------------------------------------===// 629// 630// The X86 'fast' calling convention passes up to two integer arguments in 631// registers (an appropriate portion of EAX/EDX), passes arguments in C order, 632// and requires that the callee pop its arguments off the stack (allowing proper 633// tail calls), and has the same return value conventions as C calling convs. 634// 635// This calling convention always arranges for the callee pop value to be 8n+4 636// bytes, which is needed for tail recursion elimination and stack alignment 637// reasons. 638// 639// Note that this can be enhanced in the future to pass fp vals in registers 640// (when we have a global fp allocator) and do other tricks. 641// 642 643/// AddLiveIn - This helper function adds the specified physical register to the 644/// MachineFunction as a live in value. It also creates a corresponding virtual 645/// register for it. 646static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 647 TargetRegisterClass *RC) { 648 assert(RC->contains(PReg) && "Not the correct regclass!"); 649 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 650 MF.addLiveIn(PReg, VReg); 651 return VReg; 652} 653 654 655std::vector<SDOperand> 656X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) { 657 std::vector<SDOperand> ArgValues; 658 659 MachineFunction &MF = DAG.getMachineFunction(); 660 MachineFrameInfo *MFI = MF.getFrameInfo(); 661 662 // Add DAG nodes to load the arguments... On entry to a function the stack 663 // frame looks like this: 664 // 665 // [ESP] -- return address 666 // [ESP + 4] -- first nonreg argument (leftmost lexically) 667 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size 668 // ... 669 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 670 671 // Keep track of the number of integer regs passed so far. This can be either 672 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 673 // used). 674 unsigned NumIntRegs = 0; 675 676 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 677 MVT::ValueType ObjectVT = getValueType(I->getType()); 678 unsigned ArgIncrement = 4; 679 unsigned ObjSize = 0; 680 SDOperand ArgValue; 681 682 switch (ObjectVT) { 683 default: assert(0 && "Unhandled argument type!"); 684 case MVT::i1: 685 case MVT::i8: 686 if (NumIntRegs < 2) { 687 if (!I->use_empty()) { 688 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, 689 X86::R8RegisterClass); 690 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8); 691 DAG.setRoot(ArgValue.getValue(1)); 692 if (ObjectVT == MVT::i1) 693 // FIXME: Should insert a assertzext here. 694 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue); 695 } 696 ++NumIntRegs; 697 break; 698 } 699 700 ObjSize = 1; 701 break; 702 case MVT::i16: 703 if (NumIntRegs < 2) { 704 if (!I->use_empty()) { 705 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, 706 X86::R16RegisterClass); 707 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16); 708 DAG.setRoot(ArgValue.getValue(1)); 709 } 710 ++NumIntRegs; 711 break; 712 } 713 ObjSize = 2; 714 break; 715 case MVT::i32: 716 if (NumIntRegs < 2) { 717 if (!I->use_empty()) { 718 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX, 719 X86::R32RegisterClass); 720 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 721 DAG.setRoot(ArgValue.getValue(1)); 722 } 723 ++NumIntRegs; 724 break; 725 } 726 ObjSize = 4; 727 break; 728 case MVT::i64: 729 if (NumIntRegs == 0) { 730 if (!I->use_empty()) { 731 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass); 732 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); 733 734 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); 735 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32); 736 DAG.setRoot(Hi.getValue(1)); 737 738 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); 739 } 740 NumIntRegs = 2; 741 break; 742 } else if (NumIntRegs == 1) { 743 if (!I->use_empty()) { 744 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); 745 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); 746 DAG.setRoot(Low.getValue(1)); 747 748 // Load the high part from memory. 749 // Create the frame index object for this incoming parameter... 750 int FI = MFI->CreateFixedObject(4, ArgOffset); 751 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 752 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 753 DAG.getSrcValue(NULL)); 754 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); 755 } 756 ArgOffset += 4; 757 NumIntRegs = 2; 758 break; 759 } 760 ObjSize = ArgIncrement = 8; 761 break; 762 case MVT::f32: ObjSize = 4; break; 763 case MVT::f64: ObjSize = ArgIncrement = 8; break; 764 } 765 766 // Don't codegen dead arguments. FIXME: remove this check when we can nuke 767 // dead loads. 768 if (ObjSize && !I->use_empty()) { 769 // Create the frame index object for this incoming parameter... 770 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 771 772 // Create the SelectionDAG nodes corresponding to a load from this 773 // parameter. 774 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 775 776 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 777 DAG.getSrcValue(NULL)); 778 } else if (ArgValue.Val == 0) { 779 if (MVT::isInteger(ObjectVT)) 780 ArgValue = DAG.getConstant(0, ObjectVT); 781 else 782 ArgValue = DAG.getConstantFP(0, ObjectVT); 783 } 784 ArgValues.push_back(ArgValue); 785 786 if (ObjSize) 787 ArgOffset += ArgIncrement; // Move on to the next argument. 788 } 789 790 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 791 // arguments and the arguments after the retaddr has been pushed are aligned. 792 if ((ArgOffset & 7) == 0) 793 ArgOffset += 4; 794 795 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 796 ReturnAddrIndex = 0; // No return address slot generated yet. 797 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. 798 BytesCallerReserves = 0; 799 800 // Finally, inform the code generator which regs we return values in. 801 switch (getValueType(F.getReturnType())) { 802 default: assert(0 && "Unknown type!"); 803 case MVT::isVoid: break; 804 case MVT::i1: 805 case MVT::i8: 806 case MVT::i16: 807 case MVT::i32: 808 MF.addLiveOut(X86::EAX); 809 break; 810 case MVT::i64: 811 MF.addLiveOut(X86::EAX); 812 MF.addLiveOut(X86::EDX); 813 break; 814 case MVT::f32: 815 case MVT::f64: 816 MF.addLiveOut(X86::ST0); 817 break; 818 } 819 return ArgValues; 820} 821 822std::pair<SDOperand, SDOperand> 823X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, 824 bool isTailCall, SDOperand Callee, 825 ArgListTy &Args, SelectionDAG &DAG) { 826 // Count how many bytes are to be pushed on the stack. 827 unsigned NumBytes = 0; 828 829 // Keep track of the number of integer regs passed so far. This can be either 830 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 831 // used). 832 unsigned NumIntRegs = 0; 833 834 for (unsigned i = 0, e = Args.size(); i != e; ++i) 835 switch (getValueType(Args[i].second)) { 836 default: assert(0 && "Unknown value type!"); 837 case MVT::i1: 838 case MVT::i8: 839 case MVT::i16: 840 case MVT::i32: 841 if (NumIntRegs < 2) { 842 ++NumIntRegs; 843 break; 844 } 845 // fall through 846 case MVT::f32: 847 NumBytes += 4; 848 break; 849 case MVT::i64: 850 if (NumIntRegs == 0) { 851 NumIntRegs = 2; 852 break; 853 } else if (NumIntRegs == 1) { 854 NumIntRegs = 2; 855 NumBytes += 4; 856 break; 857 } 858 859 // fall through 860 case MVT::f64: 861 NumBytes += 8; 862 break; 863 } 864 865 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 866 // arguments and the arguments after the retaddr has been pushed are aligned. 867 if ((NumBytes & 7) == 0) 868 NumBytes += 4; 869 870 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 871 DAG.getConstant(NumBytes, getPointerTy())); 872 873 // Arguments go on the stack in reverse order, as specified by the ABI. 874 unsigned ArgOffset = 0; 875 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 876 X86::ESP, MVT::i32); 877 NumIntRegs = 0; 878 std::vector<SDOperand> Stores; 879 std::vector<SDOperand> RegValuesToPass; 880 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 881 switch (getValueType(Args[i].second)) { 882 default: assert(0 && "Unexpected ValueType for argument!"); 883 case MVT::i1: 884 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first); 885 // Fall through. 886 case MVT::i8: 887 case MVT::i16: 888 case MVT::i32: 889 if (NumIntRegs < 2) { 890 RegValuesToPass.push_back(Args[i].first); 891 ++NumIntRegs; 892 break; 893 } 894 // Fall through 895 case MVT::f32: { 896 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 897 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 898 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 899 Args[i].first, PtrOff, 900 DAG.getSrcValue(NULL))); 901 ArgOffset += 4; 902 break; 903 } 904 case MVT::i64: 905 if (NumIntRegs < 2) { // Can pass part of it in regs? 906 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 907 Args[i].first, DAG.getConstant(1, MVT::i32)); 908 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 909 Args[i].first, DAG.getConstant(0, MVT::i32)); 910 RegValuesToPass.push_back(Lo); 911 ++NumIntRegs; 912 if (NumIntRegs < 2) { // Pass both parts in regs? 913 RegValuesToPass.push_back(Hi); 914 ++NumIntRegs; 915 } else { 916 // Pass the high part in memory. 917 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 918 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 919 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 920 Hi, PtrOff, DAG.getSrcValue(NULL))); 921 ArgOffset += 4; 922 } 923 break; 924 } 925 // Fall through 926 case MVT::f64: 927 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 928 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 929 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 930 Args[i].first, PtrOff, 931 DAG.getSrcValue(NULL))); 932 ArgOffset += 8; 933 break; 934 } 935 } 936 if (!Stores.empty()) 937 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 938 939 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 940 // arguments and the arguments after the retaddr has been pushed are aligned. 941 if ((ArgOffset & 7) == 0) 942 ArgOffset += 4; 943 944 std::vector<MVT::ValueType> RetVals; 945 MVT::ValueType RetTyVT = getValueType(RetTy); 946 947 RetVals.push_back(MVT::Other); 948 949 // The result values produced have to be legal. Promote the result. 950 switch (RetTyVT) { 951 case MVT::isVoid: break; 952 default: 953 RetVals.push_back(RetTyVT); 954 break; 955 case MVT::i1: 956 case MVT::i8: 957 case MVT::i16: 958 RetVals.push_back(MVT::i32); 959 break; 960 case MVT::f32: 961 if (X86ScalarSSE) 962 RetVals.push_back(MVT::f32); 963 else 964 RetVals.push_back(MVT::f64); 965 break; 966 case MVT::i64: 967 RetVals.push_back(MVT::i32); 968 RetVals.push_back(MVT::i32); 969 break; 970 } 971 972 if (X86DAGIsel) { 973 // Build a sequence of copy-to-reg nodes chained together with token chain 974 // and flag operands which copy the outgoing args into registers. 975 SDOperand InFlag; 976 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 977 unsigned CCReg; 978 SDOperand RegToPass = RegValuesToPass[i]; 979 switch (RegToPass.getValueType()) { 980 default: assert(0 && "Bad thing to pass in regs"); 981 case MVT::i8: 982 CCReg = (i == 0) ? X86::AL : X86::DL; 983 break; 984 case MVT::i16: 985 CCReg = (i == 0) ? X86::AX : X86::DX; 986 break; 987 case MVT::i32: 988 CCReg = (i == 0) ? X86::EAX : X86::EDX; 989 break; 990 } 991 992 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag); 993 InFlag = Chain.getValue(1); 994 } 995 996 std::vector<MVT::ValueType> NodeTys; 997 NodeTys.push_back(MVT::Other); // Returns a chain 998 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 999 std::vector<SDOperand> Ops; 1000 Ops.push_back(Chain); 1001 Ops.push_back(Callee); 1002 if (InFlag.Val) 1003 Ops.push_back(InFlag); 1004 1005 // FIXME: Do not generate X86ISD::TAILCALL for now. 1006 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); 1007 InFlag = Chain.getValue(1); 1008 1009 SDOperand RetVal; 1010 if (RetTyVT != MVT::isVoid) { 1011 switch (RetTyVT) { 1012 default: assert(0 && "Unknown value type to return!"); 1013 case MVT::i1: 1014 case MVT::i8: 1015 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); 1016 Chain = RetVal.getValue(1); 1017 break; 1018 case MVT::i16: 1019 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); 1020 Chain = RetVal.getValue(1); 1021 break; 1022 case MVT::i32: 1023 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 1024 Chain = RetVal.getValue(1); 1025 break; 1026 case MVT::i64: { 1027 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 1028 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, 1029 Lo.getValue(2)); 1030 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1031 Chain = Hi.getValue(1); 1032 break; 1033 } 1034 case MVT::f32: 1035 case MVT::f64: { 1036 std::vector<MVT::ValueType> Tys; 1037 Tys.push_back(MVT::f64); 1038 Tys.push_back(MVT::Other); 1039 std::vector<SDOperand> Ops; 1040 Ops.push_back(Chain); 1041 Ops.push_back(InFlag); 1042 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); 1043 Chain = RetVal.getValue(1); 1044 if (X86ScalarSSE) { 1045 unsigned Size = MVT::getSizeInBits(MVT::f64)/8; 1046 MachineFunction &MF = DAG.getMachineFunction(); 1047 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 1048 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1049 Tys.clear(); 1050 Tys.push_back(MVT::Other); 1051 Ops.clear(); 1052 Ops.push_back(Chain); 1053 Ops.push_back(RetVal); 1054 Ops.push_back(StackSlot); 1055 Ops.push_back(DAG.getValueType(RetTyVT)); 1056 Chain = DAG.getNode(X86ISD::FST, Tys, Ops); 1057 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, 1058 DAG.getSrcValue(NULL)); 1059 Chain = RetVal.getValue(1); 1060 } else if (RetTyVT == MVT::f32) 1061 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 1062 break; 1063 } 1064 } 1065 } 1066 1067 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1068 DAG.getConstant(ArgOffset, getPointerTy()), 1069 DAG.getConstant(ArgOffset, getPointerTy())); 1070 return std::make_pair(RetVal, Chain); 1071 } else { 1072 std::vector<SDOperand> Ops; 1073 Ops.push_back(Chain); 1074 Ops.push_back(Callee); 1075 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 1076 // Callee pops all arg values on the stack. 1077 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 1078 1079 // Pass register arguments as needed. 1080 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end()); 1081 1082 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 1083 RetVals, Ops); 1084 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); 1085 1086 SDOperand ResultVal; 1087 switch (RetTyVT) { 1088 case MVT::isVoid: break; 1089 default: 1090 ResultVal = TheCall.getValue(1); 1091 break; 1092 case MVT::i1: 1093 case MVT::i8: 1094 case MVT::i16: 1095 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); 1096 break; 1097 case MVT::f32: 1098 // FIXME: we would really like to remember that this FP_ROUND operation is 1099 // okay to eliminate if we allow excess FP precision. 1100 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); 1101 break; 1102 case MVT::i64: 1103 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), 1104 TheCall.getValue(2)); 1105 break; 1106 } 1107 1108 return std::make_pair(ResultVal, Chain); 1109 } 1110} 1111 1112SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1113 if (ReturnAddrIndex == 0) { 1114 // Set up a frame object for the return address. 1115 MachineFunction &MF = DAG.getMachineFunction(); 1116 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 1117 } 1118 1119 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32); 1120} 1121 1122 1123 1124std::pair<SDOperand, SDOperand> X86TargetLowering:: 1125LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 1126 SelectionDAG &DAG) { 1127 SDOperand Result; 1128 if (Depth) // Depths > 0 not supported yet! 1129 Result = DAG.getConstant(0, getPointerTy()); 1130 else { 1131 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 1132 if (!isFrameAddress) 1133 // Just load the return address 1134 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, 1135 DAG.getSrcValue(NULL)); 1136 else 1137 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI, 1138 DAG.getConstant(4, MVT::i32)); 1139 } 1140 return std::make_pair(Result, Chain); 1141} 1142 1143//===----------------------------------------------------------------------===// 1144// X86 Custom Lowering Hooks 1145//===----------------------------------------------------------------------===// 1146 1147/// SetCCToX86CondCode - do a one to one translation of a ISD::CondCode to 1148/// X86 specific CondCode. It returns a X86ISD::COND_INVALID if it cannot 1149/// do a direct translation. 1150static unsigned CCToX86CondCode(SDOperand CC, bool isFP) { 1151 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 1152 unsigned X86CC = X86ISD::COND_INVALID; 1153 if (!isFP) { 1154 switch (SetCCOpcode) { 1155 default: break; 1156 case ISD::SETEQ: X86CC = X86ISD::COND_E; break; 1157 case ISD::SETGT: X86CC = X86ISD::COND_G; break; 1158 case ISD::SETGE: X86CC = X86ISD::COND_GE; break; 1159 case ISD::SETLT: X86CC = X86ISD::COND_L; break; 1160 case ISD::SETLE: X86CC = X86ISD::COND_LE; break; 1161 case ISD::SETNE: X86CC = X86ISD::COND_NE; break; 1162 case ISD::SETULT: X86CC = X86ISD::COND_B; break; 1163 case ISD::SETUGT: X86CC = X86ISD::COND_A; break; 1164 case ISD::SETULE: X86CC = X86ISD::COND_BE; break; 1165 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break; 1166 } 1167 } else { 1168 // On a floating point condition, the flags are set as follows: 1169 // ZF PF CF op 1170 // 0 | 0 | 0 | X > Y 1171 // 0 | 0 | 1 | X < Y 1172 // 1 | 0 | 0 | X == Y 1173 // 1 | 1 | 1 | unordered 1174 switch (SetCCOpcode) { 1175 default: break; 1176 case ISD::SETUEQ: 1177 case ISD::SETEQ: X86CC = X86ISD::COND_E; break; 1178 case ISD::SETOGT: 1179 case ISD::SETGT: X86CC = X86ISD::COND_A; break; 1180 case ISD::SETOGE: 1181 case ISD::SETGE: X86CC = X86ISD::COND_AE; break; 1182 case ISD::SETULT: 1183 case ISD::SETLT: X86CC = X86ISD::COND_B; break; 1184 case ISD::SETULE: 1185 case ISD::SETLE: X86CC = X86ISD::COND_BE; break; 1186 case ISD::SETONE: 1187 case ISD::SETNE: X86CC = X86ISD::COND_NE; break; 1188 case ISD::SETUO: X86CC = X86ISD::COND_P; break; 1189 case ISD::SETO: X86CC = X86ISD::COND_NP; break; 1190 } 1191 } 1192 return X86CC; 1193} 1194 1195/// LowerOperation - Provide custom lowering hooks for some operations. 1196/// 1197SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1198 switch (Op.getOpcode()) { 1199 default: assert(0 && "Should not custom lower this!"); 1200 case ISD::ADD_PARTS: 1201 case ISD::SUB_PARTS: { 1202 assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 && 1203 "Not an i64 add/sub!"); 1204 bool isAdd = Op.getOpcode() == ISD::ADD_PARTS; 1205 std::vector<MVT::ValueType> Tys; 1206 Tys.push_back(MVT::i32); 1207 Tys.push_back(MVT::Flag); 1208 std::vector<SDOperand> Ops; 1209 Ops.push_back(Op.getOperand(0)); 1210 Ops.push_back(Op.getOperand(2)); 1211 SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG, 1212 Tys, Ops); 1213 SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32, 1214 Op.getOperand(1), Op.getOperand(3), 1215 Lo.getValue(1)); 1216 Tys.clear(); 1217 Tys.push_back(MVT::i32); 1218 Tys.push_back(MVT::i32); 1219 Ops.clear(); 1220 Ops.push_back(Lo); 1221 Ops.push_back(Hi); 1222 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 1223 } 1224 case ISD::SHL_PARTS: 1225 case ISD::SRA_PARTS: 1226 case ISD::SRL_PARTS: { 1227 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1228 "Not an i64 shift!"); 1229 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 1230 SDOperand ShOpLo = Op.getOperand(0); 1231 SDOperand ShOpHi = Op.getOperand(1); 1232 SDOperand ShAmt = Op.getOperand(2); 1233 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, 1234 DAG.getConstant(31, MVT::i32)) 1235 : DAG.getConstant(0, MVT::i32); 1236 1237 SDOperand Tmp2, Tmp3; 1238 if (Op.getOpcode() == ISD::SHL_PARTS) { 1239 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); 1240 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); 1241 } else { 1242 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); 1243 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt); 1244 } 1245 1246 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag, 1247 ShAmt, DAG.getConstant(32, MVT::i8)); 1248 1249 SDOperand Hi, Lo; 1250 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 1251 1252 std::vector<MVT::ValueType> Tys; 1253 Tys.push_back(MVT::i32); 1254 Tys.push_back(MVT::Flag); 1255 std::vector<SDOperand> Ops; 1256 if (Op.getOpcode() == ISD::SHL_PARTS) { 1257 Ops.push_back(Tmp2); 1258 Ops.push_back(Tmp3); 1259 Ops.push_back(CC); 1260 Ops.push_back(InFlag); 1261 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1262 InFlag = Hi.getValue(1); 1263 1264 Ops.clear(); 1265 Ops.push_back(Tmp3); 1266 Ops.push_back(Tmp1); 1267 Ops.push_back(CC); 1268 Ops.push_back(InFlag); 1269 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1270 } else { 1271 Ops.push_back(Tmp2); 1272 Ops.push_back(Tmp3); 1273 Ops.push_back(CC); 1274 Ops.push_back(InFlag); 1275 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1276 InFlag = Lo.getValue(1); 1277 1278 Ops.clear(); 1279 Ops.push_back(Tmp3); 1280 Ops.push_back(Tmp1); 1281 Ops.push_back(CC); 1282 Ops.push_back(InFlag); 1283 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1284 } 1285 1286 Tys.clear(); 1287 Tys.push_back(MVT::i32); 1288 Tys.push_back(MVT::i32); 1289 Ops.clear(); 1290 Ops.push_back(Lo); 1291 Ops.push_back(Hi); 1292 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 1293 } 1294 case ISD::SINT_TO_FP: { 1295 assert(Op.getValueType() == MVT::f64 && 1296 Op.getOperand(0).getValueType() == MVT::i64 && 1297 "Unknown SINT_TO_FP to lower!"); 1298 // We lower sint64->FP into a store to a temporary stack slot, followed by a 1299 // FILD64m node. 1300 MachineFunction &MF = DAG.getMachineFunction(); 1301 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 1302 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1303 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 1304 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL)); 1305 std::vector<MVT::ValueType> RTs; 1306 RTs.push_back(MVT::f64); 1307 RTs.push_back(MVT::Other); 1308 std::vector<SDOperand> Ops; 1309 Ops.push_back(Store); 1310 Ops.push_back(StackSlot); 1311 return DAG.getNode(X86ISD::FILD64m, RTs, Ops); 1312 } 1313 case ISD::FP_TO_SINT: { 1314 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && 1315 Op.getOperand(0).getValueType() == MVT::f64 && 1316 "Unknown FP_TO_SINT to lower!"); 1317 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 1318 // stack slot. 1319 MachineFunction &MF = DAG.getMachineFunction(); 1320 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; 1321 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 1322 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1323 1324 unsigned Opc; 1325 switch (Op.getValueType()) { 1326 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 1327 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 1328 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 1329 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 1330 } 1331 1332 // Build the FP_TO_INT*_IN_MEM 1333 std::vector<SDOperand> Ops; 1334 Ops.push_back(DAG.getEntryNode()); 1335 Ops.push_back(Op.getOperand(0)); 1336 Ops.push_back(StackSlot); 1337 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); 1338 1339 // Load the result. 1340 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, 1341 DAG.getSrcValue(NULL)); 1342 } 1343 case ISD::READCYCLECOUNTER: { 1344 std::vector<MVT::ValueType> Tys; 1345 Tys.push_back(MVT::Other); 1346 Tys.push_back(MVT::Flag); 1347 std::vector<SDOperand> Ops; 1348 Ops.push_back(Op.getOperand(0)); 1349 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops); 1350 Ops.clear(); 1351 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1))); 1352 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX, 1353 MVT::i32, Ops[0].getValue(2))); 1354 Ops.push_back(Ops[1].getValue(1)); 1355 Tys[0] = Tys[1] = MVT::i32; 1356 Tys.push_back(MVT::Other); 1357 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 1358 } 1359 case ISD::SETCC: { 1360 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 1361 SDOperand CC = Op.getOperand(2); 1362 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1363 Op.getOperand(0), Op.getOperand(1)); 1364 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 1365 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); 1366 unsigned X86CC = CCToX86CondCode(CC, isFP); 1367 if (X86CC != X86ISD::COND_INVALID) { 1368 return DAG.getNode(X86ISD::SETCC, MVT::i8, 1369 DAG.getConstant(X86CC, MVT::i8), Cond); 1370 } else { 1371 assert(isFP && "Illegal integer SetCC!"); 1372 1373 std::vector<MVT::ValueType> Tys; 1374 std::vector<SDOperand> Ops; 1375 switch (SetCCOpcode) { 1376 default: assert(false && "Illegal floating point SetCC!"); 1377 case ISD::SETOEQ: { // !PF & ZF 1378 Tys.push_back(MVT::i8); 1379 Tys.push_back(MVT::Flag); 1380 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); 1381 Ops.push_back(Cond); 1382 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1383 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1384 DAG.getConstant(X86ISD::COND_E, MVT::i8), 1385 Tmp1.getValue(1)); 1386 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 1387 } 1388 case ISD::SETOLT: { // !PF & CF 1389 Tys.push_back(MVT::i8); 1390 Tys.push_back(MVT::Flag); 1391 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); 1392 Ops.push_back(Cond); 1393 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1394 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1395 DAG.getConstant(X86ISD::COND_B, MVT::i8), 1396 Tmp1.getValue(1)); 1397 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 1398 } 1399 case ISD::SETOLE: { // !PF & (CF || ZF) 1400 Tys.push_back(MVT::i8); 1401 Tys.push_back(MVT::Flag); 1402 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); 1403 Ops.push_back(Cond); 1404 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1405 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1406 DAG.getConstant(X86ISD::COND_BE, MVT::i8), 1407 Tmp1.getValue(1)); 1408 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 1409 } 1410 case ISD::SETUGT: { // PF | (!ZF & !CF) 1411 Tys.push_back(MVT::i8); 1412 Tys.push_back(MVT::Flag); 1413 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); 1414 Ops.push_back(Cond); 1415 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1416 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1417 DAG.getConstant(X86ISD::COND_A, MVT::i8), 1418 Tmp1.getValue(1)); 1419 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 1420 } 1421 case ISD::SETUGE: { // PF | !CF 1422 Tys.push_back(MVT::i8); 1423 Tys.push_back(MVT::Flag); 1424 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); 1425 Ops.push_back(Cond); 1426 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1427 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1428 DAG.getConstant(X86ISD::COND_AE, MVT::i8), 1429 Tmp1.getValue(1)); 1430 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 1431 } 1432 case ISD::SETUNE: { // PF | !ZF 1433 Tys.push_back(MVT::i8); 1434 Tys.push_back(MVT::Flag); 1435 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); 1436 Ops.push_back(Cond); 1437 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1438 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1439 DAG.getConstant(X86ISD::COND_NE, MVT::i8), 1440 Tmp1.getValue(1)); 1441 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 1442 } 1443 } 1444 } 1445 } 1446 case ISD::SELECT: { 1447 SDOperand Cond = Op.getOperand(0); 1448 SDOperand CC; 1449 if (Cond.getOpcode() == X86ISD::SETCC) { 1450 CC = Cond.getOperand(0); 1451 Cond = Cond.getOperand(1); 1452 } else if (Cond.getOpcode() == ISD::SETCC) { 1453 CC = Cond.getOperand(2); 1454 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType()); 1455 unsigned X86CC = CCToX86CondCode(CC, isFP); 1456 CC = DAG.getConstant(X86CC, MVT::i8); 1457 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1458 Cond.getOperand(0), Cond.getOperand(1)); 1459 } else { 1460 CC = DAG.getConstant(X86ISD::COND_E, MVT::i8); 1461 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); 1462 } 1463 1464 std::vector<MVT::ValueType> Tys; 1465 Tys.push_back(Op.getValueType()); 1466 Tys.push_back(MVT::Flag); 1467 std::vector<SDOperand> Ops; 1468 Ops.push_back(Op.getOperand(1)); 1469 Ops.push_back(Op.getOperand(2)); 1470 Ops.push_back(CC); 1471 Ops.push_back(Cond); 1472 return DAG.getNode(X86ISD::CMOV, Tys, Ops); 1473 } 1474 case ISD::BRCOND: { 1475 SDOperand Cond = Op.getOperand(1); 1476 SDOperand Dest = Op.getOperand(2); 1477 SDOperand CC; 1478 // TODO: handle Cond == OR / AND / XOR 1479 if (Cond.getOpcode() == X86ISD::SETCC) { 1480 CC = Cond.getOperand(0); 1481 Cond = Cond.getOperand(1); 1482 } else if (Cond.getOpcode() == ISD::SETCC) { 1483 CC = Cond.getOperand(2); 1484 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType()); 1485 unsigned X86CC = CCToX86CondCode(CC, isFP); 1486 CC = DAG.getConstant(X86CC, MVT::i8); 1487 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1488 Cond.getOperand(0), Cond.getOperand(1)); 1489 } else { 1490 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 1491 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); 1492 } 1493 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 1494 Op.getOperand(0), Op.getOperand(2), CC, Cond); 1495 } 1496 case ISD::RET: { 1497 // Can only be return void. 1498 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0), 1499 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 1500 } 1501 case ISD::GlobalAddress: { 1502 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1503 SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy()); 1504 // For Darwin, external and weak symbols are indirect, so we want to load 1505 // the value at address GV, not the value of GV itself. This means that 1506 // the GlobalAddress must be in the base or index register of the address, 1507 // not the GV offset field. 1508 if (getTargetMachine(). 1509 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() && 1510 (GV->hasWeakLinkage() || GV->isExternal())) 1511 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), 1512 GVOp, DAG.getSrcValue(NULL)); 1513 else 1514 return GVOp; 1515 break; 1516 } 1517 } 1518} 1519 1520const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 1521 switch (Opcode) { 1522 default: return NULL; 1523 case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG"; 1524 case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG"; 1525 case X86ISD::ADC: return "X86ISD::ADC"; 1526 case X86ISD::SBB: return "X86ISD::SBB"; 1527 case X86ISD::SHLD: return "X86ISD::SHLD"; 1528 case X86ISD::SHRD: return "X86ISD::SHRD"; 1529 case X86ISD::FILD64m: return "X86ISD::FILD64m"; 1530 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 1531 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 1532 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 1533 case X86ISD::FLD: return "X86ISD::FLD"; 1534 case X86ISD::FST: return "X86ISD::FST"; 1535 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT"; 1536 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT"; 1537 case X86ISD::CALL: return "X86ISD::CALL"; 1538 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 1539 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 1540 case X86ISD::CMP: return "X86ISD::CMP"; 1541 case X86ISD::TEST: return "X86ISD::TEST"; 1542 case X86ISD::SETCC: return "X86ISD::SETCC"; 1543 case X86ISD::CMOV: return "X86ISD::CMOV"; 1544 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 1545 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 1546 } 1547} 1548 1549bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op, 1550 uint64_t Mask) const { 1551 1552 unsigned Opc = Op.getOpcode(); 1553 1554 switch (Opc) { 1555 default: 1556 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node"); 1557 break; 1558 case X86ISD::SETCC: return (Mask & 1) == 0; 1559 } 1560 1561 return false; 1562} 1563