basic-thumb-instructions.s revision 2c3f70e5d4b4f179f21ed1b2ba14674f9d65c9b0
1@ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s 2 .syntax unified 3 .globl _func 4 5@ Check that the assembler can handle the documented syntax from the ARM ARM. 6@ For complex constructs like shifter operands, check more thoroughly for them 7@ once then spot check that following instructions accept the form generally. 8@ This gives us good coverage while keeping the overall size of the test 9@ more reasonable. 10 11 12@ FIXME: Some 3-operand instructions have a 2-operand assembly syntax. 13 14_func: 15@ CHECK: _func 16 17@------------------------------------------------------------------------------ 18@ ADC (register) 19@------------------------------------------------------------------------------ 20 adcs r4, r6 21 22@ CHECK: adcs r4, r6 @ encoding: [0x74,0x41] 23 24 25@------------------------------------------------------------------------------ 26@ ADD (immediate) 27@------------------------------------------------------------------------------ 28 adds r1, r2, #3 29 adds r2, #3 30 adds r2, #8 31 32@ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c] 33@ CHECK: adds r2, r2, #3 @ encoding: [0xd2,0x1c] 34@ CHECK: adds r2, #8 @ encoding: [0x08,0x32] 35 36 37@------------------------------------------------------------------------------ 38@ ADD (register) 39@------------------------------------------------------------------------------ 40 adds r1, r2, r3 41 add r2, r8 42 43@ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18] 44@ CHECK: add r2, r8 @ encoding: [0x42,0x44] 45 46 47@------------------------------------------------------------------------------ 48@ FIXME: ADD (SP plus immediate) 49@------------------------------------------------------------------------------ 50@------------------------------------------------------------------------------ 51@ FIXME: ADD (SP plus register) 52@------------------------------------------------------------------------------ 53 54 55@------------------------------------------------------------------------------ 56@ ADR 57@------------------------------------------------------------------------------ 58 adr r2, _baz 59 60@ CHECK: adr r2, _baz @ encoding: [A,0xa2] 61 @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10 62 63 64@------------------------------------------------------------------------------ 65@ ASR (immediate) 66@------------------------------------------------------------------------------ 67 asrs r2, r3, #32 68 asrs r2, r3, #5 69 asrs r2, r3, #1 70 71@ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10] 72@ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11] 73@ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10] 74 75 76@------------------------------------------------------------------------------ 77@ ASR (register) 78@------------------------------------------------------------------------------ 79 asrs r5, r2 80 81@ CHECK: asrs r5, r2 @ encoding: [0x15,0x41] 82 83 84@------------------------------------------------------------------------------ 85@ B 86@------------------------------------------------------------------------------ 87 b _baz 88 beq _bar 89 90@ CHECK: b _baz @ encoding: [A,0xe0'A'] 91 @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br 92@ CHECK: beq _bar @ encoding: [A,0xd0] 93 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc 94 95 96@------------------------------------------------------------------------------ 97@ BICS 98@------------------------------------------------------------------------------ 99 bics r1, r6 100 101@ CHECK: bics r1, r6 @ encoding: [0xb1,0x43] 102 103 104@------------------------------------------------------------------------------ 105@ BKPT 106@------------------------------------------------------------------------------ 107 bkpt #0 108 bkpt #255 109 110@ CHECK: bkpt #0 @ encoding: [0x00,0xbe] 111@ CHECK: bkpt #255 @ encoding: [0xff,0xbe] 112 113 114@------------------------------------------------------------------------------ 115@ BL/BLX (immediate) 116@------------------------------------------------------------------------------ 117 bl _bar 118 blx _baz 119 120@ CHECK: bl _bar @ encoding: [A,0xf0'A',A,0xf8'A'] 121 @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl 122@ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xe8'A'] 123 @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx 124 125 126@------------------------------------------------------------------------------ 127@ BLX (register) 128@------------------------------------------------------------------------------ 129 blx r4 130 131@ CHECK: blx r4 @ encoding: [0xa0,0x47] 132 133 134@------------------------------------------------------------------------------ 135@ BX 136@------------------------------------------------------------------------------ 137 bx r2 138 139@ CHECK: bx r2 @ encoding: [0x10,0x47] 140 141 142@------------------------------------------------------------------------------ 143@ CMN 144@------------------------------------------------------------------------------ 145 146 cmn r5, r1 147 148@ CHECK: cmn r5, r1 @ encoding: [0xcd,0x42] 149 150 151@------------------------------------------------------------------------------ 152@ CMP 153@------------------------------------------------------------------------------ 154 cmp r6, #32 155 cmp r3, r4 156 cmp r8, r1 157 158@ CHECK: cmp r6, #32 @ encoding: [0x20,0x2e] 159@ CHECK: cmp r3, r4 @ encoding: [0xa3,0x42] 160@ CHECK: cmp r8, r1 @ encoding: [0x88,0x45] 161 162@------------------------------------------------------------------------------ 163@ EOR 164@------------------------------------------------------------------------------ 165 eors r4, r5 166 167@ CHECK: eors r4, r5 @ encoding: [0x6c,0x40] 168 169 170@------------------------------------------------------------------------------ 171@ LDM 172@------------------------------------------------------------------------------ 173 ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} 174 ldm r2!, {r1, r3, r4, r5, r7} 175 ldm r1, {r1} 176 177@ CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb] 178@ CHECK: ldm r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca] 179@ CHECK: ldm r1, {r1} @ encoding: [0x02,0xc9] 180 181 182@------------------------------------------------------------------------------ 183@ LDR (immediate) 184@------------------------------------------------------------------------------ 185 ldr r1, [r5] 186 ldr r2, [r6, #32] 187 ldr r3, [r7, #124] 188 ldr r1, [sp] 189 ldr r2, [sp, #24] 190 ldr r3, [sp, #1020] 191 192 193@ CHECK: ldr r1, [r5] @ encoding: [0x29,0x68] 194@ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a] 195@ CHECK: ldr r3, [r7, #124] @ encoding: [0xfb,0x6f] 196@ CHECK: ldr r1, [sp] @ encoding: [0x00,0x99] 197@ CHECK: ldr r2, [sp, #24] @ encoding: [0x06,0x9a] 198@ CHECK: ldr r3, [sp, #1020] @ encoding: [0xff,0x9b] 199 200 201@------------------------------------------------------------------------------ 202@ LDR (literal) 203@------------------------------------------------------------------------------ 204 ldr r1, _foo 205 206@ CHECK: ldr r1, _foo @ encoding: [A,0x49] 207 @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp 208 209 210@------------------------------------------------------------------------------ 211@ LDR (register) 212@------------------------------------------------------------------------------ 213 ldr r1, [r2, r3] 214 215@ CHECK: ldr r1, [r2, r3] @ encoding: [0xd1,0x58] 216 217 218@------------------------------------------------------------------------------ 219@ LDRB (immediate) 220@------------------------------------------------------------------------------ 221 ldrb r4, [r3] 222 ldrb r5, [r6, #0] 223 ldrb r6, [r7, #31] 224 225@ CHECK: ldrb r4, [r3] @ encoding: [0x1c,0x78] 226@ CHECK: ldrb r5, [r6] @ encoding: [0x35,0x78] 227@ CHECK: ldrb r6, [r7, #31] @ encoding: [0xfe,0x7f] 228 229 230@------------------------------------------------------------------------------ 231@ LDRB (register) 232@------------------------------------------------------------------------------ 233 ldrb r6, [r4, r5] 234 235@ CHECK: ldrb r6, [r4, r5] @ encoding: [0x66,0x5d] 236 237 238@------------------------------------------------------------------------------ 239@ LDRH (immediate) 240@------------------------------------------------------------------------------ 241 ldrh r3, [r3] 242 ldrh r4, [r6, #2] 243 ldrh r5, [r7, #62] 244 245@ CHECK: ldrh r3, [r3] @ encoding: [0x1b,0x88] 246@ CHECK: ldrh r4, [r6, #2] @ encoding: [0x74,0x88] 247@ CHECK: ldrh r5, [r7, #62] @ encoding: [0xfd,0x8f] 248 249 250@------------------------------------------------------------------------------ 251@ LDRH (register) 252@------------------------------------------------------------------------------ 253 ldrh r6, [r2, r6] 254 255@ CHECK: ldrh r6, [r2, r6] @ encoding: [0x96,0x5b] 256 257 258@------------------------------------------------------------------------------ 259@ LDRSB/LDRSH 260@------------------------------------------------------------------------------ 261 ldrsb r6, [r2, r6] 262 ldrsh r3, [r7, r1] 263 264@ CHECK: ldrsb r6, [r2, r6] @ encoding: [0x96,0x57] 265@ CHECK: ldrsh r3, [r7, r1] @ encoding: [0x7b,0x5e] 266 267 268@------------------------------------------------------------------------------ 269@ LSL (immediate) 270@------------------------------------------------------------------------------ 271 lsls r4, r5, #0 272 lsls r4, r5, #4 273 274@ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00] 275@ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01] 276 277 278@------------------------------------------------------------------------------ 279@ LSL (register) 280@------------------------------------------------------------------------------ 281 lsls r2, r6 282 283@ CHECK: lsls r2, r6 @ encoding: [0xb2,0x40] 284 285 286@------------------------------------------------------------------------------ 287@ LSR (immediate) 288@------------------------------------------------------------------------------ 289 lsrs r1, r3, #1 290 lsrs r1, r3, #32 291 292@ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08] 293@ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08] 294 295 296@------------------------------------------------------------------------------ 297@ LSR (register) 298@------------------------------------------------------------------------------ 299 lsrs r2, r6 300 301@ CHECK: lsrs r2, r6 @ encoding: [0xf2,0x40] 302 303 304@------------------------------------------------------------------------------ 305@ MOV (immediate) 306@------------------------------------------------------------------------------ 307 movs r2, #0 308 movs r2, #255 309 movs r2, #23 310 311@ CHECK: movs r2, #0 @ encoding: [0x00,0x22] 312@ CHECK: movs r2, #255 @ encoding: [0xff,0x22] 313@ CHECK: movs r2, #23 @ encoding: [0x17,0x22] 314 315 316@------------------------------------------------------------------------------ 317@ MOV (register) 318@------------------------------------------------------------------------------ 319 mov r3, r4 320 movs r1, r3 321 322@ CHECK: mov r3, r4 @ encoding: [0x23,0x46] 323@ CHECK: movs r1, r3 @ encoding: [0x19,0x00] 324 325 326@------------------------------------------------------------------------------ 327@ MUL 328@------------------------------------------------------------------------------ 329 muls r1, r2, r1 330 muls r3, r4 331 332@ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43] 333@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43] 334 335 336@------------------------------------------------------------------------------ 337@ MVN 338@------------------------------------------------------------------------------ 339 mvns r6, r3 340 341@ CHECK: mvns r6, r3 @ encoding: [0xde,0x43] 342 343 344@------------------------------------------------------------------------------ 345@ NEG 346@------------------------------------------------------------------------------ 347 negs r3, r4 348 349@ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42] 350