| 0c2dc522d0e120f346cf0a40c8cf0c93346131c2 |
|
03-Jul-2012 |
Dong-Yuan Chen <dong-yuan.chen@intel.com> |
[X86] X86 trace JIT compiler support
This patch provides a fully functional x86 trace JIT compiler for Dalvik
VM. It is built on top of the existing x86 fast interpreter
with bug fixes and needed extension to support trace JIT interface. The
x86 trace JIT code generator was developed independent of the existing
template-based code generator and thus does not share exactly the same
infrastructure. Included in this patch are:
* Deprecated and removed the x86-atom fast interpreter that is no
longer functional since ICS.
* Augmented x86 fast interpreter to provide interfaces for x86 trace JIT
compiler.
* Added x86 trace JIT code generator with full JDWP debugging support.
* Method JIT and self-verification mode are not supported.
The x86 code generator uses the x86 instruction encoder/decoder library
from the Apache Harmony project. Additional wrapper extension and bug
fixes were added to support the x86 trace JIT code generator. The x86
instruction encoder/decoder is embedded inside the x86 code generator
under the libenc subdirectory.
Change-Id: I241113681963a16c13a3562390813cbaaa6eedf0
Signed-off-by: Dong-Yuan Chen <dong-yuan.chen@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Johnnie Birch <johnnie.l.birch.jr@intel.com>
Signed-off-by: Udayan <udayan.banerji@intel.com>
Signed-off-by: Sushma Kyasaralli Thimmappa <sushma.kyasaralli.thimmappa@intel.com>
Signed-off-by: Bijoy Jose <bijoy.a.jose@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Tim Hartley <timothy.d.hartley@intel.com>
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| 9a3147c7412f4794434b4c2604aa2ba784867774 |
|
03-Mar-2011 |
buzbee <buzbee@google.com> |
Interpreter restructuring
This is a restructuring of the Dalvik ARM and x86 interpreters:
o Combine the old portstd and portdbg interpreters into a single
portable interpreter.
o Add debug/profiling support to the fast (mterp) interpreters.
o Delete old mechansim of switching between interpreters. Now, once
you choose an interpreter at startup, you stick with it.
o Allow JIT to co-exist with profiling & debugging (necessary for
first-class support of debugging with the JIT active).
o Adds single-step capability to the fast assembly interpreters without
slowing them down (and, in fact, measurably improves their performance).
o Remove old "polling for safe point" mechanism. Breakouts now achieved
via modifying base of interpreter handler table.
o Simplify interpeter control mechanism.
o Allow thread-granularity control for profiling & debugging
The primary motivation behind this change was to improve the responsiveness
of debugging and profiling and to make it easier to add new debugging and
profiling capabilities in the future. Instead of always bailing out to the
slow debug portable interpreter, we can now stay in the fast interpreter.
A nice side effect of the change is that the fast interpreters
got a healthy speed boost because we were able to replace the
polling safepoint check that involved a dozen or so instructions
with a single table-base reload. When combined with the two earlier CLs
related to this restructuring, we show a 5.6% performance improvement
using libdvm_interp.so on the Checkers benchmark relative to Honeycomb.
Change-Id: I8d37e866b3618def4e582fc73f1cf69ffe428f3c
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| f3e177289ac078f18401cfd8eebafe584dd0d01f |
|
12-Sep-2010 |
buzbee <buzbee@google.com> |
x86 mterp: reduce x86/x86-atom differences
To ease future x86 development, elminate unnecessary differences
between x86 and x86-atom targets.
1. Macros instead of defines (cosmetic change)
2. Register naming convention (cosmetic change)
3. Register usage convention
- Drop rIBASE, freeing %edx for general usage
- use %edi for rPC (callee-save) & eliminate spills
4. Spill & temp frame layout
5. rGLUE usage 0(%ebp) instead of -24(%ebp)
6. Jump table transition between instruction interpretations
instead of computed goto.
7. Change entry convention for instruction handlers:
Previously:
%bl contains 8-bit Dalvik opcode
%bh contains 2nd half of 16-bit Dalvik insn (usually AA or BA)
upper 16 bits of %ebx are zero
Now:
%bl contains 2nd half of 16-bit Dalvik insn (usually AA or BA)
upper 24 bits of %ebx are zero
8. Include copies of x86-atom macros and defines into x86 build. This
allows the x86 build to mix-and-match x86 and x86-atom handlers
via the normal config mechanism. [Note - only for non-control-flow
instructions. There are still some conflicts in the footer.S
main loop re-entry points].
Change-Id: Ib9d549b56f7ffd7420f9dbf97b2169f65603ee83
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| f6c387128427e121477c1b32ad35cdcaa5101ba3 |
|
04-Mar-2009 |
The Android Open Source Project <initial-contribution@android.com> |
auto import from //depot/cupcake/@135843
|
| f72d5de56a522ac3be03873bdde26f23a5eeeb3c |
|
04-Mar-2009 |
The Android Open Source Project <initial-contribution@android.com> |
auto import from //depot/cupcake/@135843
|
| 89c1feb0a69a7707b271086e749975b3f7acacf7 |
|
18-Dec-2008 |
The Android Open Source Project <initial-contribution@android.com> |
Code drop from //branches/cupcake/...@124589
|