| f2c64ef519b38a4328809b27b4a3a8e0c26e9709 |
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17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MCID::Select flag and TII hooks for optimizing selects.
Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.
Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 39bdc5526f9bb4985c5ea7711e603bb44707ed42 |
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11-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Shrink and reorder some fields in MCOperandInfo to fit it in 8 bytes to reduce size of static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| fac259814923d091942b230e7bd002a8d1130bc3 |
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08-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| c667ba69ac342563c0886e20509e68705d78a0a5 |
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10-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.
Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 133f9d989485376ce8ad0d6c61ba12e913fa6366 |
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09-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per entry on x86_64.
No change on i386.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
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07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 7c2a4a30e0e16762c75adacebd05ec9fcbccf16b |
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06-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| c291e2f5780c3a8470113a2a58c1fa680cd54b20 |
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25-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add target hook for pseudo instruction expansion.
Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 83a8031336a1155e6b0c3e9a84164324e08d1c8b |
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20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 4815d56bb2c356a610f46753c5f1cefafa113b21 |
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20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 37fefc20d3a1e3934a377567d54a141f67752227 |
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30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| f8e1e3e729473b8b2b7ee6134b6417976af84d05 |
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30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 7e0d22cbf7b41e93279f574c9b3c557cdf517dcb |
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29-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 0ba45d4fb3e11d8085b01008e31477bece20d01d |
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16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 5196c12e9fdec9ef3c63d96cb529c1c1cb732773 |
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14-Jul-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add a new field to MCOperandInfo that contains information about the type of the Operand.
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 16884415db751c75f2133bd04921393c792b1158 |
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14-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| 22fee2dff4c43b551aefa44a96ca74fcade6bfac |
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28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
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| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
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28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/include/llvm/MC/MCInstrDesc.h
|