| 1525260b3e50cc578939ef41b60609689eecfdd2 |
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06-Jun-2012 |
Andrew Trick <atrick@apple.com> |
Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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| b6632ba380cf624e60fe16b03d6e21b05dd07724 |
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04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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| dd5a8471526ceadf9bceb1a1221299b3db49c33a |
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17-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename TRI::getAllocationOrder() to getRawAllocationOrder().
Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.
The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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| a46a100945c839a9b9baa6da0dcafafcd42d1085 |
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06-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Get allocation orders from RegisterClassInfo when possible.
Only target-dependent hints require callbacks. The RCI allocation order
has CSR aliases last according to their order of appearance in the
getCalleeSavedRegs list. This can depend on the calling convention.
This way, AllocationOrder::next doesn't have to check for reserved
registers, and CSRs are always allocated last, even with weird calling
conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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| 5f2316a3b55f88dab2190212210770180a32aa95 |
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03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers.
Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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| c9df025e33ac435adb3b3318d237c36ca7cec659 |
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10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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| dd479e9769eceee9fcc34e2173376024f3aa3c5f |
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10-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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| c9672cb8bea13fcbcbdb1cf26708d831c034c089 |
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10-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an AllocationOrder class that can iterate over the allocatable physical
registers for a given virtual register.
Reserved registers are filtered from the allocation order, and any valid hint is
returned as the first suggestion.
For target dependent hints, a number of arcane target hooks are invoked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/AllocationOrder.cpp
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