| fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 1fb27eccf5b7eabde9678d84411eb1df8a693683 |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 7e99a60857532ca2973cf9dabc790d84a2e15a8a |
|
18-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Define generic HINT instruction.
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.
rdar://11600518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| f49a4092bcf679d1634a8023efc593e98a3e5663 |
|
16-Jun-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe |
|
18-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| ca3cd419a52c1dedee133d79772ef97f30e5d20b |
|
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 4d2f077df1b46a126b5595d983f233ec896b757e |
|
27-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 6c22695c6d10036f5635caec7ea84dbe84cc6bea |
|
13-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
For ARM disassembly only print 32 unsigned bits for the address of branch
targets so if the branch target has the high bit set it does not get printed as:
beq 0xffffffff8008c404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| c97ef618d2d849a272a353c2b4343fc5902cd921 |
|
02-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
All implementations used the same code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 7c0b3c1fb6395475e262d66ee403645f0c67dee2 |
|
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 17463b3ef1a3d39b10619254f12e806c8c43f9e7 |
|
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 4d0983a4d734280d481bb56472fe44ad0ddc447d |
|
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| c0fc450f0754508871bc70f21e528bf2f1520da1 |
|
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| bde1b2a5a8cef66f67513c9f4309b7fae798c679 |
|
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Kill some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| c3384c93c0e4c50da4ad093f08997507f9281c75 |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM Refactor VLD/VST spaced pair instructions.
Use the new composite physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 28f08c93e75d291695ea89b9004145103292e85b |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor away a bunch of VLD/VST pseudo instructions.
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| c6449b636f4984be88f128d0375c056ad05e7e8f |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Make MCRegisterInfo available to the the MCInstPrinter.
Used to allow context sensitive printing of super-register or sub-register
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b0578512c79134136e8b53c62a8677ab8e600be2 |
|
01-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
runs into the undefined 15 condition code value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b0934ab7d811e23bf530371976b8b35f3242169c |
|
19-Feb-2012 |
Ahmed Charles <ace2001ac@gmail.com> |
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| bc2198133a1836598b54b943420748e75d5dea94 |
|
07-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| a57a36abe7d0b769a495ed886246db157aff4add |
|
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 5e59f7e15ed3770b32481cd72d2c15b159e991e6 |
|
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 8abe7e33641fccfa70a7e335939e83dfbf654fe8 |
|
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| c387fc66bd52e4276fdc2704a3aaed57cc1f9a11 |
|
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 4050bc4cab61f8d3c7583a9b60f17c7da47bbf69 |
|
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 3471d4fbbd50eabb12511b711cbd2afd7bb9d962 |
|
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 2f196747f15240691bd4e622f7995edfedf90f61 |
|
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| e90ac9bce9aa6de288568df9bf6133c08534ae2f |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 13af222bab6fdc77d8193eb38e78a9cbed1d9d1f |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 two register all lanes, no writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 98b05a57b67d1968381563c8cccbbb6c6cb65e3d |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing aliases for VLD1 single register all lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 70be28a5adba5bcae0c6dcd63f17592864c351fc |
|
07-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 81550dc0a866e27a1efbc5de616fb366ebb547cd |
|
02-Nov-2011 |
Owen Anderson <resistor@mac.com> |
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 293a5f69fad6053a328bf454e3f28d724d989231 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 862019c37f5b5d76e34eeb0d5686e617d544059f |
|
19-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VTBL (one register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 01208d56e8341c17bb7dbeaf6c081fdffe523786 |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| bc9c80240bc922cffb02cae390181bf42ad231e5 |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 460a90540b045c102012da2492999557e6840526 |
|
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 2dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31 |
|
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 9e5887b17e634b98f7c1cf0ee4f25c218097d08e |
|
05-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 4ebbf7b8a8e80532bd2ddf7209e62689c1698a96 |
|
30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| acad68da50581de905a994ed3c6b9c197bcea687 |
|
28-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 0781c1f700886f94f5430380a5e82d7ccf6bbdc0 |
|
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 61268701931d747fa95e0be8a368101e7f97b83c |
|
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| e1368729700f1a51ee5cf33431df985e232bcc68 |
|
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 519020adf1cf57e2e93cc4fd49c385c47f7ff0f7 |
|
21-Sep-2011 |
Owen Anderson <resistor@mac.com> |
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 317eaf19937813d630166bfec7b933a98ea89aa5 |
|
21-Sep-2011 |
Owen Anderson <resistor@mac.com> |
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 7f739bee261debdf56bd89ac922b57eca53e91dc |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 705b48ff860e7484f0adee88362dbe1936ae936b |
|
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 98c5ddabca1debf935a07d14d0cbc9732374bdb8 |
|
16-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| ede042dc8d59ff48a48ef8e2271f2a7ee8324ba5 |
|
15-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 7782a58b87923cc293d4e4422729ac0a582bb5c1 |
|
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b950585cc5a0d665e9accfe5ce490cd269756f2e |
|
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 0da10cf44d0f22111dae728bb535ade2283d976b |
|
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| df9ce6bbc5b66c3c4d30c2f32b6f17c690cfa004 |
|
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
rdar://10015134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| cefe4c9c483d8a50ff13f36881090ab44ec67f13 |
|
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 0780b6303b99441fef04340b7a083006484f4743 |
|
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 93b3eff62322803a520e183fdc294bffd6d99bfa |
|
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 2f815c0b50acc506a7bdcdfb63966c40a0d2e71b |
|
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove extraneous newline from operand print method. PR10569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 70939ee1415722d7f39f13faf9b3644b96007996 |
|
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 3dac0bec7e7874ffb378385b6160bd2117184ca9 |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| f6713916fb4504aab617f0e317689acd878cc37f |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| f8fce711e8b756adca63044f7d122648c960ab96 |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 16578b50889329eb62774148091ba0f38b681a09 |
|
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| ca8c70b9536bf351ee92395dae6f99a59c011a3d |
|
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM use a dedicated printer for postidx_reg operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 154c41dbbc06284efd56782a8bc137a25148918e |
|
04-Aug-2011 |
Owen Anderson <resistor@mac.com> |
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
|
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 45f3929ef0dcdf281a10f23e031ffaba7664e7c0 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 85bfd3b023d4d70936006eadd86588b03e5f40c0 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| f49433523e8a39db6d83503e312ae55160eed90a |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9f |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| be74029f44c32efc09274a16cbff588ad10dc5ea |
|
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARM mc routines into MCTargetDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 4a5ffb399f841783c201c599b88d576757f1922e |
|
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 152d4a4bb6b75de740b4b8a9f48abb9069d50c17 |
|
22-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| ee04a6d3a40c3017124e3fd89a0db473a2824498 |
|
21-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| dde038af59506c631ce181aff66e315a0c477f4d |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b29b4dd988c50d5c4a15cd196e7910bf46f30b83 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 565a0366974d82c3efe8a31e0ecc0609c67cad3e |
|
19-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135442 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| e8606dc7c878d4562da5e3e5609b9d7d734d498c |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 589130fac11bc8c186736161600575c3ed6acc5b |
|
11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| cde4ce411b1ace4a80ea1dd38df97e8508aed0c9 |
|
02-Jun-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't hardcode the %reg format in the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 12bb2958c4f335e79c831136d2dfed9f375f06ff |
|
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| ac79e4c82f201c30a06c2cd05baebd20f5b49888 |
|
04-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| ae0855401b8c80f96904b6808b0bc4c89216aecd |
|
01-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b41aaab5a1769f4df04d566da37866ac91b6ee9e |
|
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert r128632 again, until I figure out what break the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| bcd3a9cd84d3bb143075d31bdf631f621f44f9e7 |
|
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r128585 without generating a lib depedency cycle. An updated log:
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| e4345c9977e65b14fa4b93d19c7e67a7b15f7f40 |
|
31-Mar-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 40829ed6f5e449fa33a9cd7022ce6c3941dace3d |
|
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
|
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| e2189144d45be78a89f0daf3df3cf12e38221d86 |
|
14-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove some dead patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| 57caad7a33ff145b71545f10dcfbbf2fd0f595d3 |
|
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 584bf7bb03e4cf1475b26851edcc1ddb66b85028 |
|
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
|
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 971b83b67a9812556cdb97bb58aa96fb37af458d |
|
08-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 8cb415e4c0032300a1b728c942f8b31acec0a9f5 |
|
26-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Add support for printing out floating point values from the ARM assembly
parser. The parser will always give us a binary representation of the floating
point number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 0f4db7efa1aa901d798df95f16d8361450b69fe1 |
|
25-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert 124230. It was causing test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| 261b9c1a35e1c2ef7e4cc387443dd8544d8b48de |
|
25-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
The floating point value is encoded in its binary form as an Imm. Convert it
appropriately so that it prints out the decimal representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| e4e5e2aae7e1e0e84877061432e7b981a360a77d |
|
13-Jan-2011 |
Owen Anderson <resistor@mac.com> |
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.
With this, we can properly pretty-print and encode assembly like:
mrc p15, #0, r3, c13, c0, #3
Fixes <rdar://problem/8857858>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| f4caf69720d807573c50d41aa06bcec1c99bdbbd |
|
14-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| eb6779c5b98383e33542207f062102e79263df16 |
|
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 41ad0c4c730bdbd4ec3a03868b81a56b6b1b01a1 |
|
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
32-bit wide version by adding the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 5ca66696e734f963b613de51e3df3684395daf1c |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
instructions. This simplifies instruction printing and disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| d092a87ba3f905a6801a0bdf816267329cf0391c |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 73fe34a3ee866867d5028f4a9afa2c3b8efebcba |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 04863d06fb3f2972355c990b29edcab1d9a85b41 |
|
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Minor cleanups:
- Get the opcode once.
- Add a ParserMatchClass to reglist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 11c11f8ab0e97150998db2a44cec9d334b0bd154 |
|
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| 92b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4 |
|
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 2915eb44301f1943df870efe37c424a6e8bdacfe |
|
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 0a2287b909634991a8e8aa7a93f81f09375227b1 |
|
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove the no longer used 'Modifier' optional operand to the ARM
printOperand() asm printer helper functions. rdar://8425198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| 496e2b2908820348163e2271708c40e8e398315c |
|
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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| e6913600c723a10ab1f06a43c93d82ee8e26c71c |
|
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 6274ec48b3a3e1fbaf3a359868d53a76f20a4245 |
|
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| ab682a2090f795d0b67f29889622da0a74cd97c3 |
|
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 77aee8e22c36257716c2df2f275724765704f20c |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 3e5561247202bae994dd259a2d8dc4eff8f799f3 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 458f2dc5d1b0120bd5921582eb1149ea770568bd |
|
25-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
imm12 operands aren't Thumb2 only, so rename the printer helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| b3af5de2d97c30355b8109e149326b0664d34085 |
|
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 1d6111c5ac97c321782637b2cd72e2c3e4d3d694 |
|
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 35636281c7ab6eb128b4ced6bf7ae0b6b8458dd2 |
|
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
"lane" operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|
| 7ac1609a3b81504d269bf967060241c309771f23 |
|
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename the AsmPrinter directory to InstPrinter for those targets that have
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
|