| 75dc33a60b65bbbf2253b0b916df1d36a4da4237 |
|
18-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 1f7a1b68a07ea6bdf521525a7928f4a8c5216713 |
|
26-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add GATHER intrinsics (AVX2) in LLVM
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 6f36fa981a59461466e12e5056ba209d289b81b1 |
|
11-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.
Patch by Sean Silva!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| e546c4c9c3004274c8e275e8303ca078b794bf28 |
|
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 769bbfd951018f9b36f3d2f0d70a23d81f2d3287 |
|
03-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 5b2f9136644c58ae32e00d8317540692a697d1c9 |
|
28-Mar-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Spill DPair registers, not just QPR.
The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.
This fixes PR12389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 4d0983a4d734280d481bb56472fe44ad0ddc447d |
|
07-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM more NEON VLD/VST composite physical register refactoring.
Register pair, all lanes subscripting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| c0fc450f0754508871bc70f21e528bf2f1520da1 |
|
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| c3384c93c0e4c50da4ad093f08997507f9281c75 |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM Refactor VLD/VST spaced pair instructions.
Use the new composite physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 28f08c93e75d291695ea89b9004145103292e85b |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor away a bunch of VLD/VST pseudo instructions.
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 9e3d0b335111b2df73984a6cfd9ef1cd5d323872 |
|
18-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 88b6fc06db667bd26d6ef661597affaa6abfdd0d |
|
11-Feb-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make the EDis tables const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 4050bc4cab61f8d3c7583a9b60f17c7da47bbf69 |
|
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 3471d4fbbd50eabb12511b711cbd2afd7bb9d962 |
|
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 3b8991cc98a469cbf8d9fa2a2ad971f46b8b6fd2 |
|
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: NEON SHLL instruction immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 587f5062b9e4532c4f464942e593cb87c58ac153 |
|
03-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VEXT aliases for data type suffices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 13af222bab6fdc77d8193eb38e78a9cbed1d9d1f |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing for VLD1 two register all lanes, no writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| d4578a4f8d61b5ca0f686b14a5d734eb97694fcf |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
llvm_unreachable() is not for user diagnostics....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 98b05a57b67d1968381563c8cccbbb6c6cb65e3d |
|
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing aliases for VLD1 single register all lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| eaa192af18677c4dc5894e049514d8a6b1d6d7c2 |
|
15-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 4661d4cac3ba7f480a91d0ccd35fb2d22d9692d3 |
|
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 862019c37f5b5d76e34eeb0d5686e617d544059f |
|
19-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VTBL (one register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| f2f5bc60f61acf0490d856ddd09e461bf93c5459 |
|
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV.i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 6248a546f23e7ffa84c171dc364b922e28467275 |
|
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| ea46110f57b293844a314aec3b8092adf21ff63f |
|
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 0e387b2877e4eebeedfcb26b08253f9c1b946035 |
|
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 819a2abc72e9e27d105ebc085aac09c6029db4a6 |
|
10-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit full ED initializers even for pseudo-instructions.
This should unbreak the picky buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| a0ed0c0fcdd8b94f741f296a67669da3180fb42c |
|
10-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Insert dummy ED table entries for pseudo-instructions.
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 460a90540b045c102012da2492999557e6840526 |
|
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 7ea16b01fad5236cc132cb5fc3e443fcbf70d3b8 |
|
06-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 7c788888872233748da10a8177a9a1eb176c1bc8 |
|
01-Oct-2011 |
Peter Collingbourne <peter@pcc.me.uk> |
Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 0afa0094afdfe589f407feb76948f273b414b278 |
|
26-Sep-2011 |
Owen Anderson <resistor@mac.com> |
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 7f739bee261debdf56bd89ac922b57eca53e91dc |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| f0eee6eca8c39b11b6a41d9b04eba8985655df77 |
|
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| a8307dd1c9279cbde1f3497e530d2ed9d014a0c5 |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDR(immediate).
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| f1eab597b2316c6cfcabfcee98895fedb2071722 |
|
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 72f39f8436848885176943b0ba985a7171145423 |
|
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 5b81584f7403ffdb9cc6babaaeb0411c080e0f81 |
|
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 51c9805c4bcca635bc6a854e4a246ebd4258f512 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 6d74631062e4464326eb5c680a4d62d340fa42eb |
|
08-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 154c41dbbc06284efd56782a8bc137a25148918e |
|
04-Aug-2011 |
Owen Anderson <resistor@mac.com> |
LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
|
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| e39389a58d54208fe005aba1709c601ef78b3ec1 |
|
02-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| c37d4bbf1f33c5e4b1c2f1bf1a6e2cae2ae5603a |
|
28-Jul-2011 |
Kevin Enderby <enderby@apple.com> |
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 793e79601f0fd68ba082fa2016018f80b2379460 |
|
26-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| ed8384806e56952c44f8a717c1ef54a8468d2c8d |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| f49433523e8a39db6d83503e312ae55160eed90a |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 4a5ffb399f841783c201c599b88d576757f1922e |
|
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 152d4a4bb6b75de740b4b8a9f48abb9069d50c17 |
|
22-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 92a202213bb4c20301abf6ab64e46df3695e60bf |
|
21-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| dde038af59506c631ce181aff66e315a0c477f4d |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| ffa3225e26cc1977d20f0d9649fcd6f38a3c4815 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 83ab070fc1fbb02ca77b0a37e6ae0eacf58001e1 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 619e0d6d95879a08ede97c171e1c8712554c7951 |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 7ae0df41422193e65231a0f9526bfe66067c6532 |
|
11-Jul-2011 |
Shantonu Sen <ssen@apple.com> |
Resynchronize EDInfo.h and EDEmitter.cpp.
The enum names as well as order (i.e. value)
had skewed, which means that consumers of the
tablegen-ed table would see different values than
intended. Make both files have a superset of enums,
and add classification as needed for numMCOperands.
Reviewed by Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 806fcc040e0bc7962891f12d6e09fc86f0bc2184 |
|
06-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 6b8f1e35eacba34a11e2a7d5f614efc47b43d2e3 |
|
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 895c1e2deea3e6118b159c26b3f86d40a37e8501 |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 183c627d89be5d0e8f3255ab7f6d1204c2fabedf |
|
09-May-2011 |
Mon P Wang <wangmp@apple.com> |
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| ddcdcc88631c6bd4ad43d9198b98bc9a829be036 |
|
23-Apr-2011 |
Jay Foad <jay.foad@gmail.com> |
Remove unused STL header includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
|
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| c9bd496aa206746d0bc114d15781650a5b543296 |
|
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 PC-relative loads require a fixup rather than just an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 3116dce33840a115130c5f8ffcb9679d023496d6 |
|
08-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| a656b63ee4d5b0e3f4d26a55dd4cc69795746684 |
|
01-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Narrow right shifts need to encode their immediates differently from a normal
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
|
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 685c350ae76b588e1f00c01a511fe8bd57f18394 |
|
04-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 36c3bc431b92f1573b3f3bd75b644774681998ee |
|
26-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
TableGen: PointerLikeRegClass can be accepted to operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124271 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| a461d4222877f43588da38c466145f38dd74e229 |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing and encoding ARM's official syntax for the BFI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| e4e5e2aae7e1e0e84877061432e7b981a360a77d |
|
13-Jan-2011 |
Owen Anderson <resistor@mac.com> |
Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.
With this, we can properly pretty-print and encode assembly like:
mrc p15, #0, r3, c13, c0, #3
Fixes <rdar://problem/8857858>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 7597212abced110723f2fee985a7d60557c092ec |
|
13-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| d40963c4065432ec7e47879d3ca665a54ee903b6 |
|
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| f4caf69720d807573c50d41aa06bcec1c99bdbbd |
|
14-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| a838a25d59838adfa91463f6a918ae3adeb352c1 |
|
14-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
process cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 6b8719fd7dc527e4c1910ae49ebee61d90907c08 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Revert r121721, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| e8d02539d7981c07d301d91a6a5b6ad34099b510 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| c266600bec4b5ba0ee93ffdfeaafcab8f1295145 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 67db883487fca3472fdde51e931657e22d4d0495 |
|
13-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
eliminate the Records global variable, patch by Garrison Venn!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| e246717c3a36a913fd4200776ed621649bb2b624 |
|
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb unconditional branch binary encoding. rdar://8754994
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 01086451393ef33e82b6fad623989dd97dd70edf |
|
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb conditional branch binary encodings. rdar://8745367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| cf6220a9de15d8a2a431f2672ebab3ffb0048c78 |
|
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb needs a few different encoding schemes for branch targets. Rename
t_brtarget to be more specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 09aa3f0ef35d9241c92439d74b8d5e9a81d814c2 |
|
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
The BLX instruction is encoded differently than the BL, because why not? In
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| dff2f7151f695b86db8c4b0c6604463bdb8a63ea |
|
09-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Support the "target" encodings for the CB[N]Z instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| b8958b031ec5163261f490f131780c5dc3d823d6 |
|
08-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for loading from a constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 662a816e89a9d77bf75e1328b09cf9235b4682aa |
|
07-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add fixup for Thumb1 BL/BLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 5d14f9be7ba64162c7b996f36d419b11d8cdbe9a |
|
01-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 80dd3e06129e2b570cbd65cba850571981df693a |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 0e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609 |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add encoding support for Thumb2 PLD and PLI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 8e0c7b52877983b4838e54e233449912fc1a2325 |
|
30-Nov-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix the encoding of VLD4-dup alignment.
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 837caa9313e1f9480721f232f89f5c7b1b9c9d09 |
|
19-Nov-2010 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 0f6307561359fac4425a0b9e512931cf96c1ec5b |
|
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| d1d5a39cada320949353e8b2c59b6a160a67f7bf |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM fixup encoding for direct call instructions (BL).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| e6913600c723a10ab1f06a43c93d82ee8e26c71c |
|
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| c240bb0ede0541426254d0e0dc81d891beda4b22 |
|
01-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| f40deed62f4f0126459ed7bfd1799f4e09b1aaa7 |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Shifter ops are not always free. Do not fold them (especially to form
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 498ec20703c89d0c2890b0967791f0f5f2b59a2f |
|
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 3e5561247202bae994dd259a2d8dc4eff8f799f3 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 8abe32af38b66bf4577526b23b6af6ec7eb6c155 |
|
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for UBFX and SBFX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| b3af5de2d97c30355b8109e149326b0664d34085 |
|
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| b35ad41fef5d1edd9495f708fb7eae1a0a94ef9d |
|
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 519c893c2682a597049f958b2842e34c456b0434 |
|
12-Oct-2010 |
Cameron Esfahani <dirty@apple.com> |
Fix spelling error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 9c3aa4d4cd8227858fbb4b84c6ea88ff9da2ba99 |
|
05-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 373c458850a963ab062046529337fe976e1f944d |
|
09-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix bugs in push/pop segment support, rdar://8407242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 8861e275d0947a0a3cdf7722feaee2fd02058ad0 |
|
01-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 22f5dc79c05d69391b17e14ed912aa8e98a63027 |
|
16-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename sat_shift operand to shift_imm, in preparation for using it for other
instructions besides saturate instructions. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 1adc40cac314b0a77b790b094bca146a3a868452 |
|
12-Aug-2010 |
Johnny Chen <johnny.chen@apple.com> |
Cleaned up the for-disassembly-only entries in the arm instruction table so that
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| eaf1c98a7c38444d41d1c6dc2074736eec7d452f |
|
12-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 6ccfc507dc1f7ad8c8964193a2407264ca644f0d |
|
30-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 444e2f530e8ee74a4628e68f6f33f079f83ed2b2 |
|
20-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
remove option from tablegen for building static header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 94143ee6254944a26adba2200037328c2c8ef289 |
|
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| e86b01c153ba52307ecb6e7513ec33f57caedfdd |
|
09-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 9fc05227a2596c545b845ed9a72673995e49d16b |
|
08-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 50b9efc2a852bab753948a35e6615ace3100c9da |
|
23-Jun-2010 |
Nico Weber <nicolasweber@gmx.de> |
Add support for the x86 instructions "pusha" and "popa".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 6470a116f17b70aba0c2e7ee751551a5ac9797f6 |
|
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 1a913ed17875d1a0fb490e1266b74c057c76a94b |
|
11-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add instruction encoding for the Neon VMOV immediate instruction. This changes
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 22c687b6421d9cc03351ddb0c7fd3d45382bc01a |
|
14-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 1a8b789a4b8290d263c1c75411788ca45bae3230 |
|
06-May-2010 |
Sean Callanan <scallanan@apple.com> |
Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| b63387afc6b10e88631d1ef232c41ab6c18c8581 |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| a0f914b6c1fa9708d9b2d2712930430de4f1afac |
|
24-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixes to edis that mark x86 call targets as
memory operands rather than immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| be10811323f1cc5386abe6d99d36653a5b1f729d |
|
14-Apr-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
EDis: Don't include inttypes.h. We support compilers which don't provide it. It was unused anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 9899f70a7406d632c82849978bf6981f1ee4ccb5 |
|
13-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed a nasty layering violation in the edis source
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.
Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 127dc5e615390609540b07ce262ac368278ddb88 |
|
08-Apr-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Use errs instead of fprintf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 8f993b8c244bb5ec19d004a070eb9f32c5a29b1a |
|
08-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.
I will add the test harness for all this stuff in
a separate commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| f65027842e82027dd6e8020586a299aaa548e355 |
|
19-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every
call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 5e81716425dc3373fbc834bfa7936a5c1205579b |
|
14-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Check in tablegen changes to fix disassembler related failures caused by r98465.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| cf57c7084afa98e7719173f792eb2b3e28f42630 |
|
10-Feb-2010 |
Sean Callanan <scallanan@apple.com> |
Updated the enhanced disassembly library's TableGen
backend to not use exceptions at all except in cases
of actual error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 2db6ff2285bbfacf675739f46008581517abe8bf |
|
10-Feb-2010 |
Sean Callanan <scallanan@apple.com> |
Updated the TableGen emitter for the Enhanced
Disassembler to take advantage of the refactored
AsmWriterInst.h. Note removed parser code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| d0bc7f060ece77c670794ef60f7052e2ff1847c9 |
|
10-Feb-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed some indentation in the AsmWriterInst
implementation. Also changed the constructor
so that it does not require a Record, making it
usable by the EDEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 9988ab04961c5bdb8fd622e2ceff4407493cd15e |
|
29-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Quick fix to make the header file for the enhanced
disassembly information have a better comment (and
better guard macros).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|
| 95fcebd5c490c725ee5d88be963d39ddaf0971bd |
|
29-Jan-2010 |
Sean Callanan <scallanan@apple.com> |
Added a custom TableGen backend to support the
enhanced disassembler, and the necessary makefile
rules to build the table for X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/EDEmitter.cpp
|