Cross Reference: /external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines Matching refs:VReg
271     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
274     if (!VReg) {
276       VReg = MRI->createVirtualRegister(RC);
279             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
280     return VReg;
302   unsigned VReg = getVR(Op, VRBaseMap);
303   assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
311   // shrink VReg's register class within reason.  For example, if VReg == GR32
312   // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
319     if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
322               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
323       VReg = NewVReg;
348   MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
429 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
431   const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
434   // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
437     RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
439   // VReg has been adjusted.  It can be used with SubIdx operands now.
441     return VReg;
443   // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
449     .addReg(VReg);
483     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
484     MachineInstr *DefMI = MRI->getVRegDef(VReg);
500       // VReg may not support a SubIdx sub-register, and we may need to
503       VReg = ConstrainForSubReg(VReg, SubIdx,
513               TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
576   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
578   // Create the new VReg in the destination class and emit a copy.
584     NewVReg).addReg(VReg);