| c05d30601ced172b55be81bb529df6be91d6ae15 |
|
06-Sep-2012 |
Nadav Rotem <nrotem@apple.com> |
Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 94083149fd6891c8a72472cf1814fa6600a75979 |
|
31-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add MachineInstr::tieOperands, remove setIsTied().
Manage tied operands entirely internally to MachineInstr. This makes it
possible to change the representation of tied operands, as I will do
shortly.
The constraint that tied uses and defs must be in the same order was too
restrictive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 908c0c01f634798a4c1b335a6aca0870ad1fce77 |
|
31-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't enforce ordered inline asm operands.
I was too optimistic, inline asm can have tied operands that don't
follow the def order.
Fixes PR13742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 492d76b02ec5dd84fa59f79ce83cd3e5ae6603fe |
|
30-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Verify the order of tied operands in inline asm.
When there are multiple tied use-def pairs on an inline asm instruction,
the tied uses must appear in the same order as the defs.
It is possible to write an LLVM IR inline asm instruction that breaks
this constraint, but there is no reason for a front end to emit the
operands out of order.
The gnu inline asm syntax specifies tied operands as a single read/write
constraint "+r", so ouf of order operands are not possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 66390805ad58871cde3f5ccd72a7dcac9b1cd4d8 |
|
30-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Set the isTied flags when building INLINEASM MachineInstrs.
For normal instructions, isTied() is set automatically by addOperand(),
based on MCInstrDesc, but inline asm has tied operands outside the
descriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| baa74e4b35d96ee154c68fa6d204d854cb45f969 |
|
24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid including explicit uses when counting SDNode imp-uses.
It is legal to have a register node as an explicit operand, it shouldn't
be counted as an implicit use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 74500bdba3eae36a1a8a17d8bad0b971b9c212ec |
|
08-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add SelectionDAG::getTargetIndex.
This adds support for TargetIndex operands during isel. The meaning of
these (index, offset, flags) operands is entirely defined by the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 875913439ca8f073852ec8315d3b32b875184582 |
|
11-Jul-2012 |
Evan Cheng <evan.cheng@apple.com> |
InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:
r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4
to a copy:
r1026 = copy r1024
This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.
rdar://11849816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 33a537a5c41e60507ac9a4ea987c1a395cbb74fe |
|
05-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.
The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.
Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 8ccaad526abdf39141b11b6d480b027d73a2d2a8 |
|
29-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clear kill flags in InstrEmitter::EmitSubregNode().
When a local virtual register is made global, make sure to clear any
existing kill flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 |
|
08-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).
So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.
Patch by Yiannis Tsiouris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| f12f6dff9784805e8f89309787231c1ec53a8c6e |
|
03-May-2012 |
Andrew Trick <atrick@apple.com> |
Added TargetRegisterInfo::getAllocatableClass.
The ensures that virtual registers always belong to an allocatable class.
If your target attempts to create a vreg for an operand that has no
allocatable register subclass, you will crash quickly.
This ensures that targets define register classes as intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| f77c03a8599ca354393292bb6c918ea8dab6a21d |
|
24-Feb-2012 |
Hal Finkel <hfinkel@anl.gov> |
Don't crash when a glue node contains an internal CopyToReg
This is necessary to support the existing ppc lowering code for indirect calls.
Fixes PR12071.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 59cb77fb11ec547f60ef0ff4a8ccf3bd8007ae46 |
|
03-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle all live physreg defs in the same place.
SelectionDAG has 4 different ways of passing physreg defs to users.
Collect all of the uses at the same time, and pass all of them to
MI->setPhysRegsDeadExcept() to mark the remaining defs dead.
The setPhysRegsDeadExcept() function will soon add the required
implicit-defs to instructions with register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 9cf37e8b48732fccd4c301ed51aafed7074bd84e |
|
19-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a RegisterMaskSDNode class.
This SelectionDAG node will be attached to call nodes by LowerCall(),
and eventually becomes a MO_RegisterMask MachineOperand on the
MachineInstr representing the call instruction.
LowerCall() will attach a register mask that depends on the calling
convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| cd7f02bb43ec07e0a2bd6d90177b353c94408586 |
|
18-Jan-2012 |
Pete Cooper <peter_cooper@apple.com> |
Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
|
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| d2ed2d71c95462a6b14e7c7c8c82cb727ed342eb |
|
05-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify EXTRACT_SUBREG emission.
EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to
constrain the %dst register class. RegisterCoalescer will apply the
necessary constraints if it decides to eliminate the COPY.
The %src register class does need to be constrained to something with
the right sub-registers, though. This is currently done manually with
COPY_TO_REGCLASS nodes. They can possibly be removed after this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 2c3bef8a15c84ad8ef043f8e8ff08ffe1b96720b |
|
05-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify INSERT_SUBREG emission.
The register class created by INSERT_SUBREG and SUBREG_TO_REG must be
legal and support the SubIdx sub-registers.
The new getSubClassWithSubReg() hook can compute that.
This may create INSERT_SUBREG instructions defining a larger register
class than the sub-register being inserted. That is OK,
RegisterCoalescer will constrain the register class as needed when it
eliminates the INSERT_SUBREG instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| e27e1ca3c90b69e78242c98a669337f84ccded7f |
|
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move getCommonSubClass() into TRI.
It will soon need the context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 08f5cdf5b33b8202edddb24abee6af2a0b3ae49c |
|
22-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Constrain register classes instead of emitting copies.
Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.
Normally, these copies are handled by the coalescer. This saves some
coalescer work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 3be654f8082dcbdff011a6716a7c90486e28fc9e |
|
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 83a8031336a1155e6b0c3e9a84164324e08d1c8b |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 4815d56bb2c356a610f46753c5f1cefafa113b21 |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 3af7a67629292840f0dbae8fad4e333b009e69dd |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 37fefc20d3a1e3934a377567d54a141f67752227 |
|
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
|
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 15993f83a419950f06d2879d6701530ae6449317 |
|
27-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| f792fa90f1125553008659c743cba85b9b5d2e5e |
|
27-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Distinguish early clobber output operands from clobbered registers.
Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.
The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.
This will pop a register off the stack:
asm("fstp %st" : : "t"(x) : "st");
While this will pop the input and push an output:
asm("fst %st" : "=&t"(r) : "t"(x));
We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 8594d429e02c688d428036f8563f09572da3fbff |
|
24-Jun-2011 |
Devang Patel <dpatel@apple.com> |
Handle debug info for i128 constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| c02a6fa7d8f0ccf2e0059bc40978a466fff3fcab |
|
17-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't use register classes larger than TLI->getRegClassFor(VT).
In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).
<rdar://problem/9624323>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 1300f3019e5d590231bbc3d907626708515d3212 |
|
16-Jun-2011 |
Owen Anderson <resistor@mac.com> |
Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| fa226bccaa90c520cac154df74069bbabb976eab |
|
02-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| c9df025e33ac435adb3b3318d237c36ca7cec659 |
|
10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| c36b7069b42bece963b7e6adf020353ce990ef76 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.
This allows memory instructions to be moved around INLINEASM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 0b71d3972d9138c7482233bc44a9a207634769ef |
|
06-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Optimize:
r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4
to:
r1026 = copy r1024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 29d8f0cae425f1bba583565227eaebf58f26ce73 |
|
23-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
flags -> glue for selectiondag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 8e68c3873549ca31533e2e3e40dda3a43cb79566 |
|
23-Dec-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 495de3b783c239b4b3244a1e739b2a5b82561b1b |
|
17-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.
Radar 8776599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| bece04845e6746fd162bc36e79a6cfd095165c23 |
|
08-Dec-2010 |
Eric Christopher <echristo@apple.com> |
Reword comment slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 668ac2fdae69ed358ecf690d6a07428e5a9ee2f7 |
|
16-Nov-2010 |
Dan Gohman <gohman@apple.com> |
Split pseudo-instruction expansion into a separate pass, to make it
easier to debug, and to avoid complications when the CFG changes
in the middle of the instruction selection process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119382 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| c040719a153df8202f10054f33c9ac581b1c6c57 |
|
30-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Revert r112461. It was failing on PPC...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 25b141912ce4f5a4b8a0684e870569ece21facde |
|
30-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
When adding a register, we should mark it as "def" if it can optionally define
said (physical) register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 92c1f72c548e6a5e793ef19a0b04910992115b6c |
|
10-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Emit COPY instructions instead of using copyRegToReg in InstrEmitter,
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.
This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 3cd26a2909cd5d002fe2742041a264ba217ba88e |
|
10-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Insert IMPLICIT_DEF instructions at the current insert position, not
at the end of the block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 84023e0fbefc406a4c611d3d64a10df5d3a97dd7 |
|
10-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
- Eschew ST0 and ST1 for return values.
- Fix the PIC base register initialization so that it doesn't ever
fail to end up the top of the entry block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 02266e29f9250d74c5ec720aff23add3410ae920 |
|
09-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r107947 into '.':
U utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U test/CodeGen/X86/fast-isel.ll
U test/CodeGen/X86/fast-isel-loads.ll
U include/llvm/Target/TargetLowering.h
U include/llvm/Support/PassNameParser.h
U include/llvm/CodeGen/FunctionLoweringInfo.h
U include/llvm/CodeGen/CallingConvLower.h
U include/llvm/CodeGen/FastISel.h
U include/llvm/CodeGen/SelectionDAGISel.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/CallingConvLower.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
U lib/Target/XCore/XCoreISelLowering.cpp
U lib/Target/XCore/XCoreISelLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86ISelLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| bf87e2491789d6ff788629e22e93d0c1ca02ae85 |
|
09-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 0bc25f40402f48ba42fc45403f635b20d90fabb3 |
|
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| f59514152511694d46ca8b8d2db466d256ab5759 |
|
08-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 5c480432b504bfbe8b3ba028f5f48e7e2e2f1f1e |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Not all custom inserters create new basic blocks. If the inserter
didn't create a new block, don't reset the insert position.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| cc87bfb59b34a0543b48d93f661f2abaee6b4cee |
|
07-Jul-2010 |
Devang Patel <dpatel@apple.com> |
Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107796 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 14152b480d09c7ca912af7c06d00b0ff3912e4f5 |
|
06-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| f1e309eb4862459a76445942ba4dafc433b6f317 |
|
02-Jul-2010 |
Dale Johannesen <dalej@apple.com> |
Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| d31f972bd33de85071c716f69bf5c6d735f730f2 |
|
29-Jun-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.
If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| db4971259ce94cea26e555e9ade82672a3581f5c |
|
19-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Teach regular and fast isel to set dead flags on unused implicit defs
on calls and similar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 3013a2068421335304dce861dd5977e8cf43cbca |
|
09-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Mark physregs defined by inline asm as implicit.
This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| c3c2517fed43457fed8c2e891556866dba5b83cf |
|
09-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add argument name comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 5012f9b82525121c28709ad7a2cc27818a38c213 |
|
18-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 27e4840e03a6fea9f7a36a83b09a8ab7fed1a620 |
|
18-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 8b3a8f5773d799762b61adf976b9771117f0f261 |
|
15-May-2010 |
Dan Gohman <gohman@apple.com> |
Don't set kill flags for instructions which the scheduler has cloned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 9d7019f586719a03f3519142ca2166166962e433 |
|
11-May-2010 |
Dan Gohman <gohman@apple.com> |
Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn't
create separate virtual registers for CopyFromReg values, so uses of
them don't necessarily kill the value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 60ffa9467b0c7df2f76e2b2de7af17b776805e28 |
|
11-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 4ce86f459c92258f887fd8fd884fa55066b3a0cd |
|
08-May-2010 |
Dan Gohman <gohman@apple.com> |
SDDbgValues are apparently not being legalized. Fix a symptom of the problem,
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| ba609c88a5a0eb717772c89bda89157c85fdf95e |
|
04-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach scheduler about REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 2131e2a75fc562e4dbaeb6954eac35147c71104f |
|
04-May-2010 |
Dan Gohman <gohman@apple.com> |
Re-enable isel kill flags, now that the local allocator is ignoring them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 0b7afeb4408dc20476b125f66af1829d6741795e |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Re-disable kill flags, as there is more trouble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 3a401bcd04e3a04eea9e91649e1a820ff7cc60c1 |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Re-enable kill flags from SelectionDAGISel, with a fix: don't
try to put a kill flag on a DBG_INFO instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| af1d8ca44a18f304f207e209b3bdb94b590f86ff |
|
01-May-2010 |
Dan Gohman <gohman@apple.com> |
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 891ff8fbd61a06ef8ea57461fa377ebbb663ed09 |
|
30-Apr-2010 |
Dan Gohman <gohman@apple.com> |
EmitDbgValue doesn't need its EdgeMapping argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 71cee76d26bdbb50d86a206717fe5b4265b396e7 |
|
30-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Temporarily disable SelectionDAG kill flags, which are causing trouble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 47bd03b2779bc500fb0472518d0e278f080ee79a |
|
30-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Set register kill flags on the SelectionDAG path, at least in the
easy cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102678 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| cc7354e9936595fd2654e1690310fcdc5ef10971 |
|
27-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Avoid adding a null MD node operand, which crashes with "-debug" when trying
to print the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 962021bc7f6721c20c7dfe8ca809e2d98b1c554a |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| f822e733aff93b34e6cd85b2f92d86e71fe67f87 |
|
25-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Stop abusing EmitInstrWithCustomInserter for target-dependent
form of DEBUG_VALUE, as it doesn't have reasonable default
behavior for unsupported targets. Add a new hook instead.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 8b1dbebc1e783fde62d01608d5f3a436c5a1a737 |
|
20-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Delete a redundant return statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101860 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| 46510a73e977273ec67747eb34cbdb43f815e451 |
|
15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| cf9a415182aca6a432105a2a12168e1049de180a |
|
07-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Have the inst emitter add the !srcloc mdnode to the machine instr.
Have the asmprinter use the mdnode to scavenge a source location if
present. Document this nonsense in langref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| decc2671516e6c52ee2f29f7746f8d02753845ea |
|
07-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
Three changes:
1. Introduce some enums and accessors in the InlineAsm class
that eliminate a ton of magic numbers when handling inline
asm SDNode.
2. Add a new MDNodeSDNode selection dag node type that holds
a MDNode (shocking!)
3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc
metadata, propagating it to the instruction emitter, which
drops it.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| c4d7b14a92a9b34449eccdccce1263c4b68ad474 |
|
06-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Allow for the possibility that a debug-value points
to a SDNode that didn't have code generated for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|
| d05e8055362be52fc33dcc685ba2ae5c722506b5 |
|
26-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
LiveVariables should clear kill / dead markers first. This allows us to remove a hack in the scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 7bf198fd607b356e767e0577cac81c3491c4bc90 |
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25-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix a valgrind error on copy-constructor-synthesis.cpp, which is caused when
the custom insertion hook deletes the instruction, then we try to set dead
flags on it. Neither the code that I added nor the code that was there
before was safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 47cdf4abff20eb9d7d05406cc1a9be2890ed39bb |
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25-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Make the NDEBUG assertion stronger and more clear what is
happening.
Enhance scheduling to set the DEAD flag on implicit defs
more aggressively. Before, we'd set an implicit def operand
to dead if it were present in the SDNode corresponding to
the machineinstr but had no use. Now we do it in this case
AND if the implicit def does not exist in the SDNode at all.
This exposes a couple of problems: one is the FIXME, which
causes a live intervals crash on CodeGen/X86/sibcall.ll.
The second is that it makes machinecse and licm more
aggressive (which is a good thing) but also exposes a case
where licm hoists a set0 and then it doesn't get resunk.
Talking to codegen folks about both these issues, but I need
this patch in in the meantime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 3d7d07ef038696cefcaf3ce5335072964199a78d |
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25-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
reapply 99444/99445, which I speculatively reverted in
r99453.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| bfcb3051899b7141a946d769fcf6e8a8453bc530 |
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25-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.
Here is a theoretical example that illustrates why the placement is important.
tmp1 =
store tmp1 -> x
...
tmp2 = add ...
...
call
...
store tmp2 -> x
Now mem2reg comes along:
tmp1 =
dbg_value (tmp1 -> x)
...
tmp2 = add ...
...
call
...
dbg_value (tmp2 -> x)
When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1.
Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers").
This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| d41952da109565ab11b7f435c39a0c524c75298e |
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25-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
revert 99444/99445. This doesn't cause the failure of
2006-07-19-stwbrx-crash.ll for me, but it's the only likely
patch in the blame list of several bots. Lets see if this
fixes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 4020670195e96f98f949737f95dcd4916282a5e8 |
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24-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
remove dead argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| c243dea003bfe11cb4cdc0cef80997b06b96cb21 |
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24-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
split EmitNode in half to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99444 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| a8efe28a44996978faa42a387f1a6087a7b942c7 |
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14-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Rename SDDbgValue.h to SDNodeDbgValue.h for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 7561d480953e0a2faa4af9be0a00b1180097c4bd |
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14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
change the LabelSDNode to be EHLabelSDNode and make it hold
an MCSymbol. Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID. Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98463 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| e3b8533e711718ffa5366cbc8fdf7c6881b8cb02 |
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11-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
Cosmetic: lengthen names and improve comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33 |
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10-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
Progress towards shepherding debug info through SelectionDAG.
No functional effect yet. This is still evolving and should
not be viewed as final.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 06a26637daff1bb785ef0945d1ba05f6ccdfab86 |
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06-Mar-2010 |
Dale Johannesen <dalej@apple.com> |
Add some new bits of debug info handling. No
functional change yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 518bb53485df640d7b7e3f6b0544099020c42aa7 |
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09-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 80ffc965f513bed2252316af8530c14c36c2e295 |
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21-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Trim unneeded includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 29cbade25aa094ca9a149a96a8614cf6f3247480 |
|
21-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 552c0dff3408424404d1e9639a5710207b862964 |
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16-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 4cddfd9b6f2b770c0dce66792b79ac9d18bb0ca3 |
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31-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Don't mark registers dead here when processing nodes with MVT::Flag
results. This works around a problem affecting targets which rely on
MVT::Flag to handle physical register defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 8c2b52552c90f39e4b2fed43e309e599e742b6ac |
|
30-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Initial target-independent CodeGen support for BlockAddresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| 533297b58da8c74bec65551e1aface9801fc2259 |
|
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| a104d1eab279a39ebf0481269426c2e2de8f5587 |
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28-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Mark dead physregdefs dead immediately. This helps MachineSink and
MachineLICM and other things which run before LiveVariables is run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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| bcea859fc1dd1af9ac66ec93ea04ce9a19c8451c |
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10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Create a new InstrEmitter class for translating SelectionDAG nodes
into MachineInstrs. This is mostly just moving the code from
ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
|